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multimedia video electronics page 1 of 50 070595 video encoder the KS0119 combines ntsc encoding with conventional ram-dac functions so that digitized video or computer generated graphics can be displayed on either ntsc or pc monitors. there are two data input channels which allow mixing. provision is also made for analog mixing at the output. operation modes can be programmed under host control. the KS0119 can be used with other members of the samsung multimedia chip set in a typical desktop multimedia environment. features ? accepts true color; high color; color indexed; ccir 601 4:4:4, 4:2:2, 4:1:1, or 2:1:1 formatted video inputs ? supports analog ntsc cvbs, s-video, or rgb display ? fully programmable timing generation; supports cga, vga, svga display up to 45 mhz pixel clock rate (with 100 pin package) ? accepts up to 2 input channels for digital mixing ? operate as slave or master in timing generation ? supports alpha, chroma, and window keying for digital mixing ? provides an analog rgb mixing function ? contains 3 256x8 color palette tables and 3 15x8 overlay color look up tables ? contains 3 10-bit video grade dacs ? provides a parallel microprocessor or a 3-wire serial interface ? contains a two way color space converter: rgb -> ntsc, ycbcr -> rgb ? supports power down mode KS0119 data sheet 80 or 100 pqfp block diagram p[0:31] input formatter clut 3x8x256 overlay clut 3x8x15 interpolator color space converter ntsc processor triple 10-bit dac triple analog mux mixing microprocessor interface r/cvbs g/y b/c aky rin,gin,bin timing control dky/r a[0:3] d[0:7] cs r/w p/s ck27 ckv av vblk f2 mrqst hsyn vsyn csyn ckp /mode mixing control ordering information device package temp. range max. ckv KS0119 80-qfp 0 ~ +65c 32 mhz KS0119q2 100-qfp 0 ~ +65c 45 mhz applications ?pc video ? ram dac, gamma correction ? yuv dac for mpeg, jpeg play back ? ntsc video encoder related product ? ks0122 multistandard video decoder
KS0119 data sheet multimedia video electronics page 2 of 50 070595 pin assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p0 dky/r vdd ck27 vss ckv comp iref vref aky bin b/c gin g/y rin r/cvbs p21 p22 p23 p24 p25 p26 p27 p28 p29 p30 p31 vdd vss av vblk f2 KS0119 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 vdd ckp vss vss p16 p17 p18 p19 p20 vdda vss vss vdda vdd csyn hsyn vsyn d0 d1 d2 d3 d4 d5 d6 d7(sdat) r/w (sclk) cs (sfrs) p/s a0 a1 a2 a3 mrqst/mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p2 p3 p4 p5 p6 p7 p9 p10 p11 p12 p13 p14 p15 vdd ckp vss vss p16 p17 p18 KS0119q2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 p0 dky/r vdd ck27 vss ckv comp iref vref aky bin b/c gin g/y rin r/cvbs ncp vdda vss vss vdda vdd csyn hsyn vsyn d0 d1 d2 d3 d4 d5 mrqst/mode a3 a2 a0 p/s cs (sfrs) r/w (sclk) d7(sdat) d6 97 98 99 100 ncp ncp ncp p1 p8 p19 ncp ncp ncp ncp vdda ncp ncp ncp ncp a1 p20 ncp ncp ncp 61 p21 p22 p23 p24 p25 p26 p27 p28 p29 p30 p31 vdd vss av vblk f2 ncp ncp ncp ncp
KS0119 data sheet multimedia video electronics page 3 of 50 070595 typical applications the KS0119 is shown in a vga overlay application with the ks0122 multistandard video decoder in figure 1. figure 1. vga overlay figure 2 shows a video cd playback system using the KS0119 as a video encoder. figure 2. video cd playback multi memory controller frame buffer encoder KS0119 ntsc/pal video input tv,vcr,laser disc m p bus vga display ks0122 s-video or composite standard decoder video cd decoder encoder KS0119 ntsc display
KS0119 data sheet multimedia video electronics page 4 of 50 070595 pin description pin name pin # (80) pin # (100) type description video buffer interface p0 - p31 80,1-15, 20 - 35 98,4-18, 23- 27,33-43 i digital video input bus. f2 40 48 o field 2 indicator. active low signal. mrqst /mode 41 53 i/o dual function pin. during power-on, it is an input and its logic state determines whether the chip operates in ntsc mode or vga pass through mode. a 4.7 k pull-up resistor sets the chip in vga pass through mode. otherwise it defaults to ntsc mode. after power-on this pin becomes an output and is high during active lines sync tip. av 38 46 i/o active video indicator. input in slave mode; output in master mode. vblk 39 47 i/o vertical blank. input in slave mode; output in master mode. ckp 17 20 o pixel clock output. dky/r 79 97 i dual function input pin. configured by the cmd register bit 2. it can be used as either digital mixing or hardware run input. please refer to the command register description for more detail. analog multiplexer input rin 66 84 i analog r input to the analog mixing multiplexer. gin 68 86 i analog g input to the analog mixing multiplexer. bin 70 88 i analog b input to the analog mixing multiplexer. aky 71 89 i analog multiplexer control. a logic 0 connects analog rgb inputs to the output pins. a 1 connects dacs outputs to the output pins. video output port hsyn 58 70 o horizontal sync. active low, ttl signal for monitor. in the pass through mode hsyn is the inverted av (pin 38). vsyn 57 69 o vertical sync. active low, ttl signal for monitor. in the pass through mode vsyn is the inverted vblk (pin 39) csyn 59 71 o composite sync. active low, ttl signal for monitor. r/cvbs 65 83 o either an analog r or composite output, controlled by cmd bits 5 and 1. it can drive a 37.5 w load (doubly terminated 75 w load). g/y 67 85 o either an analog g or s-video y output, controlled by cmd bits 5 and 1. it can drive a 37.5 w load. b/c 69 87 o either an analog b or s-video c output, controlled by cmd bits 5 and 1. it can drive a 37.5 w load.
KS0119 data sheet multimedia video electronics page 5 of 50 070595 reference and compensation vref 72 90 i/o voltage reference. it has an internal voltage reference circuit, but may be overridden by an external voltage reference input. a 0.1 m f ceramic capacitor is required between this pin and gnd. iref 73 91 i a resistor is connected between this pin and gnd to control the dac output current. comp 74 92 i compensation capacitor for the dac internal reference amplifier. a 0.1 m f ceramic capacitor is required between this pin and vdda. host interface p/s 46 58 i microprocessor interface configuration control. tie to vdd to select parallel mode. tie to vss to select serial mode. cs (sfrs) 47 59 i chip select strobe in parallel mode (frame sync in serial mode). r/w (sclk) 48 60 i read/write in parallel mode (serial clock in serial mode). d7 (sdat) 49 61 i/o data bus msb in parallel mode (serial data in serial mode). d0 - d6 56-50 68-62 i/o parallel data bus bit 0 to 6. a0 - a3 45-42 57-54 i address bus for parallel interface. clock input ckv 75 93 i clock input used to generate pixel clock for vga display. ck27 77 95 i 27 mhz clock input, required for ntsc display. power and ground vdd 16,36, 60,78 19,44,72,96 +5v digital power supply. vss 18,19, 37,62, 63,76 21,22,45,74, 75,94 gnd digital ground. vdda 61,64 76,80 +5v analog power supply. ncp ncp n/a 1-3,28-32, 49-52,77- 79,81,82,99, 100 - these pins are directly connected to the die substrate. they are intended as heat dissipation points. it is recommended that each corner set of ncp pins be connected to as large as possible solid metal plane on the pcb component surface side. if electrical connect is desired (not required) only connection to vdda is allowed. pin description (continued) pin name pin # (80) pin # (100) type description
KS0119 data sheet multimedia video electronics page 6 of 50 070595 pin cross reference (numerical order by pin number): 80-pqfp pin # pin name pin # pin name pin # pin name pin # pin name 1 p1 21 p17 41 mrqst/mode 61 vdda 2 p2 22 p18 42 a3 62 vss 3 p3 23 p19 43 a2 63 vss 4 p4 24 p20 44 a1 64 vdda 5 p5 25 p21 45 a0 65 r/cvbs 6 p6 26 p22 46 p/s 66 rin 7 p7 27 p23 47 cs (sfrs) 67 g/y 8 p8 28 p24 48 r/w (sclk) 68 gin 9 p9 29 p25 49 d7(sdat) 69 b/c 10 p10 30 p26 50 d6 70 bin 11 p11 31 p27 51 d5 71 aky 12 p12 32 p28 52 d4 72 vref 13 p13 33 p29 53 d3 73 iref 14 p14 34 p30 54 d2 74 comp 15 p15 35 p31 55 d1 75 ckv 16 vdd 36 vdd 56 d0 76 vss 17 ckp 37 vss 57 vsyn 77 ck27 18 vss 38 av 58 hsyn 78 vdd 19 vss 39 vblk 59 csyn 79 dky/r 20 p16 40 f2 60 vdd 80 p0
KS0119 data sheet multimedia video electronics page 7 of 50 070595 pin cross reference (continued): 100-pqfp pin # pin name pin # pin name pin # pin name pin # pin name 1 ncp 26 p19 51 ncp 76 vdda 2 ncp 27 p20 52 ncp 77 ncp 3 ncp 28 ncp 53 mrqst/mode 78 ncp 4 p1 29 ncp 54 a3 79 ncp 5 p2 30 ncp 55 a2 80 vdda 6 p3 31 ncp 56 a1 81 ncp 7 p4 32 ncp 57 a0 82 ncp 8 p5 33 p21 58 p/s 83 r/cvbs 9 p6 34 p22 59 cs (sfrs) 84 rin 10 p7 35 p23 60 r/w (sclk) 85 g/y 11 p8 36 p24 61 d7(sdat) 86 gin 12 p9 37 p25 62 d6 87 b/c 13 p10 38 p26 63 d5 88 bin 14 p11 39 p27 64 d4 89 aky 15 p12 40 p28 65 d3 90 vref 16 p13 41 p29 66 d2 91 iref 17 p14 42 p30 67 d1 92 comp 18 p15 43 p31 68 d0 93 ckv 19 vdd 44 vdd 69 vsyn 94 vss 20 ckp 45 vss 70 hsyn 95 ck27 21 vss 46 av 71 csyn 96 vdd 22 vss 47 vblk 72 vdd 97 dky/r 23 p16 48 f2 73 vdda 98 p0 24 p17 49 ncp 74 vss 99 ncp 25 p18 50 ncp 75 vss 100 ncp
KS0119 data sheet multimedia video electronics page 8 of 50 070595 1. general description the KS0119 is a digital ntsc encoder combined with basic ram-dac functions. it is designed to be a high performance, cost effective ntsc or pc display driver. the chip consists of a two way color space converter, which is capable of supporting almost all the popular input formats pertaining to pc video, graphics, or image compression/decompression. the chip contains signal processing blocks to enhance image quality and reduce artifacts due to sampling. it provides image manipulation facilities such as masking, mixing, hue control, and color lookup tables to create special effects. it includes a programmable timing generator to generate the synchronization signals and color burst for different display monitors. 1.1. application the KS0119 is a versatile chip, which can be used for many application such as ntsc encoding, yuv dac, ram dac, gamma correction, mixing, and vga overlay. ck27 must be used for ntsc encoder, whereas ckv must be used for the others. it is recommended that the unused clock input pin be tied to a static state. 1.2. power on default the KS0119 can be configured for two power-on default states: one for ntsc video encoding and the other for vga overlay application. for the latter the mrqst/mode pin must be pulled up so the KS0119 defaults to sync pass through mode and channel a is set to support 8-bit pseudo color format after power up. in this mode, the KS0119 functions as a ram-dac. the internal video timing generator is disabled; the horizontal and vertical syncs are delay compensated for the video path delay and passed to the sync output pins. the sync pass through mode is recommended for vga overlay application. 1.3. operation mode the KS0119 can be configured to operate either in master mode or slave mode. in the master mode the encoder uses the parameter stored in the crt control registers to generate all the video timings and outputs synchronizing signals (refer to video operational timing on page 18). in the slave mode the encoder synchronize the internal pixel counter on the falling edge of av , and line counter on the rising edge or vblk. the sync outputs, hsyn and vsyn , waveform can be modified if sync pass through is disabled ( syncpt =0). table 2 shows the registers related to the sync generation. table 1: power on default state power on mrqst/mode pin state operations channel a input format syncpt clock source 0 ntsc encoding 4:2:2 ycbcr 0 ck27 1 vga overlay 8 bit pseudo color 1 ckv table 2: sync output generation master slave control registers mstr =1 mstr =0, syncpt =1 mstr =0, syncpt =0 hsyn , vsyn internally generated pass through regenerated video output port sync polarity active low inverted av and vblk active low input sync polarity control n/a vsp , hsp crt control registers index registers 70 - 79h comments recommend for vga overlay application
KS0119 data sheet multimedia video electronics page 9 of 50 070595 1.4. power down mode the KS0119 supports power down mode; the dac outputs can be put into high impedance state by turning off the current source to conserve power. 1.5. digital video input format the digital video input is a 32 bit port. this port can be used as a single channel or logically divided into two channels: a and b. channel as input can be true color, color indexed, or ccir 601 formats. channel bs input is restricted to ccir 601 formats.the supported formats and their bit assignments are shown in table 3 and table 4. the KS0119 accepts certain input combinations from channel a and b. however the following rules must be observed when both channels are selected (their format registers contain valid numbers): 1. channel bs input is ignored if mixing is not enabled. 2. if mixing is enabled, channel a is the foreground and will be displayed if the mixing key is false. 3. in yc/yc mixing, both channels must have the same format (e.g. channel as format is 4:1:1a, channel bs format must be 4:1:1a. see table 3 and table 4).
KS0119 data sheet multimedia video electronics page 10 of 50 070595 table 3: channel a input format format register (bit 7 - 4) value123 4 5 6 9 a b c type rgb 4:2:2 2:1:1 a 4:1:1 a 4:1:1 b # of bits 24 16 16 15 12 8 16 16 12 16 pixel bus pixel byte sequence n n n n n n2n+12n+14n+1+2+3 4n +1 +2 +3 p0 b0 b0 b0 b0 p0 p0 cb0 cr0 cb0 cr0 cb0 cr0 p1 b1 b1 b1 b1 p1 p1 cb1 cr1 cb1 cr1 cb1 cr1 p2 b2 b2 b2 b2 p2 p2 cb2 cr2 cb2 cr2 cb2 cr2 p3 b3 b3 b3 b3 p3 p3 cb3 cr3 cb3 cr3 cb3 cr3 p4 b4 b4 g0 b4 p4 p4 cb4 cr4 cb4 cr4 cr6 cr4 cr2 cr0 cb4 cr4 p5 b5 g0 g1 g0 p5 p5 cb5 cr5 cb5 cr5 cr7 cr5 cr3 cr1 cb5 cr5 p6 b6 g1 g2 g1 p6 p6 cb6 cr6 cb6 cr6 cb6 cb4 cb2 cb0 cb6 cr6 p7 b7 g2 g3 g2 p7 p7 cb7 cr7 cb7 cr7 cb7 cb5 cb3 cb1 cb7 cr7 p8 g0 g3 g4 g3 ovl0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 p9 g1 g4 g5 g4 ovl1 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1 p10 g2g5r0 r0ovl2 y2y2y2y2y2y2y2y2y2 y2 y2y2 p11 g3r0r1 r1ovl3 y3y3y3y3y3y3y3y3y3 y3 y3y3 p12 g4r1r2 r2 y4y4y4y4y4y4y4y4y4 y4 y4y4 p13 g5r2r3 r3 y5y5y5y5y5y5y5y5y5 y5 y5y5 p14 g6r3r4 r4 y6y6y6y6y6y6y6y6y6 y6 y6y6 p15 g7r4r5tkey y7y7y7y7y7y7y7y7y7 y7 y7y7 p16 r0 p17 r1 p18 r2 p19 r3 p20 r4 p21 r5 p22 r6 p23 r7
KS0119 data sheet multimedia video electronics page 11 of 50 070595 table 4: channel b input format format register (bit 3 - 0) value 1 2 3 4 5 6 7 9 type 4:4:4 4:2:2 a 4:2:2 b 2:1:1 a 2:1:1 b 4:1:1 a 4:1:1 b 4:4:4 # of bits 24 16 24 16 24 12 16 24 pixel bus pixel byte sequence n 2n+12n+12n+12n+14n+1+2+34n +1 +2 +3 n p0 cr0 p1 cr1 p2 cr2 p3 cr3 p4 cr4 p5 cr5 p6 cr6 p7 cr7 p8 cr0 cr0 cr0 p9 cr1 cr1 cr1 p10 cr2 cr2 cr2 p11 cr3 cr3 cr3 p12 cr4 cr4 cr4 p13 cr5 cr5 cr5 p14 cr6 cr6 cr6 p15 cr7 cr7 cr7 p16 cb0 cb0 cr0 cb0 cb0 cr0 cb0 cb0 cr0 cb0 p17 cb1 cb1 cr1 cb1 cb1 cr1 cb1 cb1 cr1 cb1 p18 cb2 cb2 cr2 cb2 cb2 cr2 cb2 cb2 cr2 cb2 p19 cb3 cb3 cr3 cb3 cb3 cr3 cb3 cb3 cr3 cb3 p20 cb4 cb4 cr4 cb4 cb4 cr4 cb4 cr6 cr4 cr2 cr0 cb4 cr4 cb4 p21 cb5 cb5 cr5 cb5 cb5 cr5 cb5 cr7 cr5 cr3 cr1 cb5 cr5 cb5 p22 cb6 cb6 cr6 cb6 cb6 cr6 cb6 cb6 cb4 cb2 cb0 cb6 cr6 cb6 p23 cb7 cb7 cr7 cb7 cb7 cr7 cb7 cb7 cb5 cb3 cb1 cb7 cr7 cb7 p24 y0 y0y0y0y0y0y0y0y0y0y0y0y0y0 y0 y0 y0 y0 p25 y1 y1y1y1y1y1y1y1y1y1y1y1y1y1 y1 y1 y1 y1 p26 y2 y2y2y2y2y2y2y2y2y2y2y2y2y2 y2 y2 y2 y2 p27 y3 y3y3y3y3y3y3y3y3y3y3y3y3y3 y3 y3 y3 y3 p28 y4 y4y4y4y4y4y4y4y4y4y4y4y4y4 y4 y4 y4 y4 p29 y5 y5y5y5y5y5y5y5y5y5y5y5y5y5 y5 y5 y5 y5 p30 y6 y6y6y6y6y6y6y6y6y6y6y6y6y6 y6 y6 y6 y6 p31 y7 y7y7y7y7y7y7y7y7y7y7y7y7y7 y7 y7 y7 y7
KS0119 data sheet multimedia video electronics page 12 of 50 070595 2. digital mixing the KS0119 supports digital mixing between the two input channels. digital mixing is the process of replacing a selected area in the foreground (channel a) with the corresponding area in the background (channel b) according to the output of the keying function. the result is that the foreground objects appear situated in front of the backgrounds. mixing is an indispensable tool to create special effects, such as animation, picture in picture, and video overlay. the ability to select a small area to display can be used to reduce or hide the image download time during presentations. the digital mixing is controlled by the mixing control register ( mxctr ) and control registers 05h to 0dh. figure 3. digital mixer signal flow diagram 2.1. mixing methods the KS0119 supports two types of mixing: rgb/yc and yc/yc. 2.1.1. rgb/yc mixing rgb/yc mixing is automatically selected if channel as format is either high color or pseudo color. the process simply replaces channel as video with channel bs when the output of the keying function is 1. 2.1.2. yc/yc mixing if channel as input is ycbcr formatted (format register value greater than 7), then yc/yc mixing is selected. in yc/ yc mixing, when the output of the keying function is 1, the channel as chrominance components are replaced with channel bs, while the luminance signals are linearly blended according to the equation where k is a programmable value, from 0 to 7, stored in the mixing control register ( mxctr ). linear mixing preserves the shadows inside the keyed area. 2.2. keying methods the KS0119 supports window keying, index keying, chroma keying, alpha keying, external keying, and certain combinations of them. these are described in detail below. yout 1 8 -- - k [ ya 1 ( k ) C yb ] + =
KS0119 data sheet multimedia video electronics page 13 of 50 070595 2.2.1. index keying if channel as input format is 2, 3, 4, 5, or 6, index keying can be used for mixing. channel as inputs are first compared with the contents in the two 8 bit template registers ( tmplb , tmpla ). the results are then filtered by the mask registers ( mskb , mska ) and anded together to generate the key signal. if the input is 8 or 15 bits wide, the unused bits are automatically masked out. figure 4 shows the logic operation involved in index keying. figure 4. index keying generation 2.2.2. chroma keying if channel as input is ycbcr format, chroma keying can be used for mixing. a rectangular area is specified in the cb-cr space (figure 5). if channel as cb/cr values fall within this area, channel bs video will be displayed. in this mode, tmpla and tmplb specify the lower and upper cb, respectively, and mska and mskb specify the lower and upper cr, respectively, in the cb-cr space. note that cb and cr are binary offset numbers with 128 corresponding to zero intensity, 0 and 255 corresponding to maximum intensity. figure 5. cb-cr chroma keying 2.2.3. window keying a rectangular key window is specified in x-y coordinates in the active display area. if window mixing is enabled and the outsd bit of the mixing control register is 0, channel b is displayed inside the window, and channel a is outside the window. the converse is true if the outsd bit is 1. if both the chroma and window keyings are enabled, the outsd bit specifies where the chroma keying will be applied: 0 inside the window and 1 outside the window. the 8 msbs of the four 10 bit coordinate registers, window horizontal start address, window horizontal end address, window vertical start address and window vertical end address, are stored in the whs , whe , wvs and wve registers, respectively, while the 2 lsb bits are stored in the whv register. the four msb registers are double clocked, and synchronized to the wve write. a write to the wve register will transfer the four msb registers contents, concatenated with their corresponding lsbs, to the respective final address registers. modifying the msb t e m p l a t e m a s k c h a n n e l a index key cb cr 128,128 128,255 255,128 ccir color key
KS0119 data sheet multimedia video electronics page 14 of 50 070595 register without writing to the wve register will have no effect on the final address register. for multiplexed ycbcr video inputs, it is recommended that the horizontal window boundaries equal integer multiples of the block size. 2.2.4. alpha keying if channel as input is only 15 bits (format 4, rgb 5:5:5), bit 15 of the input can be used as a mixing key. 2.2.5. external key pin dky/r can be used as a mixing key if the dkf bit of the command register ( cmd ) configures this pin as an external key input.
KS0119 data sheet multimedia video electronics page 15 of 50 070595 3. signal processing 3.1. y/c interpolation filters the incoming ycbcr signals are processed by the interpolation unit to increase the data rates to 13.5 mhz. (4:4:4 format). the multiplexed chroma signals are up sampled first, and then pass through either a 6th-order half-band or an 8th-order quarter-band filter. the reconstruction filters have flat 0 to 0.6 mhz frequency response as shown in figure 6-(a). the received half-sampled luminance component (mpeg decoder output, 360 samples/line), which has a bandwidth less than 3 mhz, after being up sampled, will pass through a 14th-order smooth filter whose frequency response characteristic is shown in figure 6-(b). these filters ensure the preservation of base band signals as well as the elimination of attendant high frequency aliasing components due to up sampling. figure 6. interpolation filter characteristics 3.2. band-limit filter the ntsc encoder unit consists of a 4 mhz luminance low pass filter and two equal bandwidth 1.2 mhz chrominance low pass filters. the functions of these filters are to limit the frequency contents of the computer generated image, to reduce the cross-luminance/chrominance distortion due to the mixing processes, and to enhance the resolutions.the digital filters are designed to have faster roll-off than the analog counterparts so that the quantization noise, which is monotonic decreasing along the frequency axis, are removed as soon as they pass the band of interest. figure 7 shows the overall filter characteristics (interpolation cascaded with band-limit) for x:1:1 and x:2:2 formatted data. also shown in figure 8 are the luminance band-limit characteristics with and without the chroma filter. at the filters outputs, each pixel is represented by 3 10-bit numbers, which are maintained until the dac inputs. hence the block effects due to the limited quantization levels are reduced. (a) chrominance (b) luminance attenuation (db) attenuation (db) frequency (mhz) frequency (mhz) half-band quarter-band
KS0119 data sheet multimedia video electronics page 16 of 50 070595 figure 7. chrominance filter characteristics figure 8. luminance band-limit filter characteristics 3.3. sinc ( sin x/x) function effect the digital-to-analog converter exhibits a high frequency roll-off sinc filter characteristic owing to the zeroth order sample and hold process. the roll-off is a function of the dacs conversion rate. the ntsc encoder unit also incorporates a 6th-order interpolation filter to raise the data rate to 27 mhz. the roll-off at 4 mhz is reduced from -1 db (sampled at 13.5 mhz) to -0.2 db. the up sampling also pushes the high frequency image beyond 23 mhz, greatly reducing the analog reconstruction filter requirement at the dacs outputs. attenuation (db) frequency (mhz) x:1:1 input x:2:2 input attenuation (db) with chroma filter without chroma filter frequency (mhz)
KS0119 data sheet multimedia video electronics page 17 of 50 070595 4. signal manipulation functions the ntsc encoder unit provides the facilities for the user to control the contrast, hue, color killer and the vertical blanking period by programming the command register b ( cmdb ) and hue control register( hue ). 4.1. hue control the chromaticity can be changed by modifying the modulation angle. the entire 360 hue range is divided into 264 equal units. to move the hue angle by k units the congruent 83*k mod 264 should be loaded into the hue register and bit 7 of cmdb register. the hue register will not be transferred to the final hue control register until a write to the cmdb register occurs. therefore, when changing the hue angle, the hue register must be loaded first followed by a write to the cmdb register. the following examples show the value to be programmed into the hue register for +5 and -5 degree hue angle: examples: +5 degree hue angle -5 degree hue angle 4.2. chroma trap filter the luminance path includes a chroma trap filter. when this filter is enabled ( cmdb [4] = 1), the effective bandwidth is reduced to 2.8 mhz, resulting in a softer picture. 4.3. color killer when bit 3 of the cmdb register is set to 1, the chroma data will be removed and the picture will be displayed as black and white. 4.4. vertical blanking normally, line 1 to line 9 in field 1 and the second half of line 263 to 272 in field 2 are blanked automatically. however, if bit 2 of cmdb register is 1, the blanking period is extended to the line specified in the vblk register. k 5 360 -------- - 264 3 == hue mod k 83 264 , () mod 249 264 , () 249 === k 355 360 -------- - 264 260 == hue mod 260 83 264 , () mod 264 81 196 + 264 , () 196 == =
KS0119 data sheet multimedia video electronics page 18 of 50 070595 5. video operational timing the KS0119 can operate in either slave or master mode. in slave mode, the chip uses two external input signals, active video (av) and vertical blank (vblk), to synchronize the internal operation. in master mode, however, the chip outputs these two signals. the chip generates two additional signals: memory transfer request (mrqst) and field two indicator (f2 ), which can be used to simplify the interface to an external frame buffer controller. figure 9 shows the timing waveform for the ntsc output mode. figure 9. ntsc output timing in master mode, the timing shown in figure 10 is maintained among av, vblk, and f2 , where n is the leading pixel number (see figure 12 for more detail). in slave mode, the two inputs av and vblk must meet the timing requirement as shown in figure 11 in order for the encoder to obtain the correct field information. figure 10. master mode av, vblk, and f2 timing figure 11. slave mode av and vblk timing requirement 5251234567891011 2021 263 264 265 266 267 268 269 270 271 272 273 274 283 284 first field second field cvbs vblk av f2 mrqst(blkall=0) mrqst(blkall=1) cvbs vblk av f2 mrqst(blkall=0) mrqst(blkall=1) n av vblk f2 av vblk f2 400 pck(max) 4 pck(min) 4 pck(min)
KS0119 data sheet multimedia video electronics page 19 of 50 070595 5.1. horizontal timing each scan line contains hn pixels as shown in figure 12. of the hn pixels, only (hn - hblk) pixels are displayed. the av signal is used to indicate the active portion of the horizontal scan line. the horizontal blank portion actually consists of three parts: horizontal front porch, horizontal sync, and horizontal back porch. the KS0119 outputs the horizontal sync signal to the display monitor. in master mode, the ntsc encoder generates the av signal. av can be used by the external frame buffer to control the pixel read out. because of the memory access latency associated with the external memory subsystem, av should lead the pixel data by n pixel clocks. this is done by controlling the hav parameter. all horizontal timing parameters are programmable and table 5 contains the information on how to calculate the line timing control register values for both ntsc and rgb displays. figure 12. horizontal timing *: this number is not used to control the horizontal sync tip in ntsc mode. 5.2. vertical timing each field contains the active line and vertical blank portions. the vertical blank portion is further divided into vertical front porch, verical sync, and vertical back porch.there are four parameters that control the vertical timing: vfp, vsyn, vblk, and vn. they are specified in terms of lines. figure 13 shows the timing related to the four parameters. for ntsc output, these parameters are fixed and the power on default values should be used. however, if the blkall bit in the command register is set to 1, the vblk value will be used instead. table 6 provides information on how to program these parameters. table 5: line timing register values register parameter ntsc value rgb value hfp horizontal front porch 11 thfp + 1 hsyn horizontal sync tip 184* thsyn + 1 hblk horizontal blanking 135 thblk - 3 hn number of pixels per line 856 thn - 2 hav end of active video 854 - n thn - 4 - n hfp hsyn hblk n hn hav hn cvbs av
KS0119 data sheet multimedia video electronics page 20 of 50 070595 in master mode, the ntsc encoder outputs the vblk signal. this signal can be used to synchronize the external frame buffer controllers line counter. in slave mode, vblk is an input and is used to synchronize the chips internal operation. figure 13. vertical timing . 5.3. mrqst/mode and f 2 mrqst/mode is output during av low for the active lines. this signal can be used to transfer video data from dram to shift registers in the vram. f2 can be used by the external frame buffer controller for interlaced display. table 6: frame timing register value register parameter value vfp vertical front porch tvfp - 1. vsyn vertical sync tip tvsyn - 1. vblk vertical blanking tvblk - 1. vn number of lines per frame tvn - 1. vertical sync vertical blanking vfp vsyn vblk vn
KS0119 data sheet multimedia video electronics page 21 of 50 070595 6. color palette ram, overlay lookup table, and pixel mask register the KS0119 contains a color palette ram, an overlay lookup table, and a pixel mask register. they can be accessed through the host interface. 6.1. accessing the color palette ram the color palette ram is organized as 3 256x8 arrays. from the programmers point of view, there are 256 entries; each entry has 3 bytes. to write to the color palette ram, the entry offset is written to the color palette write index register, then three bytes, in the order of r, g, and b, are written to the color palette data register. if consecutive entries are to be written, only the first offset address needs to be written to the color palette write index register. it is important to note that writing to the color palette data register should always consist of multiples of three bytes. unpredictable result will occur if this is not strictly followed. reading the color palette ram is similar to writing the color palette ram except the entry offset is written to the color palette read index register. the color palette ram is located at the center of the rgb path. there is no bypass path. consequently, for 24-bit true color inputs even though the translations are not required the color palette ram still needs to be loaded. 6.2. 6-bit color palette mode the KS0119 also supports 6-bit color palette mode. when this mode is selected by setting command register bit 3 to 0, only the 6 lsbs for each color entry are loaded into the corresponding color palette register. internally, the 6 lsbs are shifted to the msb positions with the 2 lsbs padded with 0s. when reading from the palette ram, the two msbs must be ignored. 6.3. high color and pseudo color input lookup address. the high color and pseudo color inputs pass through a formatter, which expands the inputs to a full 24 bits according to table 7. for inputs with r, g, and b components less than 8 bits, the lsbs are padded with 0s. the outputs of the formatter, after passing through the pixel mask filter, become the color palette table addresses. 6.4. overlay lookup table four overlay input bits address the overlay lookup table. if the overlay input is non-zero, overlay data will be displayed. the overlay look up table contains 15 entries, and each entry has three bytes, in the order of r, g, and b. the entry offset starts from 1 instead of 0. the access method for the overlay lookup table is the same as that for the color palette ram. table 7: rgb input formatter conversion table mode video input color lookup table input byte 2byte 1byte 0 1 r<7:0>:g<7:0>:b<7:0> r<7:0> g<7:0> b<7:0> 2 r<4:0>:g<5:0>:b<4:0> r<4:0>000 g<5:0>00 b<4:0>000 3 r<5:0>:g<5:0>:b<3:0> r<5:0>00 g<5:0>00 b<3:0>0000 4 r<4:0>:g<4:0>:b<4:0> r<4:0>000 g<4:0>000 b<4:0>000 5 and 6 p<7:0> p<7:0> p<7:0> p<7:0>
KS0119 data sheet multimedia video electronics page 22 of 50 070595 6.5. pixel mask register the pixel mask register is used to filter the pixel data coming out from the rgb input formatter. each r, g, b pixel byte is bit-wise anded with the pixel mask register. special effects can be created by selectively masking out certain bits. this register needs to be initialized after power up.
KS0119 data sheet multimedia video electronics page 23 of 50 070595 7. dac and external reconstruction filter the three dacs on the chip are identical; they are video grade 10 bit current dacs. figure 14 shows a typical configuration for the dac portion of the chip. r ref is connected to iref to adjust the dac output full scale. the dac output is designed to drive a doubly terminated 75 w load. a 105 w resistor connected to r ref can be used to set the output voltage peak to the rs-170a standard of 1 v. the built-in voltage reference has a large variation due to manufacturing technology limitations. for precise control of the dac, an external voltage reference can be used. a variable resistor may also be used for r ref to adjust the full scale dac output current. the recommended analog filter circuit and its characteristic are shown in figure 15 and figure 16, respectively. figure 14. dac reference circuit and termination figure 15. dac output analog reconstruction filter figure 16. dac output analog reconstruction filter response dac + - 1.2v c comp c vref analog power plane analog ground plane aky vref iref gin g/y r ref KS0119 to 75 w display 1.235v r bias only one dac output is shown with the optional 1.235v external voltage reference and r bias lpf 75 w 100pf 2.0 m h 1.3 m h 300pf 100pf frequency (mhz) attenuation (db)
KS0119 data sheet multimedia video electronics page 24 of 50 070595 8. host interface the KS0119 contains a conventional parallel microprocessor interface and a proprietary serial interface. the parallel microprocessor interface consists of 11 pins, some of which are shared by the three pin serial bus. the logic sense of the p/s control pin defines the host interface mode, parallel or serial. three of the interface pins serve a dual purpose depending upon the mode selected. the cs , r/w , and d7 pins in parallel mode become sfrs, sclk, and sdat pins in serial mode, respectively. 8.1. microprocessor address map the KS0119 contains three groups of registers. the first group is the control registers. the control registers are used for feature/option selection. the second group is the color palette ram. the third group is the overlay color look up table. table 8 shows the microprocessor address map for the KS0119. 8.2. transfer mode both the read and write cycles require that the index be written to the KS0119 first. the index is written to location addr = 08. the index is the internal address location for each register. the internal address is indicated by the register number associated with each register. once the index is written, the selected register can have data read from or written to location addr = 09. non-sequential internal registers are accessed individually by writing an index and then reading or writing one byte of data. sequential locations can be accessed by writing the index for the first register and then reading or writing multiple bytes of data. the index auto-increments internally by one for each successive byte of data accessed while adde = 09. this mode is useful when initializing the device or when accessing word wide or blocks of registers. the color palette and overlay clut operate in a similar fashion, except that separate index locations exist for read and write operations. the color palette write index is written to addr=00, and palette data is written to addr=01. for read operation, the index is written to addr=03. the color palette and overlay exhibit the same auto-increment capability as the control registers. this simplifies loading the color palette. 8.3. serial host interface the serial interface is selected by connecting the p/s pin to ground. this interface uses three signals: sfrs, sdat, table 8: microprocessor address map address (hex) description 00 color palette write index 01 color palette data 02 pixel mask register 03 color palette read index 04 overlay clut write index 05 overlay clut data 06 reserved 07 overlay clut read index 08 control register index 09 control register data
KS0119 data sheet multimedia video electronics page 25 of 50 070595 and sclk. the sfrs indicates a valid data transfer. serial data is carried through the sdat and clocked in or out with the sclk. the data protocol sends each byte as msb first. 8.3.1. serial host write/read to KS0119 each data transfer cycle is called a frame. a valid frame is indicated by a high on the sfrs signal. a frame consists at least three bytes: the first byte contains a 7-bit slave device id and a r/w bit (bit assignment shown in figure 17); the second byte indicates the internal address of register the data transfer is intended for (see table 8); and the third and consequent byte(s) are the data to be transferred to/from the register. if the data transfer is to/ from the index register, three bytes are needed each frame. since the KS0119 features an auto index increment function, consecutive data transfer to/from the data registers can be completed within the same frame. figure 17. KS0119 device id and r/w figure 18 shows an example of a write to the index register. each bit is latched into the device by the rising edge of the sclk. a write to the data register is similar to a write to the index register except the second byte is 01h and the third and so on byte(s) are the data to be written (figure 19). when the data is read from the device, the KS0119 outputs each bit is after the falling edge of the sclk. figure 18. serial host write to index register figure 19. serial host write to data register r/w 0000011 msb lsb slave device id sfrs sclk sdat 0 device id 08h index sfrs sclk sdat 0 device id 09h data data
KS0119 data sheet multimedia video electronics page 26 of 50 070595 8.4. parallel host interface figure 20 shows the timing relation for a parallel read cycle. figure 21 shows the timing for a parallel write cycle. the address addr and read/write r/w are stable before the cs signal is lowered. data written to the KS0119 must be stable before cs goes high. data is read from the KS0119 when cs is low. figure 20. parallel host interface read cycle figure 21. parallel host interface write cycle cs r/w addr d[0:7] index data 1 data 2 w rr cs r/w addr d[0:7] index data 1 data 2 w w w
KS0119 data sheet multimedia video electronics page 27 of 50 070595 9. detailed control register description this section contains the detailed description of the control registers. the control registers can be categorized into three functional groups: indexes 60h to 63h are general control registers; indexes 64h to 6dh are mixing control registers; indexes 70h to 79h are crt control registers. table 9 is a register summary, followed by the individual register description. default values are noted with an asterisk (*) after the value description. table 9: control registers index mnemonic default description 60h cmd 12h/a2h command register 61h fmt 90h/60h input format 62h cmdb 02h second command register 63h hue 00h chroma phase offset bits 7..0 64h mxctr 00h mixing control 65h whs 00h window row start address 66h whe 00h window row end address 67h wvs 00h window column start address 68h wve 00h window column end address 69h whv 00h window overflow address(lsbs) 6ah tmpla 00h chroma key tmplate byte 0 6bh tmplb 00h chroma key tmplate byte 1 6ch mska 00h chroma key mask byte 0 6dh mskb 00h chroma key mask byte 1 70h havn 33h/b3h hn and hav overflow bits 71h hav 54h master modes avout lead control 72h hn 58h number of pixels per line 73h hfp 0bh horizontal front porch 74h hsyn b8h end of horizontal sync 75h hblk 87h end of horizontal blanking 76h vn 00h number of lines per field 77h vfp 83h vertical front porch 78h vsyn 06h end of vertical sync 79h vblk 14h end of vertical blanking note : some registers have two default values. the first number is for mrqst/moed pin pulled low. the second number is for mrqst/mode pin pulled high.
KS0119 data sheet multimedia video electronics page 28 of 50 070595 command register index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 60h cmd run mstr rgb cksl 8/6* dkf cvbs yc run software run control. the internal state machine is controlled by the logically ored software and hardware run inputs. 1 software run enable. 0 software run disable. the logic state of the mrqst/mode is latched into this bit during power-on. mstr timing generation master/slave mode select. 1master. 0slave.* rgb analog output format select. 1rgb. 0 composite and super video. the logic state of the mrqst/mode is latched into this bit during power-on. cksl clock input and output control. 1 ck27 is selected, and pixel clock ckps rate is f(ck27) / 2. 0 ckv is selected as the source, and ckp has the same rate as the clock input. the inverted logic state of the mrqst/mode is latched into this bit during power-on. 8/6* 8/6 bit palette select. 1 8 bit palette. 0 6 bit palette.* dkf dky/r pin configuration control. 1 dky/r is input key for digital mixing. 0 dky/r is hardware run input.* cvbs if bit 5 of this register is 0 this bit controls r/cvbs dac. 1 r/cvbs dac is on.* 0 r/cvbs dac is in the power down state. yc if bit 5 of this register is 0 this bit controls g/y and b/c dacs. 1 g/y and b/c dacs are on. 0 g/y and b/c dacs are in power down state.*
KS0119 data sheet multimedia video electronics page 29 of 50 070595 input format register index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 61h fmt fmta3 fmta2 fmta1 fmta0 fmtb3 fmtb2 fmtb1 fmtb0 fmta channel a input format. see table 3 for supported format on channel a. the power-on default is 6 if there is an external pull-up resistor on the mrqst/mode pin, or 9 otherwise. fmtb channel b input format. see table 4 for supported format on channel b. command register b index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 62h cmdb hue8 vsp hsp ctrap mono blkall slt1 slt0 vsp vertical sync input (vblk) polarity control. 1 vertical sync input is active low. 0 vertical sync input is active high.* hsp horizontal sync input (av) polarity control. 1 horizontal sync input is active high. 0 horizontal sync input is active low.* ctrap chroma trap filter control. when enabled, the high frequency luminance signals near the color subcarrier are filtered out. this function is available for ntsc output only. 1 enables filtering. 0 disables filtering.* mono color killer control. when enabled, the chrominance signal is suppressed. this function is available for ntsc output only. 1 color killer enable. 0 color killer disable.* blkall when set, the output from line 1 to the line set by the vblk register is blanked. slt[1:0] these two bits control the assertion of the mrqst signal. 00 mrqst is asserted for the active lines whose line numbers are greater than or equal to the value contained in the vblk register. 01 mrqst is always asserted. 10 mrqst is not asserted during the vertical blanking period.* 11 reserved. do not use.
KS0119 data sheet multimedia video electronics page 30 of 50 070595 this register controls the digital mixing function. please see the digital mixing section for additional information. hue control register index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 62h cmdb hue8 vsp hsp ctrap mono blkall slt1 slt0 63h hue hue7 hue6 hue5 hue4 hue3 hue2 hue1 hue0 hue[8:0] hue control. to have a phase shift of k divisions, the 9 bit register should be loaded with the value <83*k> mod 264. each division is equal to 360/264 degrees. hue can be adjusted only for ntsc output mode. mixing control register index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 64h mxctr mxen cmen amen wmen outsd k2 k1 k0 mxen master mixing control. 1 mixing is allowed. 0 no mixing is allowed.* cmen index or chroma mixing control. 1 index or chroma mixing enable. 0 index or chroma mixing disable.* amen alpha mixing control. 1 alpha mixing enable. 0 alpha mixing disable.* wmen window mixing control. 1 window mixing enable. 0 window mixing disable.* outsd channel b inside/outside mixing window control. 1 channel b is outside the mixing window. 0 channel b is inside the mixing window.* k[2:0] during linear blend mixing, these bits set the luminance attenuation factors for channel a and channel b. for channel a, the attenuation factor is k/8, and for channel b, the attenuation factor is 1-k/8, where k = k[2:0].
KS0119 data sheet multimedia video electronics page 31 of 50 070595 window horizontal start address index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 65h whs whs9 whs8 whs7 whs6 whs5 whs4 whs3 whs2 69h whv whs1 whs0 whe1 whe0 wvs1 wvs0 wve1 wve0 whs[9:0] this 10-bit register contains the horizontal pixel start location for the mixing window. window horizontal end address index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 66h whe whe9 whe8 whe7 whe6 whe5 whe4 whe3 whe2 69h whv whs1 whs0 whe1 whe0 wvs1 wvs0 wve1 wve0 whe[9:0] this 10-bit register contains the horizontal pixel end location for the mixing window. window vertical start address index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 67h wvs wvs9 wvs8 wvs7 wvs6 wvs5 wvs4 wvs3 wvs2 69h whv whs1 whs0 whe1 whe0 wvs1 wvs0 wve1 wve0 wvs[9:0] this 10-bit register contains the vertical line start number for the mixing window.
KS0119 data sheet multimedia video electronics page 32 of 50 070595 window vertical end address index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 68h wve wve9 wve8 wve7 wve6 wve5 wve4 wve3 wve2 69h whv whs1 whs0 whe1 whe0 wvs1 wvs0 wve1 wve0 wve[9:0] this 10-bit register contains the vertical line end number for the mixing window. chroma key template byte 0 (a) index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6ah tmpla tmpla 7 tmpla 6 tmpla 5 tmpla 4 tmpla 3 tmpla 2 tmpla 1 tmpla 0 tmpla[7:0] for rgb index keying, this register is the lower byte of the template register. for cbcr chroma keying, this register contains the lower limit of the cb key. see the section digital mixing for a more detailed description of this register. chroma key template byte 1 (b) index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6bh tmplb tmplb 7 tmplb 6 tmplb 5 tmplb 4 tmplb 3 tmplb 2 tmplb 1 tmplb 0 tmplb[7:0] for rgb index keying, this register is the higher byte of the template register. for cbcr chroma keying, this register contains the upper limit of the cb key. see the section digital mixing for a more detailed description of this register.
KS0119 data sheet multimedia video electronics page 33 of 50 070595 chroma key mask byte 0 (a) index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6ch mska mska7 mska6 mska5 mska4 mska3 mska2 mska1 mska0 mska[7:0] for rgb index keying, this is the lower byte of the mask register. for cbcr chroma keying, this register contains the lower limit of the cr key. see the section digital mixing for more detail. chroma key mask byte 1 (b) index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6dh mskb mskb7 mskb6 mskb5 mskb4 mskb3 mskb2 mskb1 mskb0 mskb[7:0] for rgb index keying, this is the upper byte of the mask register. for cbcr keying, this register sets the upper limit of the cr key. see the section digital mixing for more detail. master modes avout lead control index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 70h havn syncpt hn10 hn9 hn8 0 hav10 hav9 hav8 71h hav hav7 hav6 hav5 hav4 hav3 hav2 hav1 hav0 syncpt sync pass through. 1 hsyn and vsyn are the delayed outputs of av and vblk, respectively. 0 hsyn and vsyn are internally generated. the logic state of the mrqst/mode is latched into this bit during power-on. hav[10:0] in master mode, this 11-bit register defines the avout lead control timing. in slave mode, this register has no effect. see the section horizontal timing for detail.
KS0119 data sheet multimedia video electronics page 34 of 50 070595 number of pixels per line index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 70h havn syncpt hn10 hn9 hn8 0 hav10 hav9 hav8 72h hn hn7 hn6 hn5 hn4 hn3 hn2 hn1 hn0 hn[10:0] this 11-bit register controls the total number of pixels per line, which is equal to hn[10:0]+2. horizontal front porch index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 73h hfp hfp7 hfp6 hfp5 hfpb4 hfp3 hfp2 hfp1 hfp0 hfp[7:0] this register controls the horizontal front porch timing in number of pixels, which is equal to hfp[7:0]-1. horizontal sync end index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 74h hsyn hsyn7 hsyn6 hsyn5 hsyn4 hsyn3 hsyn2 hsyn1 hsyn0 hsyn[7:0] this register controls the horizontal sync end timing in number of pixels, which is equal to hsyn[7:0]-1. horizontal blanking end index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 75h hblk hblk7 hblk6 hblk5 hblk4 hblk3 hblk2 hblk1 hblk0 hblk[7:0] this register controls the horizontal blanking end timing in number of pixels, which is equal to hblk[7:0]+3.
KS0119 data sheet multimedia video electronics page 35 of 50 070595 number of lines per field index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 76h vn vn7 vn6vn5vn4vn3vn2vn1vn0 77h vfp vn9 vn8 vfp5 vfp4 vfp3 vfp2 vfp1 vfp0 vn[9:0] this 10-bit register controls the total number of lines per field, which is equal to vn[9:0]+1. vertical front porch index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 77h vfp vn9 vn8 vfp5 vfp4 vfp3 vfp2 vfp1 vfp0 vfp[5:0] this 6-bit register controls the vertical front porch in number of lines, which is equal to vfp[5:0]+1. vertical sync end index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 78h vsyn vsyn7 vsyn6 vsyn5 vsyn4 vsyn3 vsyn2 vsyn1 vsyn0 vsyn[7:0] this register controls the end of vertical sync in number of lines, which is equal to vsyn[7:0]+1. vertical blanking end index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 79h vblk vblk7 vblk6 vblk5 vblk4 vblk3 vblk2 vblk1 vblk0 vblk[7:0] this register has three functions: 1. it controls the vertical blank timing for vga monitors, and for ntsc monitors if the blkall bit is set in the command register. 2. it defines line zero of the active display. 3. in conjunction with slt[1:0] it controls for which lines the mrqst signal will be asserted for ntsc monitors.
KS0119 data sheet multimedia video electronics page 36 of 50 070595 absolute maximum ratings notes: 1. absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. functional operation under any of these conditions is not implied. 3. applied voltage must be current limited to a specified range. recommended operating conditions characteristics symbol value unit supply voltage (measured to gnd) v dd -0.5 to +7.0 v digital input voltage v i 0.5 to (v dd +0.5) v ambient operating temperature range ta -10 to +100 c storage temperature range tstg -60 to +150 c junction temperature tj 150 c soldering temperature (5 sec., 1/4 from pin) tsol 300 c vapor phase soldering (1 min.) tvsol 220 c characteristics symbol min typ max unit supply voltage v dd 4.7555.25v reference voltage internal external vref 1.235 1.235 v reference current iref 11.56 ma analog output load r l 37.5 w ambient operating temperature range ta 0 70 c
KS0119 data sheet multimedia video electronics page 37 of 50 070595 dc electrical characteristics characteristics symbol min typ max unit digital input high voltage v ih 2.0 v dd +0.5 v digital input low voltage v il gnd-0.5 0.8 v digital input high current(v in =2.4v) i ih 1 m a digital input low current(v in =0.4v) i il -1 m a digital input capacitance(f=1mhz,v in =2.4v) c in 7pf digital output high voltage(i oh =-400 m a) v oh 2.4 v digital output low voltage(i ol =3.2ma) v ol 0.4 v digital three-state current i oz 50 m a digital output capacitance cd out 7pf supply current i cc 150 ma analog multiplexer on resistance ra on 10 w analog multiplexer off resistance ra off 10 k w
KS0119 data sheet multimedia video electronics page 38 of 50 070595 ac electrical characteristics characteristics symbol min typ max unit cs or sclk low t pwlc 50 ns cs or sclk high t pwhc 4ck27/ckv r/w setup time t sr/w 10 ns r/w hold time t hr/w 10 ns a[0:3] setup time t sa 10 ns a[0:3] hold time t ha 10 ns cs or sclk active to data valid t validd 40 ns cs or sclk inactive to data 3-state t 3-stated 20 ns data setup time t sd 10 ns data hold time t hd 10 ns sfrs setup time t sfrm 10 ns sfrs hold time t hfrm 10 ns setup time (p[0:31], dky/r, av, vblk) t spix -9 ns hold time (p[0:31], dky/r, av, vblk) t hpix 18.5 ns ckp to output delay t dpix 9ns video pipeline delay (ntsc output) t dntsc 53 54 ck27 video pipeline delay (rgb output) t drgb 23 ckv ck27 clock rate f ck27 26.9999 27 27.0001 mhz ckv clock rate f ckv note1 mhz ck27, ckv to ckp delay t dckp 7 9 12.5 ns 32 for KS0119, 45 for KS0119q2.
KS0119 data sheet multimedia video electronics page 39 of 50 070595 parallel host interface timing figure 22. parallel host interface write cycle figure 23. parallel host interface read cycle figure 24. serial host interface detailed timing t pwlc t pwhc t sr/w t hr/w t sa t ha t sd t hd cs r/w a[0:3] d[0:7] i n d e x data 1 data 2 t pwlc t pwhc t sr/w t hr/w t sa t ha t sd t hd cs r/w a[0:3] d[0:7] index data 1 data 2 t validd t 3-stated t pwlc t pwh c t sfrm t sd t hd sclk sfrs sdat data write (to slave) data read (to slave) t validd t 3-stated t hfrm
KS0119 data sheet multimedia video electronics page 40 of 50 070595 figure 25. pixel data setup and hold time figure 26. ckp to output delay ckp pd[0:31] dky/r av vblk t spix t hpix ckv t dckp ckp av vblk mrqst f2 t dpix
KS0119 data sheet multimedia video electronics page 41 of 50 070595 test conditions: in ntsc operation, with dac output = 1.0 v p-p , v ref = 1.235 v, r ref = 105 w, 75 w load . dac dc characteristics characteristics symbol min typ max unit resolution rgb output 8 bits ntsc or y/c output 10 bits integral non-linearity error il 0.15% differential non-linearity error dl 0.1% gray scale error 0 5% monotonicity guaranteed coding binary analog outputs (ntsc) full scale current range 25.3 26.67 28 ma output current white level relative to black 16.74 17.62 18.5 ma black level relative to blank 1.44 ma blank level relative to sync 7.62 ma lsb size 26.1 m a dac to dac matching 2% 5% output compliance v oc -0.3 1.5 v output impedance ra out 10 k w output capacitance (f=1mhz, i out =0ma) ca out 15 30 pf internal reference voltage v ref 1.17 1.235 1.296 v voltage reference input current iv ref 10 m a dac reference current i ref 11.14 11.56 12.34 ma dac reference resistor (v ref =typ) r ref 105 w power supply rejection ratio (c comp =0.1 m f, f=1 khz) psrr 0.5 %/d v dd
KS0119 data sheet multimedia video electronics page 42 of 50 070595 dac ac characteristics characteristics symbol min typ max unit differential gain dg 0.5% 1.5% differential phase dp 0.5 1 degree signal to noise ratio snr 48 60 db analog output delay t d 30 ns analog output rise/fall time t r /t f 3ns analog settling time t set 20 ns clock and data feedthrough fdthr -30 db glitch impulse gi 75 pv-sec analog output skew t skw 05ns
KS0119 data sheet multimedia video electronics page 43 of 50 070595 ntsc dac output waveforms figure 27. composite ntsc video output waveform figure 28. ntsc y (luminance) video output waveform note: 37.5 w load, vref=1.235 v, and r ref =105 w. rs-170a levels and tolerances are assumed. black level (16) blank level white level (235) ma code 34 ire 100 ire 20 ire 7.5 ire 20 ire 40 ire 3.58 mhz color burst (9 cycles) white yellow cyan green magenta red blue balck 27.3 1024 22.27 835 9.92 372 7.68 288 6.64 249 3.36 126 0.29 11 note: 37.5 w load, vref=1.235 v, and r ref =105 w. rs-170a levels and tolerances are assumed. black level blank level white level ma code white yellow cyan green magneta red blue black 100 ire 7.5 ire 40 ire 22.27 835 7.68 288 6.64 249 0.29 11
KS0119 data sheet multimedia video electronics page 44 of 50 070595 figure 29. ntsc c (chrominance) video output waveform ma code note: 37.5 w load, vref=1.235 v, and r ref =105 w. rs-170a levels and tolerances are assumed. black level white yellow cyan green magenta red blue balck 20 ire 20 ire 3.58 mhz color burst (9 cycles) 9.49 356 7.68 288 5.87 220
KS0119 data sheet multimedia video electronics page 45 of 50 070595 figure 30. load circuit for timing measurements. digital outputs figure 31. esd protection vdd 2k 30pf (60pf for fsmp) equivalent input circuit equivalent output circuit
KS0119 data sheet multimedia video electronics page 46 of 50 070595 package dimension ( dimensions are in millimeters ) 20.000.20 23.900.30 0.800.2 0.80 0.350.10 0.800.20 1.00 14.000.20 17.900.30 3.00max 0.10max 2.650.10 0.15 +0.10 -0.05 #1 #80 80-qfp-1420c
KS0119 data sheet multimedia video electronics page 47 of 50 070595 package dimension (continued) 100-qpf-1420c (0.58) 0.30 0.10 0.65 #1 #100 (0.83) 20.00 0.20 23.90 0.30 17.90 0.30 14.00 0.20 0.10max 0.80 0.20 2.65 0.10 3.00max 0.00min 0.10max 0 . 1 5 + 0 . 1 0 - 0 . 0 5 0 ~ 8

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