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enhanced memory systems inc. dm512k32st6/dm512k36st6 multibank edo 512kb x 32/512kb x 36 edram simm product specification ?1996 enhanced memory sytems inc , 1850 ramtron drive, colorado springs, co 80921 telephone (800) 545-dram; fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2117-000 the information contained herein is subject to change without notice. enhanced reserves the right to change or discontinue this product without notice. features n 4kbyte sram cache memory for 12ns random reads within four actives pages (multibank cache) n fast dram array for 30ns access to any new page n write posting register for 12ns random writes and burst writes within a page (hit or miss) n 1kbyte wide dram to sram bus for 56.8 gigabytes/sec cache fill n on-chip cache hit/miss comparators maintain cache coherency on writes n edo mode for 83 mhz non-interleave burst rate n hidden precharge and refresh cycles n extended 64ms refresh period for low standby power n standard cmos/ttl compatible i/o levels and +5 volt supply n compatibility with jedec 512k x 32/36 dram simm configuration allows performance upgrade in system n industrial temperature range option description the enhanced memory systems 2mb edram simm module provides a single memory module solution for the main memory or local memory of fast embedded control, dsp, and other high performance systems. due to its fast 12ns cache row register, the edram memory module supports zero-wait-state burst read operations at up to 83mhz bus rates in a non-interleave configuration and >100mhz bus rates with a two-way interleave configuration. on-chip write posting and fast page mode operation supports 12ns write and burst write operations. on a cache miss, the fast dram array reloads the entire 1kbyte cache over a 1kbyte-wide bus in 18ns for an effective bandwidth of 56.8 gbytes/sec. this means very low latency and fewer wait states on a cache miss than a non- integrated cache/dram solution. the jedec compatible 72-bit simm configuration allows a single memory controller to be designed to support either jedec slow drams or high speed edrams to provide a simple upgrade path to higher system performance. architecture the dm512k36st6 achieves 512k x 36 density by mounting five 512k x 8 edrams, packaged in 44-pin plastic tsop-ii packages, on a multi-layer substrate. four 2203 devices and one dm2213 device provide data and parity storage. the dm512k32 contains four 2203 devices for data only. the edram memory module architecture is very similar to a standard 2mb dram module with the addition of an integrated cache and on-chip control which allows it to operate much like a page mode or static column dram. the edrams sram cache is integrated into the dram array as tightly coupled row registers. the 512k x 32/36 edram simm has a total of four independent dram memory banks each with its own 256 x 32/36 sram row register. memory reads always occur from the cache row register of one of these banks as specified by row address bits a 8 and a 9 (bank select). when the internal comparator detects that the row address matches the last row read from any of the four dram banks (page hit), the sram is accessed and data is available on the output pins in 12ns from column address input. subsequent reads within the page (burst reads or random reads) can continue at 12ns cycle time. when the row address does not match the last row read from any of the four dram banks (page miss), the new dram row is accessed and loaded into the appropriate sram row register and data is available on the output pins all within 30ns from row enable. subsequent reads within the page (burst reads or random reads) can continue at 12ns cycle time. during either read hit or read miss operations, the edo option extends data output time to allow use of the full 83mbyte/second bandwidth. since reads occur from the sram cache, the dram precharge can occur during burst reads. this eliminates the precharge time delay suffered by other drams and sdrams when accessing a new page. the edram has an independent on-chip refresh counter and dedicated refresh control pin to allow the dram array to be refreshed concurrently with cache read operations (hidden refresh). /cal a 0 - a 10 w/r /f /re v v sense amps & column write select column decoder row address latch cc ss a 0 - a 9 4 - 256 x 36 cache pages (row registers) memory array 2mbyte + parity a 0 0-3, p 0, 2 - a 7 /g /s /we dq 0-35 column address latch 4 - 9 bit comparators i/o control and data latches refresh counter row decoder row adress and refresh control 4 - last row read address latches c 1-5 functional diagram
during edram read accesses, data is accessed in edo mode. the column address is latched on the falling edge of /cal while the output data latch is transparent. on the rising edge of /cal the output data is latched while the column address latch is transparent. the edo mode allows the output data valid time to be extended so that the next column address can be latched sooner . a dedicated output enable (/g) with 5ns access time allows high speed two-way interleave without an external multiplexer . memory writes are posted to the input data latch and directed to the dram array . during a write hit, the on-chip address comparator activates a parallel write path to the sram cache to maintain coherency . random or page mode writes can be posted 5ns after column address and data are available. the edram allows 12ns page mode cycle time for both write hits and write misses. memory writes do not affect the contents of the cache row register except during a cache hit. since the dram array can be written to at sram speeds, there is no need for complex writeback schemes. by integrating the sram cache as row registers in the dram array and keeping the on-chip control simple, the edram is able to provide superior performance over standard slow 4mb drams. by eliminating the need for srams and cache controllers, system cost, board space, and power can all be reduced. functional description the edram is designed to provide optimum memory performance with high speed microprocessors. as a result, it is possible to perform simultaneous operations to the dram and sram cache sections of the edram. this feature allows the edram to hide precharge and refresh operation during reads and maximize hit rate by maintaining page cache contents during write operations even if data is written to another memory page. these capabilities, in conjunction with the faster basic dram and cache speeds of the edram, minimize processor wait states. edram basic operating modes the edram operating modes are specified in the table. hit and miss t er minology in this datasheet, ?it?and ?iss?always refer to a hit or miss to any of the four pages of data contained in the sram cache row registers. there are four cache row registers, one for each of the four banks of dram. these registers are specified by the bank select row address bits a 8 and a 9 . the contents of these cache row registers is always equal to the last row that was read from each of the four internal dram banks (as modified by any write hit data). dram read hit a dram read request is initiated by clocking /re with w/r low and /f high. the edram will compare the new row address to the last row read address latch for the bank specified by row address bits a 8-9 (lrr: a 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address matches the lrr, the requested data is already in the sram cache and no dram memory reference is initiated. the data specified by the row and column address is available at the output 2 -58 bank 3 bank 2 bank 1 cal row address latch column address latch last row read address latch + 9-bit compare bank 0 1 of 4 selector (0,0) (0,1) (1,0) (1,1) d 0-35 bank 0 bank 1 bank 2 bank 3 ca 0-7 ca 0-7 0-3, p ra 8 , ra 9 a 0-10 ra 0-10 data-out latch g s q 0-35 512k byte array 512k byte array 512k byte array 512k byte array 256 x 36 cache 256 x 36 cache 256 x 36 cache 256 x 36 cache data-in latch four bank cache ar chitectur e
2-59 pins at the greater of times t rac1 , t ac , t gqv , and t asc + t cl v . since no dram activity is initiated, /re can be brought high after time t re1 , and a shorter precharge time, t rp1 , is required. additional locations within the currently active page may be accessed concurrently with precharge by providing new column addresses to the multiplex address inputs. dram read miss a dram read request is initiated by clocking /re with w/r low and /f high. the edram will compare the new row address to the lrr address latch for the bank specified by row address bits a 8-9 (lrr: a 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address does not match the lrr, the requested data is not in sram cache and a new row is fetched from the dram. the edram will load the new row data into the sram cache and update the lrr latch. the data at the specified column address is available at the output pins at the greater of times t rac1 , t ac , t gqv , and t asc + t cl v . /re may be brought high after time t re since the new row data is safely latched into sram cache. this allows the edram to precharge the dram array while data is accessed from sram cache. additional locations within the currently active page may be accessed by providing new column addresses to the multiplex address inputs. dram w rite hit a dram write request is initiated by clocking /re while w/r, /we, and /f are high. the edram will compare the new row address to the lrr address latch for the bank specified by row address bits a 8-9 (lrr: a 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address matches the lrr, the edram will write data to both the dram page in the appropriate bank and its corresponding sram cache simultaneously to maintain coherency . the write address and data are posted to the dram as soon as the column address is latched by bringing /cal low and the write data is latched by bringing /we low (both /cal and /we must be high when initiating the write cycle with the falling edge of /re). the write address and data can be latched very quickly after the fall of /re (t rah + t asc for the column address and t ds for the data). during a write burst sequence, the second write data can be posted at time t rsw after /re. subsequent writes within a page can occur with write cycle time t pc . with /g enabled and /we disabled, read operations may be performed while /re is activated in write hit mode. this allows read-modify-write, write-verify , or random read- write sequences within the page with 12ns cycle times. at the end of any write sequence (after /cal and /we are brought high and t re is satisfied), /re can be brought high to precharge the memory . cache reads can be performed concurrently with precharge (see ?re inactive operation?. when /re is inactive, the cache reads will occur from the page accessed during the last /re active read cycle. during write sequences, a write operation is not performed unless both /cal and /we are low . as a result, the /cal input can be used as a byte write select in multi-chip systems. dram w rite miss a dram write request is initiated by clocking /re while w/r, /we, and /f are high. the edram will compare the new row address to the lrr address latch for the bank specified for row address bits a 8-9 (lrr: a 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address does not match any of the lrrs, the edram will write data to the dram page in the appropriate bank and the contents of the current cache is not modified. the write address and data are posted to the dram as soon as the column address is latched by bringing /cal low and the write data is latched by bringing /we low (both /cal and /we must be high when initiating the write cycle with the falling edge of /re). the write address and data can be latched very quickly after the fall of /re (t rah + t asc for the column address and t ds for the data). during a write burst sequence, the second write data can be posted at time t rsw after /re. subsequent writes within a page can occur with write cycle time t pc . during a write miss sequence cache reads are inhibited and the output buffers are disabled (independently of /g) until time t wrr after /re goes high. at the end of a write sequence (after /cal and /we are brought high and t re is satisfied), /re can be brought high to precharge the memory . cache reads can be performed concurrently with the precharge (see ?re inactive operation?. when /re is inactive, the cache reads will occur from the page accessed during the last /re active read cycle. during write sequences, a write operation is not performed unless both /cal and /we are low . as a result, /cal can be used as a byte write select in multi-chip systems. /re inactive operation data may be read from the sram cache without clocking /re. this capability allows the edram to perform cache read operations during precharge and refresh cycles to minimize wait states. it is only necessary to select /s and /g and provide the appropriate column address to read data. in this mode of operation, the cache reads will occur from the page accessed function /s low power standby h /re w/r /f a 0-10 comment h x x x unallowed mode h l x h x internal refresh x x l x cache reads enabled read miss l l h row 1 lrr dram row to cache standby current write hit l h h row = lrr write to dram and cache, reads enabled write miss l h h row 1 lrr write to dram, cache not updated, reads disabled read hit l l h row = lrr no dram reference, data in cache h = high; l = low; x = don? care; = high-to-low transition; lrr = last row read edram basic operating modes
2-60 during the last /re active read cycle. /cal is clocked to latch the column address and data. this option is desirable when the external control logic is capable of fast hit/miss comparison. in this case, the controller can avoid the time required to perform row/column multiplexing on hit cycles. edo mode operation the edram simm has an on-board data latch to latch output data from the sram cache while a new cache address is being specified. edo mode pipelines the fetching of new data from the cache with the transfer of the previous data to the bus. edo allows non-interleave data transfers at up to a 83 mhz data rate. in this mode, static column and page mode read operations are not supported. all read operations require /cal to be clocked to latch the input address and enable the output data to propagate through the output latch to the output pins. w rite-per -bit operation the dm512k36st6 simm provides a write-per -bit capability to selectively modify individual parity bits (dq 8, 17, 26, 35 ) for byte write operations. the parity device (dm2213) is selected via /cal p . byte write selection to non-parity bits is accomplished via cal 0-3 . the bits to be written are determined by a bit mask data word which is placed on the parity i/o data pins prior to clocking /re. the logic one bits in the mask data select the bits to be written. as soon as the mask is latched by /re, the mask data is removed and write data can be placed on the databus. the mask is only specified on the /re transition. during page mode write operations, the same mask is used for all write operations. inter nal refr esh if /f is active (low) on the assertion of /re, an internal refresh cycle is executed. this cycle refreshes the row address supplied by an internal refresh counter . this counter is incremented at the end of the cycle in preparation for the next /f refresh cycle. at least 1,024 /f cycles must be executed every 64ms. /f refresh cycles can be hidden because cache memory can be read under column address control throughout the entire /f cycle. /f cycles are the only active cycles where /s can be disabled. /re only refr esh operation although /f refresh using the internal refresh counter is the recommended method of edram refresh, it is possible to perform an /re only refresh using an externally supplied row address. /re refresh is performed by executing a write cycle (w/r and /f are high) where /cal is not clocked. this is necessary so that the current cache contents and lrr are not modified by the refresh operation. all combinations of addresses a 0-9 must be sequenced every 64ms refresh period. a 10 does not need to be cycled. read refresh cycles are not allowed because a dram refresh cycle does not occur when a read refresh address matches the lrr address latch. low power mode the edram enters its low power mode when /s is high. in this mode, the internal dram circuitry is powered down to reduce standby current. initialization cycles a minimum of eight /re active initialization cycles (read, write, or refresh) are required before normal operation is guaranteed. following these start-up cycles, two read cycles to different row addresses must be performed for each of the four internal banks of dram to initialize the internal cache logic. row address bits a 8 and a 9 define the four internal dram banks. unallowed mode read, write, or /re only refresh operations must not be initiated to unselected memory banks by clocking /re when /s is high. reduced pin count operation it is possible to simplify the interface to the 2mbyte simm to reduce the number of control lines. /re 0 and /re 2 could be tied together externally to provide a single row enable. w/r and /g can be tied together if reads are not performed during write hit cycles. this external wiring simplifies the interface without any performance impact. pin descriptions /re 0,2 ?row enable these inputs are used to initiate dram read and write operations and latch a row address and the states of w/r and /f . it is not necessary to clock /re to read data from the edram sram row registers. on read operations, /re can be brought high as soon as data is loaded into cache to allow early precharge. /cal 0-3, p ?column addr ess latch these inputs are used to latch the column address and in combination with /we to trigger write operations. when /cal is high, the column address latch is transparent. when /cal is low , the column address is closed and the output of the latch contains the address present while /cal was high. /cal can be toggled when /re is low or high. however , /cal must be high during the high-to-low transition of /re except for /f refresh cycles. the output data is latched when /cal is high. w/r ?w rite/read this input along with /f specifies the type of dram operation initiated on the low going edge of /re. when /f is high, w/r specifies either a write (logic high) or read operation (logic low). /f ?refr esh this input will initiate a dram refresh operation using the internal refresh counter as an address source when /f is low on the low going edge of /re. /we ?w rite enable this input controls the latching of write data on the input data pins. a write operation is initiated when both /cal and /we are low . /g ?output enable this input controls the gating of read data to the output data pins during read operations. /s ?chip select this input is used to power up the i/o and clock circuitry . when /s is high, the edram remains in its low power mode. /s
2-61 dm2213t 512k x 8 edram /cal dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq27 dq28 dq29 dq30 dq31 dq32 dq33 dq34 dq8 dq17 dq26 dq35 dq6 dq5 dq4 dq3 dq2 dq1 dq0 18 16 15 13 r1* r2* r3* r4* 9 7 6 4 vcc vcc vcc vcc vcc vcc vss vss vss vss vss vss vss 17 11 5 1 22 31 3 8 14 19 23 34 44 32 +5v +5v 100k w /re 33 u3 parity* byte 1 dm2203t 512k x 8 dm2203t 512k x 8 dm2203t 512k x 8 dm2203t 512k x 8 edram edram edram edram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 w/r /we /f /s /g qle /hit /cal /cal /cal /cal dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 18 16 15 13 9 7 6 4 18 16 15 13 9 7 6 4 18 16 15 13 9 7 6 4 18 16 15 13 9 7 6 4 32 32 32 32 27 28 29 30 35 36 37 38 39 40 41 43 26 2 42 12 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 /re2 /re2 /re0 /re0 w/r /we /f /s /g 10 24 /cal0 /cal1 vcc 10 11 30 59 66 12 13 14 15 16 17 18 28 31 32 19 48 47 68 69 67 40 43 41 42 46 44 34 1 29 39 71 72 70 vcc vcc vcc vcc vss vss vss vss vss pd +5v /cal2 /cal3 /calp /calp /cal0 /cal1 /cal2 /cal3 /re /re /re /re c1 c2 c3 c4 c5 *dm2213 and r 1-4 are not present on the dm512k32st6. 33 33 33 33 u1 byte 2 byte 3 byte 4 u2 u4 u5 dq35 dq34 dq33 dq32 dq31 dq30 dq29 dq28 dq27 dq26 dq25 dq24 dq23 dq22 dq21 dq20 dq19 dq18 dq17 dq16 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 38 64 62 60 58 56 54 52 50 35 27 25 23 21 9 7 5 3 37 65 63 61 57 55 53 51 49 36 26 24 22 20 8 6 4 2 j1 edge connecter 100k w r6 - r10 inter connect diagram
2-62 pin no. function 1 gnd interconnect (component pin) organization c (3, 8, 14, 19, 23, 34, 44) ground 2 3 4 u1 (6) byte 1 i/o 2 5 6 u1 (7) byte 1 i/o 3 7 8 u1 (9) byte 1 i/o 4 9 10 +5 volts c (1, 5,11, 17, 22, 31) 11 +5 volts c (1, 5, 11, 17, 22, 31) 12 c (27) address 13 14 15 16 17 18 c (37) address 19 20 u1 (13) 21 u4 (13) 22 u1 (15) 23 u4 (15) 24 u1 (16) 25 u4 (164 byte 3 i/o 7 26 u1 (18) byte 1 i/o 8 27 u4 (18) byte 3 i/o 8 28 c (38) address 29 gnd c (3, 8, 14, 19, 23, 34, 44) ground 30 +5 volts c (1, 5, 11, 17, 22, 31) 31 c (39) address 32 c (40) address 33 nc reserved for 2mb x 36 34 u3, 4, 5 (33) 35 36 a 9 row enable (bytes 3,4, parity) 37 u3 (6) parity i/o for byte 2 38 u3 (9) 39 gnd c (3, 8, 14, 19, 23, 34, 44) 40 u1 (32) byte 1 column address latch 41 u4 (32) byte 3 column address latch 42 u5 (32) byte 4 column address latch 43 u2 (32) byte 2 column address latch 44 u1, 2 (33) row enable (bytes 1,2) 45 nc reserved for 2mb x 36 46 u3 (32) parity column address latch 47 48 c (26) write enable 49 u2 (4) byte 2 i/o 1 50 u5 (4) byte 4 i/o 1 51 u2 (6) byte 2 i/o 2 52 u5 (6) byte 4 i/o 2 53 u2 (7) byte 2 i/o 3 54 u5 (7) byte 4 i/o 3 55 u2 (9) 56 u5 (9) byte 4 i/o 4 57 u2 (13) byte 2 i/o 5 58 u5 (13) byte 4 i/o 5 59 +5 volts c (1, 5, 11, 17, 22, 31) 60 u5 (15) byte 4 i/o 6 61 u2 (15) byte 2 i/o 6 62 u5 (16) byte 4 i/o 7 63 u2 (16) byte 2 i/o 7 64 u5 (18) byte 4 i/o 8 65 u2 (18) byte 2 i/o 8 66 +5 volts c (1, 5, 11, 17, 22, 31) 67 c (12) 68 c (2) 69 /s c (42) 70 pd signal gnd 71 gnd c (3, 8, 14, 19, 23, 34, 44) 72 /g c (3, 8, 14, 19 33, 34, 44) parity i/o for byte 4 /we gnd /f output enable refresh mode control chip select presence detect ground c = common to all memory chips, u1 = chip 1, etc. pin no. function interconnect (component pin) organization byte 1 i/o 5 byte 3 i/o 5 byte 1 i/o 6 byte 1 i/o 7 byte 3 i/o 6 ground byte 2 i/o 4 ground u1 (4) byte 1 i/o 1 u4 (4) byte 3 i/o 1 u4 (6) byte 3 i/o 2 u4 (7) byte 3 i/o 3 u4 (9) byte 3 i/o 4 v cc a 0 c (28) address a 1 c (29) address a 2 c (30) a 3 address c (35) address a 4 c (36) address a 5 c (41) address v cc u3 (7) parity i/o for byte 3 u3 (4) parity i/o for byte 1 v cc a 6 a 7 a 8 v cc a 10 v cc dq 0 dq 18 dq 1 dq 19 dq 2 dq 20 dq 3 dq 21 dq 4 dq 22 dq 5 dq 23 dq 6 dq 24 dq 7 dq 25 /re 2 dq * 26 dq * 8 dq 16 dq 34 dq 15 dq 33 dq 14 dq 32 dq 31 dq 13 dq 30 dq 12 dq 29 dq 11 dq 28 dq 10 dq 27 dq 9 /cal * p /re 0 /cal 1 /cal 3 /cal 2 /cal 0 dq * 35 dq * 17 c (43) w/r mode control w/r *no connect for dm512k32st6 pinout
2-63 r = 828 1 5ns v gnd 5.0v w output c = 50pf l r = 295 2 load circuit input waveforms w 5ns il v il v ih v ih ac t est load and w avefor ms must remain active throughout any read or write operation. with the exception of /f refresh cycles, /re should never be clocked when /s is inactive. dq 0-35 ?data input/output these bidirectional data pins are used to read and write data to the edram. on the dm512k36 simm, the parity pins are also used to specify the bit mask used during parity write operations. a 0-10 ?multiplex addr ess these inputs are used to specify the row and column addresses of the edram data. the 11-bit row address is latched on the falling edge of /re. the 8-bit column address can be specified at any other time to select read data from the sram cache or to specify the write column address during write cycles. v cc power supply these inputs are connected to the +5 volt power supply . v ss gr ound these inputs are connected to the power supply ground connection. ambient operating temperature (t ) description ratings in output voltage (v ) power supply voltage (v ) storage temperature (t ) static discharge voltage (per mil-std-883 method 3015) short circuit o/p current (i ) cc out a s out - 1 ~ 7v - 1 ~ 7v input voltage (v ) - 1 ~ 7v -40 ~ 85? -55 ~ 150? class 1 50ma* absolute maximum ratings (beyond which permanent damage could result) * one output at a time per device; short duration description max* pins input capacitance i/o capacitance 9pf 22/24pf a 0-10 dq 0-35 input capacitance 17pf /g input capacitance 16pf /re 0 input capacitance 24pf w/r, /we, /f, /s input capacitance 10pf /cal 0-3, p input capacitance 14/18pf /re 2 capacitance * dm512k32st6/dm512k36st6, respectively v in t iming reference point at v il and v ih v out t iming referenced to 1.5 v olts v ih
2-64 symbol parameters min max test conditions v cc supply voltage 4.75v 5.25v all voltages referenced to v ss v v i i v ih il i(l) o(l) oh v ol ov v 6.5v, all other pins not under test = 0v in ov v , ov v 5.5v out i = - 5ma out i = 4.2ma 6.5v 0.8v -50? 0.4v -50? 2.4v -1.0v -50? -50? 2.4v input high voltage input low voltage input leakage current output leakage current output high level output low level in out electrical characteristics (t a = 0 to 70 c, commercial; -40 to 85 c, industrial) symbol operating current test condition i cc1 random read /re, /cal, /g and addresses cycling: t = t minimum c all control inputs stable v - 0.2v, outputs driven cc /re, /cal, /we and addresses cycling: t = t minimum c /cal, /we and addresses cycling: t = t minimum 460ma 360ma 4ma 420ma fast page mode read static column read standby random write fast page mode write pc 720ma i cc2 i cc3 i cc4 i cc5 i cc6 600ma 33mhz typ 260ma 220ma 4ma 200ma 440ma 540ma c notes 2, 3 2, 4 2, 4 2, 3 2, 4 /cal, /g and addresses cycling: t = t minimum pc pc /g and addresses cycling: t = t minimum sc sc c pc 3 -12 max -15 max 900ma 580ma 440ma 4ma 760ma 540ma see "estimating edram operating power" application note average typical operating current i cct 120ma 1 (1) operating cur r ent ?dm512k32st6 symbol operating current -15 max test condition i cc1 random read /re, /cal, /g and addresses cycling: t = t minimum c all control inputs stable v - 0.2v, outputs driven cc /re, /cal, /we and addresses cycling: t = t minimum c /cal, /we and addresses cycling: t = t minimum 575ma 450ma 5ma 525ma fast page mode read static column read standby random write fast page mode write pc 900ma i cc2 i cc3 i cc4 i cc5 i cc6 750ma 33mhz typ 325ma 275ma 5ma 250ma 550ma 675ma c notes 2, 3 2, 4 2, 4 2, 3 2, 4 /cal, /g and addresses cycling: t = t minimum pc pc /g and addresses cycling: t = t minimum sc sc c pc 3 -12 max 1125ma 725ma 550ma 5ma 950ma 675ma see "estimating edram operating power" application note average typical operating current i cct 150ma 1 (1) (1) ?3mhz typ?refers to worst case i cc expected in a system operating with a 33mhz memory bus. see power applications note for further details. this parameter is not 100% tested or guaranteed. (2) i cc is dependent on cycle rates and is measured with cmos levels and the outputs op en. (3) i cc is measured with a maximum of one address change while /re = v il . (4) i cc is measured with a maximum of one address change while /cal = v ih . operating cur r ent ?dm512k36st6
2-65 symbol description t ac (1) t asc t asr t c t c1 t cae t cah t ch t cqv t crp t cwl t dh t ds t gqv (1) t gqx (2,3) column address access time column address setup time row enable cycle time row enable cycle time, cache hit (row=lrr), read cycle only row address setup time column address latch active time column address hold time column address latch high time (latch transparent) column address latch high to data valid column address latch setup time to row enable /we low to /cal inactive data input hold time data input setup time output enable access time output enable to output drive time 5 5 55 20 5 5 5 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min max units 12 5 0 15 0 5 t aqx column address change to output data invalid ns 5 t ach column address valid to /cal inactive (write cycle) ns 12 5 5 5 65 25 5 5 5 0 5 min max 15 6 0 15 0 5 5 15 t aci address valid to /cal inactive ns 12 15 5 -12 -15 t nrs t pc t rac (1) t rac1 (1) t rah output turn-off delay from output disabled (/g - ) /cal, /g, and /we setup time for /re-only refresh column address latch cycle time row address hold time row enable access time, on a cache miss t nrh /cal, /g, and /we hold time for /re-only refresh t msu /f and w/r mode select setup time t mh /f and w/r mode select hold time ns 0 5 0 5 ns 0 0 ns 5 5 ns 0 0 ns 5 5 ns 12 15 ns 30 35 ns 1.5 t gqz (4,5) t rac2 (1,6) row enable access time for a cache write hit ns 30 35 1 t chr /cal inactive lead time to /re inactive (write cycles only) -2 ns -2 t chw column address latch high to write enable low (multiple writes) 0 ns 0 t cqh column address latch low to data invalid 5 ns 5 t clv column address latch low to data valid 7 ns 7 row enable access time, on a cache hit (limit becomes t ac ) 15 17 ns t dmh mask hold time from row enable (write-per-bit) 5 ns 5 t dms mask setup time to row enable (write-per-bit) ns t re row enable active time ns 30 35 100000 100000 1.5 1 switching characteristics (v cc = 5v 5%, t a = 0 to 70 c, commercial; -40 to 85 c, industrial)
2-66 symbol description t rgx t rp (7) t rp1 t rrh t rsh t output enable don't care from row enable (write, cache miss), o/p hi z row precharge time row precharge time, cache hit (row=lrr) read cycle read hold time from row enable (write only) last write address latch to end of write row enable to column address latch low for second write 9 20 8 0 ns ns ns ns ns ns min max units 35 25 10 0 min max 10 t rqx1 (2,6) row enable high to output turn-on after write miss 0 ns 40 -12 -15 12 15 rsw ns t rwl last write enable to end of write ns 12 15 t sc column address cycle time ns 12 15 t shr select hold from row enable ns 0 0 t sqv (1) chip select access time ns 12 15 t sqx (2,3) output turn-on from select low ns 12 15 0 0 output turn-off from chip select ns 8 10 0 0 t ssr select setup time to row enable ns 5 5 t t transition time (rise and fall) ns 10 10 1 1 t wc write enable cycle time ns 12 15 t wch column address latch low to write enable inactive time ns 5 5 t wi write enable inactive time ns 5 5 (1) v out timing reference point at 1.5v (2) parameter defines time when output is enabled (sourcing or sinking current) and is not referenced to v oh or v ol (3) minimum specification is referenced from v ih and maximum specification is referenced from v il on input control signal (4) parameter defines time when output achieves open-circuit condition and is no t referenced to v oh or v ol (5) minimum specification is referenced from v il and maximum specification is referenced from v ih on input control signal (6) access parameter applies when /cal has not been asserted prior to t rac2 (7) for write-per-bit devices, t whr is limited by data input setup time, t ds t wp t wrp t wrr write enable active time write enable setup time to row enable write to read recovery (following write miss) 12 ns ns ns 5 data turn-off from write enable low ns t wqx (2,5) data output turn-on from write enable high ns 0 t wqv (1) data valid from write enable high ns 15 5 0 12 5 5 15 12 15 0 0 12 15 t re1 t ref row enable active time, cache hit (row=lrr) read cycle refresh period ms 64 64 8 10 ns t whr (7) write enable hold after /re ns 0 0 t sqz (4,5) t wqz (3,4) 12 0 15 switching characteristics (continued) (v cc = 5v 5%, (t a = 0 to 70 c, commercial; -40 to 85 c, industrial; c l = 50pf)
2-67 /re /f w/r a 0-10 /cal /g /s t cah column 1 column 2 t asc t aci t cah t ch t cae t pc t cqv t ac t cqh t clv t clv data 1 open data 2 t gqz t gqx t gqv t ac t sqz t sqv t sqx row t asc dq 0-35 a 0-7 a 0-10 0, 2 0-3, p /we don? care or indeterminate notes: 1. data accessed during /re inactive read is from the row address specifi ed during the last /re active read cycle. 2. latched data becomes invalid when /s is inactive. /re inactive cache read hit (edo mode)
2-68 /re t c1 row /f w/r a 0-10 0,2 0-35 0-3, p /cal /g /s t re1 t msu t mh t rp1 t asr t rah t cah column 1 column 2 t crp t asc t cah t ch t cqv t cae t pc t ac t rac1 t cqh t clv t clv data 1 open data 2 t gqz t gqx t gqv t ac t ssr t sqz t shr t mh t msu row t asc dq /we don? care or indeterminate notes: 1. latched data becomes invalid when /s is inactive. t aci /re active cache read hit (edo mode)
/re /f w/r a 0-10 0, 2 0-3, p 0-35 /cal /g /s t msu t c a 0-7 a 0-7 a 0-10 t re t rp t mh t mh t rah t msu t asr t crp t cah t asc t aci t asc t cah t ch t cae t pc t cqv t rac t cqh t clv t clv t ac open t ac t gqz t ssr t gqx t gqv t shr t sqz row column 1 column 2 row data 1 data 2 dq /we don? care or indeterminate notes: 1. latched data becomes invalid when /s is inactive. /re active cache read miss (edo mode) 2-69
2-70 /re /f w/r /cal /we /g t re /s column 1 t msu t msu t asr t mh t mh t rah t rsw column 2 row column n cache (column n) open t crp t cah t asc t cwl t cae t cwl t rsh t cae t wrp t wp t rrh t cae t asc t wch t wch t pc t wp t rwl t dh t dh t ds t ds t ac t clv t wrr t gqx t rqx1 t gqv t ssr dq 0-35 a 0-7 data 1 data 2 t cah t ach t ach t chr t ch t whr t wi t wc t chw t rp a 0-7 a 0-7 a 0-10 a 0-10 0,2 0-3, p don? care or indeterminate notes: 1. /g becomes a don? care after t rgx during a write miss. t cah burst w rite (hit or miss) followed by /re inactive cache reads
/re 0,2 /f w/r a 0-10 /cal 0-3,p /we /g t re /s column 1 t msu t msu t asr t mh t mh t rah column 2 row column 3 t wrp t pc t clv t gqx t ssr dq 0-35 a 0-7 read data t whr t c t rp don? care or indeterminate notes: 1. if column address one equals column address two, then a read-modify-write cycle is performed. t chr t asc t ac t crp t cae t ach t asc t asc t cah t rsh t wch t rrh t cae t cqv t wp t cwl write data read data t rac2 t ac t ds t rwl t wqv t clv t gqv t gqz t dh t gqz t gqv t wqx 2-71 read/w rite during w rite hit cycle (can include read-modify-w rite)
2-72 /re /cal 0-3,p w/r a 0-10 0, 2 /we /f t re a 0-7 /s t rah t msu t asr t mh t ssr dq 0-35 t rp t rsh t cae row column t asc t cah t chr t cwl mask data t t dmh dms t rwl t wch t wrp t ds t dh t wp t rrh t msu t mh t shr t ach t whr don? care or indeterminate notes: 1. 2. 3. data mask bit high (1) enables bit write; data mask bit low (0) inhibits bit wri te. write-per-bit cycle valid only for dm512k36 st6. write-per-bit waveform applies to parity bits only (dq 8, 17, 26, 35). w rite-per -bit cycle (/g=high)
2-73 /re 0, 2 /f t re t msu t mh don? care or indeterminate notes: 1. 2. during /f refresh cycles, the status of w/r, /we, a 0-10 , /cal, /s, and /g is a don? care. /re inactive cache reads may be performed in parallel with /f refresh cycles. t rp t c w/r, /f t re t rp t asr t rah row t nrs t nrh t ssr t shr t msu t mh /re a 0-10 ,/we, /g /s don? care or indeterminate notes: 1. all binary combinations of a 0-9 must be refreshed every 64ms interval. a 10 does not have to be cycled, but must remain valid during row address setup and hold times. 2. /re refresh is write cycle with no /cal active cycle. 0,2 0-3,p /cal /f refr esh cycle /re-only refr esh
2-74 dm512k36st6 - 12i dynamic memory memory depth (kilobits) i/o width packaging system access time from cache in nanoseconds special configurations 12ns 15ns no designator = 0 0 to 70 0 c commerical temperature i = 40 0 to 85 0 c industrial temperature t = 300 mil, plastic tsop-ii configuration memory module configuration s = simm 6 = +5 volt, multibank edo 32 = 32 bits 36 = 36 bits par t numbering system 4.245 (107.82) 4.255 (108.08) 3.984 (101.19) 0.133 (3.38) 0.075 (1.90) 0.085 (2.16) 0.050 (1.27) 1.750 (44.45) 2.125 (53.98) 3.750 (95.25) 0.250 (6.35) 0.040 (1.02) 0.042 (1.07) 0.060 (1.52) 0.064 (1.63) 0.250 (6.35) 0.062 (1.57) rad. 0.245 (6.22) 0.255 (6.48) 0.400 (10.16) 0.945 (24.00) 0.955 (24.26) 0.123 (3.12) 0.127 (3.22) 0.100 (2.54) u1 1 72 r6 c1 r8 r9 r7 r10 c2 c4 c5 u1-2, u4-5 u5 c1-c5 r1-r4, r6-r10 socket enhanced dm2203t-xx, 512k x 8 edrams, 300 mil tsop enhanced dm2213t-xx, 512k x 8 edram with write-per-bit (not present on dm512k32s t6) 0.22? chip capacitors 100k w chip resistors amp 822030-3 or equivalent inches (mm) 0.225 (5.72) rad. 0.010 (.254) 0.047 (1.19) 0.054 (1.37) 0.104 (2.65) u3 r4 r3 c3 r1 r2 u4 u5 u2 mechanical data 72 pin simm module the information contained herein is subject to change without notice. enhanced memory systems inc. assumes no responsibility fo r the use of any circuitry other than circuitry embodied in an enhanced product, nor does it convey or imply any license under patent or other rights.

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