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8-mbit (512k x 16) static ram cy62157e mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05695 rev. *e revised april 27, 2007 features ? very high speed: 45 ns ? industrial: ?40c to +85c ? automotive-e: ?40c to +125c ? wide voltage range: 4.5v?5.5v ? ultra low standby power ? typical standby current: 2 a ? maximum standby current: 8 a (industrial) ? ultra low active power ? typical active current: 1.8 ma @ f = 1 mhz ? ultra low standby power ? easy memory expansion with ce 1 , ce 2 and oe features ? automatic power down when deselected ? cmos for optimum speed and power ? available in pb-free 44-pin tsop ii and 48-ball vfbga package functional description [1] the cy62157e is a high performance cmos static ram organized as 512k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. place the device into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input or output pins (io 0 through io 15 ) are placed in a high impedance state when: ? deselected (ce 1 high or ce 2 low) ? outputs are disabled (oe high) ? both byte high enable and byte low enable are disabled (bhe , ble high) ? write operation is active (ce 1 low, ce 2 high and we low) to write to the device, take chip enable (ce 1 low and ce 2 high) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ), is written into the location specified on the address pins (a 0 through a 18 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the ?truth table? on page 9 for a complete description of read and write modes. logic block diagram 512k x 16 ram array io 0 ?io 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 io 8 ?io 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 10 a 18 ce 2 ce 1 power down circuit bhe ble ce 2 ce 1 notes 1. for best practice recommendations, plea se refer to the cypress application note an1064, sram system guidelines .
cy62157e mobl ? document #: 38-05695 rev. *e page 2 of 12 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( a) f = 1 mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62157ell industrial 4.5 5.0 5.5 45 1.8 3 18 25 2 8 cy62157ell automotive 4.5 5.0 5.5 55 1.8 4 18 35 2 30 pin configuration the following pictures show the tsop ii and vfbga pinouts. [3, 4] notes 2. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. 3. nc pins are not connected on the die. 4. the 44-pin tsop ii package has only one chip enable (ce ) pin. we a 11 a 10 a 6 a 0 a 3 ce 1 io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe vss a 7 io 0 bhe ce 2 a 17 a 2 a 1 ble v cc io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 nc a 18 nc 3 2 6 5 4 1 d e b a c f g h vfbga a 16 nc vcc top view 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 tsop ii top view a 6 a 7 a 3 a 2 a 1 a 0 a 17 a 4 a 9 a 10 a 11 a 12 a 15 a 16 oe bhe ble ce we io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 v cc v cc v ss v ss 10 a 18 a 14 a 8 a 13
cy62157e mobl ? document #: 38-05695 rev. *e page 3 of 12 maximum ratings exceeding maximum ratings may sh orten the battery life of the device. user guidelines are not tested. storage temperature ............. .............. ..... ?65c to + 150c ambient temperature with power applied .......... .............. .............. ..... ?55c to + 125c supply voltage to ground potential .......................................................... ?0.5v to 6.0v dc voltage applied to outputs in high-z state [5, 6] ........................................... ?0.5v to 6.0v dc input voltage [5, 6] ........................................?0.5v to 6.0v output current into outputs (low) ............................ 20 ma static discharge voltage ........ .............. .............. ...... > 2001v (mil-std-883, method 3015) latch up current .................................................... > 200 ma operating range device range ambient temperature v cc [7] cy62157ell industrial ?40c to +85c 4.5v to 5.5v automotive ?40c to +125c electrical characteristics over the operating range parameter description test conditions 45 ns (industrial) 55 ns (automotive) unit min typ [2] max min typ [2] max v oh output high voltage i oh = ?1 ma 2.4 2.4 v v ol output low voltage i ol = 2.1 ma 0.4 0.4 v v ih input high voltage v cc = 4.5v to 5.5v 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il input low voltage v cc = 4.5v to 5.5v ?0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?4 +4 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?4 +4 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels 18 25 18 35 ma f = 1 mhz 1.8 3 1.8 4 i sb1 automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v, v in < 0.2v, f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = v cc(max) 28 230 a i sb2 [8] automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = v cc(max) 28 230 a capacitance [9] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 5. v il(min) = ?2.0v for pulse durations less than 20 ns for i < 30 ma. 6. v ih(max) = v cc + 0.75v for pulse durations less than 20 ns. 7. full device ac operation assumes a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 8. only chip enables (ce 1 and ce 2 ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 9. tested initially and after any design or proce ss changes that may affect these parameters.
cy62157e mobl ? document #: 38-05695 rev. *e page 4 of 12 thermal resistance [9] parameter description test conditions tsop ii vfbga unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 77 72 c/w jc thermal resistance (junction to case) 13 8.86 c/w ac test loads and waveforms figure 1. ac test loads and waveforms parameters values unit r1 1800 ? r2 990 ? r th 639 ? v th 1.77 v data retention characteristics over the operating range parameter description conditions min typ [2] max unit v dr v cc for data retention 2 v i ccdr [8] data retention current v cc =2v, ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v industrial 8 a automotive 30 t cdr [9] chip deselect to data retention time 0ns t r [10] operation recovery time t rc ns data retention waveform [11] figure 2. data retention waveform 3v v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 v cc(min) t cdr v dr > 2v data retention mode t r v cc(min) ce 1 or v cc bhe .ble ce 2 or notes 10. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. 11. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling ch ip enable signals or by disabling both bhe and ble .
cy62157e mobl ? document #: 38-05695 rev. *e page 5 of 12 switching characteristics over the operating range [12, 13] parameter description 45 ns (industrial) 55 ns (automotive) unit min max min max read cycle t rc read cycle time 45 55 ns t aa address to data valid 45 55 ns t oha data hold from address change 10 10 ns t ace ce 1 low and ce 2 high to data valid 45 55 ns t doe oe low to data valid 22 25 ns t lzoe oe low to low-z [14] 55ns t hzoe oe high to high-z [14, 15] 18 20 ns t lzce ce 1 low and ce 2 high to low-z [14] 10 10 ns t hzce ce 1 high and ce 2 low to high-z [14, 15] 18 20 ns t pu ce 1 low and ce 2 high to power up 0 0 ns t pd ce 1 high and ce 2 low to power down 45 55 ns t dbe ble /bhe low to data valid 45 55 ns t lzbe ble /bhe low to low-z [14] 10 10 ns t hzbe ble /bhe high to high-z [14, 15] 18 20 ns write cycle [16] t wc write cycle time 45 55 ns t sce ce 1 low and ce 2 high to write end 35 40 ns t aw address setup to write end 35 40 ns t ha address hold from write end 0 0 ns t sa address setup to write start 00 ns t pwe we pulse width 35 40 ns t bw ble /bhe low to write end 35 40 ns t sd data setup to write end 25 25 ns t hd data hold from write end 00 ns t hzwe we low to high-z [14, 15] 18 20 ns t lzwe we high to low-z [14] 10 10 ns notes 12. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less, timing ref erence levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 4 . 13. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 14. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 15. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 16. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe , ble , or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
cy62157e mobl ? document #: 38-05695 rev. *e page 6 of 12 switching waveforms read cycle no. 1 (address transition controlled) [17, 18] figure 3. read cycle no. 1 read cycle no. 2 (oe controlled) [18, 19] figure 4. read cycle no. 2 previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data out v cc supply current high i cc i sb impedance notes 17. the device is continuously selected. oe , ce 1 = v il , bhe , ble or both = v il , and ce 2 = v ih . 18. we is high for read cycle. 19. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high.
cy62157e mobl ? document #: 38-05695 rev. *e page 7 of 12 write cycle no. 1 (we controlled) [16, 20, 21] figure 5. write cycle no. 1 write cycle no. 2 (ce 1 or ce 2 controlled) [16, 20, 21] figure 6. write cycle no. 2 switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 22 ce 1 address ce 2 we data io oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 22 ce 1 address ce 2 we data io oe bhe /ble notes 20. data io is high impedance if oe = v ih . 21. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 22. during this period, the ios are in output state. do not apply input signals.
cy62157e mobl ? document #: 38-05695 rev. *e page 8 of 12 write cycle no. 3 (we controlled, oe low) [21] figure 7. write cycle no. 3 write cycle no. 4 (bhe /ble controlled, oe low) [21] figure 8. write cycle no. 4 switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 22 ce 1 address ce 2 we data io bhe /ble t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 22 ce 1 address ce 2 we data io bhe /ble
cy62157e mobl ? document #: 38-05695 rev. *e page 9 of 12 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power h x x x x x high-z deselect/power down standby (i sb ) x l x x x x high-z deselect/power down standby (i sb ) x x x x h h high-z deselect/power down standby (i sb ) l h h l l l data out (io 0 ?io 15 ) read active (i cc ) l h h l h l data out (io 0 ?io 7 ); high-z (io 8 ?io 15 ) read active (i cc ) l h h l l h high-z (io 0 ?io 7 ); data out (io 8 ?io 15 ) read active (i cc ) l h h h l h high-z output disabled active (i cc ) l h h h h l high-z output disabled active (i cc ) l h h h l l high-z output disabled active (i cc ) l h l x l l data in (io 0 ?io 15 ) write active (i cc ) l h l x h l data in (io 0 ?io 7 ); high-z (io 8 ?io 15 ) write active (i cc ) l h l x l h high-z (io 0 ?io 7 ); data in (io 8 ?io 15 ) write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 45 cy62157ell-45zsxi 51-85087 44-pin thin small ou tline package type ii (pb-free) industrial 55 CY62157ELL-55ZSXE 51-85087 44-pin thin small outline package type ii (pb-free) automotive cy62157ell-55bvxe 51-85150 48-ball very fine pitch ball grid array (pb-free) contact your local cypress sales represen tative for availability of these parts.
cy62157e mobl ? document #: 38-05695 rev. *e page 10 of 12 package diagrams figure 9. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85150-*d
cy62157e mobl ? document #: 38-05695 rev. *e page 11 of 12 ? cypress semiconductor corporation, 2004-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 10. 44-pin tsop ii, 51-85087 mobl is a registered trademark, and more battery life is a tr ademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 51-85087-*a
cy62157e mobl ? document #: 38-05695 rev. *e page 12 of 12 document history page document title: cy62157e mobl ? , 8-mbit (512k x 16) static ram document number: 38-05695 rev. ecn no. issue date orig. of change description of change ** 291273 see ecn pci new data sheet *a 457689 see ecn nxr added automotive product removed industrial product removed 35 ns and 45 ns speed bins removed ?l? bin updated ac test loads table corrected t r in data retention characteristics from 100 s to t rc ns updated the ordering information and replaced the package name column with package diagram *b 467033 see ecn nxr added industrial product (final information) removed 48 ball vfbga package and its relevant information changed the i cc(typ) value of automotive from 2 ma to 1.8 ma for f = 1mhz changed the i sb2(typ) value of automotive from 5 a to 1.8 a modified footnote #4 to include current limit updated the ordering information table *c 569114 see ecn vkn added 48 ball vfbga package updated logic block diagram added footnote #3 updated the ordering information table *d 925501 see ecn vkn added footnote #9 related to i sb2 and i ccdr added footnote #14 related ac timing parameters *e 1045801 see ecn vkn converted automotive specs from preliminary to final

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