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1/12 rev. b structure silicon monolithic integrated circuit product 20488 bit electrically erasable prom part number bu 9844gul-w physical dimension fig.-1 block diagram fig.-2 use g eneral purpose features ? 2048 words 8 bits architecture serial eeprom ?wide operating voltage range (1.7 v5.5v) ?two wire serial interface ?self-timed write cycle with automatic erase ?16 byte page write mode ?low power consumption write ( 5v ) : 1.2ma (typ.) read ( 5v ) : 0.2ma (typ .) standby ( 5v ) : 0.1a(typ. ) ?data s ecurity write protect feature (wp pin) inhibit to write at low v cc ? wlcsp package ------ vcsp50l1 ?high reliability fine pattern cmos technology ?endura nce : 1,000,000 erase/write cycles ?data retention : 40 years ? filtered inputs in scl?sda for noise suppression ? initial data ffh in all address absolute maximum rating (ta=25) parameter symbol rating unit supply voltage v cc -0.36.5 v power dissipation vcsp50l1 220 mw storage temperature tstg -65125 operating temperature topr -4085 terminal voltage -0.3v cc +0.3 v * degradation is done at 2.2mw/ for operation above 25
2/12 rev. b recommended operating condition parameter symbol rating unit supply voltage v cc 1.75.5 v input voltage v in 0 v cc v dc operating characteristics (unless otherwise specified ta=-40 85?v cc =1.75.5v) parameter symbol specification unit test condition min. typ. max. ?h? input voltage1 v ih1 0.7v cc v 2.5vQvccQ5.5v ?l? input voltage1 v il1 0.3v cc v 2.5vQvccQ5.5v ?h? input voltage2 v ih2 0.9v cc v 1.7vQvcc2.5v ?l? input voltage2 v il2 0.1v cc v 1.7vQvcc2.5v ?l? output voltage1 v ol1 0.3 v i ol =3.0ma2.5vQvccQ5.5v sda ?l? output voltage2 v ol2 0.2 v i ol =1.5ma1.7vQvcc2.5v sda input leakage current i li -1 1 a v in =0vv cc output leakage current i lo -1 1 a v out =0vv cc sda operating current i cc1 2.0 ma v cc =5.5v,f scl =400hz, t wr =5ms byte write page write i cc2 0.5 ma v cc =5.5v,f scl =400hz random read current read sequential read standby current i sb 2.0 a v cc =5.5v,sda?scl=v cc a2=gnd,wp=gnd this product is not designed for protection against radioactive rays. memory cell characteristics(ta=25vcc=1.75.5v) parameter specification unit min. typ. max. write/erase cycle 1, 000,000 cycle data retention 40 year
3/12 rev. b fig.-1 physical dimension vcsp50l1 unit : mm lot no. 9844 product name BU9844GUL-W
4/12 rev. b block diagram sda scl wp a2 16kbit eeprom array address decoder slave?word address register data register control logic high voltage gen. vcc level detect 11bit 11bit 8bit ack start stop a2=don ? t use pin configuration 1 2 index post c1 b1 a1 c2 b2 a2 c b a pin name land no. pin name i/o functions a1 v power supply a2 a2 in out of use (vcc or gnd or open) b1 wp in write protect input b2 gnd in ground 0v c1 scl in serial clock input c2 sda in/out slave and word address, serial data input, serial data output *1 *1 an open drain output requires a pull-up resistor. fig.-2 block diagram fig.-3 BU9844GUL-W (bottom view) vcc gnd
5/12 rev. b ac operating characteristics (unless otherwise specified ta=- 4085?v cc =1.75.5v) parameter symbol fast-mode 2.5QvccQ5.5v standard-mode 1.7QvccQ5.5v unit min. typ. max. min. typ. max. clock frequency fscl 400 100 khz data clock high period thigh 0.6 4.0 s data clock low period tlow 1.2 4.7 s sda and scl rise time tr 0.3 1.0 s sda and scl fall time tf 0.3 0.3 s start condition hold time thd:sta 0.6 4.0 s start condition setup time tsu:sta 0.6 4.7 s input data hold time thd:dat 0 0 ns input data setup time tsu:dat 100 250 ns output data delay time tpd 0.1 0.9 0.2 3.5 s output data hold time tdh 0.1 0.2 s stop condition setup time tsu:sto 0.6 4.7 s bus free time tbuf 1.2 4.7 s write cycle time twr 5 5 ms noise spike width (sda and scl) ti 0.1 0.1 s wp hold time thdwp 0 0 ns wp setup time tsuwp 0.1 0.1 s wp high period thighwp 1.0 1.0 s
6/12 rev. b synchronous data timing sda (in) scl sda (out) t hd :sta t hd :dat t su :dat t buf t pd t dh t low t high t r t f sda scl t su :sta t su :sto t hd :sta start bit stop bit sda data is latched into the chip at the rising edge of scl clo ck. output date toggles at the falling edge of scl clock. write cycle timing sda scl d0 ack stop condition start condition t wr write data(n) fig.-5 write cycle timing fig.-4 synchronous data timing
7/12 rev. b wp timing for the write operation, wp must be "low" during the period of time from the rising edge of the clock which takes in d0 of first byte until the end of t wr. ( see fig.-6(a) ) during this period, write operation is ca nceled by setting wp "high". see fig.-6(b) in the case of setting wp "high" during t wr, write operation is stopped in the middle and the data of a ccessing address is not guaranteed. please write correct data a gain in the case. scl sda wp fig.-6(a) wp timing of the write operation wp stop bit t high : wp d1 d0 ack ack data ( 1 ) data ( n ) scl wp sda d1 d0 ack ack data ( 1 ) data ( n ) t su wp fig.-6(b) wp timing of the write cancel operation
8/12 rev. b device operation start condition (recognition of start bit) ?all commands are proceeded by the start condition, which is a high to low transition of sda when scl is high. ?the device continuously monitors the sda and scl lines for the start condition and w ill not respond to any command until this condition has been me t. see fig.-4 synchronous data timing stop condition (recognition of stop bit) ?all commands must be terminated by a stop condition, which is a low to high transition of sda w hen scl is high. see fig.-4 synchronous data timing notice about write command ?in the case that stop condition is not excuted in wr ite mode, transfered data will not be written in a memory. device addressing ?following a start condition, the master output the slave addre ss to be accessed. ?the most significant four bits of the slave address are the ? device type indentifier, ? for this device it is fixed as ?1010. ? ? the next three bits (p2,p1,p0) ar e used by the master to select eight 256 word page of memory. p2,p1,p0 set to 000 ? ? ? 1page(0000ff) p2,p1,p0 set to 001 ? ? ? 2page(1001ff) ? ? ? ? ? ? p2,p1,p0 set to 111 ? ? ? page(7007ff) ? the last bit of the stream (r/w read/write) determines the op eration to be performed. when set to ?1 ? , a read operation is selected ; when set to ?0 ? , a write operation is selected. r/w set to ?0 ? ? ? ? ? ? ? ? ? write (including word address input of random read) r/w set to ?1 ? ? ? ? ? ? ? ? ? read ?? write protect (wp) when wp pin set to v cc (h level), write protect is set for 2,048 words (all address). when wp pin set to gnd(l level), it is enable to write 2,048 wo rds (all address). either control this pin or connect to gnd ( or vcc). it is inhi bited from being left unconnected.
9/12 rev. b acknowledge ?acknowledge is a software convention used to indicate successf ul data transfers. the transmitter device will release the bus after transmitting eight bits. (when inputting the slave address in the write or read operatio n, transmitter is -com. when outputting the data in the read operation, it is this devi ce.) ?during the ninth clock cycle, the receiver will pull the sda l ine low to acknowledge that the eight bits of data has been received. (when inputting the slave address in the write or read operatio n, receiver is this device. when outputting the data in the read operation, it is -com.) ?the device will respond with an acknowledge after recognition of a start condition and its slave address (8bit). ?in the write mode, the device w ill respond with an acknowledge , after the receipt o feach subsequent 8-bit word (word address and write data). ?in the read mode, the device will transmit eight bit of data, release the sda line, and monitor the line for an acknowledge. ?if an acknowledge is detected, and no stop condition is genera ted by the master, the device will continue to transmit the data. if an acknowledge is not detected, the device will terminate further data transmissions and await a stop condition before returning to the standby mod e. (see fig-7 acknowledge response from receiver) sda scl 18 9 acknowledge signal (ack signal) start condition (start bit) from-com ic output data sda -com output data) fig.-7 acknowledge response from receiver
10/12 rev. b byte write p1p2 wa 7 d7 1100 w r i t e s t a r t r / w a c k s t o p word address data wp sda line slave address p0 wa 0 d0 a c k a c k by using this command, the data is programed into the indicate d word address. when the master generates a stop condition, the device begins the internal write cycle to the nonvolatile memory array. page write w r i t e s t a r t r / w a c k s t o p word address? data ( n ) wp sda line a c k a c k data ( n+15 ) a c k slave address 10 0 1p0 p1p2 wa 7 d0 d7 d0 wa 0 this device is capable of sixteen byte page write operation. when two or more byte data are inputted, the four low order add ress bits are internally incremented by one after the receipt of each word. the seven hi gher order bits of the address(p2p0, wa7wa4) remain constant. if the master transmits more than sixteen words, prior to gene rating the stop condition, the address counter will ? roll over,? and the previous transmitted data will be overwritten. fig.-8 byte write cycle timing fig.-9 page write cycle timing
11/12 rev. b current read p1 p2 d7 1100 r e a d s t a r t r / w s t o p data sda line slave address p0 d0 a c k a c k in case that the previous operation is random or current read ( which includes sequential read respectively), the internal address counter is increased by one from the last accessed address (n). thus current read outputs the data of the next word addres s (n+1). if the last command is byte or page write, the internal address counter stays at the last address (n). thus current read outputs the data of the word address (n) . if an acknowledge is detected, and no stop condition is generated by the master (-com), the device will continue to transmit the data. it can transmi t all data (16kbit 2048word) if an acknowledge is not detected, the device will terminate further data transmissions and await a stop condition before returning to the standby mode . note) if an acknowledge is detected with "low" level, not "high" level, command will become sequential read. so the device transmits the next data, read is not terminated. in the case of terminating read, input acknowledge with "high" always, then input stop condition. random read w r i t e s t a r t r / w a c k s t o p word address? sda line a c k a c k data ( n ) a c k slave address 10 0 1p0 p1p2 wa 7 p0 d0 slave address 10 0 1p1 p2 s t a r t d7 r / w wa 0 r e a d random read operation allows the master to access any memory location indicated word address. if an acknowledge is detected, and no stop condition is generated by the master (-com), the device will continue to transmit the data. it can transmit all data (16kbit 2048word) if an acknowledge is not detected, the device will terminate further data transmissions and await a stop condition before returning to the standby mode . note) if an acknowledge is detected with "low" level, not "high" level, command will become sequential read. so the device transmits the next data, read is not terminated. in the case of terminating read, input acknowledge with "high" always, then input stop condition. fig.-11 random read cycle timing fig.-10 current read cycle timing
12/12 rev. b sequential read r e a d s t a r t r / w a c k s t o p data ( n ) sda line a c k a c k data ( n+x ) a c k slave address 10 0 1p0 p1 p2 d0 d7 d0 d7 if an acknowledge is detected, and no stop condition is generated by the master (-com), the device will continue to transmit the data. it can transmi t all data (16kbit 2048word) if an acknowledge is not detected, the device will terminate further data transmissions and await a stop condition before returning to the standby mode . the sequential read operation can be performed with both curre nt read and random read. note) if an acknowledge is detected with "low" level, not "high" level, command will become sequential read. so the device transmits the next data, read is not terminated. in the case of terminating read, input acknowledge with "high" always, then input stop condition. fig.-12 sequential read cycle timing current read
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