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june 2000 rev. 3 - eco #12871 1 pcmcia flash memory card flf series pc card products features ? low cost, high density linear flash card ? single 5v supply - (3v/5v operation is available as option) ? based on intel 28f640j5 (mlc) components ? fast read performance - 250ns maximum access time - (200ns optional) ?pcmcia compatible - x8/ x16 data interface ? 32-byte write buffer - 6s per byte effective write time ? cross-compatible command support - intel basic command set - common flash interface (cfi) - scaleable command set ? power-down mode - reset, power down registers ? 10,000 erase cycles per block ? 128k word symmetrical block architecture ? pc card standard type ii form factor wedc?s flash memory cards - flf series - offer high density linear flash memory for code and data storage, high performance disk emulation, mobile pc and embedded applications. the wedc flf series is based on intel?s multi level cell (mlc) flash memory technology, providing high density flash components at significantly lower cost per megabyte. mlc technology allows for two bits of information to be stored in a single cell. this leads to reduced die size and reduced cost per megabyte. wedc?s flf series cards are built with intel?s 64mb components, 28f640j5, with manufacturer/device id of 89/15 h . the flf series is available in standard densities of 16, 32, 48 and 64mb. additionally, wedc?s flf series provides densities beyond the 64mb density, supported by pcmcia standard. these higher densities are based on a ?paging scheme?. by writing a page address to the configuration option register (address 4000h), an additional page of memory could be access. the current flf series supports densities to 80mb: total of 2 pages: page 0 := 64mb, page 1 := 16mb. to provide a 16 bit word wide access and to support pcmcia standard, devices are paired on the card. therefore, the flash array is structured in 128k word (256kb) blocks. write, read and block erase operations can be performed as either a word or byte wide operation. the flf series cards conform with the pc card 95 standard supported by pcmcia and jeida, providing electrical and physical compatibility. the pc card form factor offers an industry standard pinout and mechanical outline, allowing density upgrades without system design changes. wedc?s standard cards are shipped with wedc?s flash logo. cards are also available with blank housings (no logo). the blank housings are available in both, a recessed (for label) or flat housing. please contact wedc sales representative for further information on custom artwork. high density flash memory card 16, 32, 48, 64, 80 megabyte edi 7p xxx flf yy ss t zz where xxx: 016 16mb 032 32mb 048 48mb 064 64mb 080 80mb yy: 02 based on 28f640j5 with attribute memory ss: 03 wedc logo 04 blank housing type 2 05 blank housing t 2 (recessed) t: c commercial zz: 20 200ns 25 250ns ordering information general description
june 2000 rev. 3 - eco #12871 2 pcmcia flash memory card flf series pc card products r/busy r/b0 r/b(n-1) r/b1 vs2 vs1 10k n.c. n.c. vpp2 vpp1 vcc vcc gnd cd1 cd2 bvd1 bvd2 vcc open open wait open /ce1, /ce2,/oe, /we, /reg: pull up typ 100k a0, a25, reset: pull down typ 100k r/busy - open drain output (require pull up on host) data bus q8-q15 data bus q0-q7 n x 28f640j5 device 0 device 1 device 3 device 2 device (n-2) device (n-1) a0 control address buffer a1-a25 b26, (b27..) /wri q2 cl0 control logic ai qn /rdi + (a1-a25) (b26) address bus (a1-a25) attrib. mem cis e2prom 2kb management registers i/o buffer data bus d8 - d15 q0-q7 0000h 4000h a1-a23 a24, a25, b26 at/reg enable ctrl q0 device pair 0 device pair 1 device pair (n/2 - 1) address register name configuration option register 4000h 4002h 4004h 4006h 4008h config. and status reg. /we /ce1 /ce2 /oe /reg chn ch0 cln cl0 cln cl1 ch0 ch0 ch0 sr clr reg clr m res d5-d0=page number (pn) configuration option register: a=4000h (read/write) - page number (pn) - d7 d5 d6 d1 d3 d2 d4 d0 sres lvreq configuration option register: adrs=4000h d6 levelreq (not supported) - page number (pn) - d2 d4 d5-d0 configuration index d5-d1 reserved d0 page number config. (pn) power on default =0 d7 d6 d7 soft reset, active high 1=reset state 0=end reset state d0 d5 d1 d3 d7 d3 d0 d6 d2 d4 d1 d5 configuration status register: adrs=4002h d2 power down; active high 1 = place all memory devices in power down mode 0 = normal operation power on default=0 read/write read/write sres lvreq pwrdwn reserved reserved d0 - d15 flf flash card based on strata flash 28f640j5 block diagram 220k 10k c vcc m res sr clr reg clr reset reset circuit data bus d0 - d7 manufacturer id intel 89 h device id 28f640j5 15 h
june 2000 rev. 3 - eco #12871 3 pcmcia flash memory card flf series pc card products pin signal name i/o function active pin signal name i/o function active 1 gnd ground 35 gnd ground 2 dq3 i/o data bit 3 36 cd1# o card detect 1 low 3 dq4 i/o data bit 4 37 dq11 i/o data bit 11 4 dq5 i/o data bit 5 38 dq12 i/o data bit 12 5 dq6 i/o data bit 6 39 dq13 i/o data bit 13 6 dq7 i/o data bit 7 40 dq14 i/o data bit 14 7 ce1# i card enable 1 low 41 dq15 i data bit 15 8 a10 i address bit 10 42 ce2# i card enable 2 low 9 oe# i output enable low 43 vs1 o voltage sense 1 nc (2) 10 a11 i address bit 11 44 rfu reserved 11 a9 i address bit 9 45 rfu reserved 12 a8 i address bit 8 46 a17 i address bit 17 13 a13 i address bit 13 47 a18 i address bit 18 14 a14 i address bit 14 48 a19 i address bit 19 15 we# i write enable low 49 a20 i address bit 20 16 rdy/bsy # o ready/busy low(1) 50 a21 i address bit 21 17 vcc supply voltage 51 vcc supply voltage 18 vpp1 prog. voltage n.c. 52 vpp2 prog. voltage n.c. 19 a16 i address bit 16 53 a22 i address bit 22 20 a15 i address bit 15 54 a23 i address bit 23 21 a12 i address bit 12 55 a24 i address bit 24 22 a7 i address bit 7 56 a25 i address bit 25 23 a6 i address bit 6 57 vs2 o voltage sense 2 n.c. 24 a5 i address bit 5 58 rst i card reset high 25 a4 i address bit 4 59 wait# o extended bus cycle low(3) 26 a3 i address bit 3 60 rfu reserved 27 a2 i address bit 2 61 reg# i attrib mem select 28 a1 i address bit 1 62 bvd2 o bat. volt. detect 2 (3) 29 a0 i address bit 0 63 bvd1 o bat. volt. detect 1 (3) 30 dq0 i/o data bit 0 64 dq8 i/o data bit 8 31 dq1 i/o data bit 1 65 dq9 i/o data bit 9 32 dq2 i/o data bit 2 66 dq10 o data bit 10 33 wp o write potect high 67 cd2# o card detect 2 low 34 gnd ground 68 gnd ground pinout notes: 1. rdy/bsy signal is an open drain type output, pull-up resistors are required on the host side. 2. vs1 is connected to gnd for 3.3v/5v cards and n.c. for 5v only cards. 3. wait#, bvd1 and bvd2 are internally connected to vcc by resistors for compatibility. mechanical min. 1.6mm 0.05 0.063? 10.0mm min 0.400? 5.0mm t1 0.197? 1.0mm 0.05 0.039? 85.6mm 0.20 3.370? 3.0mm 54.0mm 0.10 2.126? 1.0mm 0.05 0.039? substrate area interconnect area
june 2000 rev. 3 - eco #12871 4 pcmcia flash memory card flf series pc card products symbol type name and function a0 - a25 input address inputs: a0 through a25 enable direct addressing of up to 64mb of memory on the card. signal a0 is not used in word access mode. a25 is the most significant bit dq0 - dq15 input/output data input/output: dq0 through dq15 constitute the bi-directional databus. dq15 is the msb. ce1#, ce2# input card enable 1 and 2: ce1# enables even byte accesses, ce2# enables odd byte accesses. multiplexing a0, ce1# and ce2# allows 8- bit hosts to access all data on dq0 - dq7 (see truth table). oe# input output enable: active low signal gating read data from the memory card. we# input write enable: active low signal gating write data to the memory card. rdy/bsy# output ready/busy output: indicates status of internally timed erase or program algorithms. a high output indicates that the card is ready to accept accesses. a low output indicates that one or more devices in the memory card are busy with internally timed erase or write activities. cd1#, cd2# output card detect 1 and 2: provide card insertion detection. these signals are internally connected to ground on the card. the host shall monitor these signals to detect card insertion. pulled up on host side. wp output write protect: write protect reflects the status of the write protect switch on the memory card. wp set to high = write protected, providing internal hardware write lockout to the flash array. if card does not include optional write protect switch, this signal will be pulled low internally indicating write protect = "off". vpp1, vpp2 n.c. programming voltages: not connected for 5v only card. vcc card power supply: 5.0v for all internal circuitry. gnd card ground reg# input attribute memory select: active low signal, enables access to attribute memory space, occupied by the card information structure (cis) and card registers. rst input reset: active high signal for placing card in power-on default state. reset can be used as a power-down control for the memory array. wait# output wait: this signal is pulled high internally for compatibility. no wait states are generated. bvd1, bvd2 output battery voltage detect: these signals are pulled high to maintain sram card compatibility. vs1, vs2 output voltage sense: notifies the host socket of the card's vcc requirements. vs1 and vs2 are open to indicate a 5v card. rfu reserved for future use n.c. no internal connection to card: pin may be driven or left floating. card signal description read function common memory attribute memory function mode /ce2 /ce1 a0 /oe /we /reg d15-d8 d7-d0 /reg d15-d8 d7-d0 standby mode h h x x x x high-z high-z x high-z high-z byte access (8 bits) h l l l h h high-z even-byte l high-z even-byte hlhlh h high-z odd-byte l high-z not valid word access (16 bits) l l x l h h odd-byte even-byte l not valid even-byte odd-byte only access l h x l h h odd-byte high-z l not valid high-z write function standby mode h h x x x xx x xx x byte access (8 bits) hl lhl h x even-byte l x even-byte hlhhl hxodd-byte lx x word access (16 bits) l l x h l h odd-byte even-byte l x even-byte odd-byte only access l h x h l h odd-byte x lx x functional truth table
june 2000 rev. 3 - eco #12871 5 pcmcia flash memory card flf series pc card products card interface the flf series flash card complies with pc card standard (pcmcia, march 1997). while maintaining pcmcia compatibility, the flf series card has integrated special features to extend functionality. card has built in 2 control registers: - configuration option register (cor) address = 4000 h - configuration and status register (csr) address = 4002 h cor register: provide a soft reset function (bit d7) and additional page register (bit d0) to extend card capacity beyond 64mb. sreset as defined by pcmcia, setting the sreset bit to 1, places the card in the reset state. during this state all memory devices are place in power down mode, minimizing power consumption. returning this bit to 0 leaves the reset cycle and place the card in the same condition as following a power up or hardware reset. this bit must be cleared to 0, to access any device on the card. complete soft reset cycle must consist of a 2 step write sequence to the sreset bit: 1. initialization: write 1 to sreset - reset cycle begin - memory devices enters power-down mode aborting all operations and clearing all registers. 2. write 0 to sreset - reset cycle ends - memory devices and registers enters power on default state card can be place in power down mode by activating reset signal (pin58) or by controlling the bit d2 in csr register. levlrequest not supported configuration index configuration index bits (d0 - d5) are defined to provide address extension bits -page address, to extend card capacity beyond 64mb. only bit d0 is supported: - d0 set to 0 selects page 0 - d0 set to 1 selects: page 1 d0 is set to the value of 0, during power on or any reset. csr register: provide a power control of memory array. only bit d2 is supported; all other bits are ?don?t care? pwrdwn writing 1 to pwrdwn bit (d2) forces each memory device on the card into a reset/power down mode by asserting all the devices rp# pins. writing 0 to the bit returns the array to stand by mode. card information structure (cis) contains information about registers addressing and memory structure. cards with memory capacity < 64mb do not support configuration index bits. notes: 1. reading from undefined address location or unsupported bits will return random data. 2. writing to undefined address location may result in card malfunctioning due to limited address decoding. 3. see block diagram for more details about control registers.
june 2000 rev. 3 - eco #12871 6 pcmcia flash memory card flf series pc card products absolute maximum ratings (2) operating temperature ta (ambient) commercial 0c to +60 c storage temperature -10c to +70 c voltage on any pin relative to vss -0.5v to vcc+0.5v vcc supply voltage relative to vss -0.5v to +7.0v note: stress greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol parameter density (mbytes) notes typ (3) max units test conditions iccr vcc read current 16,32,48,64,80 70 110 ma vcc = vccmax tcycle = 200ns iccw vcc program current 16,32,48,64,80 70 120 ma 2 memory devices icce vcc erase current 16,32,48,64,80 70 140 ma 2 memory devices 16 160 250 32 320 500 48 480 750 64 650 1000 iccd vcc power-down current 80 2 800 1250 a vcc = vccmax control signals = vcc reset = vcc (active) 16 0.2 0.4 32 0.4 0.7 48 0.6 1.0 64 0.8 1.3 iccs (cmos) vcc standby current 80 2 1.0 1.6 ma vcc = vccmax control signals = vcc reset = 0v (not active) notes: 1. all currents are rms values unless otherwise specified. iccr, iccw and icce are based on word wide operations (2 memory devices activated). 2. control signals: ce 1 #, ce 2 #, oe#, we#. 3. typical: vcc = 5v, t = +25c. cmos test conditions: vcc = 5v 5%, vil = vss 0.2v, vih = vcc 0.2v dc characteristics (1) symbol parameter notes min max units test conditions ili input leakage current 1, 2 20 a vcc = vccmax vin =vcc or gnd ilo output leakage current 1 20 a vcc = vccmax vin =vcc or gnd vil input low voltage 1 0 0.8 v vih input high voltage 1 0.7xvcc vcc+0.5 v vol output low voltage 1 0.4 v iol = 3.2ma voh output high voltage 1 vcc-0.4 vcc v ioh = -2.0ma vlko vcc erase/program lock voltage 13.25 v notes: 1. values are the same for byte and word wide modes for all card densities. 2. exception: leakage current on control signals with internal pull up resistors (see block diag) will be < 500 a when vin=gnd .
june 2000 rev. 3 - eco #12871 7 pcmcia flash memory card flf series pc card products 200n s 250n s symbol (pcmcia) parameter min max min max unit t rc read cycle time 200 250 ns t a (a) address access time 200 250 ns t a (ce) card enable access time 200 250 ns t a (oe) output enable access time 90 100 ns t su (a) address setup time 20 30 ns t su (ce) card enable setup time 0 0ns t h (a) address hold time 20 20 ns t h (ce) card enable hold time 20 20 ns t v (a) output hold from address change 0 0ns t dis (ce) output disable time from ce# 90 100 ns t dis (oe) output disable time from oe# 90 100 ns t dis (ce) output enable time from ce# 5 5ns t dis (oe) output enable time from oe# 5 5ns t rec (rst) power down recovery to output delay. vcc = 5v 500 500 ns ac characteristics note: ac timing diagrams and characteristics are guaranteed to meet or exceed pcmcia 2.1 specifications. read timing diagram note 1 note 1 a [25::0], /reg /ce1, /ce2 /oe d[15::0] tc(r) ta(a) th(a) tv(a) ta(ce) tsu(ce) th(ce) ten(oe) ta(oe) tsu(a) data valid tdis(ce) tdis(oe) read timing parameters
june 2000 rev. 3 - eco #12871 8 pcmcia flash memory card flf series pc card products 200ns 250ns symbol (pcmcia) parameter min max min max unit t c w write cycle time 200 250 ns t w (we) write pulse width 120 150 ns t su (a) address setup time 20 30 ns t su (a-weh) address setup time for we# 140 180 ns t su (ce-weh) card enable setup time for we# 140 180 ns t su (d-weh) data setup time for we# 60 80 ns t h (d) data hold time 30 30 ns t rec (we) write recover time/address hold 30 30 ns t dis (we) output disable time from we# 90 100 ns t dis (oe) output disable time from oe# 90 100 ns t en (we) output enable time from we# 5 5ns t dis (oe) output enable time from oe# 5 5ns t su (oe-we) output enable setup from we# 10 10 ns t h (oe-we) output enable hold from we# 50 50 ns t su (ce) card enable setup time from oe# 0 0ns t h (ce) card enable hold time 20 20 ns t rec (wel) reset recovery to we going low 1 1 s note: ac timing diagrams and characteristics are guaranteed to meet or exceed pcmcia 2.1 specifications. write timing diagram write timing parameters th(oe-we) note 1 /ce1, /ce2 note 1 tsu(ce-weh) tc(w) a[25::0], /reg tw(we) tdis(we) th(d) d[15::0](din) data input tsu(a) tsu(a-weh) /oe tsu(ce) tsu(d-weh) trec(we) th(ce) tsu(oe-we) tdis(oe) d[15::0]( dout) ten(oe) ten(we) note 2 note 2 /we
june 2000 rev. 3 - eco #12871 9 pcmcia flash memory card flf series pc card products sym parameter notes min typ (1) max units test conditions t whqv1 word/byte program time 2,4 6 s effective time per byte (using write buffer) t whqv3 byte program time (using byte program command) 120 s block program time (using write to buffer command) 2 0.8 sec word program mode t whqv4 block erase time 2 1.0 sec t whrh erase suspend latency time to read 25 35 s data write and erase performance (1,3) notes: 1. typical: nominal voltages and t a = 25c. 2. excludes system overhead. 3. valid for all speed options. 4. to maximize system performance rdy/bsy# signal should be polled. vcc = 5v 5%, t a = 0c to + 70c symbol parameter min max unit t w(rst) reset pulse high time 35 s p2 rst low to reset during erase/program/lock-bit 100 ns t rec(rst) reset low to output delay 500 ns t rec(wel) reset recovery to we going low 1 s t whrl we high to rdy/bsy going low 100 ns waveforms for reset operation tw(rst) p2 rdy/bsy rst valid output t rec (rst) t rec (wel) we# read operation write operation t whrl t whqv t whrh
june 2000 rev. 3 - eco #12871 10 pcmcia flash memory card flf series pc card products edi company name lot code / trace number date code part number product marking wed 7p016flf0200c15 c995 9915 note: some products are currently marked with our pre-merger company name/acronym (edi). during our transition period, some products will also be marked with our new company name/acronym (wed). starting october 2000 all pcmcia products will be marked only with the wed prefix. card capacity 016 16mb packaging option 00 standard, type 1 pc card p standard pcmcia r ruggedized pcmcia card family and version - see card family and version info. for details (next page) temperature range c commercial 0c to +70c i industrial -40c to +85c card access time 15 150ns 25 250ns card technology 7flash 8sram part numbering 7 p 016 flf02 00 c 15
june 2000 rev. 3 - eco #12871 11 pcmcia flash memory card flf series pc card products cis data for 16-64mb cards based on intel 28f640j5 address v alue description address v alue description 00h 01h cistpl_device 4eh 1bh cistpl_cftable_entr y 02h 03h tpl_link 50h 03h tpl_link 04h 51h flash = 250ns (device writable) 52h 00h tpce_index 06h 3eh card size: 16mb 54h 00h tpce_fs (no selection) 7eh 32mb 56h ffh end of tuple beh 48mb 58h 15h cistpl_vers1 feh 64mb 5ah 47h tpl_link 08h ffh end of tuple 5ch 05h tpllv1_major 0ah 18h cistpl_jedec_c 5eh 00h tpllv1_minor 0ch 03h tpl_link 60h 45h e 0eh 89h intel - id 62h 44h d 10h 15h intel 28f640j5 - id 64h 49h i 12h ffh end of tuple 66h 37h 7 14h 17h cistpl_device_a 68h 50h p 16h 03h tpl_link 6ah 30h 0 18h 42h eeprom - 200ns 6ch 34h 4 1ah 01h device size = 2kbytes 6eh 38h 8 1ch ffh end of tuple 70h 46h f 1eh 1eh cistpl_devicegeo 72h 4ch l 20h 07h tpl_link 74h 46h f 22h 02h dgtpl_bus 76h 30h 0 24h 12h dgtpl_ebs 78h 32h 2 26h 01h dgtpl_rbs 7ah 2dh - 28h 01h dgtpl_wbs 7ch 2dh - 2ah 01h dgtpl_part 7eh 2dh - 2ch 01h flash device 80h 32h 2 non-interleaved 82h 35h 5 2eh ffh end of tuple 84h 20h space 30h 20h cistpl_manfid 86h 00h end text 32h 05h tpl_link(04h) 88h 43h c 34h f6h edi tplmid_manf: lsb 8ah 4fh o 36h 01h edi tplmid_manf: msb 8ch 50h p 38h 00h lsb: number not assigned 8eh 59h y 3ah 00h msb: number not assigned 90h 52h r 3ch ffh end of tuple 92h 49h i 3eh 1ah cistpl_conf 94h 47h g 40h 06h tpl_link 96h 48h h 42h 01h tpcc_sz 98h 54h t 44h 00h tpcc_last 9ah 20h space 46h 00h tpcc_radr 9ch 45h e 48h 40h tpcc_radr 9eh 4ch l 4ah 03h tpcc_rmsk a0h 45h e a ddress v alue description a4h 54h t a6h 52h r a8h 4fh o aah 4eh n ach 49h i aeh 43h c b0h 20h space b2h 44h d b4h 45h e b6h 53h s b8h 49h i bah 47h g bch 4eh n beh 53h s c0h 20h space c2h 49h i c4h 4eh n c6h 43h c c8h 4fh o cah 52h r cch 50h p ceh 4fh o d0h 52h r d2h 41h a d4h 54h t d6h 45h e d8h 44h d dah 20h space dch 00h end text deh 31h 1 e0h 39h 9 e2h 39h 9 e4h 38h 8 e6h 00h end text e8h ffh end of list eah ffh
june 2000 rev. 3 - eco #12871 12 pcmcia flash memory card flf series pc card products address v alue description address v alue description 00h 01h cistpl_device 50h 20h cistpl_manfid 02h 03h tpl_link 52h 04h tpl_link(04h) 04h 51h flash = 250ns (device writable) 54h f6h edi tplmid_manf: lsb 06h feh card size: 64mb(1 st page) 56h 01h edi tplmid_manf: msb 08h ffh end of tuple 58h 00h lsb: number not assigned 0ah 09h cistpl_extdevice 5ah 00h msb: number not assigned 0ch 06h tpl_link 5ch 15h cistpl_vers1 0eh 04h mem paging info: 1bit/cor/64m 5eh 47h tpl_link 10h 51h flash = 250ns 60h 05h tpllv1_major 12h 07h device size extender 62h 00h tpllv1_minor 14h 01h 1x64mb 64h 45h e 16h 3eh +16mb 66h 44h d 18h ffh end of tuple 68h 49h i 1ah 1ah cistpl_conf 6ah 37h 7 1ch 06h tpl_link 6ch 50h p 1eh 01h tpcc_sz 6eh 30h 0 20h 00h tpcc_last(no index descript) 70h 38h 8 22h 00h tpcc_radr: lsbyte 72h 30h 0 24h 40h tpcc_radr: msbyte 74h 46h f 26h 03h tpcc_rmsk: 2 reg 76h 4ch l 28h ffh end of tuple 78h 46h f 2ah 18h cistpl_jedec_c 7ah 30h 0 2ch 03h tpl_link 7ch 32h 2 2eh 89h intel - id 7eh 2dh - 30h 15h intel 28f640j5 - id 80h 2dh - 32h ffh end of tuple 82h 2dh - 34h 17h cistpl_device_a 84h 32h 2 36h 03h tpl_link 86h 35h 5 38h 42h eeprom - 200ns 88h 20h space 3ah 01h device size = 2kbytes 8ah 00h end text 3ch ffh end of tuple 8ch 43h c 3eh 1eh cistpl_devicegeo 8eh 4fh o 40h 07h tpl_link 90h 50h p 42h 02h dgtpl_bus 92h 59h y 44h 12h dgtpl_ebs 94h 52h r 46h 01h dgtpl_rbs 96h 49h i 48h 01h dgtpl_wbs 98h 47h g 4ah 01h dgtpl_part 9ah 48h h 4ch 01h flash device 9ch 54h t non-interleaved 9eh 20h space 4eh ffh end of tuple a ddress value description a0h 45h e a2h 4ch l a4h 45h e a6h 43h c a8h 54h t aah 52h r ach 4fh o aeh 4eh n b0h 49h i b2h 43h c b4h 20h space b6h 44h d b8h 45h e bah 53h s bch 49h i beh 47h g c0h 4eh n c2h 53h s c4h 20h space c6h 49h i c8h 4eh n cah 43h c cch 4fh o ceh 52h r d0h 50h p d2h 4fh o d4h 52h r d6h 41h a d8h 54h t dah 45h e dch 44h d deh 20h space e0h 00h end text e2h 31h 1 e4h 39h 9 e6h 39h 9 e8h 38h 8 eah 00h end text ech ffh end of list eeh ffh cistpl_end d2h ffh cis data for 80mb card based on intel 28f640j5
june 2000 rev. 3 - eco #12871 13 pcmcia flash memory card flf series pc card products white electronic designs corporation one research drive, westborough, ma 01581, usa tel: (508) 366 5151 fax: (508) 836 4850 www.whiteedc.com date of revision version description 20-mar-98 -001 initial release 27-may-99 -002 logo change 5-jun-00 -003 added page 10, changed page header revision history

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