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data sheet, v 1.3, jun. 2006 microcontrollers CIC751 companion ic www.datasheet.co.kr datasheet pdf - http://www..net/
edition 2006-06 published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 2006. all rights reserved. attention please! the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet, v 1.3, jun. 2006 microcontrollers CIC751 companion ic www.datasheet.co.kr datasheet pdf - http://www..net/
template: mc_a5_ds_tmplt.fm / 5 / 2006-01-20 CIC751 confidential revision history: 2006-06 v1.3 previous version: none. page subjects (major changes since last revision) 25 chapter 4.4.4. power sequencing was reworked for version 1.2 25 chapter 4.4.4. power sequencing was reworked for version 1.3 33 table 4-13 updated for version 1.3 we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 table of contents confidential data sheet 1 v 1.3, 2006-06 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 pin configuration and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 detailed features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.2 mli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.3 ssc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 analog/digital converter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.1 definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.1.1 prescaler mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.1.2 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.2 testing waveforms of the digital input/output signals . . . . . . . . . . . . . . 23 4.4.3 output rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4.4 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4.5 timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4.5.1 micro link interface (mli) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4.6 synchronous serial channel (ssc) slave mode timing . . . . . . . . . . . . 30 4.5 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.5.1 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.5.2 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.5.3 quality declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table of contents www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 table of contents confidential data sheet 2 v 1.3, 2006-06 www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 summary of features confidential data sheet 3 v 1.3, 2006-06 1 summary of features this section provides a high-level description of the features on the CIC751. 5 v analog to digital converter 16 analog input channels internal low power oscillator slave (spi) ssc interface operating on 5 v or 3.3 v mli interface operating on 5 v or 3.3 v maximum system frequency of 40 mhz low-power design single power supply concept design (for pad and core supply) separated adc supply input and output pins with 3.3 v and 5.0 v flexible clocking concept crossbar bus architecture ordering information the ordering code for infineon microcontrollers provides an exact reference to the required product. this ordering code identifies: the derivative itself, i.e. its function set, the temperature range, and the supply voltage the package and the type of delivery. for the available ordering codes for the CIC751 please refer to the ?product catalog microcontrollers? , which summarizes all available microcontroller variants. www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 general device information confidential data sheet 4 v 1.3, 2006-06 2 general devi ce information 2.1 introduction the CIC751 is a companion ic for the infineon audo-ng family of 32-bit microcontrollers. the major function of the CIC751 is to provide the audo-ng 32-bit microcontrollers with the capability of a 5 v analog to digital converter (adc). the interconnection of the CIC751 and the microcontroller is accomplished via either the micro link interface (mli) or the synchronous serial interface (ssc). internal operations of the CIC751 are supported by the very flexible on-chip dma controller. 2.2 pin configuration and definition the pins of the CIC751 are described in detail in table 2-1 , including all their alternate functions. table 2-1 pin definitions and functions symbol pin/port i/o function ain0 35 p1.0 i analog input 0 1) for this pin a multiplexer test mode is available. ain1 36 p1.1 i analog input 1 1) ain2 37 p1.2 i analog input 2 1) ain3 38 p1.3 i analog input 3 1) ain4 1 p1.4 i analog input 4 1) ain5 2 p1.5 i analog input 5 1) ain6 7 p1.6 i analog input 6 1) ain7 8 p1.7 i analog input 7 1) ain8 5 p1.8 i analog input 8 1) ain9 6 p1.9 i analog input 9 1) www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 general device information confidential data sheet 5 v 1.3, 2006-06 ain10 3 p1.10 i analog input 10 1) ain11 4 p1.11 i analog input 11 1) ain12 11 p1.12 i analog input 12 1) ain13 12 p1.13 i analog input 13 1) ain14 13 p1.14 i analog input 14 1) ain15 14 p1.15 i analog input 15 1) varef 9 i analog reference voltage vagnd 10 i analog ground tclk/sr3 17 p0.0 i/o mode = 0: mli transmit channel clock output mode = 1: event output line 3 tready/sr4 19 p0.1 i/o mode = 0: mli transmit channel ready input mode = 1: event request output line 4 tvalid/sclk 20 p0.2 i/o mode = 0: mli transmit channel valid output mode = 1: spi serial channel clock tdata/mrst 21 p0.3 i/o mode = 0: mli transmit channel data output mode = 1: spi master receive slave transmit rclk 22 p0.4 i/o mode = 0: mli receive channel clock input mode = 1: gpio table 2-1 pin definitions and functions (cont?d) symbol pin/port i/o function www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 general device information confidential data sheet 6 v 1.3, 2006-06 rready/rdy 23 p0.5 i/o mode = 0: mli receive channel ready output mode = 1: ssc ready signal rvalid/sls 24 p0.6 i/o mode = 0: mli receive channel valid input mode = 1 : ssc select slave rdata/mtsr 25 p0.7 i/o mode = 0: mli receive channel data input mode = 1 : spi master transmit slave receive mode 2) 26 p0.8 i/o interface selection pin mode selects whether the on-chip mli or ssc are used to access the CIC751 device. 0: on-chip mli 1: on-chip ssc event request output line 5 (sr5) testmode 3) 27 p0.9 i/o test mode selection 4) 0: reserved; do no use 1: normal mode sr0 28 p0.10 i/o event request output line 0 sr1 29 p0.11 i/o external trigger sr2 30 p0.12 i/o external trigger porst 31 i power-on reset 5) v ddm 34 +5 v power supply, supply for adc module v ddp 18, 33 +3.3 v or +5.0 v power supply, supply for i/o pads v ddc 16 +2.5 v power supply, supply for digital module cores 6) v ss 15, 32 0 v ground table 2-1 pin definitions and functions (cont?d) symbol pin/port i/o function www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 general device information confidential data sheet 7 v 1.3, 2006-06 figure 2-1 shows the pin-out for a 38-pin package 1) in addition to the analog input function of pin p1.x, a digital input stage is available. this input stage is activated while stcu_syscon.p1didis = 0. 2) the initial logic state on pin mode is latched while the porst input is active. a weak pull-up can be disabled if used as the sr5 pin. 3) the initial logic state on pin testmode is latched while the porst input is active. 4) the meaning of 0 and 1 is only valid while this pin is latched. thereafter it can be used as gpio pin. 5) this pin has no internal pulls. if required an external pull has to be provided. 6) an external capacitance of 220 nf is required for this pin. www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 general device information confidential data sheet 8 v 1.3, 2006-06 figure 2-1 pins for p/pg-tssop-38 package mli ssc scu adc power modules ports pins p0 po rt control p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 ports varef vagnd ain0 ain15 vddm vddc vddp vss tclk / s r3 tready/sr4 tvalid/sclk tdata/mrst rclk rready/rd y rvalid/sls rda ta / m ts r porst sr0 m ode/sr5 testmode function p0.11 p0.12 p1 po rt control p1.15 p1.0 sr1 sr2 2 2 www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 general device information confidential data sheet 9 v 1.3, 2006-06 figure 2-2 pin numbering for p/pg-tssop-38 package pac kage_3 8 CIC751 138 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain1 0 ain1 1 ain1 2 ain1 3 ain1 4 ain1 5 varef vagnd tclk/sr3 tready/sr4 tvalid/sclk tdata/mrst rclk rready/rdy rvalid/sls rdata/mtsr mode testmode sr0 sr1 sr2 porst vddm vddp vddp vddc vss vss www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 functional description confidential data sheet 10 v 1.3, 2006-06 3 functional description figure 3-1 provides the block diagram of the CIC751 companion chip. this design allows access to the adc by the host cpu without sacrificing any of the features of the adc. this can be achieved because all registers of the adc are mapped to the on-chip bus. this bus can be accessed via one of the two serial interfaces. selection of the interface is made via pin mode, which can be directly connected to the supply voltage or via pull-up/down resistors. the bus domain is completely separated from the address domain on the cpu chip. the addresses of all modules on the companion chip are 32-bit addresses. transactions between the cpu and the ssc are executed with the ssc transmission protocol; transactions between the mli and the cpu use the mli transmission protocol. each transaction via any of the two serial interfaces is defined by address, data, data width, and type of frame. the address from wh ich data is read or written to, is related to the address domain. the data width may be 8, 16 or 32 bits for the mli and 16 bits for the ssc. the adc and the mli may send request triggers to the dma controller. figure 3-1 CIC751 block diagram 3.1 detailed features the following sections provide detailed information about each of the on-chip modules. bl oc k_ d iagram bu s switch dma master sla ve scu sla ve mli master sla ve ssc master sla ve adc slave ports www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 functional description confidential data sheet 11 v 1.3, 2006-06 3.1.1 adc the CIC751 provides an analog/digital converter with 8-bit or 10-bit resolution and a sample & hold circuit on-chip. an input multiplexer selects between up to 16 analog input channels either via software (fixed channel modes) or automatically (auto scan modes). to fulfill most requirements of embedded control applications, the adc supports the following conversion modes: standard conversions ? fixed channel single conversion produces just one result from the selected channel ? fixed channel continuous conversion repeatedly converts the selected channel ? auto scan single conversion produces one result from each of a selected group of channels ? auto scan continuous conversion repeatedly converts the selected group of channels ? wait for read mode start a conversion automatically when the previous result was read channel injection mode can insert the conversion of a specific channel into a group conversion (auto scan) the key features of the adc are: use of successive approximation method integrated sample and hold functionality analog input voltage range from 0v to 5v 16 analog input channels 16 adc result registers resolution: 8-bit or 10-bit in compatibility mode minimum conversion time:2.55 s @ 10-bit total unadjusted error (tue): 1 lsb @ 8-bit, 2 lsb @10-bit support of several conversion modes fixed channel single conversion fixed channel continuous conversion auto scan single conversion auto scan continuous conversion wait for result read and start next conversion channel injection during group conversion programmable conversion and sample timing scheme automatic self-calibration to changing temperatures or process variations www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 functional description confidential data sheet 12 v 1.3, 2006-06 3.1.2 mli the micro link interface (mli) is a fast synchronous serial interface that makes it possible to exchange data between microcontrollers or other devices. the key features of the mli are: synchronous serial communication between an mli transmitter and an mli receiver different system clock speeds are supported in the mli transmitter and mli receiver due to full handshake protocol (4 lines between a transmitter and a receiver) fully transparent read/write access is supported (= remote programming) complete address range of target device (remote controller) is available specific frame protocol to transfer commands, addresses, and data error detection by parity bit 32-bit, 16-bit, or 8-bit data transfers are supported programmable baud rate: f mli /2 (max.: f mli = f sys ) multiple receiving devices are supported 3.1.3 ssc the ssc supports full-duplex and half-duplex serial synchronous communication up to 10 mbit/s (@ 40 mhz module clock). the serial clock signal is received from an external master (slave mode). data width, shift direction, clock polarity, and phase are programmable. this allows communication with spi-compatible devices. transmission and reception of data is double-buffered. a shift clock generator provides the ssc with a separate serial clock signal. this section describes only the use of the ssc module as a slave because the CIC751 always operates as a slave to a host. features slave mode operation ? full-duplex or half-duplex operation ? automatic pad control possible flexible data format ? programmable shift direction: lsb or msb shift first ? programmable clock polarity: idle low or idle high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock internal master function ? access to the all addresses ? automatic address handling ? automatic data handling www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 13 v 1.3, 2006-06 4 electrical parameters the electrical specifications comprise parameters to ensure the product?s lifetime (absolute maximum parameters) as well as parameters to describe the product?s operating conditions. 4.1 general parameters stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions (v in >v dd or v in CIC751. all parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. table 4-1 absolute maximum ratings parameter symbol values unit note / test condit ion min. typ. max. storage temperature t st -65 ? 150 c? voltage on v ddc pins with respect to ground (v ss ) v ddc -0.5 ? 3.25 v ? voltage on v ddp pins with respect to ground (v ss ) v ddp -0.5 ? 6.2 v ? voltage on any pin with respect to ground (v ss ) v in -0.5 ? v ddp + 0.5 v? input current on any pin during overload condition ?-10?10ma? absolute sum of all input currents during overload condition ???|100|ma? junction temperature t j -40 ? 150 c under bias www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 14 v 1.3, 2006-06 table 4-2 operating condition parameters parameter symbol values unit note / test condit ion min. typ. max. system frequency f sys ??40 mhz? rcosc output frequency f rcosc 8 9 10 mhz over all conditions digital supply voltage for the core v ddc 2.25 ? 2.75 v active mode, f sys = f sysmax 1) 1) f sysmax = 40 mhz digital supply voltage for io pads for 5 v mode v ddp 4.5 5.0 5.5 v active mode 2)3) 2) external circuitry must guarantee low-level at the porst pin at least until both power supply voltages have reached the operating range. 3) the specified voltage range is allowed for operation. the range limits may be reached under extreme operating conditions. however, specified parameters, such as leakage currents, refer to the standard operating voltage range of v ddp = 4.5 v to 5.5 v. digital supply voltage for io pads for 3.3 v mode v ddp 3.13 3.3 3.47 v active mode 4)5) 4) external circuitry must guarantee low-level at the porst pin at least until both power supply voltages have reached the operating range. supply voltage difference for io pads in 5.0 v mode ? v dd -0.5 ? ? v v ddp - v ddc 6) digital ground voltage v ss 0 ? ? v reference voltage overload current i ov -5 ? 5 ma per io pin 7)8) -2 ? 5 ma per analog input pin 7)8) overload current coupling factor for analog inputs 9) k ova ? ? 1.0 10 -4 ?i ov > 0 ? ? 1.5 10 -3 ?i ov < 0 overload current coupling factor for digital i/o pins 9) k ovd ? ? 5.0 10 -3 ?i ov > 0 ? ? 1.0 10 -2 ?i ov < 0 absolute sum of overload currents |i ov |? ? 50 ma 8) external load capacitance c l ? ? 50 pf www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 15 v 1.3, 2006-06 4.2 dc parameters the following chapter describes the dc parameters of the device. 5) the specified voltage range is allowed for operation. the range limits may be reached under extreme operating conditions. however, specified parameters, such as leakage currents, refer to the standard operating voltage range of v ddp = 4.5 v to 5.5 v. 6) this limitation must be fulfilled under all operating conditions including power-ramp-up and power-ramp-down. 7) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: v ov > v ddp + 0.5 v (i ov > 0) or v ov < v ss - 0.5 v (i ov < 0). the absolute sum of input overload currents on all pins may not exceed 50 ma . the supply voltages must remain within the specified limits. proper operation is not guaranteed if overload conditions occur on functional pins. 8) not subject to production test - verified by design/characterization. 9) an overload current (i ov ) through a pin injects a certain error current ( i inj ) into the adjacent pins. this error current adds to the respective pin?s leakage current ( i oz ). the amount of error current depends on the overload current and is defined by the overload coupling factor k ov . the polarity of the injected error current is inverse compared to the polarity of the overload current that produces it. the total current through a pin is | i tot | = | i oz | + (| i ov | k ov ). the additional error current may distort the input voltage on analog inputs. table 4-3 dc characteristics (operating conditions apply) 1) parameter symbol values unit note / test condition min. typ. max. input low voltage ttl v il ? ? 0.3 v ddp v 2) input low voltage (special threshold) v ils ? ? 0.45 v ddp v 3) input high voltage ttl v ih 0.7 v ddp ?? v 2) input high voltage (special threshold) v ihs 0.8 v ddp - 0.2 ?v ddp + 0.5 v 3) input hysteresis (special threshold) hys 0.02 v ddp ?? vv ddp in [v], series resistance = 0 ? 3) output low voltage v ol ??1.0vi ol = 8ma 4) ? ? 0.45 v i ol = 2.5 ma 4)5) output high voltage 6) v oh v ddp - 1.0 ? ? v i oh = -8ma 4) v ddp - 0.45 ?? vi oh = - 2.5 ma 4)5) input leakage current (port 1) 7) i oz1 ?? 300 na 0 v < v in < v ddm , t a 125 c www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 16 v 1.3, 2006-06 leakage current of pin varef (idle mode) i varefim ?? 800 na 0 v < v in < v ddp , t a 125 c leakage current of pin varef (active mode) i varefam ?? 20 + i varefim a0 v < v in < v ddp , t a 125 c input leakage current (port 0) 7) i oz2 ?? 500 na 0.45 v < v in < v ddp configuration pull-up current 8) i cpuh 9) ??-5 av in = v ihmin i cpul 10) -100 ? ? av in = v ilmax level active hold current i lha 11) -100 ? ? av out = 0.45 v pin capacitance 12) digital inputs/outputs c io ? ? 10 pf ? 1) keeping signal levels within the limits specified in this table, ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . 2) this parameter is tested for porst 3) this parameter is tested for p0. 4) the maximum deliverable output current of a port driver depends on the selected output driver mode, see table 4-4 , current limits for port output drivers . the limit for pin groups must be respected. 5) as a rule, with decreasing output current the output levels approach the respective supply level (v ol v ss , v oh v ddp ). however, only the levels for nominal output currents are guaranteed. 6) this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the voltage results from the external circuitry. 7) an additional error current (i inj ) will flow if an overload current flows through an adjacent pin. please refer to the definition of the overload coupling factor k ov . 8) this specification is valid during reset for configuration on port0. 9) the maximum current may be drawn while the respective signal line remains inactive. 10) the minimum current must be drawn to drive the respective signal line active. 11) the minimum current must be drawn to drive the respective signal line active. 12) only one point on the curve is tested in production. the rest of the curve is verified by design/characterization. table 4-3 dc characteristics (operating conditions apply) 1) (cont?d) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 17 v 1.3, 2006-06 4.3 analog/digital converter parameters the parameters of the adc module are described below. table 4-4 current limits for port output drivers port output driver mode maximum output current (i olmax , -i ohmax ) 1) nominal output current (i olnom , -i ohnom ) strong driver 2)3) 8 ma 2.5 ma strong driver 4)5) 10 ma 2.5 ma medium driver 6) 4.0 ma 1.0 ma weak driver 6) 0.5 ma 0.1 ma 1) an output current above |i oxnom | may be drawn from up to three pins at the same time. for any group of 16 neighboring port output pins the total output current in each direction ( i ol and - i oh ) must remain below 50 ma. 2) for 3.3 v operation. 3) the strong driver is used for all pins beside pin 35 (ain0) 4) for 5.0 v operation. 5) the strong driver is used for all pins beside pin 35 (ain0) 6) the medium / weak driver is only used for pin 35 (ain0) table 4-5 power consumption CIC751 parameter symbol values unit note / test condition min. typ. max. power supply current (active) with all peripherals active i ddc ? ? 30 ma at 40 mhz system frequency power supply current (active) with all peripherals active i ddc ? ? 18 ma at 20 mhz system frequency pad i/o current i ddp ?4 ? ma v ddm supply current i ddm ?? 5 ma www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 18 v 1.3, 2006-06 table 4-6 a/d converter characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. analog supply voltage v ddm 4.5 5.0 5.5 v 1) analog reference supply v aref 4.5 ? v ddm + 0.1 v 2) analog reference ground v agnd v ss - 0.1 ? v ss + 0.1 v? analog input voltage range v ain v agnd ?v aref v 3) basic clock frequency f bc 0.5 ? 20 mhz 4) conversion time for 10-bit result 5) t c10p 52 t bc + t s + 6 t sys ? ? ? post-calibr. on t c10 40 t bc + t s + 6 t sys ? ? ? post-calibr. off conversion time for 8-bit result 5) t c8p 44 t bc + t s + 6 t sys ? ? ? post-calibr. on t c8 32 t bc + t s + 6 t sys ? ? ? post-calibr. off calibration time after reset t cal 484 ? 11,696 t bc 6) total unadjusted error tue ? ? 2lsb 2) total capacitance of an analog input c aint ? ? 15 pf 7) switched capacitance of an analog input c ains ? ? 10 pf 7) resistance of the analog input path r ain ??2k ? 7) total capacitance of the reference input c areft ? ? 20 pf 7) switched capacitance of the reference input c arefs ? ? 15 pf 7) resistance of the reference input path r aref ??1k ? 7) www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 19 v 1.3, 2006-06 figure 4-1 equivalent circuitry for analog inputs sample time and conversion time of the CIC751?s a/d converter are programmable. in compatibility mode, the above timing can be calculated using table 4-7 . the limit values for f bc must not be exceeded when selecting adctc. 1) the specified voltage range is allowed for operation. the range limits may be reached under extreme operating conditions. however, specified parameters, such as leakage currents, refer to the standard operating voltage range of v ddm = 4.5 v to 5.5 v. 2) tue is tested at v aref = v ddp + 0.1 v, v agnd = 0 v. it is verified by design for all other voltages within the defined voltage range. if the analog reference supply voltage drops below 4.5 v (i.e. v aref 4.0 v) or exceeds the power supply voltage by up to 0.2 v (i.e. v aref = v ddp + 0.2 v) the maximum tue is increased to 3 lsb. this range is not subject to production test. the specified tue is guaranteed only, if the absolute sum of input overload currents on port 1 pins (see i ov specification) does not exceed 10 ma, and if v aref and v agnd remain stable during the respective period of time. during the reset calibration sequence the maximum tue may be 4lsb. 3) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. 4) the limit values for f bc must not be exceeded when selecting the peripheral frequency and the adctc setting. 5) this parameter includes the sample time t s , the time for determining the digital result and the time to load the result register with the conversion result (t sys = 1/ f sys ). values for the basic clock t bc depend on programming and can be taken from table 4-7 . when the post-calibration is switched off, the conversion time is reduced by 12 x t bc . 6) the actual duration of the reset calibration depends on the noise on the reference signal. conversions executed during the reset calibration increase the calibration time. the tue for those conversions may be increased. 7) not subject to production test - verified by design/characterization. the given parameter values cover the complete operating range. under relaxed operating conditions (temperature, supply voltage) reduced values can be used for calculations. at room temperature and nominal supply voltage the following typical values can be used: c ainttyp = 12 pf, c ainstyp = 7 pf, r aintyp = 1.5 k ? , c arefttyp = 15 pf, c arefstyp = 13 pf, r areftyp = 0.7 k ? . a/d converter mcs05570 r sour ce v ain c ext c aint c ains - r ain, on c ains www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 20 v 1.3, 2006-06 converter timing example table 4-7 a/d converter computation table 1) 1) these selections are available in compatibility mode. an improved mechanism to control the adc input clock can be selected. adcon.15|14 (adctc) a/d converter basic clock f bc adcon.13|12 (adstc) sample time t s 00 f sys / 4 00 t bc 8 01 f sys / 2 01 t bc 16 10 f sys / 16 10 t bc 32 11 f sys / 8 11 t bc 64 assumptions: f sys = 40 mhz (i.e. t sys = 25 ns), adctc = ?01?, adstc = ?00? basic clock f bc = f sys / 2 = 20 mhz, i.e. t bc = 50 ns sample time t s = t bc 8 = 400 ns conversion 10-bit: with post-calibr. t c10p = 52 t bc + t s + 6 t sys = (2600 + 400 + 150) ns = 3.15 s post-calibr. off t c10 = 40 t bc + t s + 6 t sys = (2000 + 400 + 150) ns = 2.55 s conversion 8-bit: with post-calibr. t c8p = 44 t bc + t s + 6 t sys = (2200 + 400 + 150) ns = 2.75 s post-calibr. off t c8 = 32 t bc + t s + 6 t sys = (1600 + 400 + 150) ns = 2.15 s www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 21 v 1.3, 2006-06 4.4 ac characteristics the internal operation and consequently the timings of the CIC751 are based on the internal system clock f sys . 4.4.1 definition of internal timing the system clock signal f sys can be generated from the oscillator clock signal f osc or from the clock applied to the rclk pin via different mechanisms. the duration of system clock periods and their variation (and also the derived external timing) depend on the used mechanism to generate f sys . this influence must be regarded when calculating the timings for the CIC751. the used mechanism to generate the system clock is selected by register pllcon. 4.4.1.1 prescaler mode when prescaler mode is configured (scu_pllcon.pllctrl = 01 b ) the system clock is derived from the internal oscillator through the p- and k-dividers: f sys = f osc / ((scu_pllcon.pdiv+1) (scu_pllcon.kdiv+1)). if both divider factors are selected as ?1? (scu_pllcon.pdiv = scu_pllcon.kdiv = ?0?) the frequency of f sys directly follows the frequency of f osc so the high and low time of f sys is defined by the duty cycle of the input clock f osc . the lowest system clock frequency is achieved by selecting the maximum values for both divider factors: f sys = f osc / ((3+1) (14+1)) = f osc / 60. 4.4.1.2 phase locked loop (pll) when pll operation is configured (scu_pllcon.pllctrl = 11 b ) the on-chip phase locked loop is enabled and provides the system clock. the pll multiplies the input frequency by the factor f ( f sys = f osc f) which results from the input divider, the multiplication factor, and the output divider (f = scu_pllcon.ndiv+1 / (scu_pllcon.pdiv+1 scu_pllcon.kdiv+1)). the pll circuit synchronizes the system clock to the input clock. this synchronization is done smoothly, i.e. the system clock frequency does not change abruptly. due to this adaptation to the input clock the frequency of f sys is constantly adjusted so it is locked to f osc . the slight variation causes a jitter of f sys which also affects the duration of individual tcms. the actual minimum value for tcm depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so it corresponds to the applied input frequency the relative deviation for periods of more than one tcm is lower than for one single tcm (see formula and figure 4-2 ). www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 22 v 1.3, 2006-06 this is especially important for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is negligible. the value of the accumulated pll jitter depends on the number of consecutive vco output cycles within the respective time frame. the vco output clock is divided by the output prescaler (k = scu_pllcon.kdiv+1) to generate the system clock signal f sys . therefore, the number of vco cycles can be represented as k n , where n is the number of consecutive f sys cycles (tcm). for a period of n n tcm the accumulated pll jitter is defined by the deviation d: d n [ns] = (1.5 + 6.32 n / f sys ); f sys in [mhz], n = number of consecutive tcms. so, for a period of 3 tcms @ 20 mhz and k = 12: d 3 = (1.5 + 6.32 3 / 20) = 2.448 ns. this formula is applicable for k n < 95. for longer periods the k n =95 value can be used. this steady value can be approximated by: d nmax [ns] = (1.5 + 600 / (k f sys )). figure 4-2 approximated accumulated pll jitter note: the bold lines indicate the minimum accumulated jitter which can be achieved by selecting the maximum possible output prescaler factor k. different frequency bands can be selected for the vco, so the operation of the pll can be adjusted to a wide range of input and output frequencies: mcb04413_xc.vsd acc. jitter d n 8 6 ns 4 2 1 0 510 20 25 n 1 0 m h z k=5 2 0 m h z 4 0 m h z 7 5 3 15 k=6 k=12 k=15 k=8 k=10 1 www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 23 v 1.3, 2006-06 4.4.2 testing waveforms of the digital input/output signals the relation between a real and the ideal digital waveform, together with the characteristically measurement levels is shown below. figure 4-3 input output waveforms the figure below shows the transition between an actively driven digital output level and three-state (input state). table 4-8 vco bands for pll operation 1) 1) not subject to production test - verified by design/characterization. pllcon.pllvb vco frequency range base frequency range 00 100 150 mhz 20 80 mhz 01 150 200 mhz 40 130 mhz 10 200 250 mhz 60 180 mhz 11 reserved 0.45 v 0.8 v 2.0 v input signal (driven by tester) output signal (measured) www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 24 v 1.3, 2006-06 figure 4-4 float waveforms 4.4.3 output rise and fall times the output rise/fall time of a gpio is t r = t f = 14ns, at c l = 50pf. mca00763 - 0.1 v + 0.1 v + 0.1 v - 0.1 v reference for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded oh v timing points load v v load oh v v ol / v ol level occurs ( i oh ol i / = 20 ma). www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 25 v 1.3, 2006-06 4.4.4 power sequencing the CIC751 device needs two power supply voltages: digital ports power supply voltage v ddp , analog supply voltage v ddm . the digital core supply voltage v ddc is derived from v ddp by embedded voltage regulator of the CIC751. the following section defines the time and voltage constraints and relations between these two power supplies that have to be satisfied at power up and power down of the device. figure 4-5 describes the requirements that the external power supplies v ddp , and v ddm must satisfy in order to provide the correct operation of the device. the following rules should be applied in order to guarantee a stable power-up behavior: the active porst should not be released before v ddp reached 2.7 v at any time it is not allowed that v ddm >v ddp if v ddp < 2.1 v. the second rule can be violated (without operation lifetime reduction) if instead the following conditions are not violated: the external resistor on the analog inputs ain0 to ain15 has to be equal or greater than 2 k ? the accumulated time the second rule is violated is less than 4 % of the total product operation lifetime. figure 4-5 power-up sequence v ddp (3.3v or 5v) time voltage time porst powerseq time reset ramp-up time 2.7v 300s v ddm (5v) 2.1v www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 26 v 1.3, 2006-06 table 4-9 ramp-up times case time ramp-up after a power-on event max. 500 s ramp-up after a reset event max. 450 s www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 27 v 1.3, 2006-06 4.4.5 timing parameters peripheral timing parameters are not subject to production test. they are verified by design/characterization. 4.4.5.1 micro link interface (mli) timing the timing of the mli handshake signals refer to the system clock frequency f sys . this frequency is the base for the generation of the mli baud rate f tclk . table 4-10 mli timing (v ss = 0 v; f mli <= 40mhz v ddp = 3.13 to 3.47 v; t a = -40 c to +125 c; c l = 50 pf) parameter symbol values unit note / test con dition min. typ. max. tclk clock period t 10 2 * t sys ?? ns t sys = 1/f sys tclk high period t 11 20% 50% 80% t 10 tclk low period t 12 20% 50% 80% t 10 tclk rise time t 13 ??35%t 10 tclk fall time t 14 ??35%t 10 tdata and tvalid setup time to tclk raising edge t 20 ??10%t 10 tdata and tvalid hold time to tclk raising edge t 21 ??10%t 10 tready setup time to tclk raising edge 1) t 30 10% ? ? t 10 tready hold time to tclk raising edge 2) t 31 10% ? ? t 10 rclk clock period t 40 < 2 * t sys ?? ns t sys = 1/f sys rclk high period t 41 20% 50% 80% t 40 rclk low period t 42 20% 50% 80% t 40 rclk rise time t 43 ??35%t 40 rclk fall time t 44 ??35%t 40 rdata and rvalid setup time to rclk falling edge t 50 10% ? ? t 40 www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 28 v 1.3, 2006-06 rdata and rvalid hold time to rclk falling edge t 51 10% ? ? t 40 rready setup time to rclk falling edge 3) t 60 50% ? ? t 40 rready hold time to rclk falling edge 4) t 61 ??50%t 40 1) referring to the tclk edge when tvalid becomes 0 and the tclk edge when the ready delay time elapses. 2) referring to the tclk edge when tvalid becomes 0 and the tclk edge when the ready delay time elapses. 3) referring to the former value at the rclk edge when rvalid changes. 4) referring to the new value at the rclk edge when rvalid changes. table 4-10 mli timing (v ss = 0 v; f mli <= 40mhz v ddp = 3.13 to 3.47 v; t a = -40 c to +125 c; c l = 50 pf) parameter symbol values unit note / test con dition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 29 v 1.3, 2006-06 figure 4-6 mli timing mli_timing tdata tvalidx t 20 tclk t 10 t 11 t 12 t 14 t 13 rdatax rvalidx rclkx rreadyx t 40 t 41 t 42 t 44 t 43 treadyx t 21 t 30 t 31 t 50 t 51 t 61 t 60 0.1 v ddp 0.9 v ddp 0.1 v ddp 0.9 v ddp www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 30 v 1.3, 2006-06 4.4.6 synchronous serial channel (ssc) slave mode timing the timing of the synchronous serial channel in slave mode is defined below. table 4-11 ssc timing (vss = 0 v; f ssc <= 40mhz vddp = 3.13 to 3.47 v (class a); ta = -40 c to +125 c; cl = 50 pf) parameter sy mb ol values unit note / test co ndition min. typ. max. sclk clock period t 20 cc t ssc ?ns mrst delay from sclk rising/falling edge from sclk re (con.po,con.ph = 00) from sclk fe (con.po,con.ph = 10) t 21 cc 412ns mrst hold from sls rising edge t 26 cc ?14ns mtsr setup to sclk rising/falling edge to sclk re (con.po,con.ph = 00) to sclk fe (con.po,con.ph = 10) t 22 sr 0?ns mtsr hold from sclk rising/falling edge from sclk re (con.po,con.ph = 00) from sclk fe (con.po,con.ph = 10) t 23 sr 2+ t ssc ?ns slsi lead delay from sclk rising/falling edge from sclk re (con.po,con.ph = 00) from sclk fe (con.po,con.ph =10) t 24 sr 6?ns 1) 1) this is only valid if ssc move engine is idle (rdy = 1). rdy lead delay to sls re t 25 cc 13 15 ns sls hold from rdy re t 27 sr 4?ns www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 31 v 1.3, 2006-06 figure 4-7 ssc slave mode timing ssc_tmg_slave_moon goose sclk (con.po, con.ph = 00) sclk (con.po, con.ph = 10) mrst mtsr sls rdy 0.9 v dd 0.1 v dd first data last data data valid data valid t 20 t 21 t 21 t 23 t 22 t 24 t 25 t 23 t 22 t 27 0.9 v dd 0.1 v dd t 26 www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 32 v 1.3, 2006-06 4.5 package and reliability this chapter defines the parameters related to the package and reliability of the device. 4.5.1 packaging the parameters of the package of the CIC751 are defined below. 4.5.2 package outlines the physical characteristics of the package are described below. figure 4-8 package outlines for p/pg-tssop-38 table 4-12 package parameters (p/pg-tssop-38) parameter symbol limit values unit notes min. max. power dissipation p diss ?tbd.w? thermal resistance r thja ? 59 k/w chip-ambient www.datasheet.co.kr datasheet pdf - http://www..net/
CIC751 electrical parameters confidential data sheet 33 v 1.3, 2006-06 4.5.3 quality declarations the following chapter defines some quality parameters of CIC751. note: information about soldering can be found on the ?package? information page under: http://www.infineon.com/products . table 4-13 quality parameters parameter symbol limit values unit notes min. max. operation lifetime t op ? 18000 hours at average weighted junction temperature t j =116 c (ambient temperature t a =102 c) ? 24000 1) 1) one example of a detailed temperature profile is: 1200 hours at t j = 140 c (t a = 125 c) 3600 hours at t j = 115 c (t a = 100 c) 7200 hours at t j = 100 c (t a =85 c) 12000 hours at t j =90 c (t a =75 c) hours at average weighted junction temperature t j =106 c (ambient temperature t a =92 c) life expectancy t b 20 ? years esd susceptibility according to human body model (hbm) v hbm ? 2000 v conforming to eia/jesd22-a114-b esd susceptibility according to socketed device model (sdm) v sdm ? 500 v conforming to esda std ds5.3-1993 moisture sensitivity level (msl) ? ? 3 ? conforming to jedec j-std-020c for 240c www.datasheet.co.kr datasheet pdf - http://www..net/
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