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| 1 features ? high-performance, low-power avr ? 8-bit microcontroller ? 130 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 8 mips throughput at 8 mhz ? on-chip 2-cycle multiplier nonvolatile program and data memories self-programming in-system programmable flash memory ? 16k bytes with optional boot block (256 - 2k bytes) endurance: 1,000 write/erase cycles ? boot section allows reprogramming of program code without external programmer ? optional boot code section with independent lock bits ? 512 bytes eeprom endurance: 100,000 write/erase cycles ? 1024 bytes internal sram ? programming lock for software security peripheral features ? two 8-bit timer/counters with separate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time clock with separate oscillator and counter mode ? three pwm channels ? 8-channel, 10-bit adc ? byte-oriented two-wire serial interface ? programmable serial uart ? master/slave spi serial interface ? programmable watchdog timer with separate on-chip oscillator ? analog comparator special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated rc oscillator ? external and internal interrupt sources ? four sleep modes: idle, adc noise reduction, power-save, and power-down power consumption at 4 mhz, 3.0v, 25 c ? active 5.0 ma ? idle mode 1.9 ma ? power-down mode < 1 a i/o and packages ? 32 programmable i/o lines ? 40-pin pdip and 44-pin tqfp operating voltages ? 2.7 - 5.5v for ATMEGA163L ? 4.0 - 5.5v for atmega163 speed grades ? 0 - 4 mhz for ATMEGA163L ? 0 - 8 mhz for atmega163 8-bit microcontroller with 16k bytes in-system programmable flash atmega163 ATMEGA163L summary not recommend for new designs. use atmega16. rev.1142es?avr?02/03 n ote : thi s i s a summary d ocume nt. a comp l ete d ocumen t i s ava ila ble on our we b site at www.atmel.com .
2 atmega163(l) 1142es?avr?02/03 pin configurations (scl) (sda) (sda) (scl) 3 atmega163(l) 1142es?avr?02/03 description the atmega163 is a low-power cmos 8-bit microcontroller based on the avr architec- ture. by executing powerful instructions in a single clock cycle, the atmega163 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. block diagram figure 1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock program counter internal oscillator watchdog timer stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. portb data dir. reg. porta data dir. reg. portd data dir. reg. portc data register portb data register porta analog mux adc data register portd data register portc programming logic timing and control oscillator oscillator interrupt unit eeprom spi uart status register z y x alu portb drivers porta drivers portd drivers portc drivers pb0 - pb7 pa0 - pa7 reset vcc avcc agnd aref gnd xtal2 xtal1 control lines + - analog comp ara tor pd0 - pd7 pc0 - pc7 8-bit data bus 2-wire serial interface internal reference internal calibrated oscillator 4 atmega163(l) 1142es?avr?02/03 cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmega163 provides the following features: 16k bytes of in-system self-program- mable flash, 512 bytes eeprom, 1024 bytes sram, 32 general purpose i/o lines, 32 general purpose working registers, three flexible timer/counters with compare modes, internal and external interrupts, a byte oriented two-wire serial interface, an 8-channel, 10-bit adc, a programmable watchdog timer with internal oscillator, a programmable serial uart, an spi serial port, and four software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port, and inter- rupt system to continue func tioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchro- nous timer and adc, to minimize switching noise during adc conversions. the on-chip isp flash can be programmed through an spi serial interface or a conven- tional programmer. by installing a self-programming boot loader, the microcontroller can be updated within the application without any external components. the boot pro- gram can use any interface to download the application program in the application flash memory. by combining an 8-bit cpu with in-system self-programmable flash on a monolithic chip, the atmel atmega163 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega163 avr is supported with a fu ll suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-cir- cuit emulators, and evaluation kits. pin descriptions vcc digital supply voltage. gnd digital ground. port a (pa7..pa0) port a serves as the analog inputs to the a/d converter. port a also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port a output buffers can sink 20ma and can drive led displays directly. when pins pa0 to pa7 are used as inputs and are externally pulled low, they will source current if the internal pull- up resistors are activated. the port a pins are tristated when a reset condition becomes active, even if the clock is not running. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers can sink 20 ma. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. port b also serves the functions of various special features of the atmega83/163 as listed on page 117. the port b pins are tristated when a reset condition becomes active, even if the clock is not running. port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers can sink 20 ma. as inputs, port c pins that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tristated when a reset condition becomes active, even if the clock is not running. 5 atmega163(l) 1142es?avr?02/03 port c also serves the functions of various special features of the atmega163 as listed on page 124. port d (pd7..pd0) port d is an 8-bit bidirectional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers can sink 20 ma. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. port d also serves the functions of various special features of the atmega163 as listed on page 128. the port d pins are tristated when a reset condition becomes active, even if the clock is not running. reset reset input. a low level on this pin for more than 500 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. avcc this is the supply voltage pin for port a and the a/d converter. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be con- nected to v cc through a low-pass filter. see page 105 for details on operation of the adc. aref aref is the analog reference input pin for the a/d converter. for adc operations, a voltage in the range 2.5v to avcc can be applied to this pin. agnd analog ground. if the board has a separate analog ground plane, this pin should be con- nected to this ground plane. otherwise, connect to gnd. 6 atmega163(l) 1142es?avr?02/03 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f ($5f) sreg i t h s v n z c 20 $3e ($5e) sph ? ? ? ? ? sp10 sp9 sp8 21 $3d ($5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 21 $3c ($5c) reserved $3b ($5b) gimsk int1 int0 ? ? ? ? ? ?30 $3a ($5a) gifr intf1 intf0 ? ? ? ? ? ?31 $39 ($59) timsk ocie2 toie2 ticie1 ocie1a ocie1b toie1 ?toie0 32 $38 ($58) tifr ocf2 tov2 icf1 ocf1a ocf1b tov1 ?tov0 32 $37 ($57) spmcr ?asb ? asre blbset pgwrt pgers spmen 140 $36 ($56) twcr twint twea twsta twsto twwc twen ?twie 82 $35 ($55) mcucr ? se sm1 sm0 isc11 isc10 isc01 isc00 34 $34 ($54) mcusr ? ? ? ? wdrfborfextrf porf 28 $33 ($53) tccr0 ? ? ? ? ? cs02 cs01 cs00 41 $32 ($52) tcnt0 timer/counter0 (8 bits) 42 $31 ($51) osccal oscillator calibration register 37 $30 ($50) sfior ? ? ? ? acme pud psr2 psr10 40 $2f ($4f) tccr1a com1a1 com1a0 com1b1 com1b0 foc1a foc1b pwm11 pwm10 44 $2e ($4e) tccr1b icnc1 ices1 ? ? ctc1 cs12 cs11 cs10 45 $2d ($4d) tcnt1h timer/counter1 ? counter register high byte 46 $2c ($4c) tcnt1l timer/counter1 ? counter register low byte 46 $2b ($4b) ocr1ah timer/counter1 ? output compare register a high byte 47 $2a ($4a) ocr1al timer/counter1 ? output compare register a low byte 47 $29 ($49) ocr1bh timer/counter1 ? output compare register b high byte 47 $28 ($48) ocr1bl timer/counter1 ? output compare register b low byte 47 $27 ($47) icr1h timer/counter1 ? input capture register high byte 48 $26 ($46) icr1l timer/counter1 ? input capture register low byte 48 $25 ($45) tccr2 foc2 pwm2 com21 com20 ctc2 cs22 cs21 cs20 52 $24 ($44) tcnt2 timer/counter2 (8 bits) 53 $23 ($43) ocr2 timer/counter2 output compare register 54 $22 ($42) assr ? ? ? ? as2 tcn2ub ocr2ub tcr2ub 57 $21 ($41) wdtcr ? ? ? wdtoe wde wdp2 wdp1 wdp0 60 $20 ($40) ubrrhi ? ? ? ? ubrr[11:8] 78 $1f ($3f) eearh ? ? ? ? ? ? ?eear8 62 $1e ($3e) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 62 $1d ($3d) eedr eeprom data register 62 $1c ($3c) eecr ? ? ? ? eerie eemwe eewe eere 63 $1b ($3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 115 $1a ($3a) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 115 $19 ($39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 115 $18 ($38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 117 $17 ($37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 117 $16 ($36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 117 $15 ($35) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 123 $14 ($34) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 123 $13 ($33) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 123 $12 ($32) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 128 $11 ($31) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 128 $10 ($30) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 128 $0f ($2f) spdr spi data register 69 $0e ($2e) spsr spif wcol ? ? ? ? ? spi2x 68 $0d ($2d) spcr spie spe dord mstr cpol cpha spr1 spr0 67 $0c ($2c) udr uart i/o data register 74 $0b ($2b) ucsra rxc txc udre fe or ?u2xmpcm 74 $0a ($2a) ucsrb rxcie txcie udrie rxen txen chr9 rxb8 txb8 76 $09 ($29) ubrr uart baud rate register 78 $08 ($28) acsr acd acbg aco aci acie acic acis1 acis0 102 $07 ($27) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 110 $06 ($26) adcsr aden adsc adfr adif adie adps2 adps1 adps0 111 $05 ($25) adch adc data register high byte 112 $04 ($24) adcl adc data register low byte 112 $03 ($23) twdr two-wire serial interface data register 84 $02 ($22) twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce 85 $01 ($21) twsr tws7 tws6 tws5 tws4 tws3 ? ? ?84 7 atmega163(l) 1142es?avr?02/03 note: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers $00 to $1f only. $00 ($20) twbr two-wire serial interface bit rate register 82 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 8 atmega163(l) 1142es?avr?02/03 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd $ff ? rd z,c,n,v 1 neg rd two?s complement rd $00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? ($ff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1 / 2 / 3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1 / 2 / 3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1 / 2 / 3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1 / 2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1 / 2 9 atmega163(l) 1142es?avr?02/03 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 instruction set summary (continued) 10 atmega163(l) 1142es?avr?02/03 clh clear half carry flag in sreg h 0 h 1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 instruction set summary (continued) 11 atmega163(l) 1142es?avr?02/03 ordering information speed (mhz) power supply ordering code package operation range 4 2.7 - 5.5v ATMEGA163L-4ac ATMEGA163L-4pc 44a 40p6 commercial (0 c to 70 c) ATMEGA163L-4ai ATMEGA163L-4pi 44a 40p6 industrial (-40 c to 85 c) 8 4.0 - 5.5v atmega163-8ac atmega163-8pc 44a 40p6 commercial (0 c to 70 c) atmega163-8ai atmega163-8pi 44a 40p6 industrial (-40 c to 85 c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-lead, 0.600" wide, plastic dual inline package (pdip) 12 atmega163(l) 1142es?avr?02/03 packaging information 44a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ 13 atmega163(l) 1142es?avr?02/03 40p6 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0?~ 15? d e eb common dimensions (unit of measure = mm) symbol min nom max note a 4.826 a1 0.381 d 52.070 52.578 note 2 e 15.240 15.875 e1 13.462 13.970 note 2 b 0.356 0.559 b1 1.041 1.651 l 3.048 3.556 c 0.203 0.381 eb 15.494 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010"). 14 atmega163(l) 1142es?avr?02/03 erratas atmega163(l) errata rev. f increased interrupt latency interrupts abort twi power-down twi master does not accept spikes on bus lines twcr write operations ignored pwm not phase correct twi is speed limited in slave mode 6. increased interrupt latency in this device, some instructions are not interruptable, and will cause the interrupt latency to increase. the only practical problem concerns a loop followed by a two- word instruction while waiting for an interrupt. the loop may consist of a branch instruction or an absolute or relative jump back to itself like this: loop: rjmp loop 15 atmega163(l) 1142es?avr?02/03 problem fix/workaround ensure at least one instruction (e.g., nop) is executed between two writes to twcr. 2. pwm not phase correct in phase-correct pwm mode, a change from ocrx = top to anything less than top does not change the ocx output. this gives a phase error in the following period. problem fix/workaround make sure this issue is not harmful to the application. 1. twi is speed limited in slave mode when the two-wire serial interface operates in slave mode, frames may be unde- tected if the cpu frequency is less than 64 times the bus frequency. problem fix/workaround ensure that the cpu frequency is at least 64 times the twi bus frequency. 16 atmega163(l) 1142es?avr?02/03 change log this section containes a log on the changes made to the data sheet for atmega163. all refereces to pages in change log, are referred to this document. changes from rev. 1142c-09/01 to rev. 1142d-09/02 1. added ?not recommend for new designs. use atmega16.?. changes from rev. 1142d-09/09 to rev. 1142e-02/03 1. updated table 52, ?boot reset fuse,? on page 136. 2. corrected pin numbers in figure 62 on page 113. 3. corrected a constant in the boot loader code example on page 141. 4. changed max bit rate for the twi from 400 khz to 217 khz. 5. removed redundant and harmful loop in a code example for slave receiver mode for the twi on page 96. 6. added agnd and avcc in figure 81 on page 145 and figure 86 on page 154. 7. updated the ?packaging information? on page 12. 8. added ?erratas? on page 14. 17 atmega163(l) 1142es?avr?02/03 printed on recycled paper. ? atmel corporation 2003. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 1142es?avr?02/03 0m at m e l ? and avr ? are the registered trademarks of atmel. other terms and product names may be the trademarks of others. |
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