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application note printed in japan 1996 m pd784915, 784928, 784928y subseries 16-bit single-chip microcontrollers vcr servo basics m pd784915 m pd784927 m pd784927y m pd784915a m pd78f4928 m pd78f4928y m pd784916a m pd784915b m pd784916b m pd78p4916 document no. u11361ej3v0an00 (3rd edition) date published march 1998 n cp(k)
2 [memo]
3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
4 the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.
5 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j98. 2
6 major revisions in this edition page description throughout the m pd784928, 784928y subseries and the m pd784915b, 784916b are added. introduction document numbers of related documents are added or corrected. p. 15 chapter 1 outline of nec vcr servo microcontroller products is added. p. 19 table 2-1 differences among m pd784915 subseries products is added. p. 25 chapter 3 outline of m pd784928, 784928y subseries is added. the mark shows major revised points.
7 introduction readers this application note is intended for user engineers who understand the functions of the m pd784915, 784928, 784928y subseries and wish to design and develop its application systems and programs. purpose the purpose of this application note is to help users understand the hardware capa- bilities of the target device using application examples. organization the main topics of this application note are listed below. ? outline of m pd784915 subseries ? outline of m pd784928, 784928y subseries ? outline of vcr servo ? servo control examples of stationary vcr ? analog circuit ? viss how to read this manual it is assumed that the readers of this manual have a general knowledge of electronics, logical circuits, and microcontrollers. moreover, readers should also have a general knowledge of vcrs and servo control. when there are no functional differences in the products, the application note men- tions the m pd784915 subseries as the representative subseries and the m pd784915 as the representative version, although its descriptions also apply to the versions other than the m pd784915. quality grade standard (for general electronic appliances) legends data significance : left: higher digit, right: lower digit active low : (top bar over pin or signal name) note : footnote explaining items marked with note in the text caution : description of point that requires particular attention remark : supplementary information numerical representation : binary ... b or decimal ... hexadecimal ... h easily confused characters : 0 (zero), o (uppercase letter o) 1 (one), l (lowercase of letter l), i (uppercase of letter i)
8 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. device related documents document name document number japanese english m pd784915 data sheet u11044j u11044e m pd784915a, 784916a data sheet u11022j u11022e m pd784915b, 784916b data sheet u11930j to be prepared m pd78p4916 data sheet u11045j u11045e m pd784915 subseries special function register table u10976j m pd784915 subseries users manual u10444j u10444e m pd784927 data sheet u12255j to be prepared m pd78f4928 preliminary product information u12188j u12188e m pd784928 subseries special function register table u12798j m pd784927y data sheet u12373j u12373e m pd78f4928y preliminary product information u12271j u12271e m pd784928y subseries special function register table u12719j m pd784928, 784928y subseries users manual u12648j u12648e m pd784915, 784928, 784928y subseries application note vcr servo basics u11361j this manual 78k/iv series users manual instruction u10905j u10905e 78k/iv series instruction table u10594j 78k/iv series instruction set u10595j 78k/iv series application note software basics u10095j u10095e register format never write a combination of codes marked setting prohibited in the register formats in the text. 7 b 6 1 5 0 4 3 a 2 1 1 0 0 edc bit number that is circled indicates that it is a reserved word in the ra78k4 and sfr variable with #pragma sfr instruction in the cc78k4, and it is defined with a file. write operation read operation write 0 or 1. neither value affects operation. write 0. write 1. write the value corres- ponding to a function to use. read 0 or 1. read a value according to operation status. register name
9 contents chapter 1 outline of nec vcr servo microcontroller products ......................... 15 1.1 outline ..................................................................................................................... ......... 15 1.2 features .................................................................................................................... ........ 17 chapter 2 outline of m pd784915 subseries ......................................................................... 19 2.1 features and application fields .................................................................................... 20 2.2 pin configuration (top view) ......................................................................................... 21 2.3 block diagram ............................................................................................................... ... 23 2.4 outline of functions ........................................................................................................ 24 chapter 3 outline of m pd784928, 784928y subseries ......................................................... 25 3.1 features and application fields .................................................................................... 26 3.2 pin configuration (top view) ......................................................................................... 27 3.3 internal block diagram .................................................................................................... 29 3.4 outline of functions ........................................................................................................ 30 3.5 differences among m pd784928, 784928y subseries and m pd784915 subseries ...... 32 chapter 4 outline of vcr servo system ............................................................................. 33 4.1 outline of software servo ............................................................................................... 33 4.2 servo control of vcr ...................................................................................................... 34 4.3 servo for recording ........................................................................................................ 3 6 4.4 servo for playback .......................................................................................................... 36 4.5 motor to be used ............................................................................................................ .37 4.6 vcr control systems ...................................................................................................... 38 4.7 vcr servo system control ............................................................................................. 38 chapter 5 examples of stationary type vcr servo control ................................... 39 5.1 examples of system configuration ............................................................................... 39 5.2 outline of system ........................................................................................................... .41 5.3 using example of super timer unit............................................................................... 43 5.4 head switching signal generation ................................................................................ 46 5.4.1 internal head switching signal (hsw-n) generation .............................................................. 46 5.4.2 head switching signal (v-hsw) generation .......................................................................... 48 5.4.3 audio head switching signal (a-hsw) generation ................................................................. 54 5.5 drum speed control ........................................................................................................ 58 5.6 drum phase control ........................................................................................................ 60 5.6.1 phase reference ........................................................................................................... ......... 60 5.6.2 drum phase control for playback ........................................................................................... 69 5.6.3 drum phase control for recording .......................................................................................... 74 5.7 capstan speed control ................................................................................................... 79 5.8 capstan phase control ................................................................................................... 83 5.8.1 capstan phase control for playback ...................................................................................... 83 5.8.2 capstan phase control for recording ..................................................................................... 90 5.9 recording control signal generation ........................................................................... 94 5.10 quasi vertical synchronizing signal (quasi-v sync ) generation ................................. 100
10 5.11 treatment of servo error amount .................................................................................. 103 5.11.1 drum control system processing ........................................................................................... 103 5.11.2 capstan control system processing ...................................................................................... 10 7 5.12 compensation filter ........................................................................................................ 112 5.12.1 filter types ............................................................................................................. ................ 112 5.12.2 biprimary conversion method .............................................................................................. .. 113 5.12.3 digital filter designing method .......................................................................................... ..... 119 5.12.4 primary iir type digital filter transfer function ........................................................................ 120 5.12.5 lag-lead filter configuration method ..................................................................................... . 121 5.12.6 filter processing method ................................................................................................. ...... 124 chapter 6 ctl amplifier ...................................................................................................... ....... 127 6.1 ctl amplifier auto gain control processing ............................................................... 127 6.1.1 ctl amplifier auto gain control method ................................................................................ 129 6.1.2 ctl amplifier auto gain control processing ........................................................................... 134 chapter 7 viss detection ..................................................................................................... ...... 137 7.1 what is viss ................................................................................................................ ..... 137 7.2 viss detection .............................................................................................................. ... 138 7.2.1 viss detection method ..................................................................................................... ..... 138 7.2.2 viss detection processing ................................................................................................. ... 142 7.3 viss rewrite ................................................................................................................ .... 147 7.3.1 viss rewrite method ....................................................................................................... ...... 147 7.3.2 viss rewrite processing ................................................................................................... ..... 149 chapter 8 program list ........................................................................................................ ...... 151 appendix revision history ..................................................................................................... ..... 221
11 list of figures (1/2) figure no. title page 4-1 track pattern on video tape ................................................................................................. ........... 35 5-1 application to stationary type vcr .......................................................................................... ........ 40 5-2 software digital servo system block diagram ................................................................................. 42 5-3 super timer unit block diagram .............................................................................................. ........ 44 5-4 use of event counter (ec) ................................................................................................... ............ 46 5-5 event counter (ec) operation timing ......................................................................................... ..... 47 5-6 use of timer 0 .............................................................................................................. ..................... 49 5-7 head switching signal (v-hsw) timing (pto00) ............................................................................ 50 5-8 input control register (icr) format (when generating v-hsw) ...................................................... 51 5-9 timer 0 output mode register (tom0) format (when generating v-hsw) ..................................... 52 5-10 timer 0 output control register (toc0) format (when generating v-hsw) ................................... 52 5-11 timer control register 0 (tmc0) format (when generating v-hsw) .............................................. 53 5-12 assigning a-hsw to timer 0 ................................................................................................. ........... 54 5-13 v-hsw and a-hsw timings .................................................................................................... ......... 55 5-14 timer 0 output mode register (tom0) format (when generating a-hsw) ..................................... 55 5-15 timer 0 output control register (toc0) format (when generating a-hsw) ................................... 56 5-16 timer control register 0 (tmc0) format (when generating a-hsw) .............................................. 57 5-17 drum speed error amount detection method .................................................................................. 5 8 5-18 drum speed control timings ................................................................................................. ........... 59 5-19 timer 1 peripheral circuit ................................................................................................. ................ 61 5-20 example of timer 1 operation timings (for playback) ...................................................................... 63 5-21 timer control register 0 (tmc0) format (drum phase control for playback) ................................... 64 5-22 example of timer 1 operation timings (for recording) ..................................................................... 67 5-23 timer control register 0 (tmc0) format (drum phase control for recording) .................................. 68 5-24 use of timer for drum phase control (for playback) ........................................................................ 6 9 5-25 drum phase control timing (for playback) ................................................................................... .... 70 5-26 capture mode register (cptm) format ........................................................................................ ... 73 5-27 use of timer for drum phase control (for recording) ....................................................................... 7 5 5-28 drum phase control timing (for recording) .................................................................................. .... 76 5-29 capture mode register (cptm) format ........................................................................................ ... 77 5-30 capstan speed detection method ............................................................................................. ....... 81 5-31 capstan speed control timing ............................................................................................... .......... 82 5-32 model of capstan phase control ............................................................................................. ......... 83 5-33 capstan phase error detection method (for playback) .................................................................... 85 5-34 capture mode register (cptm) format ........................................................................................ ... 86 5-35 capstan phase control timing (playback mode, phase locked) ...................................................... 87 5-36 capstan phase control timing (playback mode, phase delayed) .................................................... 88 5-37 capstan phase control timing (playback mode, phase advanced) ................................................. 89 5-38 capstan phase error detection method (for recording) .................................................................... 91 5-39 capture mode register (cptm) format ........................................................................................ ... 92 5-40 capstan phase control timing (for recording) ............................................................................... .. 93 5-41 connection of m pd784915 and control head ................................................................................... 95
12 list of figures (2/2) figure no. title page 5-42 recctl driver block diagram ................................................................................................ ......... 95 5-43 example of recctl signal writing operation timings ................................................................... 96 5-44 timer 1 output mode register (tom1) format ................................................................................ 9 8 5-45 recctl write timing using cr11 ............................................................................................. ..... 99 5-46 quasi-v sync waveform ..................................................................................................................... 1 01 5-47 middle level generation .................................................................................................... ............... 101 5-48 quasi-v sync generation timing ........................................................................................................ 102 5-49 drum control system configuration .......................................................................................... ....... 103 5-50 trapezoidal pattern for error value detection (drum control system) .............................................. 104 5-51 capstan control system configuration ....................................................................................... ...... 107 5-52 trapezoidal pattern for error value detection (capstan control system) .......................................... 108 5-53 fold error ................................................................................................................. ......................... 114 5-54 pole location when sampling theorem is satisfied ......................................................................... 11 5 5-55 pole location when sampling theorem is not satisfied .................................................................. 115 5-56 mapping by standard z transform ............................................................................................ ........ 116 5-57 mapping by biprimary transform ............................................................................................. ......... 118 5-58 primary iir type digital filter block diagram .............................................................................. ..... 120 5-59 lag-lead filter configuration and characteristics .......................................................................... ... 121 6-1 ctl amplifier configuration ................................................................................................. ............. 127 6-2 relationship between ctl amplifier output and each detection level/flag ................................... 128 6-3 gain change timing for play or cue/rev in forward direction ................................................... 130 6-4 gain change timing for play or cue/rev in reverse direction ................................................... 131 6-5 gain change timing for ff/rew in forward direction .................................................................... 132 6-6 gain change timing for ff/rew in reverse direction .................................................................... 133 7-1 viss cue code ............................................................................................................... .................. 137 7-2 viss detection circuit (pulse width detection circuit) configuration .............................................. 138 7-3 data pattern discrimination mode block configuration .................................................................... 140 7-4 addressing and data setting in data pattern discrimination mode .................................................. 141 7-5 intcr12 macro service processing in forward direction ............................................................... 145 7-6 intcr12 macro service processing in reverse direction ............................................................... 146 7-7 viss rewrite ................................................................................................................ ..................... 147 7-8 viss = 1 signal rewrite operation timing chart ............................................................................. 1 49
13 list of tables table no. title page 2-1 differences among m pd784915 subseries products ........................................................................ 19 3-1 differences among m pd784928, 784928y subseries products ....................................................... 25 3-2 differences among m pd784928, 784928y subseries and m pd784915 subseries .......................... 32 5-1 using examples of super timer unit .......................................................................................... ...... 43 5-2 recctl driver rec mode sequence ............................................................................................. 95 5-3 capstan loop gain in each operation mode ................................................................................... 1 10 5-4 capstan bias value in each operation mode ................................................................................... 111 6-1 ctl detection flag read value and ctl amplifier gain adjustment .............................................. 128 7-1 viss data ................................................................................................................... ...................... 137 7-2 recctl driver rewrite mode sequence ......................................................................................... 148 7-3 viss write operation timings ................................................................................................ .......... 150
14 [memo]
chapter 1 outline of nec vcr servo microcontroller products 15 chapter 1 outline of nec vcr servo microcontroller products 1.1 outline necs microcontrollers for vcr servos are 78k/iv series products featuring a high-speed, high-performance 16- bit cpu that are improved versions of the 78k/i series of 8-bit single-chip microcontrollers for vcr software servo control. microcontrollers for vcr servo control comprise the following three subseries. ? m pd784915 subseries ? m pd784928 subseries ? m pd784928y subseries necs lineup of microcontrollers for vcr servo control is shown below. the y subseries support i 2 c bus specifications. pd78138 100-pin qfp expanded on-chip ram capacity. on-chip operational amplifier, clock function, multiplier. 80-pin qfp m m pd784915 pd78148 under mass production under development 100-pin qfp expanded on-chip memory capacity on-chip analog amplifiers. enhanced super timer. low-power-dissipation mode added. 100-pin qfp. internal flash memory expanded on-chip memory capacity enhanced analog amplifiers. improved vcr functions. increased number of i/os. large-current port added. i 2 c function added (y products only). m pd784928 pd784928y 78k/iv series 78k/i series mm
chapter 1 outline of nec vcr servo microcontroller products 16 ? microcontrollers for vcr servo control ? m pd784915 subseries part number m pd784915, 784915a, m pd784916a, m pd78p4916 parameter m pd784915b m pd784916b internal rom capacity mask rom one-time prom 48 kbytes 62 kbytes internal ram capacity 1280 bytes 2048 bytes ? m pd784928, 784928y subseries part number m pd784927, m pd78f4928 note , parameter m pd784927y m pd78f4928y note internal rom capacity mask rom flash memory 96 kbytes 128 kbytes internal ram capacity 2048 bytes 3584 bytes note under development
chapter 1 outline of nec vcr servo microcontroller products 17 1.2 features in this section, the m pd784915 subseries is explained as the representative subseries, which is enhanced, compared with the 78k/i series, in the points mentioned below. (1) equipped with the 78k/iv core, a 16-bit high-performance cpu the instruction set of the m pd784915 subseries is perfectly upward-compatible with that of the existing 78k/ i series. therefore, the software assets of the 78k/i series are effectively utilized. the 78k/iv series supports 1-mbyte linear address space, resulting in improved program handlability. moreover, the instruction set of the 78k/iv series has been greatly enhanced, and realizes high-speed servo arithmetic processing by using powerful multiplication and 16-bit transmit instructions. (2) enhanced power management function the m pd784915 subseries realizes internal 8 mhz (minimum instruction execution time = 250 ns) high-speed operation in 4.5 to 5.5 v voltage range in normal operation. its cpu guarantees 4.0-v operation. moreover, the m pd784915 subseries is equipped with a low power consumption mode which enables cpu operation using 32.768-khz subsystem clock. selection of cpu clock dividing ratio is made possible by on- chip clock frequency dividing circuit. since operation up to 2.7 v is guaranteed, reduction of the power consumption of the whole system is possible using these functions. the use of these functions in combination with the standby function realizes ultra low power consumption according to the operation conditions, that is, back-up supply voltage operation or battery operation. (3) realizes low-frequency/high-speed operation for reducing radiation noise the m pd784915 subseries provides a low-frequency oscillation mode which enables internal operation with the clock frequency equal to the external oscillation frequency. it realizes reduction of radiation noise by enabling high-speed operation with a frequency lower than that of conventional products. (4) on chip vcr servo control timer super timer unit the super timer unit consists of six 16-bit timers, two 8-bit timers, and a 5-bit up/down counter for linear tape in addition to 22-bit free running counter (frc) to carry out cycle measurement of various vcr motors. therefore, vcr servo control by software can be performed easily. the m pd784915 is incorporated with special circuits such as v sync and h sync separation circuits required for vcr servo control in addition to three 16-bit resolution pwm outputs and three 8-bit resolution pwm outputs required for motor control. (5) on-chip analog circuits for vcr the analog circuits for vcr consist of a ctl amplifier to amplify record signals of the tape with any gain, a recctl driver required for writing ctl and viss signals, and other constituents required for vcr servo control such as a drum fg amplifier, drum pg comparator, dpfg separation circuit (three-value separation circuit), cfg amplifier, reel fg comparator (2 channels), and c sync comparator. the ctl amplifier can switch gain in 32 steps by software. in actuality, the ctl amplifier output gain is controlled by setting the ctl detection plug with software. compared with conventional ctl amplifiers, the circuit configuration is more optimized, which results in a reduction of the number of pins from eleven to six. the analog circuits for vcr have made it possible to largely reduce the number of parts, enabling system cost reduction.
chapter 1 outline of nec vcr servo microcontroller products 18 [memo]
chapter 2 outline of m pd784915 subseries 19 chapter 2 outline of m pd784915 subseries the m pd784915 subseries under the 78k/iv series consists of products provided with an on-chip high-speed, high- performance 16-bit cpu that are improved versions of the 78k/i series of 8-bit single-chip microcontrollers for vcr software servo control. the m pd784915 subseries provides on chip optimum peripheral hardware for vcr control, including a multifunc- tion timer unit (super timer unit) ideal for software servo control, and analog circuits, thus enabling the realization of vcr system/servo/timer control with a single chip. moreover, a product with on-chip one-time prom, the m pd78p4916, is also available. this chapter describes the m pd784915 as the representative product. table 2-1. differences among m pd784915 subseries products part number m pd784915, 784915a, m pd784916a, m pd78p4916 parameter m pd784915b m pd784916b internal rom capacity mask rom one-time prom 48 kbytes 62 kbytes internal ram capacity 1280 bytes 2048 bytes internal memory capacity not provided provided selection register (ims) ic pin provided not provided v pp pin not provided provided electrical characteristics refer to data sheet of individual products.
chapter 2 outline of m pd784915 subseries 20 2.1 features and application fields (1) features ? minimum instruction execution time: 250 ns (operation when internal clock = 8 mhz) ? on-chip timer unit for vcr servo control (super timer unit) ? i/o ports: 54 ? on-chip vhs-compliant vcr analog circuits ? ctl amplifier ? dpg comparator ? recctl driver (rewrite-capable) ? dpfg separation circuit (3-value separation circuit) ? cfg amplifier ? reel fg comparator (2 channels) ? dfg amplifier ? csync comparator ? serial interface: 2 channels (3-wire serial i/o) ? a/d comparator: 8-bit resolution 12 channels (conversion time: 10 m s) ? pwm output: 16-bit resolution 3 channels, 8-bit resolution 3 channels ? interrupt functions ? vectored interrupt function ? macro service function ? context switching function ? low-frequency oscillation mode supported: main system clock frequency = internal clock frequency ? low-power-dissipation mode supported: cpu operation using subsystem clock possible ? power supply voltage: v dd = 2.7 to 5.5 v ? on-chip hardware clock function: low voltage (v dd = 2.7 v (min.)), low-current-dissipation clock operation possible (2) application fields system/servo/timer control for vcr (stationary type, camcorder)
chapter 2 outline of m pd784915 subseries 21 2.2 pin configuration (top view) ? 100-pin plastic qfp (14 20 mm) m pd784915gf- -3ba, 784915agf- -3ba, 784916agf- -3ba, m pd784915bgf- -3ba, 784916bgf- -3ba, 78p4916gf-3ba caution connect ic (internally connected) pin directly to v ss . remark ( ): m pd78p4916 ani9 ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 av ref av dd2 p96 p95/key4 p94/key3 p93/key2 p92/key1 p91/key0 p90/env nmi intp0 intp1 intp2 p00 p01 p02 p03 p04 p05 p06 p64 p65/hwin p66/pwm4 p67/pwm5 p60/strb/clo p61/sck1/buz p62/so1 p63/si1 pwm0 pwm1 sck2 so2 si2/busy v dd xt1 xt2 v ss x2 x1 reset ic (v pp ) pto02 pto01 pto00 p87/pto11 p86/pto10 p85/pwm3 p84/pwm2 p83/rotc p82/hasw p80 p57 p56 p55 p54 p53 p52 p51 p50 v ss v dd p47 p46 p45 p44 p43 p42 p41 p40 p07 csyncin reel0in/intp3 reel1in dfgin dpgin cfgcpin cfgampo cfgin av dd1 av ss1 vrefc ctlout2 ctlout1 ctlin recctl recttl+ ctldly av ss2 ani11 ani10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
chapter 2 outline of m pd784915 subseries 22 ani0 to ani11 : analog input p00 to p07 : port0 av dd1 , av dd2 : analog power supply p40 to p47 : port4 av ss1 , av ss2 : analog ground p50 to p57 : port5 av ref : analog reference voltage p60 to p67 : port6 busy : serial busy p70 to p77 : port7 buz : buzzer output p80, p82 to p87 : port8 cfgampo : capstan fg amplifier output p90 to p96 : port9 cfgcpin : capstan fg capacitor input pto00 to pto02, : programmable timer output cfgin : analog unit input pto10, pto11 clo : clock output pwm0 to pwm5 : pulse width modulation output csyncin : analog unit input recctl+, recctlC : recctl output/pbclt input ctldly : control delay input reel0in, reel1in : analog unit input ctlin : ctl amplifier input capacitor reset : reset ctlout1, ctlout2 : ctl amplifier output rotc : chrominance rotate output dfgin : analog unit input sck1, sck2 : serial clock dpgin : analog unit input si1, si2 : serial input env : envelope input so1, so2 : serial output hasw : head amplifier switch output strb : serial strobe hwin : hardware timer external input v dd : power supply ic : internally connected vrefc : reference amplifier capacitor intp0 to intp3 : interrupt from peripherals v ss : ground key0 to key4 : key return x1, x2 : crystal (main system clock) nmi : non-maskable interrupt xt1, xt2 : crystal (subsystem clock)
chapter 2 outline of m pd784915 subseries 23 2.3 block diagram remarks 1. internal rom capacity and ram capacity differ depending on the product. 2. the broken line indicates the connection in prom programming mode. nmi intp0 to intp3 pwm0 to pwm5 pto00 to pto02 pto10 and pto11 vrefc reel0in reel1in csyncin dfgin dpgin cfgin cfgampo cfgcpin ctlout1 ctlout2 ctlin recctl + recctl ctldly av dd1 and av dd2 av ss1 and av ss2 av ref ani0 to ani11 si1 so1 sck1 si2/busy so2 sck2 strb interrupt control super timer unit serial interface 1 analog unit & a/d converter serial interface 2 78k/iv 16-bit cpu core ram rom system control clock output buzzer output key input real - time output port port0 port4 port5 port6 port7 port8 port9 p00 to p07 p40 to p47 p50 to p57 p60 to p67 p70 to p77 p80, p82 to p87 p90 to p96 p00 to p07 p80, p82, p83 key0 to key4 clo buz v dd v ss x1 x2 xt1 xt2 reset ce oe pgm v pp d0 to d7 a0 to a16
chapter 2 outline of m pd784915 subseries 24 2.4 outline of functions part number m pd784915, 784915a, m pd784916a, m pd78p4916 parameter m pd784915b m pd784916b instructions 113 minimum instruction execution time 250 ns (internal clock: 8 mhz) internal rom capacity mask rom one-time prom 48 kbytes 62 kbytes internal ram capacity 1280 bytes 2048 bytes interrupt 4-level (programmable), vectored interrupts, macro service, context switching external source 9 (including nmi) internal source 19 macro service available interrupt 25 number of macro service 10 (4 types) i/o ports input 8 i/o 46 time-based counter ? 22-bit frc ? resolution: 125 ns, maximum count time: 524 ms capture register input signal number of bits measurement cycle operation edge cfg 22 125 ns to 524 ms ? dfg 22 125 ns to 524 ms hsw 16 1 m s to 65.5 ms ? v sync 22 125 ns to 524 ms ctl 16 1 m s to 65.5 ms ? t reel 22 125 ns to 524 ms ? s reel 22 125 ns to 524 ms ? general-purpose timer 16-bit timer 3 pbctl duty discrimination ? duty discrimination for play control signal ? viss detection, wide aspect detection linear time counter ctl signal counting with 5-bit udc real-time output port 11 serial interface clock synchronous (3-wire): 2 channels a/d converter 8-bit resolution 12 channels, conversion time: 10 m s pwm output ? 16-bit resolution 3 channels, 8-bit resolution 3 channels ? carrier frequency: 62.5 khz clock function 0.5-second measurement, low-voltage operation possible standby function halt mode/stop mode/low power dissipation mode/low power dissipation halt mode analog circuits ? ctl amplifier ? dpg comparator ? recctl driver (rewrite-capable) ? dpfg separation circuit (3-value separation circuit) ? cfg amplifier ? reel fg comparator ? dfg amplifier ? csync comparator power supply voltage v dd = 2.7 to 5.5 v package 100-pin plastic qfp (14 20 mm)
chapter 3 outline of m pd784928, 784928y subseries 25 chapter 3 outline of m pd784928, 784928y subseries the m pd784928, 784928y subseries under the 78k/iv series of products with an on-chip high-speed, high- performance 16-bit cpu consists of products for vcr software servo control. the m pd784928, 784928y subseries provides on chip optimum peripheral hardware for vcr control, including a multifunction timer unit (super timer unit) ideal for software servo control, and analog circuits, thus enabling the realization of vcr system/servo/timer control with a single chip. moreover, products with on-chip flash memory, the m pd78f4928 and 78f4928y, are now under development. this chapter describes the m pd784927 as the representative product. table 3-1. differences among m pd784928, 784928y subseries products part number m pd784927, m pd78f4928 note , parameter m pd784927y m pd78f4928y note internal rom capacity 96 kbytes (mask rom) 128 kbytes (flash memory) internal ram capacity 2048 bytes 3584 bytes internal memory capacity not provided provided selection register (ims) ic pin provided not provided v pp pin not provided provided electrical characteristics refer to data sheet of individual products. note under development
chapter 3 outline of m pd784928, 784928y subseries 26 3.1 features and application fields (1) features ? minimum instruction execution time: 250 ns (operation when internal clock = 8 mhz) ? on-chip timer unit for vcr servo control (super timer unit) ? i/o ports: 74 ? on-chip vhs-compliant vcr analog circuits ? ctl amplifier ? dpg amplifier ? recctl driver (rewrite-capable) ? dpfg separation circuit (3-value separation circuit) ? cfg amplifier ? reel fg comparator (2 channels) ? dfg amplifier ? csync comparator ? serial interface: 3 channels ? 3-wire serial i/o: 2 channels ?i 2 c bus interface: 1 channel ( m pd784928y subseries only) ? a/d converter: 12 channels (conversion time: 10 m s) ? pwm output: 16-bit resolution 3 channels, 8-bit resolution 3 channels ? interrupt functions ? vectored interrupt function ? macro service function ? context switching function ? low-frequency oscillation mode supported: main system clock frequency = internal clock frequency ? low-power-dissipation mode supported: cpu operation using subsystem clock possible ? power supply voltage: v dd = 2.7 to 5.5 v ? on-chip hardware clock function: low voltage (v dd = 2.7 v (min.)), low-current-dissipation clock operation possible (2) application fields stationary type vcrs, camcorders, etc.
chapter 3 outline of m pd784928, 784928y subseries 27 3.2 pin configuration (top view) ? 100-pin plastic qfp (14 20 mm) m pd784927gf- -3ba, 78f4928gf-3ba note 1 , m pd784927ygf- -3ba, 78f4928ygf-3ba note 1 notes 1. under development 2. the v pp pin is provided only for the m pd78f4928, 78f4928y. 3. the scl pin and sda pin are provided only for the m pd784928y subseries. caution in the normal operation mode, connect the ic (internally connected)/v pp pin directly to v ss . ani9/p111 ani8/p110 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 av ref av dd2 p96 p95/key4 p94/key3 p93/key2 p92/key1 p91/key0 p90/env nmi/p20 intp0/p21 intp1/p22 intp2/p23 p00 p01 p02 p03 p04 p05 p06 dfgmon/p64/buz dpgmon/p65/hwin cfgmon/p66/pwm4 ctlmon/p67/pwm5 p60/strb/clo p61/sck1/buz p62/so1 p63/si1 p37/pwm0 p36/pwm1 p35/sck2 p34/so2 p33/si2/busy v dd xt1 xt2 v ss x2 x1 reset ic/v pp note 2 p32/pto02 p31/pto01 p30/pto00 p87/pto11 p86/pto10 scl note 3 /p85/pwm3 sda note 3 /p84/pwm2 p83/rotc p82/hasw p80 p57 p56 p55 p54 p53 p52 p51 p50 v ss v dd p47 p46 p45 p44 p43 p42 p41 p40 p07 csyncin/p103 reel0in/intp3/p102 reel1in/p101 dfgin dpgin/p100 cfgcpin cfgampo cfgin av dd1 av ss1 vrefc ctlout2 ctlout1 ctlin recctl recttl+ ctldly av ss2 ani11/p113 ani10/p112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
chapter 3 outline of m pd784928, 784928y subseries 28 ani0 to ani11 : analog input p30 to p37 : port3 av dd1 , av dd2 : analog power supply p40 to p47 : port4 av ss1 , av ss2 : analog ground p50 to p57 : port5 av ref : analog reference voltage p60 to p67 : port6 busy : serial busy p70 to p77 : port7 buz : buzzer output p80, p82 to p87 : port8 cfgampo : capstan fg amplifier output p90 to p96 : port9 cfgcpin : capstan fg capacitor input p100 to p103 : port10 cfgin : analog unit input p110 to p113 : port11 cfgmon : capstan fg monitor pto00 to pto02, : programmable timer output clo : clock output pto10, pto11 csyncin : analog unit input pwm0 to pwm5 : pulse width modulation output ctldly : control delay input recctl+, recctlC : recctl output/pbclt input ctlin : ctl amplifier input capacitor reel0in, reel1in : analog unit input ctlmon : ctl amplifier monitor reset : reset ctlout1, ctlout2 : ctl amplifier output rotc : chrominance rotate output dfgin : analog unit input sck1, sck2 : serial clock dfgmon : dfg monitor scl note 1 : serial clock dpgin : analog unit input sda note 1 : serial data dpgmon : dpg monitor si1, si2 : serial input env : envelope input so1, so2 : serial output hasw : head amplifier switch output strb : serial strobe hwin : hardware timer external input v dd : power supply ic : internally connected v pp note 2 : programming power supply intp0 to intp3 : interrupt from peripherals vrefc : reference amplifier capacitor key0 to key4 : key return v ss : ground nmi : non-maskable interrupt x1, x2 : crystal (main system clock) p00 to p07 : port0 xt1, xt2 : crystal (subsystem clock) p20 to p23 : port2 notes 1. the scl pin and sda pin are provided only for the m pd784928y subseries. 2. the v pp pin is provided only for the m pd78f4928, 78f4928y.
chapter 3 outline of m pd784928, 784928y subseries 29 3.3 internal block diagram notes 1. the v pp pin is provided only for the m pd78f4928, 78f4928y. 2. provided only for the m pd784928y subseries. supports the i 2 c bus interface. remark the internal rom and ram capacities differ according to the product. nmi intp0 to intp3 pwm0 to pwm5 pto00 to pto02 pto10, pto11 vrefc reel0in reel1in csyncin dfgin dpgin cfgin cfgampo cfgcpin ctlout1 ctlout2 ctlin recctl+ recctl _ ctldly dfgmon dpgmon cfgmon ctlmon av dd1 , av dd2 av ss1 , av ss2 av ref ani0 to ani11 si1 so1 sck1 sda scl interrupt control super timer unit serial interface 1 analog unit & a/d converter serial interface 3 note 2 78k/iv 16-bit cpu core (ram : 512 bytes) ram rom system control clock output buzzer output key input real - time output port port3 port4 port5 port6 port7 port10 port11 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 p100 to p103 p110 to p113 p00 to p07 p80, p82, p83 key0 to key4 clo buz v dd v ss x1 x2 xt1 xt2 reset si2/busy so2 sck2 strb serial interface 2 port0 port2 p00 to p07 p20 to p23 port8 port9 p80, p82 to p87 p90 to p96 v pp note 1
chapter 3 outline of m pd784928, 784928y subseries 30 3.4 outline of functions (1/2) part number m pd784927, m pd78f4928 note , parameter m pd784927y m pd78f4928y note instructions 113 minimum instruction execution time 250 ns (internal clock: 8 mhz) internal memory capacity type mask rom flash memory rom 96 kbytes 128 kbytes ram 2048 bytes 3584 bytes interrupt sources external 9 (including nmi) ( m pd784928 subseries) internal 22 (including software interrupts) ? 4-level programmable priority ? 3 types of servicing: vectored interrupts, macro service, context switching interrupt sources external 9 (including nmi) ( m pd784928y subseries) internal 23 (including software interrupts) ? 4-level programmable priority ? 3 types of servicing: vectored interrupts, macro service, context switching i/o ports input 20 i/o 54 (including 8 led direct drive ports) time-based counter ? 22-bit frc ? resolution: 125 ns, maximum count time: 524 ms capture register input signal number of bits measurement cycle operation edge cfg 22 125 ns to 524 ms ? dfg 22 125 ns to 524 ms hsw 16 1 m s to 65.5 ms ? v sync 22 125 ns to 524 ms ctl 16 1 m s to 65.5 ms ? t reel 22 125 ns to 524 ms ? s reel 22 125 ns to 524 ms ? general-purpose timer 16-bit timer 3 pbctl duty discrimination ? duty discrimination for play control signal ? viss detection, wide aspect detection linear time counter ctl signal counting with 5-bit udc real-time output port 11 serial interface ? 3-wire serial i/o: 2 channels (including 1 busy/strb function-enabled channel) ?i 2 c bus interface (multi-master supported): 1 channel ( m pd784928y subseries only) buzzer output function 1.95 khz, 3.91 khz, 7.81 khz, 15.6 khz (operation when internal clock = 8 mhz) 2.048 khz, 4.096 khz, 32.768 khz (operation when subsystem clock = 32.768 khz) a/d converter 8-bit resolution 12 channels, conversion time: 10 m s pwm output ? 16-bit resolution 3 channels, 8-bit resolution 3 channels ? carrier frequency: 62.5 khz clock function 0.5-second measurement, low-voltage operation possible (v dd = 2.7 v) standby function halt mode/stop mode/low power dissipation mode/low power dissipation halt mode note under development
chapter 3 outline of m pd784928, 784928y subseries 31 (2/2) part number m pd784927, m pd78f4928 note , parameter m pd784927y m pd78f4928y note analog circuits ? ctl amplifier ? dpg amplifier ? recctl driver (rewrite-capable) ? dpfg separation circuit (3-value separation circuit) ? cfg amplifier ? reel fg comparator ? dfg amplifier ? csync comparator power supply voltage v dd = 2.7 to 5.5 v package 100-pin plastic qfp (14 20 mm) note under development
chapter 3 outline of m pd784928, 784928y subseries 32 3.5 differences among m pd784928, 784928y subseries and m pd784915 subseries the m pd784927 is a vcr software servo control product that includes on-chip a high-speed, high-performance 16-bit cpu, enabling the realization of vcr system/servo/timer control with a single chip. the m pd784928 subseries is an enhanced function version of the m pd784915 subseries. moreover, the m pd784928y subseries is a product featuring the addition of the i 2 c bus interface. table 3-2 shows the differences among these three subseries. table 3-2. differences among m pd784928, 784928y subseries and m pd784915 subseries parameter m pd784928 subseries, m pd784915 subseries m pd784928y subseries internal rom capacity 96 kbytes/128 kbytes 48 kbytes/62 kbytes internal ram capacity 2048/3584 bytes 1280/2084 bytes i/o ports total 74 54 input 20 8 i/o 54 46 serial interface ? 3-wire serial i/o : 2 channels ? 3-wire serial i/o : 2 channels ?i 2 c bus interface note : 1 channel analog ctl amplifier ? circuit recctl driver ? dpfg separation circuit ? dfg amplifier ? dpg comparator ? dpg amplifier cfg amplifier ? reel fg comparator ? csync comparator ? interrupt external 9 (including nmi) 9 (including nmi) internal 22 (including software interrupts) 19 (including software interrupts) 23 (including software interrupts) note flash memory/prom m pd78f4928, 78f4928y m pd78p4916 note in the case of the m pd784928y subseries
chapter 4 outline of vcr servo system 33 chapter 4 outline of vcr servo system 4.1 outline of software servo in the current vcr market, software servo has become the mainstream in vcr servo systems in order to reduce the manufacturing process and improve the reliability of sets. high-performance microcontrollers which can control the whole system with a single chip have been called for to simplify the manufacturing process and lower costs by reducing the number of parts. on the other hand, along with the trend toward sets with high performance and a many functions, microcontrollers with larger memory capacity are increasingly being used. analog control servo systems, which have conventionally been the mainstream in vcr servos, present the following problems: (1) reliability the analog servo system uses many components whose characteristics are affected by external environment, such as resistors and capacitors, which makes it difficult to keep the characteristics constant over a long period of time. moreover, analog servo systems tend to have changing characteristics over-time, which affects reliability. (2) system adjustment due to the uneven characteristics of the resistors/capacitors, a lot of adjustments are required prior to shipment in order to gain desired characteristics. (3) number of parts analog servos have a large number of parts, which makes it difficult to reduce the size of sets. vcr servo systems, then, have switched over to digital servos with dedicated ics. however, servos with dedicated ics cannot perform flexible control because the servo control algorithm is fixed, and it cannot integrate compensation elements such as digital filter into a device. in order to solve the above problems, software digital servos using single-chip microcontrollers have come into increasing use in recent years. realizing vcr servo systems by software offers the following advantages: <1> improved reliability because software digital servo systems carry out control using the cpu system clock as a reference, stable operation free from environmental conditions can be realized. moreover, software digital servos convert all error amounts to digital values and store them in memory, resulting in accurate sample-and-hold operation. therefore, unlike analog servo systems, hold values do not change due to capacitor leak.
chapter 4 outline of vcr servo system 34 <2> compactness and light weight the number of discrete parts is minimized to enable high-density mounting (reduced mounting space). moreover, compensation filter is realized as a digital filter, resulting in improved reliability as well as reduction of the number of parts. <3> flexible of servo control software servos can freely change servo system gain according to the amount of speed error/phase error. moreover, trick plays such as suspension of control and open loop control for a given time period according to the error amount can be easily realized. also, ai-related functions such as digital tracking can be integrated. <4> easy product development of vcr set software servos easily keep up with changes of the drum motor and capstan motor to be used simply by changing software. as a result, design with a high degree of freedom is made possible. software servos flexibly support various tv broadcasting systems in the world (such as ntsc and pal), enabling worldwide use of vcr sets. to realize software servo control of a vcr, the microcontroller to be used is required to have an advanced arithmetic ability and strong timer function. in order to easily realize servo control, the m pd784915 subseries incorporates a variety of peripheral hardware such as the super timer unit and analog circuits for vcr, which are ideal for software servo control of vcrs. by incorporating a 16-bit cpu, the m pd784915 supports high-speed arithmetic instructions and large capacity memory. therefore, it can easily handle servo processing, which must be real-time, and makes system/servo/timer control of vcrs possible with a single chip. 4.2 servo control of vcr a vcr records video signals forming diagonal patterns on magnetic tape (video tape) using a rotary head. this recording method is called rotary head azimuth recording system. the recorded pattern of the video signals on the magnetic tape is strictly specified with each format such as vhs system and b system. figure 4-1 shows the track pattern of video tapes. the recording pattern of video signals is as thin as several tens of microns. during vcr playback, the head must accurately trace the recording pattern. this operation is called tracking. forming of the recording pattern and playback tracking are controlled by the rotating condition of the rotary head and the running condition of the tape. a vcr has a drum motor to control the rotation of the rotary head and a capstan motor to control tape running. the vcr carries out record/playback by controlling these two motors. the servo for recording and playback is explained below.
chapter 4 outline of vcr servo system 35 figure 4-1. track pattern on video tape remark vhs standard tape speed standard mode : 33.35 mm/s triple mode : 11.12 mm/s audio head audio track control track control head tape running direction playback control signal head direction one field? video signal vertical synchronous signal video track
chapter 4 outline of vcr servo system 36 4.3 servo for recording a vcr records exactly one fields video signals on each video track recorded diagonally on a video tape. in tv broadcasting, a frame is composed of two fields. on a video track, positions on which synchronous signals are recorded are specified. therefore, control should be made so that the recording drum motor servo synchronizes with the frame cycle of the input video signal and the relation of the position of the video head and vertical synchronous signal are kept constant. on the other hand, the capstan motor rotates at constant speed because it runs tape accurately at the speed defined in each format. in addition to these, home vcrs of vhs and b system, etc., record control signals synchronized with the rotation of the drum along with the longer direction of the tape when recording is performed. control signal is a pulse signal with 30 [hz] cycle which is used as a mark when performing playback tracking. remarks 1. video tape running speed of vhs system vcr is 33.35 [mm/s] in standard mode and 11.12 [mm/s] in triple mode. 2. for vhs system vcrs, control signal pulse is normally specified as a signal with 60% high level and 40% low level. 4.4 servo for playback when playing back, rotation of a drum motor and control signals played back from the video tape is synchronized with the reference frame cycle generated in the servo control circuit. thereby, the drum motor and the control signals are synchronized indirectly using the reference signal as an intermediary so that the relation between them are made the same as when recording. as a result, the head is controlled to accurately trace the track on the tape, because the running condition of the tape and the rotation of the head become the same as when recording. in addition, because the recording condition of the control signals are uneven among sets, it needs to be corrected. thereby, the relation of the position of the control signals and the video head can be externally adjusted. this is called tracking adjustment. when playing back, the amount of the tracking adjustment is set using an external potentiometer (vr).
chapter 4 outline of vcr servo system 37 4.5 motor to be used generally, a dc motor is used for vcrs (drum motor and capstan motor). dc motors are motors whose rotation speed varies according to the applied voltage. direct drive systems, in which no belts and gears are involved, are becoming the mainstream in the driving method of drum and capstan. the rotation speed of dc motors fluctuates according to variations in the load and the applied voltage. therefore, servo systems must control the rotation speed and rotation phase. rotation speed control keeps the motor rotation constant. rotation phase control keeps the relationship between the phase signal and reference phase signal of the motor constant.
chapter 4 outline of vcr servo system 38 4.6 vcr control systems vcrs are mainly composed of the following control systems. (1) system control supervises and controls the whole vcr system. (2) servo control controls drum motor, capstan motor, and related operations. (3) timer control performs clock function such as timer reservation, front panel control, and display control. (4) camera control (camcorder) performs camera section control such as af and ae. (5) others blurring correction control, etc. (camcorder). the m pd784915 is a 16-bit single-chip microcontroller which can perform the three types of control (1) to (3) listed above. especially, the super timer unit incorporated in the m pd784915 is designed to easily realize software digital servo control. 4.7 vcr servo system control servo systems for vcrs control the drum motor for the rotating head and the capstan motor, which runs the tape in low speed. the vcr elements controlled by a servo system are shown below. (1) drum motor speed/phase control (2) capstan motor speed/phase control (3) generation of head switching signal (4) generation of quasi-v sync signal for special playback (5) generation of recording control signal (recctl) (for recording), rewriting (for playback) (6) index search control (viss detection) remark this manual mainly explains the method to perform servo control shown in 4.6 (2) and other controls shown in 4.7 (1) to (6) .
chapter 5 examples of stationary type vcr servo control 39 chapter 5 examples of stationary type vcr servo control this chapter describes examples of stationary type vcr servo system control. 5.1 examples of system configuration in this chapter, the drum motor whose fg wave number (the number of fg signals generated in one rotation of the motor) is 24 poles and the capstan motor whose fg wave number is 36 poles are assumed to be used. the drum motor is controlled so that the number of rotations is equal to the frame frequency of tv broadcast f f = 29.97 hz (ntsc) (the number of rotation is 29.97 r.p.s.) with the servo system locked. therefore, the drum fg signal frequency f dfg is as follows: ? f dfg = f f fg wave number = 719.28 [hz] similarly, the capstan motor fg frequency in standard mode (sp mode) is as follows: ? f cfgsp = 1080 [hz] the capstan motor fg frequency in triple mode (ep mode), since it is one third the speed of the standard mode, is as follows: ? f cfgsp = 1080 3 = 360 [hz] each motor is driven by pwm output pulse smoothed in external circuit and input to motor driving driver. pwm0 output is used for driving the drum motor and pwm1 output for capstan motor. pwm output pulse is smoothed (carrier elimination) through external low pass filter (c-r filter, etc.), impedance converted with operation amplifier, etc., and then input to motor driving driver. figure 5-1 shows an example of vcr system configuration to be controlled in this manual.
chapter 5 examples of stationary type vcr servo control 40 figure 5-1. application to stationary type vcr stb clk dout din fip c/d pd16311 cs clk data tuner remote control signal pc2800a remote control receive signal port sck2 so2 csyncin pto00 pto01 p80 port intp2 x1 x2 xt1 xt2 8 mhz 32.768 khz dfgin dpgin pwm0 cfgin pwm1 recctl+ recctl pwm2 reel0in reel1in video head switch audio head switch audio video system signal processing circuit m loading motor ctl head capstan motor cfg m drum motor driver dpg dfg low-frequency oscillation mode mechanical block m m m osd pd6454 reel motor reelfg0 reelfg1 pwm4 pwm3 port sck1 si1 so1 port port pwm5 fip key matrix pd784915 driver driver driver driver composite synchronizing signal quasi-vertical synchronizing signal m m m m
chapter 5 examples of stationary type vcr servo control 41 5.2 outline of system this system performs vcr servo control using the m pd784915. the system executes most of the dedicated digital servo ic functions which have been built in the original sets by software. moreover the system configures the loop filter, which is a compensation element of the servo system, with a digital filter and realizes it with arithmetic processing by software. figure 5-2 shows the processing block diagram in the software digital servo system. the vcr servo system performs speed/phase control of the drum and capstan motor. therefore, speed control loop and phase control loop exist in the control loop of each motor. the fg signal output from the motor is used for detection of the speed error amount and pg signal for detection of the phase error amount. the gains of speed control system and phase control system are set independently from each other. the detected speed and phase error amount are added respectively and then converted to pwm with bias value added. pwm pulse drives each motor after carriers are eliminated through external low pass filter. the m pd784915 is equipped with analog amplifiers so that amplification of fg and pg signal output from each motor is possible. the value of the servo circuit built in the set is used as it is for the error amount detection gain and the characteristics of loop filter in the servo system. in addition to the speed/phase control of drum and capstan motor explained above, the system also generates head switching signal, quasi vertical synchronizing signal, etc.
chapter 5 examples of stationary type vcr servo control 42 figure 5-2. software digital servo system block diagram remark the process in the m pd784915 is shown in the broken line. m m carrier elimination filter carrier elimination filter recctl head hsw generation recctl generation pbctl amplifier composite synchronizing signal speed error detection phase error detection phase error detection digital filter dfgamplifier dpgcomparator (drum speed gain) (drum phase gain) (capstan phase gain) kv kp kv kp cfgamplifier (capstan speed gain) dfgsignal dpgsignal (buffer) (buffer) digital filter bias value addition bias value addition pwm conversion pwm conversion cfgsignal motor driver motor driver drum motor capstan motor v sync separation circuit vertical synchronizing signal speed error detection digital filter
chapter 5 examples of stationary type vcr servo control 43 5.3 using example of super timer unit table 5-1 shows the using examples of the super timer unit, and figure 5-1 shows the super timer unit block diagram. table 5-1. using examples of super timer unit timer/counter name register use event counter (ec) ecc0/ecc1/ecc2/ecc3 generation of internal head switching signal timer 0 (tm0) cr00 video head switching signal delay control cr01 audio head switching signal delay control cr02 quasi-vsync output timing control free running counter (frc) cpt0 reference phase detection (for drum phase control) cpt1 drum motor phase detection (for drum phase control) cpt2 drum motor speed detection (for drum speed control) cpt3 capstan motor speed detection (for capstan speed control) cpt4, cpt5 tape remain detection by reel fg input timer 1 (tm1) cr10 generation of internal reference signal (for playback) buffer oscillator for missing vsync (for recording) cr11 recctl output timing control cr12 capstan motor phase control (for capstan phase controller) cr13 unnecessary vsync input mask control timer 3 (tm3) cr30, cr31 pbctl signal duty detection timing control cpt30 pbctl signal cycle measurement timer 2 (tm2) cr20 can be used as an interval timer (for system controller) timer 4 (tm4) cr40 remote control signal duty detection (for remote control decode) cr41 remote control signal cycle measurement (for remote control decode) timer 5 (tm5) cr50 can be used as internal timer (for system controller) up/down counter udcc generation of linear tape counter
chapter 5 examples of stationary type vcr servo control 44 figure 5-3. super timer unit block diagram (1/2) capture dpgin dfgin csyncin reel0in reel1in cfgin pbctl pto10 pto11 frequency divider selector clear ec ecc3 ecc2 ecc1 ecc0 f/f f/f mask mask v sync separation circuit capture capture capture capture capture clear edv edvc clear tm3 cr30 cr31 cpt30 capture ctl f/f fflvl capture tm1 cr10 cr11 cr12 cr13 clear output control circuit output control circuit output control circuit frc cpt0 cpt1 cpt2 cpt3 cpt4 cpt5 h sync separation circuit cr00 tm0 cr01 cr02 rtp,a/d rtp rtp,a/d p80 intcr00 intcr01 intcr02 intclr1 intcpt1 intcpt2 intcpt3 intp3 intcr10 intcr11 intcr12 intcr13 intcr30 to pbctl signal input pto11 pto10 pto02 pto01 pto00 00h write to ec output control circuit output control circuit v-hsw a-hsw recctl pbctl cfg comp sync dfg dpg analog circuit superim -position selector selector selector selector selector selector selector selector selector selector selector selector superim -position selector selector selector clear
chapter 5 examples of stationary type vcr servo control 45 figure 5-3. super timer unit block diagram (2/2) clear tm2 cr20 intcr20 clear intcr40 tm4 cr40 cr41 mask intp2 clear intcr50 tm5 cr50 intudc udc udcc pbctl pto11 pto10 up/down edvcoutput p77 selud rtp, a/d remote control receive signal pbctl selector selector selector selector selector
chapter 5 examples of stationary type vcr servo control 46 5.4 head switching signal generation 5.4.1 internal head switching signal (hsw-n) generation (a) hsw-n generation method this system uses timer 0 clear pulse as phase comparison signal in the drum phase control system. this is called internal head switching signal (hsw-n). hsw-n is a pulse with 50% duty which is generated from pg and fg signals from the drum motor and synchronizes with the drum rotation. m pd784915 can generate hsw-n from drum fg signal (dfg signal) and drum pg signal (dpg signal) using event counter (ec). the dpg signal is input to the dpgin pin and the dfg signal to the dfgin pin of the m pd784915. the pulse generated here is one which is reset, after dpg input, at the rising edge of the second dfg signal and at the falling edge of the fourteenth dfg signal. in this case, the following values are set to the two compare registers of ec. ecc1...01h ecc0...0dh ec output changes at the clock after the clock at which the ec coincides with the compare register. therefore, the value with 1 subtracted is set as the setting value to the compare register. figure 5-4 shows the use of ec, and figure 5-5 shows the operation timing of ec. timer 0 is cleared at the rising and falling edges of hsw-n generated in ec. figure 5-4. use of event counter (ec) ecc3 = 00h ecc2 = 00h ecc1 = 01h ecc0 = 0dh dfgsignal through clear 00h write to ec coincidence coincidence s r q ec- f/f1 internal head switching signal (hsw-n) dpgin dfgin dpgsignal ec analog circuit
chapter 5 examples of stationary type vcr servo control 47 figure 5-5. event counter (ec) operation timing 1234567891011121314151617181920212223241234 123456789abcdef1011121314151617 18 1234 0 19 (clear) 0 (clear) (set) (reset) (set) 29.97 hz (33.37 ms) dfg signal input (dpgin pin) dfg signal input (dfgin pin) ec count value hsw-n internal head switching signal
chapter 5 examples of stationary type vcr servo control 48 5.4.2 head switching signal (v-hsw) generation (a) v-hsw generation method a vcr is required to externally adjust the head switching signal (v-hsw) and correct the mounting position of the pg signal detector. in order to perform the correction, the internal head switching signal (hsw-n) generated as shown in 5.4.1 is delayed using timer 0 programmable pulse delay circuit. figure 5-6 shows the use of timer 0. figure 5-7 shows the v-hsw timing. timer 0 is a timer which is cleared at both rising and falling edges of hsw-n. when a digital value equivalent to the amount of the head switching signal delay is set to compare register 00 (cr00), signals with hsw-n are delayed according to the value set to the compare register are output from the pto00 output pin. this signal is used as the actual v-hsw. the relation between the digital value set to cr00 and the delay amount is as follows: delay amount = (setting value to cr00) 8/f clk at 16-mhz operation, 8/f clk = 1 [ m s], then, this is the resolution of timer 0. in order to correct the positional relation of the pg signal detector and pg magnet, the delay amount to hsw- n should be externally adjustable. thereby, the data stored in cr00 should be adjustable with analog voltage externally input using the a/d comparator of the m pd784915. the digital value stored in cr00 is set as follows: ? in ep mode/ lp mode (setting value to cr00) = (a/d conversion result) 11 + 012ch ? in sp mode (setting value to cr00) = (a/d conversion result) 13 + 0190h when using analog circuit, ec is counted at the reverse edge of the dfg signal, so that correction is required as follows: ? in ep mode/lp mode (setting value to cr00) = (a/d conversion result) 11 + 0120h ? in sp mode (setting value to cr00) = (a/d conversion result) 13 + 0150h
chapter 5 examples of stationary type vcr servo control 49 figure 5-6. use of timer 0 dpgin pin input internal pulse by ec selector en clr0 internal head switching signal(hsw-n) output control circuit output control circuit output control circuit intcr00 intcr01 intcr02 pto00 pto01 pto02 rtp h sync separation circuit tm0 v-hsw (cr00) a-hsw (cr01) quasi-v sync (cr02) f clk /8
chapter 5 examples of stationary type vcr servo control 50 figure 5-7. head switching signal (v-hsw) timing (pto00) remark t d1 : head switching signal delay amount (clear) (16.68 ms) cr00 cr00 cr00 cr00 d1 2 131415 24 2 131415 2 29.97 hz (33.37 ms) dpg signal input (dpgin pin) dfg signal input (dfgin pin) internal head switching signal (hsw-n) head switching pulse signal (v-hsw) (pto00 pin) tm0 count value (clear) (clear) (clear) (clear)
chapter 5 examples of stationary type vcr servo control 51 (b) timer mode setting the timer mode setting when generating head switching signal (v-hsw) is as shown in figure 5-8 to 5-11. figure 5-8. input control register (icr) format (when generating v-hsw) 7 selclr0 6 ecfflvl 5 ecmod 4 ecffclr 3 seldpg1 2 seldpg0 1 0 0 0 icr address ff50h seldpg1 0 dpg signal frequency division specification do not divide seldpg0 0 ecffclr reset ff1 and ff2 of ec when writing 0 (when reading, 1 is always read ) after reset 10h r/w r/w r/w r/w ecmod 1 event counter operation mode selection internal pulse generation mode r/w ecfflvl ec output pulse level r selclr0 1 r/w timer 0 clear pulse selection ec output pulse
chapter 5 examples of stationary type vcr servo control 52 figure 5-9. timer 0 output mode register (tom0) format (when generating v-hsw) figure 5-10. timer 0 output control register (toc0) format (when generating v-hsw) 7 6 5 mod021 4 mod020 3 mod011 2 mod010 1 mod001 0 mod000 tom0 address ff58h mod001 1 pto00 output mode specification delay pulse output mode 2 mod000 1 mod0n1 0 0 1 1 pto0n output mode specification (n=1, 2) general-purpose output mode rs output mode delay pulse output mode 1 delay pulse output mode 2 mod0n0 0 1 0 1 after reset 000000 r/w w 7 enhsy 6 selpto 5 ento02 4 alv02 3 ento01 2 alv01 1 ento00 0 alv00 toc0 address ff59h alv00 1 pto00 timer output active level specification active high ento00 1 pto00 timer output enable specification output enabled after reset 00h r/w w alv0n 0 1 pto0n timer output active level specification (n = 1, 2) active low active high ento0n 0 1 pto0n timer output enable specification output disabled (fixed to inactive level) output enabled selpto 0 1 h sync superimposition pin specification superimpose to pto02 superimpose to pto01 enhsy 0 1 h sync superimposition enable to pto0n pin specification do not superimpose superimpose
chapter 5 examples of stationary type vcr servo control 53 figure 5-11. timer control register 0 (tmc0) format (when generating v-hsw) 7 cs1 6 selfflg 5 atmsk 4 enclr1 3 cs0 2 inttmsk 1 0 0 enclr0 tmc0 address ff38h inttmsk h sync separation circuit initialization flag initialize h sync separation circuit mask period measurement counter when writing 1. when reading, 0 is always read. after reset 00h r/w r/w r/w r/w cs0 1 timer 0 operation count operation r/w r/w atmsk 0 1 r/w csync signal mask auto cancellation control csync signal mask is not canceled with tm1-cr13 coincidence signal csync signal mask is canceled (set enclr1) with tm1- cr13 coincidence signal enclr0 1 timer 0 clear control clear tm0 with tm0 clear signal enclr1 0 1 timer 1 clear control mask csync signal input. tm1 is not cleared. tm1 is cleared with csync signal input selfflg 0 1 r h sync self generation condition self generation pulse is not output self generation pulse is output cs1 0 1 r/w timer 1 operation control clear and stop counting count operation
chapter 5 examples of stationary type vcr servo control 54 5.4.3 audio head switching signal (a-hsw) generation (a) a-hsw generation method a hi-fi vcr requires audio head switching signal (a-hsw) because it records audio signals on the video track with a rotating head. the audio head is tilted at 270 degrees against the video head, so that a-hsw is output at 270 degrees against the head switching signal (v-hsw). a-hsw is generated, as well as v-hsw, using timer 0 pulse delay circuit. the compare register uses cr01. figure 5-12. assigning a-hsw to timer 0 a-hsw is tilted at 270 degrees, so that correction of more than 180 degrees is necessary. the delay pulse output mode 1 is used for 180 -degree correction of a-hsw while the delay pulse output mode 2 is used for v-hsw. therefore, the delay amount to cr01 is set for the remaining 90 degrees. the value of v-hsw delay amount with one fourth of a cycle (90 degrees) added is set as the digital value to cr01. cr01 = cr00 + 1/4 of one v-hsw cycle (1/4 of frame cycle) figure 5-13 shows the v-hsw and a-hsw timings. hsw-n tm0 pto00 (v-hsw signal) pto01 (a-hsw signal) f clk /8 coincidence coincidence clear cr00 cr01
chapter 5 examples of stationary type vcr servo control 55 figure 5-13. v-hsw and a-hsw timings (b) timer mode settings figures 5-14 to 5-16 show the timer mode settings when generating audio head switching signal (a-hsw). figure 5-14. timer 0 output mode register (tom0) format (when generating a-hsw) (set) (reset) (set) (reset) clear clear clear clear cr01 cr01 cr01 cr00 cr00 cr00 12345678910 12 14 16 18 20 22 dpg signal input (dpgin pin) dfg signal input (dfgin pin) hsw-n internal head switching signal a-hsw (pto01 pin) v-hsw (pto00 pin) timer 0 count value ec clear ec clear t d1 t d2 2 4 6 8 10 12 14 16 24 7 6 5 mod021 4 mod020 3 mod011 2 mod010 1 mod001 0 mod000 tom0 address ff58h mod011 1 pto01 output mode specification delay pulse output mode 1 mod010 0 mod0n1 0 0 1 1 pto0n output mode specification (n = 0, 2) general-purpose output mode rs output mode delay pulse output mode 1 delay pulse output mode 2 mod0n0 0 1 0 1 after reset 000000 r/w w
chapter 5 examples of stationary type vcr servo control 56 figure 5-15. timer 0 output control register (toc0) format (when generating a-hsw) 7 enhsy 6 selpto 5 ento02 4 alv02 3 ento01 2 alv01 1 ento00 0 alv00 toc0 address ff59h alv0n 0 1 pto0n timer output active level specification (n = 0, 2) active low active high after reset 00h r/w w ento0n 0 1 pto0n timer output enable specification (n = 0, 2) output disabled (fixed to inactive level) output enabled ento01 1 pto01 timer output enable specification output enabled selpto 0 1 h sync superimposition pin specification superimpose to pto02 superimpose to pto01 enhsy 0 1 h sync superimposition enable to pto0n pin specification do not superimpose superimpose alv01 1 pto01 timer output active level specification active high
chapter 5 examples of stationary type vcr servo control 57 figure 5-16. timer control register 0 (tmc0) format (when generating a-hsw) 7 cs1 6 selfflg 5 atmsk 4 enclr1 3 cs0 2 inttmsk 1 0 0 enclr0 tmc0 address ff38h inttmsk h sync separation circuit initialization flag initialize mask period measurement counter of h sync separation circuit when writing 1. when reading, 0 is always read. after reset 00h r/w r/w r/w r/w cs0 1 timer 0 operation control count operation r/w r/w atmsk 0 1 r/w csync signal mask auto cancellation control csync signal mask is not canceled with tm1-cr13 coincidence signal csync signal mask is canceled (set enclr1) with tm1-cr13 coincidence signal enclr0 1 timer 0 clear control clear tm0 with tm0 clear signal enclr1 0 1 timer 1 clear control mask csync signal input. tm1 is not cleared. tm1 is cleared with csync signal input selfflg 0 1 r h sync self generation condition self generation pulse is not output self generation pulse is output cs1 0 1 r/w timer 1 operation control clear and stop counting count operation
chapter 5 examples of stationary type vcr servo control 58 5.5 drum speed control the drum fg signal (dfg) from the drum motor is input to dfgin input pin of the m pd784915. the value of the free running counter (frc) is captured to capture register 2 (cpt2h and cpt2l) at the rising edge of dfg and intcpt2 interrupt request is generated. since the frc of the m pd784915 is 22-bit configuration and has 6 cpts (22-bit), the measurement of generation cycle can be carried out for 6 types of capture trigger. the cpt is configured with cpt2h, which captures the higher 6 bits, and the cpt2l, which captures the lower 16 bits. the frc value is stored in cpt2h and cpt2l respectively with dfg input. this program uses the frc as speed control information by dfg input. the drum speed error amount is calculated in intcpt2 interrupt processing routine. in intcpt2 interrupt processing routine, the cycle of fg signal is measured by subtracting the current capture value. then, the speed error amount is detected by comparing the cycle data when the speed control system is locked. the concrete method of finding the drum speed error amount is shown below. figure 5-18 shows an example of drum speed control timings. figure 5-17. drum speed error amount detection method dfgin pin input intcpt2 f clk (8 mhz) drum speed control interrupt frch cpt2h frcl cpt2l
chapter 5 examples of stationary type vcr servo control 59 figure 5-18. drum speed control timings when the frame frequency of tv broadcast is assumed as f f , the f f is as follows: ? f f = 29.97 [hz] then, since the drum fg wave number is 24 poles, the drum fg signal frequency in the standard playback is as follows: ? f dfg = 24 f f = 719.28 [hz] therefore, the drum fg signal cycle ndfg becomes as follows: t dfg = 1 f dfg n dfg = t dfg = 1 = 11122.2 = 2b72h [count] t frc t frc f dfg where: t frc = 125 [ns] the drum speed error amount e dv is represented by the following expression: e dv = (n dv n C n dv nC1 ) C n dfg = d n dv n C n dfg intcpt2 intcpt2 intcpt2 n? n n+1 n n? dv n n dv n n+1 dv d n n dv dfgin drum fg signal 719.28 [hz] (1.39 [ms]) frc count
chapter 5 examples of stationary type vcr servo control 60 in the above expression, n dv n represents the value of the free running counter (frc) captured at the n-th fg pulse. the meanings of the signs for the drum speed error amount e dv calculated from the expression above are as follows: (1) when dfg cycle is longer than the target value...+ (when the rotation of the drum motor is slow) (2) when dfg cycle is shorter than the target value...C (when the rotation of the drum motor is fast) 5.6 drum phase control the drum phase error amount is detected by comparing the capture value (cpt1) of the free running counter (frc) by the internal head switching signal (hsw-n) and the frc capture value (cpt0) by the reference frame cycle (v sync for recording, the coincidence of timer 0 and compare register 10 (cr10) for playback). basically, the only difference between the processing for recording and for playback is that the capture source of the capture 0 (cpt0) of frc is switched. 5.6.1 phase reference timer 1 of the super timer unit is used to generate the phase/reference signal of the servo system in all the modes. the tm1 operation differs for recording and for playback. figure 5-19 shows the tm1 peripheral circuit. the setting of selectors differs for recording and playback. [for recording] when recording, tm1 is operated as an interval timer synchronized with the frame cycle of tv broadcast. composite synchronizing signal is input for csyncin input pin. tm1 is cleared at the rising edge of the composite synchronizing signal using a digital noise elimination circuit incorporated in the cpu. thus, timer 1 is operated as a frame synchronous interval timer synchronized with vertical synchronous signal input externally. approximately 90% of the frame sync of the csyncin pin input should be masked so that misoperation caused by noise, etc., is prevented. [for playback] when playing back, tm1 is operated as a free running interval timer which has the frequency equal to the frame cycle of tv broadcast. the value corresponding to the frame cycle is stored in cr10 of tm1 because vertical synchronous signal is not externally input when playing back. when playing back, tm1 clear timing is the reference signal of phase control. the phase reference signal is the tm1 clear timing.
chapter 5 examples of stationary type vcr servo control 61 figure 5-19. timer 1 peripheral circuit (selector) event counter output csyncin composite synchronizing signal input digital noise elimination circuit block en clr1 tmc0 at msk internal head switching signal (hsw-n) csync signal input edge (selector) (vsync signal) tm1-cr10 coincidence signal tm1 clear signal f clk /8 f clk frc cpt0 cpt1 clear tm1 cr10 cr13 coincidence coincidence intcr10 intcr13 intcpt1 intclr1 ...
chapter 5 examples of stationary type vcr servo control 62 (1) phase reference for playback when playing back, enclr1 flag is reset and timer 1 (tm1) clear by clr1 input is always disabled. data which makes the tm1 clear interval equal to the frame cycle is set to compare register 10 (cr10). thereby, tm1 is operated as a free running interval timer having the frequency equal to the frame cycle. figure 5-20 shows the tm1 operation timings for playback. since the reference frame cycle is 33.366 [ms], the set value of cr10 is as follows: cr10 = 33.366 [ms] = 33366 = 8256h 1.0 [ m s] figure 5-21 shows the mode settings of timer 1 for playback.
chapter 5 examples of stationary type vcr servo control 63 figure 5-20. example of timer 1 operation timings (for playback) frame cycle (33.37 ms) coincides with cr10 (clear) cr10 = 8256h (clear) coincides with cr10 (clear) coincides with cr10 (clear) tm1 count value
chapter 5 examples of stationary type vcr servo control 64 figure 5-21. timer control register 0 (tmc0) format (drum phase control for playback) 7 cs1 6 selfflg 5 atmsk 4 enclr1 3 cs0 2 inttmsk 1 0 0 enclr0 tmc0 address ff38h inttmsk h sync separation circuit initialization flag when writing 1, mask period measurement counter of h sync separation circuit is initialized. when reading, 0 is always read. after reset 00h r/w r/w r/w r/w cs0 0 1 timer 0 operation control clear and stops counting count operation r/w r/w atmsk 0 1 r/w csync signal mask auto cancellation control csync signal mask is not canceled by tm1-cr13 coincidence signal csync signal mask is canceled by tm1-cr13 coincidence signal (enclr1 is set). enclr0 0 1 timer 0 clear control mask timer 0 clear signal. tm0 is not cleared. tm0 is cleared by tm0 clear signal enclr1 0 timer 1 clear control mask csync signal input. tm1 is not cleared. selfflg 0 1 r h sync self generation condition self generation pulse is not output self generation pulse is output cs1 1 r/w timer 1 operation control count operation
chapter 5 examples of stationary type vcr servo control 65 (2) phase reference for recording when recording, timer 1 (tm1) is operated as an interval timer synchronized with a vertical synchronizing signal. figure 5-22 shows an example of tm1 operation timings for recording. composite synchronizing signals are input from the video processing circuit to the csyncin input pin. the composite synchronizing signal includes cut-in pulse, equalizing pulse, and horizontal synchronizing signal, as well as vertical synchronizing signal, so that vertical synchronizing signal needs to be separated from these signals. the digital noise elimination circuit incorporated in the m pd784915 is used for this purpose. by using the digital noise elimination circuit, it is possible to clear tm1 at the rising edge of the vertical synchronizing signal included in the composite synchronizing signal and generate interrupt for intclr1. tm1 is cleared in synchronization with the falling edge of the vertical synchronizing signal in the composite synchronizing signal input to the csyncin pin. if noise is mixed in the composite synchronizing signal input to the csyncin pin, tm1 clear may be mistakenly carried out. tm1 clear by csyncin input is disabled for the certain period of time using the enclr1 flag and compare register 13 (cr13) in csyncin input which controls tm1 clear enable/disable. figure 5-23 shows the timer 1 mode setting for recording. in this program, tm1 clear input disabled time is set to approximately 90% of the frame cycle after inputting a separated vertical synchronizing signal. since the frame cycle is 33.36 [ms], the time 90% of it is calculated as follows: 33.36 0.9 = 30.03 [ms] in this program, the mask period is set with cr13 so that interrupt is generated at a point which is 90% of a field cycle. since the tm1 count clock frequency is f clk /8 = (1.0 [ m s]), the value set for cr13 is as follows: cr13 = 30.03 [ms] = 30030 = 754eh 1.0 [ m s] when the atmsk flag, which controls csyncin signal mask auto cancellation, is set, 754eh is set to cr13, and the timer is started, enclr1 control bit is set when 90% of a field cycle is passed. if enclr1 control bit is controlled, csyncin pin input is masked for the 90% period of time of a frame cycle. if, for some reason, vertical synchronizing signal is not input, the compare register 10 (cr10) value is set so that clear is executed at a cycle approximately equal to the frame cycle by coincidence signal of cr10 of timer 1 and timer 1. in this case, cr10 is set with additional 3% of the frame cycle. therefore, as the frame frequency is 29.97 [hz] (33.36 [ m s]), the set cycle is as follows: 33.36 1.03 = 34.37 [ms]
chapter 5 examples of stationary type vcr servo control 66 since the count clock frequency of timer 1 is f clk /8 = (1.0 [ m s]), the set value to cr10 is as follows: cr10 = 34.37 [ms] = 34370 = 8642h 1.0 [ m s]
chapter 5 examples of stationary type vcr servo control 67 figure 5-22. example of timer 1 operation timings (for recording) missing vertical synchronizing signal occurs field cycle 59.94 (hz) (16.68 ms) cr10 = 8642h coincidence with cr13 (clear) clear at coincidence with cr10 vertical synchronizing signal after separation frame cycle 29.97(hz) (33.37 ms) (mask) (mask) (window) (window) tm1 count value enclr1 bit 90% of frame cycle is masked (mask time is set with cr13) ? ? cr13 = 754eh (window) (mask) (clear)
chapter 5 examples of stationary type vcr servo control 68 figure 5-23. timer control register 0 (tmc0) format (drum phase control for recording) 7 cs1 6 selfflg 5 atmsk 4 enclr1 3 cs0 2 inttmsk 1 0 0 enclr0 tmc0 address ff38h inttmsk h sync separation circuit initialization flag when writing 1, h sync separation circuit mask period measurement counter is initialized. when reading, 0 is always read. after reset 00h r/w r/w r/w r/w cs0 0 1 timer 0 operation control clear and stops counting count operation r/w r/w atmsk 1 r/w csync signal mask auto cancellation control csync signal mask is canceled by tm1-cr13 coincidence signal (enclr1 is set) enclr0 0 1 timer 0 clear control mask timer 0 clear signal. tm0 is not cleared. tm0 is cleared by tm0 clear signal enclr1 1 timer 1 clear control tm1 is cleared by csync signal input selfflg 0 1 r h sync self generation condition self generation pulse is not output self generation pulse is output cs1 1 r/w timer 1 operation control count operation
chapter 5 examples of stationary type vcr servo control 69 5.6.2 drum phase control for playback for drum phase control for playback, drum motor rotation phase is synchronized with a reference timer which has the frequency equal to the tv broadcast frame cycle f f . timer 1 (tm1) of super timer unit is used for the reference timer as mentioned earlier. for vhs standards, the locking point of the drum phase in this program is specified as 6.5h before the phase reference signal. 1h, here, shows one cycle of horizontal synchronizing signal (1h = 63.56 [ m s]). figure 5-24 shows the use of timer for drum phase control for playback. figure 5-25 shows the drum phase control timing chart for playback. figure 5-24. use of timer for drum phase control (for playback) capture frc cpt0 tm1 (clear) cr10 intcr10 operates as a reference timer for generating phase reference signal for playback
chapter 5 examples of stationary type vcr servo control 70 figure 5-25. drum phase control timing (for playback) tm1 count value frc count value hsw-n hsw pulse delay amount phase lock delay amount cpt1 cr10 intcr10 (drum phase error amount detection) hsw-n falling edge cpt0 coincidence signal with tm1 and cr10 v-hsw (pto00)
chapter 5 examples of stationary type vcr servo control 71 the drum phase error amount detection method is shown below. the count value of free running counter (frc) is stored in the capture register 1 (cpt1) at the falling edge of internal head switching signal (hsw-n). intcr10 interrupt is generated at the coincidence timing with the count value of timer 1 (tm1) and compare register 10 (cr10). the value of frc is, at the same time, stored in cpt0. the drum phase error amount e dp is shown in the expression below. figure 5-26 shows the method to set cpt0 and cpt1 capture trigger source. e dp = ( (cpt0 value) C (cpt1 value) ) C n dpl n dpl , here, is the target value of drum phase control. the count clock of the capture registers of cpt0 and cpt1 is 125 [ns] of frc. however, since timer 0 (tm0) to generate head switching signal (v-hsw), which is the object of comparison, is 1 [ m s], cpt1 is subtracted from cpt 0, and then the result is made 1/4 so that data can be handled in 16 bits. the sampling clock cycle of drum phase error, hereafter, is calculated as 0.5 [ m s]. the target value of the drum phase control n dpl is the remainder of the subtraction between cpt0 and cpt1, therefore, calculated with the following expression. n dpl =+++ each value of the above expression is calculated here. (1) the digital value equivalent to the head switching signal (v-hsw) delay amount the digital value equivalent to the head switching signal (v-hsw) is calculated. the v-hsw delay is stored in compare register 00 (cr00) of timer 0 as the delay amount from hsw-n. the tm0 sampling clock frequency is twice as large as that of the drum phase error. therefore, the value equivalent to v-hsw delay amount when counted with frc is twice as large as the value set in cr00. (2) the delay amount for half a frame cycle the half of a frame cycle t f /2 is stored in cr10, therefore: cr10/2 = 16.68 [ms] the above value is counted with the sampling clock cycle 0.5 [ m s] of drum phase error as follows: video head switching pulse delay amount delay amount for half a frame cycle delay amount for 6.5h delay for v sync separation
chapter 5 examples of stationary type vcr servo control 72 cr10/2 = cr10 0.5 [ m s] (3) the delay amount for 6.5h 1h = 63.56 [ m s], therefore, the time for 6.5 h is: 63.56 6.5 = 413.14 [ m s] therefore, if counted with the drum phase error sampling clock: 413 [ m s] = 826 0.5 [ m s] (4) the delay for v sync separation drum control system for recording uses the vertical synchronizing signal v sync as the phase reference signal. v sync , here, is acquired by being separated from the composite synchronizing signal in order to make the phase control system program for playback and recording equal. the delay time for v sync separation is with the time for the separation is considered. m pd784915 is equipped with digital noise elimination circuit, so that 13.5 [ m s] (inttm2.4 = 0) of the delay is the delay for v sync separation. if the time for 13.5 [ m s] necessary for v sync separation is counted with the sampling clock of the drum phase error, the value is as follows: 13.5 [ m s] = 27 0.5 [ m s] from above, n dpl is calculated as follows: ndpl = (cr00 2) + (cr10) + 826 + 27 = (cr00 2) + (cr10) + 355h the drum phase error amount is calculated from the free running counter (frc) value (cpt1) captured at the falling edge of the internal head switching signal (hsw-n) and the frc value (cpt0) captured at the timer 1 (tm1) clear timing. therefore, the capture trigger selector of cpt0 is switched so that the cpt0 capture trigger source becomes the coincidence signal of the tm1 value and compare register 10 (cr10).
chapter 5 examples of stationary type vcr servo control 73 timer 1 (tm1) is used as a reference timer which is cleared with frame cycle. the value set to cr10 of tm1 is as follows: cr10 = 33.366 [ms] = 33366 = 8256h 1.0 [ m s] figure 5-26. capture mode register (cptm) format 7 fcpt5 6 fcpt4 5 trgs011 4 trgs010 3 0 2 trgs120 1 trgs001 0 trgs000 cptm address ff53h trgs001 0 cpt0 capture trigger specification tm1-cr10 coincidence signal trgs000 0 trgs120 0 1 cr12 capture trigger specification pbctl signal input edge detection signal (signal specified with bits 6 and 7 of intm1) cfg signal input frequency dividing signal (edv-edvc coincidence signal) after reset 00h r/w r/w r/w r/w r/w fcpt4 0 1 cpt4 capture flag cpt4 is not captured cpt4 is captured r fcpt5 0 1 r cpt5 capture flag cpt5 is not captured cpt5 is captured trgs011 0 cpt1 capture trigger specification falling edge of timer 0 clear pulse trgs010 0
chapter 5 examples of stationary type vcr servo control 74 5.6.3 drum phase control for recording for drum phase control for recording, the rotational phase of the drum motor is synchronized with vertical synchronizing signal externally input. the point of phase lock is where the rising and falling edges of the head switching signal (v-hsw) are 6.5h before the vertical synchronizing signal, which complies with vhs standard. however, the time required for v sync separation, as mentioned in the section about the control for playback, must be taken in consideration. figure 5-27 shows the use of the timer in drum phase control for recording. figure 5-28 shows the drum phase control timing chart for recording. when recording, the phase error amount is calculated from the free running counter (frc) value (cpt1) captured at the falling edge of internal head switching signal (hsw-n) and the frc value (cpt0) captured at the falling edge of the vertical synchronizing signal input from the csyncin pin. the phase error amount detection method is described below. the method to capture the frc value in cpt1 only at the falling edge of hsw-n is the same as for playback. on the other hand, the cpt0 capture operation is performed when the vertical synchronizing signal is input to the csyncin input pin, and tm1 is cleared simultaneously. in fact, the phase error detection is performed in frame cycle, so that tm1 clearance by inputting csync is masked for the 90% time period of a frame cycle. compare register 13 (cr13) is used for the setting of the mask time. figure 5-29 shows the cpt0 and cpt1 capture trigger source setting method for recording. the phase error amount is detected in intclr1 interrupt processing. the phase error amount e dp is calculated as follows: e dp = ( (cpt0 value) C (cpt1 value) ) C n dpl n dpl , here, is the difference between cpt0 and cpt1 when the drum phase control is locked, that is, the target value of the phase control. the difference between cpt0 and cpt1 when the phase is locked, is the sum of head switching signal delay amount, frame half cycle, vhs standard 6.5h delay, and the delay amount for v sync separation.
chapter 5 examples of stationary type vcr servo control 75 figure 5-27. use of timer for drum phase control (for recording) frc cpt0 tm1 cr10 cr13 coincidence coincidence clear capture tmc0 en clr1 at msk intcr10 intcr13 intclr1 selector digital noise elimination circuit csyncin (composite synchronizing signal) phase reference signal input analog circuit selector timer 1 operates as a buffer oscillator to correctly capture the contents of frc even when phase reference signal input is missing. ...
chapter 5 examples of stationary type vcr servo control 76 figure 5-28. drum phase control timing (for recording) remark phase lock delay amount: value determined by vcr standard v-hsw tm1 count value frc count value hsw - n cpt1 cpt0 v sync cpt1 cpt0 coincides with cr10 v sync missing (pto00) (mask) (mask) (mask) phase lock delay amount v-hsw pulse delay amount cr10 hsw-n falling edge v sync rising edge (drum phase error amount detection) intclr1 (drum phase error amount detection)
chapter 5 examples of stationary type vcr servo control 77 figure 5-29. capture mode register (cptm) format 7 fcpt5 6 fcpt4 5 trgs011 4 trgs010 3 0 2 trgs120 1 trgs001 0 trgs000 cptm address ff53h trgs001 1 cpt0 capture trigger specification tm1 clear signal trgs000 0 trgs120 0 1 cr12 capture trigger specification pbctl signal input edge detection signal (signal specified with bits 6 and 7 of intm1) cfg signal input frequency dividing signal (edv-edvc coincidence signal) after reset 00h r/w r/w r/w r/w r/w fcpt4 0 1 cpt4 capture flag cpt4 is not captured cpt4 is captured r fcpt5 0 1 r cpt5 capture flag cpt5 is not captured cpt5 is captured trgs011 0 cpt1 capture trigger specification falling edge of timer 0 clear pulse trgs010 0
chapter 5 examples of stationary type vcr servo control 78 the m pd784915 uses vertical synchronizing signal (v sync ) as phase reference signal. therefore, digital noise elimination circuit is used to separate only vertical synchronizing signals from composite synchronizing signals. in this application example, the amount of time required for v sync of digital noise elimination circuit is 13.5 [ m s]. the count value of drum phase error for 6.5h sampling clock is 826. the count value for 13.5 [ m s] required for v sync separation is shown in the following expression: 13.5 [ m s] = 27 0.5 [ m s] therefore, the target value is represented with the expressions as follows: n dpl =+++ = (cr00 2) + (cr10) + 826 + 27 = (cr00 2) + (cr10) + 355h this expression is the same as that for phase error amount for playback. delay amount for half a frame cycle delay amount for 6.5h delay for v sync separation digital value equivalent to video head switching pulse delay amount
chapter 5 examples of stationary type vcr servo control 79 5.7 capstan speed control delay of capstan speed error amount is carried out, as well as drum speed control, by capturing the free running counter (frc) value at the capstan fg signal input edge. the capstan fg signal (cfg) is input to the dfgin input pin. intcpt3 interrupt request occurs simultaneously with the capture of the frc value to cpt3 at the cfg edge input. the difference from drum speed control is that cfg frequency f cf varies according to the tape running mode. in this set, the cfg frequency for normal playing back is as follows: ? sp mode : 1080.00 [hz] ? lp mode : 540.00 [hz] ? ep mode : 360.00 [hz] in order to equalize error detection gain in the servo system according to each running mode, cfg is divided with the 8-bit event divider control register (edvc) incorporated in the cfgin pin input of the super timer unit. since this counter operates as the event divider of the dfgin pin input pulse, the detection cycle in the sp mode becomes the same as that in the ep mode if cfg is divided by one third. figure 5-30 shows the capstan speed detection method. figure 5-31 shows the capstan speed control timing chart. the capstan speed error ecv is calculated in the intcpt3 interrupt request processing routine. the expression is as follows: d n cv n = d n cv n Cn cv n e cv n =n cvl n C d n cv n n cvl , here, is the target value of capstan speed control. the cfg frequency f cf in the ep mode is as follows: f cf = 360.00 [hz] f cfep = 360.00 [hz] therefore, it becomes the cfg frequency in the sp mode, and the cfg cycle f cf is calculated with the following expressions: f cfsp /3 = 360.00 f cf /3 = 239.7602093 [hz] t cf = 2.7778 [ms]
chapter 5 examples of stationary type vcr servo control 80 the time interval counted by the free running counter (frc) becomes the target value n cfl of capstan fg signal (cfg). since the frc count pulse cycle (t frc ) is 125 [ns], n cfl is as follows: n cfl = 2.778 [ms] = 22222 = 56ceh 125 [ns] the meaning of the signs for capstan speed error amount e cv is shown below: (1) when cfg cycle is longer than the target value...C (when the rotation of capstan motor is slow) (2) when cfg cycle is shorter than the target value...+ (when the rotation of capstan motor is fast)
chapter 5 examples of stationary type vcr servo control 81 figure 5-30. capstan speed detection method frc cpt3 intcpt3 f clk /4 capture edv 8-bit counter edvc capstan fg signal cfgin clear (capstan speed control interrupt) analog circuit
chapter 5 examples of stationary type vcr servo control 82 figure 5-31. capstan speed control timing 360.00 hz (2.78 ms) capstan fg signal ep mode (cfgin) sp mode (cfgin) number of frc count intcpt3 n n? cv d n n cv intcpt3 n n cv 1080.00 hz (0.93 ms) 1/3 frequency divide with edvc
chapter 5 examples of stationary type vcr servo control 83 5.8 capstan phase control the phase detection of the capstan motor is performed by compare register 12 (cr12), and capstan phase control is performed by the intcr12 interrupt routine. the control method differs for playback and recording. the control method for each case is explained below. 5.8.1 capstan phase control for playback the purpose of capstan phase control for playback is to keep the phase relation constant between the playback control signal (pbctl) and the head switching signal (v-hsw) acquired when playing back. the relation between timer 1 (tm1), which is the reference timer in drum phase control, and v-hsw is already kept constant (refer to 5.6.2 drum phase control for playback ). therefore, the phase relation between v-hsw and pbctl is indirectly kept constant by keeping the phase relation between tm1 and pbctl constant (refer to figure 5-32). figure 5-32. model of capstan phase control in capstan phase control for playback, the selector is selected so that pbctl signal is set to cr12 of timer 1. figure 5-33 shows the capstan phase error detection method for playback. figure 5-34 shows how to set the capture trigger source of cr12 for playback. in capstan phase control, the lock point is the point tilted for the amount of time from video head to control head (x value correction amount). the x value correction amount differs according to the vcr sets and the tape running mode. figures 5-35 to 5-37 show the phase control timing charts. the phase error amount e cp is calculated from the following expression. e cp = (value captured by pbctl signal) C n cpl = (cr12 value) C n cpl n cpl : capstan phase control target value the capstan phase control target value (n cpl ), here, is the tm1 value captured in cr12 when the phase is locked. taking it into account that the phase between the video head position (v-hsw timing) and the reference timer is 6.5h, n cpl is calculated as follows: v-hsw timer 1 pbctl phase is indirectly kept constant keep phase constant (drum phase control) keep phase constant (capstan phase control)
chapter 5 examples of stationary type vcr servo control 84 n cpl = (x value correction amount) C 6.5h + tracking adjustment amount t tm1 = (x value correction amount) C 6.5h + tracking adjustment amount 8/f clk = (x value correction amount) C 6.5h 63.55 [ m sec] + tracking adjustment amount 8/8[mhz] if the phase control range is set equally for both advance/delay directions centered in the phase lock, the amount of time before the phase lock is shortened. in other words, in the condition of figure 5-36, the distance to the lock point is shorter if the condition is considered as advanced rather than delayed so that the amount of time before the phase lock is shorter. concretely, the n f /2 range (n f : the full count value of timer 1: cr10 set value) is regarded as it is, centered in the locking point, and the value corrected by adding n f to (or subtracting n f from) the value captured is used for the other range. in addition, digital filter arithmetic is performed to the capstan phase error amount acquired here so that the result is used for the phase control.
chapter 5 examples of stationary type vcr servo control 85 figure 5-33. capstan phase error detection method (for playback) tm1 cr10 cr12 intcr12 f clk /8 (1 mhz) clear coincidence (capstan phase control interrupt) capture pbctl signal
chapter 5 examples of stationary type vcr servo control 86 figure 5-34. capture mode register (cptm) format 7 fcpt5 6 fcpt4 5 trgs011 4 trgs010 3 0 2 trgs120 1 trgs001 0 trgs000 cptm address ff53h trgs001 0 0 1 1 cpt0 capture trigger specification tm1-cr10 coincidence signal csync signal input edge detection signal tm1 clear signal or of tm1-cr10 coincidence signal and csync signal input edge detection signal trgs000 0 1 0 1 trgs120 0 cr12 capture trigger specification pbctl signal input edge detection signal after reset 00h r/w r/w r/w r/w r/w fcpt4 0 1 cpt4 capture flag cpt4 is not captured cpt4 is captured r fcpt5 0 1 r cpt5 capture flag cpt5 is not captured cpt5 is captured trgs011 0 0 1 1 cpt1 capture trigger specification falling edge of timer 0 clear pulse rising edge of timer 0 clear pulse setting prohibited both falling/rising edge of timer 0 clear pulse trgs010 0 1 0 1
chapter 5 examples of stationary type vcr servo control 87 figure 5-35. capstan phase control timing (playback mode, phase locked) pbctl v-hsw tm1 count value 6.5 h target value x value timer 1 clear if this section is assumed to be placed in the section indicated with the broken line below, the control ranges of phase advanced and phase delayed are the same. timer 1 clear timer 1 clear capture cr12 capture cr12 phase advanced area phase delayed area (n f /2) phase advanced area virtual phase advanced area (n f /2) capture cr12
chapter 5 examples of stationary type vcr servo control 88 figure 5-36. capstan phase control timing (playback mode, phase delayed) pbctl v-hsw tm1 count value 6.5 h target value x value timer 1 clear timer 1 clear timer 1 clear capture cr12 capture cr12 phase advanced area phase delayed area (n f /2) phase advanced area virtual phase advanced area (n f /2) capture cr12 phase lock point error amount phase lock point phase lock point
chapter 5 examples of stationary type vcr servo control 89 figure 5-37. capstan phase control timing (playback mode, phase advanced) remark error amount 1 > error amount 2, therefore, error amount 2 is used as the error amount. pbctl v-hsw ttm1 count value 6.5 h target value x value timer 1 clear timer 1 clear timer 1 clear capture cr12 capture cr12 phase advanced area phase advanced area phase lock point phase lock point phase lock point capture cr12 error amount 1 error amount 2 phase delayed area (n f /2) virtual phase advanced area (n f /2)
chapter 5 examples of stationary type vcr servo control 90 5.8.2 capstan phase control for recording the capstan control for recording is performed by dividing capstan fg signal (cfg). as long as the capstan motor is steadily rotating while recording, it is not necessary to consider absolute phase. figure 5-38 shows the capstan phase error detection method for recording. figure 5-39 shows the method of setting the capture trigger source of compare register 12 (cr12) for recording. the capstan phase control for recording, as well as for playback, uses the cr12 and intcr12 interrupts. although a value is captured in cr12 every time cfg is input, cfg has to be divided because only one captured value is needed for one frame. in actuality, the input is not divided but interrupt is divided using the macro service counter mode, and the cr12 value when a vectored interrupt is generated is used. the number of frequency division is the same as the fg wave number (in ep mode). cfg input is triple divided by event divider control register (edvc) in sp mode. therefore, the required value is acquired by dividing the interrupt for the capstan fg wave number in ep mode. figure 5-40 shows the phase control timing chart. capstan phase error amount is calculated in the same way as for playback. e cp = (captured value by cfg frequency dividing signal) C n cpl = (cr12 value) C n cpl remark n cpl : capstan phase control target value however, since there is not an absolute phase for recording, target value n cpl can be any value. capstan phase control range is determined in the same way as for playback. further, digital filter arithmetic is performed to the capstan phase error amount acquired from the above calculation, and the result is used for phase control.
chapter 5 examples of stationary type vcr servo control 91 figure 5-38. capstan phase error detection method (for recording) tm1 cr10 cr12 intcr12 f clk /8 (1 mhz) clear coincidence (capstan phase control interrupt) capture edvc clear evd 8-bit counter coincidence number of interrupt occurrence is divided by counter mode macro service cfgin (capstan fg signal) csyncin (v sync ) analog circuit
chapter 5 examples of stationary type vcr servo control 92 figure 5-39. capture mode register (cptm) format 7 fcpt5 6 fcpt4 5 trgs011 4 trgs010 3 0 2 trgs120 1 trgs001 0 trgs000 cptm address ff53h trgs001 0 0 1 1 cpt0 capture trigger specification tm1-cr10 coincidence signal csync signal input edge detection signal tm1 clear signal or of tm1-cr10 coincidence signal and csync signal input edge detection signal trgs000 0 1 0 1 trgs120 1 cr12 capture trigger specification cfg signal input dividing signal (edv-edvc coincidence signal) after reset 00h r/w r/w r/w r/w r/w fcpt4 0 1 cpt4 capture flag cpt4 is not captured cpt4 is captured r fcpt5 0 1 r cpt5 capture flag cpt5 is not captured cpt5 is captured trgs011 0 0 1 1 cpt1 capture trigger specification falling edge of timer 0 clear pulse rising edge of timer 0 clear pulse setting prohibited both falling/rising edges of timer 0 clear pulse trgs010 0 1 0 1
chapter 5 examples of stationary type vcr servo control 93 figure 5-40. capstan phase control timing (for recording) note the arrows have the following meanings. (solid line) : vectored interrupt (broken line) : macro service 011109 8 011109 8 21 note 1234 361 tm1 count value cfg sp mode edvc (1/3) cfg ep mode macro service (1/12) (capture) (capture) (clear) (clear) macro service counter value intcr12 interrupt request v sync (csyncin) 0
chapter 5 examples of stationary type vcr servo control 94 5.9 recording control signal generation recording control signal (recctl) is a signal synchronized with head switching signal (v-hsw) and recorded on the control track for recording. the recctl cycle is equal to t f and the duty is normally 60% (27.5% for index signal, may become other duty). recctl rising timing t recr is the point tilted for the amount of time from video head to control head (x value correction amount). the x value correction amount differs according to the vcr sets and the tape running mode. the recctl write timing is calculated as follows: (1) [recctl rising timing (t recr )] recctl rising timing (t recr ) is the point tilted for the amount of time from the video head position to control head (x value correction amount). the video head position has the phase tilted for 6.5h from the reference timer. therefore, t recr is represented as follows: t recr = (x value correction amount) C 6.5h C t d remark t d : digital noise elimination circuit (v sync separation) delay time (80/f clk or 128/f clk ) 0 if not using digital noise elimination circuit (2) recctl falling timing (t recf ) recctl falling timing (t recf ) is the point tilted for 60% of the frame frequency from rising timing. t recf =t recr + (60% of frame frequency) = [(x value correction amount) C 6.5h C t d] + (t f 0.6) remark t d : digital noise elimination circuit (v sync separation) delay time (80/f clk or 128/f clk ) 0 if not using digital noise elimination circuit t f : tv broadcast frame frequency (33.36 msec: ntsc) first, connect directly the m pd784915 and control head as shown in figure 5-41 and set registers so that recctl write circuit is used.
chapter 5 examples of stationary type vcr servo control 95 figure 5-41. connection of m pd784915 and control head the recording control signal (recctl) driver of the m pd784915 has the rec mode, which is used for recctl signal write. figure 5-42 shows recctl driver configuration. figure 5-42. recctl driver block diagram the rec mode sequence of recctl driver operates recctl+ pin and recctlC pin as shown in table 5-2. therefore, recctl signal write is realized taking only the interrupt occurrence timing, which is a trigger signal, into consideration. table 5-2. recctl driver rec mode sequence sequence recctl+ recctlC 0 low level high level 1 high level low level figure 5-43 shows an example of recctl signal writing operation timings. pd784915 recctl+ recctl control head m drv mod sel 13 sel 11 sel 30 tom1 en rec sel ctld ampm0 write strobe signal recctl control intcr13 intcr11 intcr30 initialization recctl output ctldly ani11 recctl+ recctle ctl head internal bus selector
chapter 5 examples of stationary type vcr servo control 96 figure 5-43. example of recctl signal writing operation timings note r/w to tom1 register is not executed until approximately 800 m s from the setting of enrec = 1 (start of rec mode), or enrec = 0 (end of rec mode). caution keep ctl amplifier in operation (enctl (ampc.1) = 1) even while rec driver is operating. tm1 cr11 rewrite cr11 rewrite cr11 rewrite cr11 rewrite cr11 rewrite cr11 rewrite tom1 write intcr11 enrec bit 0 1 0 1 0 1 0 recctl+ recctlC ctl signal written sequence (sequence initialized) when writing ends note when writing starts note
chapter 5 examples of stationary type vcr servo control 97 the case using only compare register 11 (cr11) as a register for setting timing is explained here. set timer 1 output mode register (tom1) to use cr11 as shown in figure 5-44. then, write the value corresponding to rising timing to cr11. when timer register 1 (tm1) coincides with cr11, the rising edge is recorded and intcr11 interrupt occurs. rewrite the value to the value corresponding to the falling timing. and the falling edge is recorded at the next coincidence of tm1 and cr11, then write again the value corresponding to the rising timing to cr11. by repeating this procedure, recctl can be recorded. figure 5-45 shows the timing chart.
chapter 5 examples of stationary type vcr servo control 98 figure 5-44. timer 1 output mode register (tom1) format 7 drvmod 6 sel13 5 sel11 4 sel30 3 mod111 2 mod110 1 mod101 0 mod100 tom1 address ff5ah mod101 0 0 1 1 after reset 80h r/w r/w sel30 0 1 recctl write circuit operation trigger setting tm3-cr30 coincidence signal is not selected as a trigger tm3-cr30 coincidence signal is selected as a trigger sel11 1 recctl write circuit operation trigger setting tm1-cr11 coincidence signal is selected as a trigger drvmod 0 recctl write circuit operation mode setting rec mode mod100 0 0 1 1 pto10 output mode specification general purpose output mode setting prohibited delay pulse output mode 1 delay pulse output mode 2 mod111 0 0 1 1 mod110 0 0 0 1 pto11 output mode specification general purpose output mode setting prohibited delay pulse output mode 1 delay pulse output mode 2 sel13 0 1 recctl write circuit operation trigger setting tm1-cr13 coincidence signal is not selected as a trigger tm1-cr13 coincidence signal is selected as a trigger r/w w w w w w
chapter 5 examples of stationary type vcr servo control 99 figure 5-45. recctl write timing using cr11 v-hsw tm1 count value 6.5 h v sync intcr11 timer 1 clear intcr11 recctl cr11 value intcr11 timer 1 clear coincides with cr11 coincides with cr11 intcr11 timer 1 clear intcr11 coincides with cr11 coincides with cr11 intcr11 x value t recf t recr t recf t recr t recf t recr t recf coincides with cr11
chapter 5 examples of stationary type vcr servo control 100 5.10 quasi vertical synchronizing signal (quasi-v sync ) generation the method to generate quasi vertical synchronizing signal (quasi-v sync ) for special playback is explained. there are several types of wave forms for quasi-v sync depending on the signal processing circuit to be used. the method to output the wave form shown in figure 5-48 is explained here. the wave form shown in figure 5-46 requires not only h and l but also m (middle level) outputs. real-time output port rtp80 incorporated with the m pd784915 is used, for this port can output h, l, and hi- z. for the middle level, the level of hi-z output is set with external pull-up and pull-down resistors (refer to figure 5-47 ). rtp80 can superimpose h sync pulse during hi-z period, so that h sync does not need to occur for every h sync . the procedure is shown below: <1> set p80 in real time output port mode. and select tm0-cr02 coincidence signal as the rtp8 output trigger. <2> set h sync output timing (rising (figure 5-48 <1>)) to cr02. and set 00010001b (superimpose high-level h sync to hi-z) to p8l. <3> the wave form with hi-z that have high-level hsync superimposed is output from p80 pin by the coincidence of tm0 and cr02. intcr02 occurs simultaneously. <4> set v sync output timing (rising (figure 5-48 <2>)) to cr02 by the intcr02 interrupt routine. set 00000001b (high-level output) to p8l. <5> high level is output from p80 pin by the coincidence of tm0 and cr02. intcr02 occurs simultaneously. <6> set v sync output timing (falling (figure 5-48 <3>)) by the intcr02 interrupt routine. set 00000000b (low- level output) to p8l. <7> low level is output from p80 pin by the coincidence of tm0 and cr02. intcr02 occurs simultaneously. <8> set h sync output timing (rising (figure 5-48 <1>)) to cr02 by the intcr02 interrupt routine. set 00010001b (superimpose high-level h sync to hi-z) to p8l. <9> go back to <3> (repeat this procedure).
chapter 5 examples of stationary type vcr servo control 101 figure 5-46. quasi-v sync waveform figure 5-47. middle level generation remark when p80 is hi-z, the output level is r2 v dd r1 + r2 h m l pd784915 v dd r 1 r 2 quasi-v sync p80 m
chapter 5 examples of stationary type vcr servo control 102 figure 5-48. quasi-v sync generation timing intcr02 n 1 rewrite intcr02 rewrite intcr02 n 2 rewrite intcr02 n 3 h m l cr02 p8l n 1 00010001b n 2 00000001b n 3 00000000b n 1 00010001b 12 3 h sync pulse is superimposed by hardware tm0 count value
chapter 5 examples of stationary type vcr servo control 103 5.11 treatment of servo error amount 5.11.1 drum control system processing drum control system performs the calculation and filtering processing of drum speed error and phase error and output of drum motor control signal (pwm0). figure 5-49 shows the drum control system configuration. figure 5-49. drum control system configuration as shown in figure 5-49, the drum speed control system performs only phase error calculation and phase control system filtering. the drum phase control system reads out the filtered phase error, adds it with speed system error, and performs pwm output. first, the total error amount of drum motor is calculated from the speed error amount and phase error amount. the speed error amount e dv acquired from drum speed control interrupt and the phase error amount e dp (digital filter arithmetic result) acquired from drum phase control interrupt are multiplied with gains, respectively (the gains are defined as k dv and k dp , respectively). the sum of these results is defined as the drum error amount e d . e d = k dv ? e dv + k dp ? e dp the sum of the drum total error amount and the bias value is pwm output. the bias value is pwm output to control the motor in open loop and output the voltage required to rotate the motor in the approximate target rotation. however, the bias is not necessarily a strict value because the actual control is carried out by feedback control and errors are automatically corrected to a certain extent. in addition, the servo system characteristics can be improved, such as reduction of motor rising time and improvement of locking stability, by changing the gain according to the speed error amount and phase error amount and canceling phase control. + (drum speed gain) speed error detection phase error detection digital filter k v k p bias value addition pwm conversion drum speed control interrupt processed with intcpt2 drum phase control interrupt processed with intcr10 (drum phase gain)
chapter 5 examples of stationary type vcr servo control 104 the speed error gain k dv and phase error gain k dp vary according to the motor characteristics. set these values according to the characteristics of the motor to be used (in fact, find the value that has the best characteristics in cut and try). (1) error amount maximum control processing (limit limiter) error amount maximum control processing is the same as trapezoidal pattern for servo ic error value detection, and it controls the maximum of internal error value (error amount) to input to digital filter. figure 5-50. trapezoidal pattern for error value detection (drum control system) in this application example, the control range is specified also from loop gain so as to prevent data overflow in the arithmetic processing of digital filter. a maximum limit is set for speed error and phase error, respectively, and each control range is set as follows: ? drum speed control range 735h (1 count = 125 nsec) 230.625 m sec ? drum phase control range 2220h (1 count = 500 nsec) 4368 m sec C limiter lock point + limiter
chapter 5 examples of stationary type vcr servo control 105 (2) special processing in drum control system (a) special processing for error amount calculation by checking the drum speed error amount detected in the drum speed error amount calculation routine, if the drum speed deviates 5% or more from the target value, 0 is set to the drum phase error amount. the purpose of this processing is to prohibit addition of the drum phase error amount while the drum speed control system is not in operation and to reduce the lock time of the motor by operating the drum motor only with the speed control system. (b) special processing in drum phase system digital filter this special processing limits the maximum of y n-1 data value in the arithmetic processing of drum phase system digital filter. y n-1 is the data to reflect the past output data of the filter. if the drum phase becomes out of phase for a long period of time (when applying load by lightly holding the drum manually, etc.), y n-1 data keeps increasing. the increased y n-1 data will start decreasing gradually when the applied load is removed. however, the lock time is affected because it takes an extremely long time before y n-1 is decreased. in order to avoid this, the lock time should be reduced by setting the maximum limit for y n-1 data. the limit value for y n-1 is set as follows: y n-1 maximum : 13fh the y n-1 limit value setting method is adopted according to experimental values. (3) loop gain multiplication k v and k p shown in figure 5-50 are loop gains in speed control system and phase control system, respectively. when handling the error amount data (calculated from frc) which is digital filtering processed as pwm data, the variable range of pwm data is small (the dynamic range is narrow) because the range available for the data is narrow. loop gain also has the functions to widen the dynamic range by amplifying the filtered data and to adjust the addition rate of speed system and phase system. the loop gains of the speed system and phase system are as follows: speed system loop gain : k v = 17.76 times phase system loop gain : k p = 46.0 times speed/phase addition rate : k v : k p = 4.74 :1
chapter 5 examples of stationary type vcr servo control 106 (4) bias value addition bias value addition is carried out to keep the motor control voltage at the lock point during servo lock (speed/ phase error amount 0). the bias value setting method is adopted according to experimental values. pwm output data in the condition that drum is controlled only with speed control and stabilized at the drum speed target value is adopted as the bias value. the bias value in drum control system is as follows: bias value in ntsc : 66f0 [hex] bias value is added to the sum of speed correction amount and phase correction amount. however, the arithmetic result may overflow, so that overflow check is carried out. the arithmetic result is fixed to the maximum if overflow occurs and to the minimum if borrow occurs. (5) pwm output for drum motor control the pwm of the data which is the addition of speed/phase correction amount and bias value is output. the data is processed as 16-bit data. however, since the operation range of pwm output unit is 0ff00h to 0100h, when operating outside this range, the maximum or the minimum is written. the pwm for drum motor control is output in the drum speed control interrupt routine.
chapter 5 examples of stationary type vcr servo control 107 5.11.2. capstan control system processing capstan control system performs the calculation and filtering processing of capstan speed error and phase error and the output of capstan motor control signal (pwm1). figure 5-51 shows the capstan control system configuration. figure 5-51. capstan control system configuration as shown in figure 5-51, capstan phase control system performs the calculation of phase error amount and filtering of phase system. capstan speed control system reads out the filtered phase error, adds it with speed system error, and performs pwm output. first, the capstan motor total error amount is calculated from the speed error amount and phase error amount. speed error amount e cv acquired from the capstan speed control interrupt and phase error amount e cp (digital filter arithmetic result) acquired from the capstan phase control interrupt are multiplied with gains, respectively (the gains are defined as k cv and k cp , respectively). the sum of these results are defined as capstan error amount e c . e c = k cv ? e cv + k cp ? e cp the sum of the capstan total error amount and bias value is pwm output. the bias value is pwm output to control the motor in open loop and output the voltage required to rotate the motor in the approximate target rotation. however, the bias is not necessarily a strict value because the actual control is carried out by feedback control and errors are automatically corrected to a certain extent. in addition, the servo system characteristics can be improved, such as reduction of motor rising time and improvement of locking stability, by changing the gain according to the speed error amount and phase error amount and canceling phase control. the speed error gain k cv and phase error gain k cp vary according to the motor characteristics. set these values according to the characteristics of the motor to be used (in fact, find the value that has the best characteristics in cut and try). + (capstan mix gain) speed error amount detection phase error amount detection k v /k p bias value addition pwm conversion capstan speed control interrupt processed with intcpt3 capstan phase control interrupt processed with intcr12 digital filter k m digital filter
chapter 5 examples of stationary type vcr servo control 108 (1) error amount maximum control processing (limit limiter) error amount maximum control processing is the same as trapezoidal pattern for servo ic error value detection, and it controls the maximum of internal error value (error amount) to input to digital filter. figure 5-52. trapezoidal pattern for error value detection (capstan control system) this also prevents data overflow in digital filter arithmetic processing. the limit range is specified by limiting the error maximum. the maximum limit is set for speed error and phase error, respectively, and each control range is set as follows: ? capstan speed control range 1e79h (1 count = 125 nsec) 975.125 m sec ? capstan phase control range 15a0h (1 count = 1 m sec) 5536 m sec (2) special processing in capstan control system (a) special processing for error amount calculation < 1> relation with drum speed error amount in drum speed error calculation, if the drum speed deviates 10% or more from the target value, 0 is set to the capstan phase error amount. the purpose of this processing is to prohibit addition of the capstan phase error amount while the drum speed control system is not in operation and to reduce the lock time of the motor by operating the capstan motor only with the speed control system. <2> relation with capstan speed error amount by checking the capstan speed error amount detected in the capstan speed error amount calculation routine, if the capstan speed deviates 5% or more from the target value, 0 is set to the capstan phase error amount. the purpose of this processing is to prohibit addition of the capstan phase error amount while the capstan speed control system is not in operation and to reduce the lock time of the motor by operating the capstan motor only with the speed control system. C limiter lock point + limiter
chapter 5 examples of stationary type vcr servo control 109 <3> relation with playback control (pbctl) signal missing when playback control (pbctl) signal missing occurs, 0 is set to the capstan phase error amount. pbctl signal missing is detected by pbctl signal missing counter. normally, while pbctl signal is input, the pbctl signal missing counter is incremented in the capstan speed control interrupt (intcpt3), and the pbctl signal missing counter is reset to 0 in the capstan phase control interrupt (intcr12). however, the pbctl signal missing counter is not reset if the pbctl signal misses. therefore, if pbctl signal missing counter is 28h (40d) by checking during intcpt3 interrupt processing, it is judged that pbctl signal missing has occurred and a flag is set. this processing prevents pbctl signal missing due to tape damage and misdetection of the phase error amount for playback non-recorded tapes, etc. and keeps the tape speed at the target value. (b) capstan extreme high-speed rotation processing when the capstan rotates in an extremely high speed (when motor control shorts to 5 v, etc.), cfg interrupt occurs extremely frequently, interrupt processing gets behind, and runs out of time to return to main routine. once lapsed into this condition, even the short circuit is repaired, the speed error amount detection continues to misdetect, keeps high speed rotation, and is unable to return to main routine, so that pushing keys has no effect. to avoid this, when the capstan rotates faster than at a certain speed, the interrupt processing thereafter is not performed and interrupt processing ends by lowering pwm data (to shorten the processing time). in this program, the processing becomes effective when the cfg cycle becomes 600 m s or higher.
chapter 5 examples of stationary type vcr servo control 110 (3) loop gain multiplication for each running mode k v and k p shown in figure 5-51 are, as well as drum control system, loop gains for speed control system and phase control system, respectively. k m is the gain correction coefficient corresponding to each operation mode and changes according to vcr playback modes. as discussed in drum control system, k v and k p are for adjusting the addition rate of speed system and phase system. in the drum control system, there is little speed difference among the operation modes. accordingly, the entire loop gain is not varied. however, in capstan control system, there is a large difference between the sp and ep modes even in standard playback, and speed difference exists in special playback such as cue/review. therefore, the gain also varies according to each operation mode. k m is set as the correction coefficient to correct the variation. k v and k p are used only as adjustment of addition rate, so that they are represented as k v /k p . table 5-3 shows the capstan loop gain in each operation mode. table 5-3. capstan loop gain in each operation mode operation mode k v /k p k m standard playback (pb) sp 4.2 6.0 lp 1.1 5.25 ep 1.1 4.25 fast forward search 1 (cue1) sp 4.2 6.0 lp 3.3 6.0 ep 3.3 6.0 fast forward search 2 (cue2) sp 4.2 6.0 lp 3.3 6.0 ep 3.3 6.0 rewind search 1 (rev1) sp 4.2 6.0 lp 3.3 6.0 ep 3.3 6.0 rewind search 2 (rev2) sp 4.2 6.0 lp 3.3 6.0 ep 3.3 6.0 still, frame (still, frame) sp 4.2 6.0 lp 3.3 5.25 ep 3.3 4.25
chapter 5 examples of stationary type vcr servo control 111 (4) bias value addition bias value addition is carried out to keep the motor control voltage at the lock point during servo lock (speed/ phase error amount 0). the bias value setting method is adopted according to the experimental values. pwm output data in the condition that capstan is controlled by only speed control and stabilized at the capstan speed target value is adopted as the bias value. since capstan speed differs according to each operation mode, different bias value is required in each operation mode. table 5-4 shows the capstan bias value in each operation mode. table 5-4. capstan bias value in each operation mode operation mode bias value standard playback (pb) sp 85e0h lp 8695h ep 86dfh fast forward search 1 (cue1) sp 8678h lp 8695h ep 86dfh fast forward search 2 (cue2) sp 8678h lp 8695h ep 86dfh rewind search 1 (rev1) sp 8678h lp 8695h ep 86dfh rewind search 2 (rev2) sp 8678h lp 8695h ep 86dfh still, frame (still, frame) sp 8678h lp 8695h ep 86dfh bias value is added to the sum of speed correction amount and phase correction amount. however, the arithmetic result may overflow, so that overflow check is carried out. the arithmetic result is fixed to the maximum if overflow occurs and to the minimum if borrow occurs. (5) pwm output for capstan motor control pwm output of the data which is the addition of speed/phase correction amount and bias value is performed. the data is processed as 16-bit data. however, since the operation range of the pwm output unit is 0ff00h to 0100h, when operating outside this range, the maximum or the minimum is written. the pwm for capstan motor control is output in the capstan speed control interrupt routine.
chapter 5 examples of stationary type vcr servo control 112 5.12 compensation filter the digital servo system only with proportional control element requires a digital filter in the control system for steady-state deviation elimination. the configuration method of the lag-lead type digital filter, which is often used in vcr servo systems, is discussed here. 5.12.1 filter types filters are divided into analog filter and digital filter by the difference of operational principle. analog filters are configured with circuits such as capacitors (c) and resistors (r) and realize filter characteristics electronically. digital filters are configured also with microcontrollers and signal processors, and realize the characteristics equal to analog filters by performing various arithmetic processing on the input signals which are sampled and quantized. digital filters are divided into fir type and iir type by the difference of filter configurations. (1) fir type (finite impulse response) filter the finite impulse response filter is also called acyclic filter. fir has finite response and no feedback loop due to its filter configuration, that is, the filter output value is determined only with the input value of the present and the past. (2) iir type (infinite impulse response) filter the infinite impulse response filter is also called cyclic filter. since fir has feedback loop due to its filter configuration, impulse response continues infinitely. therefore, the filter output value is determined not only with the input of the present and the past but also with the output value of the past. this type of filter realizes steep cut-off characteristics in much lower degree than that of fir type filter. the vcr servo system mainly uses the iir type filter.
chapter 5 examples of stationary type vcr servo control 113 5.12.2 biprimary conversion method (1) sampling theorem when using a digital filter, sampling processing is required in the course of converting analog input signals to digital values. that is, analog signals are converted to discrete numeric sequences in certain constant time intervals t s . however, if the sampling cycle t s is made too long, restoration of the original analog signal is impossible. the limit of the cycle that the original analog signal can be restored is described with the well-known sampling theorem below: 2f max. f s = 1 t s f max . ........... the maximum frequency included in the original analog signal f s ............... sampling frequency that is, unless the frequency twice or more of the maximum frequency included in the original analog signal is selected for the sampling frequency f s , it is impossible to restore the original analog signal from the sampled digital signal. figure 5-53 shows sampling theorem observed on frequency spectrum. figure 5-53 (1) shows the case the maximum frequency component f max . satisfies 2f max . < f s that is, the original signal is band limited. in such case, the original signal can be completely restored if the sideband component is eliminated, extracting only the basic spectral component using ideal low-pass filter whose cut-off frequency f c is f c = f s /2. however, in the case that f max . does not satisfy sampling theorem, that is, 2f max . > f s sections where the original signal spectrum and fold spectrum are overlapped, that is, fold error is generated as shown in figure 5-53 (2). in this case, the restoration of the original signal is impossible even if ideal low-pass filter is used. next, sampling theorem is examined on s planar. the time function of the original signal is defined as f (t), and the result of laplace transform of the function is defined as f (s). further, f (s) is sampled with sampling cycle t s . this is defined as f* (s). now, assuming the maximum frequency f max . of the original signal satisfies sampling theorem, the pole of f (s), as shown in figure 5-54 (1), is in basic band. the basic band is folded as shown in figure 5-54 (2) by sampling processing, as a result, sideband whose width is 2 p /t s is generated, and the pole of f (s) is also folded.
chapter 5 examples of stationary type vcr servo control 114 since the basic band and sideband are exactly the same, the original signal can be completely restored if only the basic band component is extracted using ideal low-pass filter. on the other hand, the case that the original signal does not satisfy sampling theorem is shown in figure 5- 55. in this case, the pole of f (s) is located out of the basic band. therefore, if pole is folded by sampling processing, pole is generated in the basic band, where pole is not originally located. once this happens, the restoration of the original signal is impossible even if only the basic band component is extracted using ideal low-pass filter, since the basic band component is different from the original one. figure 5-53. fold error (1) when 2f max . < f s (2) when 2f max . > f s f f s f max. f s /2 original spectrum (sampling) original spectrum ideal low-pass filter fold spectrum f max. f s f s /2 f f f s f max. f s /2 original spectrum fold error f max. f s f s /2 f original spectrum fold spectrum
chapter 5 examples of stationary type vcr servo control 115 figure 5-54. pole location when sampling theorem is satisfied (1) pole location of f (s) (2) pole location of f (s) before sampling processing after sampling processing figure 5-55. pole location when sampling theorem is not satisfied (1) pole location of f (s) (2) pole location of f (s) before sampling processing after sampling processing 3 p t s p t s p t s 3 p t s e e f (s) pole basic band 0 f (s) j w 3 p t s p t s p t s 3 p t s e e sideband 0 f* (s) j w folded pole basic band sideband 2 p t s 3 p t s p t s p t s 3 p t s e e f (s) pole basic band 0 f (s) j w 3 p t s p t s p t s 3 p t s e sideband 0 f* (s) j w basic band sideband 2 p t s pole generated by fold e
chapter 5 examples of stationary type vcr servo control 116 (2) biprimary transform method biprimary transform is a transform method to prevent intrusion of fold errors in the standard z function for analysis of control. generally, when analyzing a control system, the analysis in a continuous system is performed on s planar using laplace transform and the analysis in a discrete system on z planar using z transform. transform of s planar to z planar is called standard z transform. when configuring a digital filter, it is easier if the filter is designed in a continuous system before transforming to a discrete system. the issue here is the effect by sampling processing. that is, if t s is made too long when transforming analog signal to discrete numeric sequence in certain time interval t s , the restoration of original signal is impossible. the limit sampling frequency fs to restore the original analog signal can be described with the well-known sampling theorem below: 2 ? f max. f s = 1 t s f max. : the maximum frequency included in the original analog signal f s : sampling frequency t s : sampling cycle the expression above shows that the restoration of the original analog signal from the sampled digital signal unless setting the sampling frequency f s to twice or more of the frequency included in the original analog signal. in the following paragraph, this is considered in the corresponding relation of s planar and z planar. figure 5-56 shows the mapping by standard z transform. the band of 2 p /t s width on s planar is generated with sampling processing. the area corresponding to the width of this band is mapped on the whole z planar. that is, block a on s planar (shaded area) is mapped to inside the unit circle on z planar and block b on s planar is mapped to outside the unit circle on z planar, respectively. therefore, if a pole by fold error exists in the 2 p /t s band on s planar, the fold error is also mapped on z planar. figure 5-56. mapping by standard z transform 3 p t s p t s p t s 3 p t s e e 0 j w (s planar) c a e d b f (z planar) j e1 e1 1 1 b, d, f a, ce
chapter 5 examples of stationary type vcr servo control 117 biprimary transform is one of the processing methods to prevent fold errors from intruding into z planar. in biprimary conversion, when sampling processing is performed, the whole s planar is transformed to 2 p /t s band area before performing standard z transform so that fold errors are not generated. the planar where the whole s planer is transformed to is defined as s planar. figure 5-57 shows the mapping by biprimary transform. since s transform is a cyclic function consisting of the band with 2 p /t s width, s-z transform with no fold error is acquired if standard z transform is carried out after s transform. in biprimary transform, the relation between s operator, which is the parameter of a continuous system, and z operator, which is the parameter of a discrete system, is represented in the following expression: s = 2 1 C z C1 t s 1 + z C1 t s : sampling cycle from the above expression, the following operation is performed to transform transfer function g (s) expressed in a continuous system to transfer function g (z) of a discrete system with no fold error. g (z) = g (s) | s = 2 1 C z C1 t s 1 + z C1
chapter 5 examples of stationary type vcr servo control 118 figure 5-57. mapping by biprimary transform 3 p t s p t s p t s 3 p t s e e 0 j w (s planar) (z planar) j e 1 e 1 1 1 0 basic band 2 p t s (standard z transform) (s planar) 0 j w biprimary transform
chapter 5 examples of stationary type vcr servo control 119 5.12.3 digital filter designing method an example of digital filter designing methods is shown below. (1) determination of specification determine the specification of the digital filter to realize, such as frequency characteristics, cut-off frequency, time area response, and sampling cycle. (2) configuration on analog circuit design the analog filter satisfying the specification in (1). at this time, transform operation to digital filter is made easier if the analog circuit is configured with passive filter using lcr. (3) calculation of transfer function find the transfer function g (s) in continuous time area of the analog filter found in (2). (4) biprimary transform processing transform the analog filter transfer function g (s) to discrete time sequence transfer function g (z). at this time, perform biprimary transform to (s) so that fold errors by sampling processing are avoided. (5) determination of filter constant calculate digital filter constant from the specification in (1) and quantize the filter coefficient. the setting of the coefficient word length of the digital filter is determined according to the filter cut-off frequency, sampling cycle, and dynamic range. (6) program generation of digital filter (7) measurement of characteristics measure whether the digital filter generated in (6) is operating or not as specified using servo analyzer. also, measure the dynamic range of the digital filter. the dynamic range refers to the maximum digital value which will not cause overflow if input to the filter. (8) improvement of characteristics change the arithmetic word length and filter configuration to improve the characteristics acquired in (7). also, shorten the arithmetic word length and change algorithm if the calculation time of the digital filter is too long.
chapter 5 examples of stationary type vcr servo control 120 5.12.4 primary iir type digital filter transfer function figure 5-58 shows primary iir type digital filter block diagram. figure 5-58. primary iir type digital filter block diagram in figure 5-58, a, b, and g are filter constants and the meanings of them are as follows: a : non-cyclic filter constant b : cyclic filter constant g : filter gain constant assume n-th input value of this filter as x n , output value as y n , calculation value in n-th filter arithmetic process as u n , calculation value of nC1-th filter arithmetic process as u nC1 . from the block diagram in figure 5-58 , the following expression is found: u n = x n C b u nC1 y n = (u n + a u n-1 ) g (expression 5-1) if the expression above is solved for x n : x n = u n + b u nC1 y n = (u n + a u n-1 ) g (expression 5-2) both parts in the expressions above are z transformed to acquire the following expression: x (z) = u (z) + bz C1 u (z) y (z) = g (u (z) + az C1 u (z)) (expression 5-3) from the expression above, the transfer function g (z) in the system is as follows: g (z) = y (z) = g (u (z) + az C1 u (z)) x (z) u (z) + bz C1 u (z) = g 1 + az C1 1 + bz C1 (expression 5-4) x n y n z C1 ba u n u n C 1 g + C + +
chapter 5 examples of stationary type vcr servo control 121 5.12.5 lag-lead filter configuration method the lag-lead filter is often used as the drum phase control system compensation filter for vcrs. the purpose is to eliminate the constant deviation and improve the accuracy of the system. figure 5-59 shows the lag-lead filter configuration and characteristics. figure 5-59. lag-lead filter configuration and characteristics (a) lag-lead filter configuration (b) lag-lead filter board line graph r1 r2 c i vout vin cut-off frequency f1 = 1 2 p c (r1+r2) f2 = 1 2 p cr2 ig (j w ) i [db] g (j w ) i [deg] f1 f2 f f 0 0 (gain characteristics) (phase characteristics)
chapter 5 examples of stationary type vcr servo control 122 figure 5-59 (b) shows lag-lead filter gain characteristics and phase characteristics (board line graph) of the analog circuit configuration shown in figure 5-59 (a). lag-lead filter has two segmented point frequencies f1 and f2. by freely setting these, the filter gain characteristics and phase characteristics can be changed. the method to find the constants (a, b, and g) used in primary iir type digital filter to realize lag-lead filter characteristics is as follows: in the case of the filter shown in figure 5-59 (a), the segmented point frequencies f1 and f2 are found in the following expression: f1 = 1 2 p c (r1 + r2) (expression 5-5) f2 = 1 2 p cr2 (expression 5-6) the transfer function of the filter in figure 5-59 (a) is found as follows (the transfer function is find by plus transforming the relational expressions for vin and vout, respectively): g (s) = 1 + s cr2 1 + s c (r1 + r2) 1 + 1 s = 2 p f1 1 + 1 s 2 p f2 (expression 5-7) a = 1 b = 1 2 p f2 2 p f1 (expression 5-8) now, if parameter a and b are assumed and assigned as the expression above, the transfer function of lag-lead filter is as follows: g (s) = 1 + bs 1 + as (expression 5-9) since the transfer function in the expression above is represented in continuous time system, this is transformed to be represented in discrete time system. in this case, biprimary transform is used because fold error is generated if standard z transform is performed. that is, s arithmetic operator is replaced as follows: s = 2 1 C z C1 t s 1 + z C1 t s : sampling cycle (expression 5-10) the s operator is assigned to the transfer function, the expression is reorganized.
chapter 5 examples of stationary type vcr servo control 123 1 + 2a 1 C z C1 g (z) = t s 1 + z C1 = t s (1 + z C1 ) +2a (1 C z C1 ) 1 + 2b 1Cz C1 t s (1 + z C1 ) +2b (1 C z C1 ) t s 1 + z C1 1 + t s C 2a z C1 = t s + 2a t s + 2a = g 1 + az C1 t s + 2b 1 + t s C 2b z C1 1 + bz C1 t s + 2b (expression 5-11) the above transfer function found here has the same configuration as the one found from the primary iir type digital filter block diagram in figure 5-58. g, a, and b in the expression above are filter coefficients, and turn out as follows: g = t s + 2a t s + 2b a = t s C 2a t s + 2a b = t s C 2b t s + 2b (expression 5-12) if g, a, and b are found from sampling cycle t s [sec] and two segmented point frequencies, f1 and f2, which are filter characteristics, primary iir type digital filter coefficient can be found. an example of this is shown below. ? filter design specification sampling cycle t s : 4.0 [msec] (sampling frequency 250 hz) segmented point frequency f1 : 1.0 [hz] f2 : 10.0 [hz] filter coefficients, g, a, and b are found from the above filter design specification. a and b are found from expression 5-8. a = 1 = 1 = 0.01591549 2 p f2 2 p 10 b = 1 = 1 = 0.15915494 2 p f1 2 p 1
chapter 5 examples of stationary type vcr servo control 124 if a, b, and t s found from the above are assigned to expression 5-12, filter coefficients g, a, and b are found as follows: g = 0.111169375 a = C0.77672957 b = C0.97517917 5.12.6 filter processing method lag-lead filter is configured with product-sum instruction. lag-lead filter propagation function is as follows: y n =g (x n + ax nC1 ) C by nC1 =g ? x n + ag ? x nC1 + (Cb) ? y nC1 the operation of product-sum instruction when the number of operations is two is as follows: axde ? (b) (c) + (b + 2) (c + 2) + axde then each parameter of lag-lead filter is assigned as follows: axde (left part) : y n signed 32 bits (b) : g signed 16 bits (c) : x n signed 16 bits (b + 2) : ag signed 16 bits (c + 2) : x nC1 signed 16 bits axde (right part) : (Cb) ? y nC1 signed 32 bits signed multiplication is considered here. first, the coefficients g, ag, and (Cb) of lag-lead filter are designed with gain of 1, so that they become values with an absolute value of 1 or less. | g | <1, | ag | <1, | (Cb) | <1 therefore, the values multiplied with the 15th power of 2 (32768) are actually used for operation. for example, 0.980 ? 0.98 32768 = 32112.64 ? 7d70h C 0.980 ? C0.98 32768 = C32112.64 ? 8290h
chapter 5 examples of stationary type vcr servo control 125 the data has the following range if the error amount is also dealt with signs. 8000hC7fffh (C32768 to +32767) if this is calculated with signed multiplier: the 1/2 of the actual calculation result enters higher 16 bits of the arithmetic result of signed multiplication. therefore, the result is doubled (right shift) after executing product-sum instruction. however, gain multiplication is normally performed after digital filter calculation, so that there is a method which abbreviates the shift processing if the gain is doubled. the propagation function becomes as follows: y n = g ? x n + ag ? x nC1 + (Cb) ? y nC1 where y n = y n /2 (Cb) ? y nC1 = (Cb) ? y nC1 /2 this enables filter calculation only with product-sum instruction. however, calculation of (Cb) y nC1 is necessary for the following sampling timing, then, singed multiplication is performed again. since the result is made 1/2 as it is, right shift processing is performed before multiplication. g x n example hex data 8290h 1000h f8290000h decimal e 0.980 4096 e 4014.08 f052 0000h left shift 1 bit pick higher 16 bits e 4014 . sign . sign sign
chapter 5 examples of stationary type vcr servo control 126 filter calculation is summarized as follows: (1) set values for each register (b) : g (c) : xn (b + 2) : ag (c + 2) : x nC1 axde : (Cb) ? y nC1 (already stored in memory at the previous sampling timing) (2) execute product-sum instruction macsw 2 the value stored in calculation result axde is y n (3) right shift axde 1 bit to y n shlw de rolc x rolc a (4) find (Cb) ? yn mulw de ; de ? (Cb) store calculation result axde in memory and use it as (Cb) ? y nC1
chapter 6 ctl amplifier 127 chapter 6 ctl amplifier 6.1 ctl amplifier auto gain control processing ctl amplifier is used for amplifying the playback control (pbctl) signal which is the playback of the ctl signal recorded on vcr tape. figure 6-1 shows the ctl amplifier configuration. figure 6-1. ctl amplifier configuration ctl detection flag s (ampm0.3) ctl detection flag l (ampm0.1) ctl detection flag clear (write 1 to ampm0.6) pbctl signal (to timer) gain control signal generation circuit waveform shaping circuit ctlm.0-ctlm.4 ctlout2 ctlout1 ctlin recctlC recctl+ ctl head to recctl driver v ref ampc.1 ampc.1 + C + C
chapter 6 ctl amplifier 128 ctl amplifier is configured with two op amplifiers and the forestage amplifier is fixed to 20 db. therefore, gains are adjusted by changing the gain of the second stage amplifier. the gain setting of ctl amplifier can be changed with ctlm register in 32 steps (by 1.78 db). caution changing of the gain setting should be avoided while ctl signal is being input. the m pd784915 has a gain control signal generation circuit which uses ctl detection flags to discriminate the amplifying state of ctl amplifier output. ctl detection flags are divided into ctl detection flag s and ctl detection flag l according to the detection level. ctl detection flags s and l can be cleared by writing 1 to flgclr (ampc0.6). using these two detection flags, auto gain control of ctl amplifier is carried out. table 6-1 shows the relation between the ctl detection flag read value and ctl amplifier gain adjustment. table 6-1. ctl detection flag read value and ctl amplifier gain adjustment ctl detection flag read discrimination ctl amplifier gain adjustment flag l flag s 1 1 gain large lower gain 0 1 gain optimum no change 0 0 gain small raise gain figure 6-2 shows the relationship between ctl amplifier output and each detection level/flag. figure 6-2. relationship between ctl amplifier output and each detection level/flag detection level l detection level s v ref waveform shaping detection level s detection level l 1 0 1 0 waveform shaping detection flag s detection flag l
chapter 6 ctl amplifier 129 6.1.1 ctl amplifier auto gain control method ctl amplifier auto gain control is performed with the timings of ctl detection flag read and the amplifier gain setting which are determined by the playback control (pbctl) signal edge interrupt. ? timing of ctl detection flag read and ctl amplifier gain setting as mentioned earlier, change of the gain setting must be done avoiding pbctl signal input (rising and falling edges of amplifier amplifying point). moreover, since ctl detection flag s and l are specified at the rising and falling edges of pbctl signal, so that after changing ctl amplifier gain, the both edge must be passed more than once before flag is read. in order to pass both edges avoiding pbctl signal input, the timings of the ctl detection flag read and the amplifier gain setting are determined by the pbctl signal edge interrupt (one edge). ? for play, cue/rev (refer to figure 6-3 ) gain is changed at 70% point of pbctl signal. (refer to figure 6-4 ) gain is changed at 30% point of pbctl signal. ? for ff/rew (refer to figure 6-5 ) gain is changed at 180% point of pbctl signal. (refer to figure 6-6 ) gain is changed at 120% point of pbctl signal. remark for play or cue/rev, gain is changed 65% or more of pbctl signal in forward direction and less than 35% in reverse direction and the order of the signal input has been set so that the rising edge of the pbctl signal is input first and then the falling edge is input. in addition, for ff/rew, ctl signal input is the fastest, approx. 130 m s (= 33.37 ms/256) in 256-time speed (when tape mode is ep), and it would take 198 m s max. before pbctl signal input intcr12 interrupt (due to other priority interrupt), so that the timing has been set at +100%.
chapter 6 ctl amplifier 130 figure 6-3. gain change timing for play or cue/rev in forward direction tape running direction 100 % 70 % pbctl signal (before waveform shaping) pbctl signal (after wave form shaping) specify pbctl signal rising edge tm3 count value tm1 count value (n) (n+1) (n+2) cpt30 (n) cr13 (n+1) intcr12 vectored interrupt processing intcr13 vectored interrupt processing execute the following processings by intcr12 vectored interrupt capture current tm1 count value to cr12 (automatic) cr13 (n+1) ? cr12 + (cpt30 (n) 0.7) intcr13 interrupt request clear and interrupt enabled execute the following processings by intcr13 vectored interrupt read ctl detection flag if ctl detection flag s and l are both 1 , the gain is large; therefore, decrease the gain for 1.78 db if ctl detection flag s and l are both 0 , the gain is small; therefore, increase the gain for 1.78 db intcr13 interrupt disabled
chapter 6 ctl amplifier 131 figure 6-4. gain change timing for play or cue/rev in reverse direction tape running direction 100 % 30 % pbctl signal (before waveform shaping) pbctl signal (after wave form shaping) specify pbctl signal falling edge tm3 count value tm1 count value (n) (n+1) (n+2) cpt30 (n) intcr12 vectored interrupt processing intcr13 vectored interrupt processing execute the following processings by intcr12 vectored interrupt capture current tm1 count value to cr12 (automatic) cr13 (n+1) ? cr12 + (cpt30 (n) 0.3) intcr13 interrupt request clear and interrupt enabled execute the following processings by intcr13 vectored interrupt read ctl detection flag if ctl detection flag s and l are both 1 , the gain is large; therefore, decrease the gain for 1.78 db if ctl detection flag s and l are both 0 , the gain is small; therefore, increase the gain for 1.78 db intcr13 interrupt disabled cr13 (n+1)
chapter 6 ctl amplifier 132 figure 6-5. gain change timing for ff/rew in forward direction tape running direction 180 % 100 % pbctl signal (before waveform shaping) pbctl signal (after wave form shaping) specify pbctl signal rising edge tm3 count value tm1 count value (n) (n+1) (n+2) cpt30 (n) cr13 (n+1) intcr12 vectored interrupt processing intcr13 vectored interrupt processing execute the following processings by intcr12 vectored interrupt capture current tm1 count value to cr12 (automatic) cr13 (n+1) ? cr12 + (cpt30 (n) 1.8) intcr13 interrupt request clear and interrupt enabled execute the following processings by intcr13 vectored interrupt read ctl detection flag if ctl detection flag s and l are both 1 , the gain is large; therefore, decrease the gain for 1.78 db if ctl detection flag s and l are both 0 , the gain is small; therefore, increase the gain for 1.78 db intcr13 interrupt disabled
chapter 6 ctl amplifier 133 figure 6-6. gain change timing for ff/rew in reverse direction tape running direction 120 % 100 % pbctl signal (before waveform shaping) pbctl signal (after wave form shaping) specify pbctl signal falling edge tm3 count value tm1 count value (n) (n+1) (n+2) cpt30 (n) intcr12 vectored interrupt processing intcr13 vectored interrupt processing execute the following processings by intcr12 vectored interrupt capture current tm1 count value to cr12 (automatic) cr13 (n+1) ? cr12 + (cpt30 (n) 1.2) intcr13 interrupt request clear and interrupt enabled execute the following processings by intcr13 vectored interrupt read ctl detection flag if ctl detection flag s and l are both 1 , the gain is large; therefore, decrease the gain for 1.78 db if ctl detection flag s and l are both 0 , the gain is small; therefore, increase the gain for 1.78 db intcr13 interrupt disabled cr13 (n+1)
chapter 6 ctl amplifier 134 6.1.2 ctl amplifier auto gain control processing the following setting and processing are carried out to perform ctl amplifier auto gain control. (1) the following setting is carried out at every forward/reverse direction change ? pbctl signal input edge is set as follows: the input edge is generated at rising edge of pbctl signal. the input edge is generated at falling edge of pbctl signal. remark when the tape mode is ep, intcr12 vectored interrupt is generated with every pbctl signal for play, every nine pbctl signals for cue/rev, and every eight pbctl signals for ff/rew at the edge shown above. (2) the following setting and processing are carried out by intcr12 vectored interrupt ? the following time is set to compare register 13 (cr13) by intcr12 vectored interrupt ? for play/cue/rev set time 70% of pbctl signal cycle to cr13 cr13 = cr12 + (cpt30 70%) set time 30% of pbctl signal cycle to cr13 cr13 = cr12 + (cpt30 30%) ? for ff/rew set time 180% of pbctl signal cycle to cr13 cr13 = cr12 + (cpt30 180%) set time 120% of pbctl signal cycle to cr13 cr13 = cr12 + (cpt30 120%)
chapter 6 ctl amplifier 135 explanation ? cr12 : tm1 count value is captured with every intcr12 vectored interrupt by pbctl signal ? cpt30 : tm3 count value is captured with every intcr12 vectored interrupt by pbctl signal since cr12 captures tm1 count value and cr13 captures tm3 count value, value need to be set to cr13 after adding up the input clock ratio of tm1 and tm3 (however, in this time, the setting is unnecessary because both have the same clock [f clk /8]). ? intcr13 interrupt request clear and interrupt enabled (3) processing at intcr13 ? ctl gain control signal detection and gain change according to the status of ctl detection flag s and l, gain is changed by 1 step as follows: ? if ctl detection flag s and l are both 1, gain is large; therefore, decrease the gain for 1 step (1.78 db) ? if ctl detection flag s and l are both 0, gain is small; therefore, decrease the gain for 1 step (1.78 db) ? if ctl detection flag s is 1 and l is 0, gain is optimum; therefore, no change is made for the gain. ? intcr13 interrupt disabled (4) processing at pbctl ? increase the gain by +5 steps, every time there is no ctl signal and 40 interrupts does not occur continuously at intcpt13 interrupt (capstan fg interrupt) ? the gain is maximum (1fh) on non-recorded tape (5) processing in each mode transition ? set the optimum gain previously measured in each mode in every mode transition of each mode (equipment operation such as play and cue, and tape mode such as ep and sp) (this processing is optional; however, it has the advantage that the optimum gain can be quickly achieved.)
chapter 6 ctl amplifier 136 [memo]
chapter 7 viss detection 137 chapter 7 viss detection the following shows the viss detection method. 7.1 what is viss viss stands for vhs index search system. in vhs, cue code is set by varying the duty ratio of control signal to be recorded on control track. each viss data is specified as shown in table 7-1. the cue code as index information is set by data sequence of control signal as shown in figure 7-1. table 7-1. viss data figure 7-1. viss cue code waveform in forward direction waveform in reverse direction data 0 1 pbctl signal (before wave- form shaping) pbctl signal (after wave- form shaping) 100% 60 5% 100% 27.5 2.5% 100% 60 5% 100% 27.5 2.5% pbctl signal (before wave- form shaping) pbctl signal (after wave- form shaping) pbctl signal (before wave- form shaping) pbctl signal (after wave- form shaping) pbctl signal (before wave- form shaping) pbctl signal (after wave- form shaping) 0111 1110 ........ ... 61 3 bits 63 3 bits reference point tape running direction control track
chapter 7 viss detection 138 viss write (cue code write) is carried out at the following timings. ? when starting recording (except joint recording) ? when starting programmed recording ? when index writing by pushing down index key 7.2 viss detection 7.2.1 viss detection method viss detection is performed using macro service in data pattern discrimination mode by playback control (pbctl) signal edge interrupt (intcr12). intcr12 interrupt also performs pbctl signal frequency division. (1) about viss detection method in viss detection, pbctl signal level is taken at 43.75% (in forward direction) or 56.25% (in reverse direction) of one pbctl signal cycle as viss detection point. according to the level, if the level is high, 0 is set, if it is low, 1 is set. it is judged that viss signal exists when 0 is detected 10 times after 1 is consecutively detected 15 times (according to the specification of system controller, it may be judged viss signal exists if 1 is consecutively detected several times). the m pd784915 is provided with timer 3 (tm3) and capture register 30 (cpt30) to find a cycle, compare register (cr30) to store viss detection point, and control flip flop (ctl f/f) to take in control signal level at detection point, in order to keep up with the change of tape running speed, so that it can perform viss detection. figure 7-2. viss detection circuit (pulse width detection circuit) configuration pbctl ptr10 ptr11 tm3 (16) cr30 (16) cr31 (16) cpt30 ( 16) cptm (8) cr12 (16) tm1 (16) intcr12 internal bus tmc3 edvc 16 8 clear d ctl f/f ck ff lvl2 fasp ff lvl1 . . . 710 capture selector selector selector
chapter 7 viss detection 139 m pd784915 uses macro service in data pattern discrimination mode to perform viss detection. the comparison data to perform comparison with the data stored in buffer area is set to an address indicated with comparison area pointer (not only program space in memory but also internal ram space can be specified as the comparison area). (2) about macro service in data pattern discrimination mode (viss detection mode) this is a macro service to sequentially store the output from control flip flop (ctl f/f) in the pulse detection circuit (timer 3) in the super timer unit into the buffer set in the ram area with left shift. the timer measures the pbctl signal pulse duty from the ctl amplifier circuit, and latches 1 to ctl f/f if the duty is larger than the value previously set, and 0 if the duty is smaller. caution take note that 1 and 0 of the viss signal are reversed. the contents of sfr (bit 7 of timer control 3) specified with sfr pointer 1 is buffer area left shifted at interrupt generation. at the same time, the data of buffer area and comparison area are compared, and a vectored interrupt is generated if they coincide (macro service counter is decremented and if it becomes 0, a vectored interrupt is also generated). by option specification (bit 5 of macro service mode register = 1), the operation is made so that the contents of sfr [capture trigger 30 (cpt30)] specified with sfr pointer 2 is multiplied with the coefficient and stored to sfr [compare register 30 (cr30)] specified with sfr pointer 3 (automatic updating of discrimination threshold when tape speed is varying).
chapter 7 viss detection 140 figure 7-3. data pattern discrimination mode block configuration ? explanation cpt30 : pbctl signal cycle enters coefficient : multiplier to find detection point enters cr30 : detection point (the result of cpt30 multiplied with coefficient) enters buffer area : viss signal data with left shift enters comparison area : viss detection pattern enters vectored interrupt is generated when either one of the following conditions is satisfied. <1> if the contents of macro service counter 8 (msc) is 0 (if interrupt request is generated for the number of times set in msc). <2> if the data stored in buffer area coincides with the data in the comparison area separately set. buffer area (memory) comparison area (memory) intcr12 vectored interrupt upper address ctl f/f (bit 7 of tmc3) coefficient (memory) multiplication cpt30 tm3 cr30
chapter 7 viss detection 141 figure 7-4 shows the addressing and data setting in data pattern discrimination mode. figure 7-4. addressing and data setting in data pattern discrimination mode channel pointer (sets lower 8 bits of the address in msc) mode register ( 00100100b : sets multiplication in data pattern discrimination mode) macro service counter (sets number of pbctl signal frequen- cy division in each mode to msc) sfr pointer 2 (sets lower 8 bits of the address in cpt30) multiplication coefficient (sets forward direction: 43.75%(70h), reverse direction: 56.25% (90h)) sfr pointer 3 (sets lower 8 bits of the address in cr30) sfr pointer 1 (sets lower 8 bits of the address in tmc3) buffer size specification register (sets 2 bytes) buffer area (upper) buffer area (lower) comparison area pointer [upper] (sets upper 8 bits of upper address in comparison area) comparison area pointer [lower] (sets lower 8 bits of upper address in comparison area) data comparison area [upper] (00000000b) data comparison area [lower] (0000001b) timer control register (tmc3) compare register (cr30) timer (tm3) capture register (cpt30) multiplication intcr12 macro service control register fe0dh fe0ch upper address lower address intcr12 vectored interrupt (msc = 0) intcr12 vectored interrupt (coincidence) bit 7 (coincidence) pbctl (explanation) data flow data flow address specification interrupt generation d clt ck f/f
chapter 7 viss detection 142 7.2.2 viss detection processing the following setting and processing are carried out to perform viss detection. (1) macro service initialization is performed before starting viss detection ? set data with data pattern discrimination mode multiplication (14h) to mode register ? set lower 8 bits of the address in macro service counter (msc) to channel pointer ? set buffer area size specification register to 2 bytes (02h) ? set clear (0ffffh) to 2 bytes of buffer area ? set lower 8 bits (3bh) of the address in timer control register 3 (tmc3) to sfr pointer 1 ? set lower 8 bits (56h) of the address in timer 3 capture register 0 (cpt30) to sfr pointer 2 ? set lower 8 bits (5ch) of the address in timer 3 compare register 0 (cr30) to sfr pointer 3 ? set data comparison area address to comparison area pointer ? set comparison data (0001h) in comparison area remark the value in the comparison setting area (0001h) means that viss data 0 is entered once after viss data 1 is entered 15 times. caution duty detection malfunction prevent circuit control (tmc3.6) is made operation enable for preventing viss signal malfunction. therefore, take note that unless viss data 0 is entered twice consecutively, it is not judged that data 0 is entered (if viss 1 data is entered once, it is judged that 1 is entered). (2) the frequency division of ctl signal is also set in each mode transition (equipment operation such as play/ cue, and macro service counter (msc) of tape mode such as ep and sp) caution pbctl signal frequency division is also performed in intcr12 interrupt. in sets not provided with viss detection, the counter mode macro service is used for pbctl signal frequency division while, in sets provided with viss detection, the data pattern discrimination mode macro service is used.
chapter 7 viss detection 143 (3) the following setting is carried out at every forward/reverse direction change ? set each multiplication coefficient as follows: set 0.4375 time multiplier (70h) which is the value of the 43.75% position of pbctl signal. set 0.5625 time multiplier (90h) which is the value of the 56.25% position of pbctl signal. remark <1> the middle point of the percentage of viss data 0 and 1 is adopted for multiplication coefficient. in forward direction ... (60% + 27.5%) ? 2 = 43.75% in reverse direction ... (40% + 72.5%) ? 2 = 56.25% <2> the multiplication coefficient set value is set as follows: in forward direction ... 0.4375 256 = 112 (70h) in reverse direction ... 0.5625 256 = 144 (90h) ? set pbctl signal input 4 edge as follows: generated at pbctl signal rising edge generated at pbctl signal falling edge
chapter 7 viss detection 144 (4) intcr12 macro service processing (automatically executed by macro service) the following intcr12 macro service processing is automatically executed with trigger by pbctl signal edge. ? the result of the automatic multiplication of the value of cpt30 and multiplication coefficient is set to cr30. (viss detection setting) (refer to figure 7-5 ) set 43.75% time of pbctl signal cycle to cr30. cr30 ? cpt30 43.75% (refer to figure 7-6 ) set 56.25% time of pbctl signal cycle to cr30. cr13 ? cpt30 56.25% (explanation) cpt30: tm3 count value (a cycle of pbctl signal) is captured at every pbctl signal edge interrupt. ? value of clt f/f (tmc3.7) is left shifted to buffer area (the entire buffer is also left shifted). ? compared with the value in comparison area, and if they coincide, intcr12 vectored interrupt is generated. intcr12 vectored interrupt is also generated when macro service counter is 0.
chapter 7 viss detection 145 figure 7-5. intcr12 macro service processing in forward direction pbctl signal (before waveform shaping) pbctl signal (after waveform shaping) specify pbctl signal rising edge ctl f/f (tmc3.7) tm3 count value cpt30 (n) cr30 (n+1) (n) (n+1) 43.75% 100% tape running direction intcr12 macro service processing level taken into ctl f/f (viss detection point) the following processings are automatically performed with intr12 macro service cr30 (n+1) ? cpt30 (n) 0.4375 left shift ctl f/f (tmc3.7) value to buffer area compare the values in comparison area and buffer area if they coincide, intcr12 vectored interrupt is generated (if msc is 0 , intcr12 vectored interrupt is also generated).
chapter 7 viss detection 146 figure 7-6. intcr12 macro service processing in reverse direction (5) the following processing is performed at intcr12 vectored interrupt ? since interrupt is generated either at every ctl signal frequency division or coincidence of data comparison, the following method is taken to judge which one is generated. ? if macro service counter (msc) is not 00h, it is judged as ? if macro service counter (msc) is 00h and the contents of buffer area is 0001h (the same value as that of comparison discrimination area) , it is judged as ? ? set macro service counter value again ? set macro service interrupt enable ? viss signal is detected. set viss detection flag and notify system controller processing ? ? set macro service counter value again ? set macro service interrupt enable pbctl signal (before waveform shaping) pbctl signal (after waveform shaping) specify pbctl signal falling edge ctl f/f (tmc3.7) tm3 count value cpt30 (n) cr30 (n+1) (n) (n+1) 56.25% 100% tape running direction intcr12 macro service processing level taken into ctl f/f (viss detection point) the following processings are automatically performed with intr12 macro service cr30 (n+1) ? cpt30 (n) 0.5625 left shift ctl f/f (tmc3.7) value to buffer area compare the values in comparison area and buffer area if they coincide, intcr12 vectored interrupt is generated (if msc is 0 , intcr12 vectored interrupt is also generated).
chapter 7 viss detection 147 7.3 viss rewrite 7.3.1 viss rewrite method newly writing viss signal on recorded tape or erasing viss signal already written is called viss rewrite. rewrite is performed by rewriting pbctl signal as shown in figure 7-7. figure 7-7. viss rewrite (a) viss write (b) viss delete pbctl signal recctl + recctl C pbctl signal after rewrite hi-z
chapter 7 viss detection 148 the recording control signal (recctl) driver of m pd784915 has rewrite mode used for rewriting viss signal. recctl driver internally holds sequence data, and the sequence is updated with specific interrupt as trigger. recctl driver sequence in rewrite mode operates recctl+ pin and recctlC pin as shown in table 7-2. therefore, viss signal rewrite is realized considering only the interrupt generation timing, which is a trigger signal. table 7-2. recctl driver rewrite mode sequence sequence recctl+ recctlC 0 high impedance 1 low level 2 low level high level 3 high level
chapter 7 viss detection 149 7.3.2 viss rewrite processing rewrite processing is realized using intcr11 and intcr12. for rewrite timing, trigger timing is set to compare register 11 (cr11) using pbctl signal interrupt intcr12 as reference. figure 7-8 shows viss = 1 signal rewrite operation timing. figure 7-8. viss = 1 signal rewrite operation timing chart 01 2 3 01 sequence reference viss = 0 erase intcr11 intcr11 intcr11 intcr12 intcr11 pbctl signal recctl + pin recctl C pin pbctl signal after rewrite timer 1 viss = 1 rewrite 12 3 4
chapter 7 viss detection 150 timing <1> in figure 7-8 is pbctl signal rising. at this point, the sequence is initialized, and the changing point from sequence 0 to sequence 1 is found with timer 1 (tm1) using the captured value as reference value, stored in compare register 11 (cr11), and intcr11 interrupt is enabled. for the following timing <2> and <3> intcr11 interrupt, each changing point to sequence 2 and 3 is found on timer 1 and stored in cr11. rewrite is completed at timing <4> and intcr11 interrupt is disabled. each timing in ntsc is as shown in table 7-3. viss = 1 signal and viss = 0 signal have different timings. table 7-3. viss write operation timings timings viss = 1 write viss = 0 write pbctl rising <1> ? <2> 5 ms 5 ms <2> ? <3> 4.176 ms 20.021 ms <3> ? <4> 16.192 ms 5.345 ms <4> ? pbctl rising 5 ms 5 ms hi-z cancellation timing from pbctl rising is not specified for the period between the timing to become hi-z <4> and pbctl rising. however, it is set as 5 ms for the sake of convenience, assuming it as the timing approximately a half way from pbctl high pulse to pbctl low pulse when viss is 1.
chapter 8 program list 151 chapter 8 program list this chapter lists programs of this application software.
chapter 8 program list 152 $ debug swold equ 0 ;----------------------------- public, extrn declaration ;----------------------------- ;------------------------------ public ;------------------------------ ;///// process /////// public vpt2_000 ; intcpt2 drum fg interruption ; process routine public vr10_000 ; intcr10 drum phase error detection ; interruption process public vpt3_000 ; intcrp3 capstan fg ; interruption public vr12_000 ; intcr12 capstan phase error ; detection interrupt public vr00_000 ; intcr00 quasi vsync ; timing setting public vr02_000 ; intcr02 quasi vsync ; timing setting public vr02_000 ; intcr02 quasi vsync ; timing setting public vr13_000 ; %intcr13 ctl detection & output setting ; %ctl ;///// subroutine ///// public yvtbl_00 ; servo data setting sub ;///// ram /////////////// public rvscr12 ; intcr12 macro service mode register public rvccr12 ; intcr12 macro service ; channel pointer public rvmcmpp ;%intcr12 macro service compare area ; pointer public rvb2cr12 ; intcr12 macro service buffer ; area 2(l) public rvb1cr12 ; intcr12 macro service buffer ; area 1(h) public rvbfreg ; intcr12 macro service buffer size reg public rvmsfrp1 ;%intcr12 macro service sfr pointer 1 public rvmsfrp3 ;%intcr12 macro service sfr pointer 3 public rvmkeisu ;%intcr12 macro service keisu area public rvmsfrp2 ;%intcr12 macro service sfr pointer 2 public rvmccr12 ; intcr12 macro service counter area public rvmcmpd ;%intcr12 macro service compare data ;//// macro service data //// ;% public ptn_ff ;%positive direction multiplier coefficient (0.4375) data public ptn_rew ;%reverse direction multiplier coefficient (0.5625) data public dt_cmp ;%cr12 comparison data ;%viss
chapter 8 program list 153 public rvcpt3 ;_l ; cpt3 low data memory public rvsrvcd ; servo code area public rvcprf ;_l ; capstan phase reference low public rvcpt2 ;_l ; cpt2 low data memory public rvcpt2 ;_m ; cpt2 middle & high data memory public rvcpt1 ; % cpt1 public rvcpt0 ; % cpt0 public rvfsrv_2 ; servo data flag area 2 public rvcevfg ; sp/lp/ep auto detect cfg divide ; counter public rvpsvcnt ; quasi v signal counter public rvcram ; macro service count data public rvbcr10 ; cr10 data buffer area ;///// bit /////////////// public fvpblp ; running mode fpblp fpbsep public fvpbsep ; sp : 0 0 ;lp: 1 0 ;ep: 0 1 ; pal : 1 1 public fvdout ; quasi vsync output public fvflctl ; set pbctl missing flag ;///// constant ///// public vsp public vlp public vslp public vpal $ eject ;------------------------------ ; extrn ;------------------------------ ;///// process /////// extrn sr12_000 ;///// sub /////////////// extrn ypgadchg ; set pg value extrn ysa01_r1 ; 1sec timer start for auto-tracking ;///// ram /////////////// extrn rsnow ; transition now mode
chapter 8 program list 154 extrn rsnext ; transition next mode extrn rscfg90c ; cfg 90 pulse counter check extrn rnstimo ; transition timer area extrn rsfrsped ; capstan ff/rew speed level ;///// bit /////////////// extbit fsvmofrq ; v-mute off request extbit fsmdchg ; flag during mode transition extbit fseicpt2 ; intcpt2 enable request flag extbit fsdrmon ; drum on/off flag extbit fhifim ; hi-fi mode flag extbit fsvissi ; index search mode flag extbit fsvisso ; once more search mode flag extbit fsvissme ; viss mark/erase mode flag extbit fsvistr ; viss search start flag extbit fsvissok ; viss detection flag extbit fsafrq ; rfs down edge for auto-tracking extbit fscapon ; capstan on flag extbit fscrrfrq ; capstan reverse rfs edge on request ; flag extbit fnstena ; search detect di timer end flag extbit fsaend ; auto tracking end flag extbit fnsteno ; transition timer end flag extbit fsdfg ; dfg edge detection flag extbit fsspdchg ; tape speed change flag ;///// port /////////////// extbit prfs ; rf switching pulse extbit pqvd ; v-mute extbit pcapfwd ; capstan forward/reverse extbit pcapf_r ; capstan forward/reverse (to deck) $ include (port. inc) ; % extbit fpcapf_r ; flag for port refresh
chapter 8 program list 155 extbit fpqvd ; flag for port refresh ;///// code ///////////// extrn csmload ; tape loading extrn csmplay ; play extrn cvplay ; play extrn cvffrw2h ; 2hrs play (ph fix) extrn cvffrw6h ; 6hrs play (ph fix) extrn cvffrwx3 ; 3hrs play x3 (ph fix) extrn cvffrew ; ff/rew (ph fix) extrn cvcue ; cue (vd out) extrn cvrev ; review (vd out) extrn cvstill ; still (vd out) extrn cvcupl ; cue ? play (vd out) extrn cvrvs ; rvs play (vd out & ph fix) extrn cvfr6hvd ; 6hrs play (vd out & ph fix) $ eject ;-------------------------------- ; servo related equ area ;-------------------------------- ;*** servo data area *** vsequ1 dseg saddr ;% ;*** servo reference data *** rvdfrf: ds 3 ; drum speed reference rvcpt2: ds 3 ; cpt2 data memory rvcpt22: ds 3 ; for debug ;*** capture data memory *** rvcpt0: ds 3 ; cpt0 data memory rvcpt1: ds 3 ; cpt1 low data memory ;*** servo error data *** rverdf: ds 2 ; drum speed error rverdf_1: ds 2 ; drum speed error(C1) rverdp: ds 2 ; drum phase error rverdp_1: ds 2 ; drum phase error(C1) ;--- pwm output bias data area --- rvdbas: ds 2 ;rvdbas_l: ds 1 ; drum bias low byte ;rvdbas_h: ds 1 ; drum bias high byte ;--- drum phase filter unknown-quantity --- rverdp_y: ds 2 rverdp_by: ds 4 rverdf_y ds 2 rverdf_by ds 4
chapter 8 program list 156 $ eject ;*** filter memory *** ;*** filter coefficient data *** ; %filter product-sum operation work area b_buf: ds 2 ; (loop gain) ds 2 ; (filter coefficient a ) x ; (loop gain) ds 2 ; (filter coefficient b ) x ; (output) x (C1) rvc_kmp: ds 2 ; capstan loop gain g1 $eject ;*** capstan data *** rvcfrf: ds 3 ; capstan speed reference rvcprf: ds 2 ; capstan phase reference ;*** servo error data *** rvercf: ds 2 ; capstan speed error rvercp: ds 2 ; capstan phase error rvercp_1: ds 2 ; capstan phase error(C1) rvercmx: ds 2 ; capstan speed & phase mixed ; error rvercmx_1 ds 2 : capstan speed & phase mixed ; error(C1) ;*** capture data memory *** rvcpt3 : ds 3 ; cpt3 data memory ;--- pwm output bias data area --- rvcbas: ds 2 ; capstan bias level ;--- capstan phase filter unknown-quantity --- rvercp_y: ds 2 ; capstan phase y rvercp_by: ds 4 ; capstan phase b x y ;--- capstan speed/phase mix filter unknown-quantity --- rvercmx_y: ds 2 ; capstan speed/phase mix ; y rvercmx_by: ds 4 ; capstan speed/phase mix ; b x y rvsrvcd: ds 1 ; servo code area fvdout equ rvsrvce.7 ; quasi vsync output fvphfx equ rvsrvcd.6 ; phase control is not performed rvcram: ds 1 ; macro service count data rvcevfg: ds 1 ; sp/lp/ep auto detect cfg ; divide counter
chapter 8 program list 157 rvslpch: ds 1 ; sp/lp/ep chattering count ; area rvfsrv_2: ds 1 ; servo data flag area 2 fvdfe10 equ rvfsrv_2.7 ; drum speed error 10% over flag fvcferr equ rvfsrv_2.6 ; capstan speed error (+/C)sign flag fvcplck equ rvfsrv_2.5 ; capstan phase lock flag ; 0:lock 1: unlock fvcfe05 equ rvfsrv_2.4 ; capstan speed error 5% over flag fvhqvdt equ rvfsrv_2.3 ; qvd high timing flag fvflctl equ rvfsrv_2.2 ; pbctl error flag fvpblp equ rvfsrv_2.1 ; pb lp data flag fvpbsep equ rvfsrv_2.0 ; pb sp/ep data flag ; fpblp fpbsep ;sp:00 ;lp:10 ;ep:01 ; pal : 1 1 rvpsvcnt: ds 1 ; quasi v signal counter ;///// capstan kv/kp //////////////// rvc_kvp: ds 2 ; ; kv/kp real number (1 byte) + decimal fraction (1 byte) ;*** cr10 data buffer area *** ; %930 rvbcr10: ds 2 ; cr10 buffer reg low ;--- mode ntsc/mode pal for rom read --- mode ntsc equ 0 ; mode pal equ 2 ; mode lp equ 4 ; ntsc_pal: ds 1 ; for speed up ;*** intcr12 macro service data *** mcrarea dseg at 0fe0ch ;% rvscr12: ds 1 ; intcr12 macro service mode register rvccr12: ds 1 ; intcr12 macro service channel ; pointer rvmcmpp: ds 2 ;%intcr12 macro service compare area ; pointer rvb2cr12: ds 1 ; intcr12 macro service buffer area 2(l) rvb1cr12: ds 1 ; intcr12 macro service buffer area 1(h) rvbfreg: ds 1 ; intcr12 macro service buffer size reg rvmsfrp1: ds 1 ;%intcr12 macro service sfr pointer 1 rvmsfrp3: ds 1 ;%intcr12 macro service sfr pointer 3 rvmkeisu: ds 1 ;%intcr12 macro service keisu area rvmsfrp2: ds 1 ;%intcr12 macro service sfr pointer 2 rvmccr12: ds 1 ; intcr12 macro service counter rvmcmpd: ds 2 ;%intcr12 macro service compare area
chapter 8 program list 158 ptn_ff equ 70h ; %positive direction multiplier ; coefficient (0.4375) ptn_rew equ (ptn_ff xor 0ffh)+1 ; %reverse direction multiplier ; coefficient (0.5625) dt_cmp equ 0000h or 0001h ; %cr30 comparison data ; %viss ;--- for debug ---- %%%% deb dseg unit save_cnt: ds 2 ; save_area: ds 256 ; ;--- sp/lp/ep pal mode code ---- cvsp equ 00h ; sp mode cvslp equ 01h ; ep mode cvlp equ 02h ; lp mode cvpal equ 03h ; sp (pal) mode $ eject ;----------------------------- servo data table ;----------------------------- vtsrvo cseg unit ;//// 5% of maximum drum speed error amount //// tdf_5per: dw 022ch ; ntsc 1.3903ms / 125ns * 0.05 = 556.1 dw 029ah ; pal 1.6667ms / 125ns * 0.05 = 666.7 ;//// 10% of maximum drum speed error amount //// tdf_10per: dw 0458h ; ntsc 1.3903ms / 125ns * 0.1 = 1112.2 dw 0535h ; pal 1.6667ms / 125ns * 0.1 = 1333.3 ;//// drum speed gain //// tdf_kv: dw 011c2h ; ntsc 32767 / (0.23066ms / 125ns)= 17.76 dw 011c2h ; pal ;//// maximum drum speed error amount xx.xx //// tdf_max: dw 0735h ; ntsc 8388607 / 4546 = 1845.3 dw 0735h ; pal ;//// minimum drum speed error amount //// tdf_min: dw 10000h - 0735h ; ntsc dw 10000h - 0735h ; pal ;//// filter coefficient of drum speed (g) //// tdf_fg:
chapter 8 program list 159 dw 015fdh ; ntsc dw 015a0h ; pal ;//// filter coefficient of drum speed (ag) //// tdf_fag: dw 0f2a8h ; ntsc dw 0f22ch ; pal ;//// filter coefficient of drum speed (-b) //// tdf_fb: dw 0775ah ; ntsc dw 07832h ; pal ;//// drum phase gain //// tdp_kp: ; ntsc 32767 / (5.710ms / 125ns) = 0.717 dw 0fc40h ; ntsc %8/18 adjustment dw 0fc40h ; pal ;//// maximum drum phase error amount //// tdp_max: dw 2220h ; ntsc 8386607 / 0b7 = 45839.4 > 32767 dw 2220h ; ntsc ;//// minimum drum phase error amount //// tdp_min: dw 10000h - 2220h ; ntsc dw 10000h - 2220h ; pal ;//// filter coefficient of drum phase (g) //// tdp_fg: dw 006d2h ; ntsc dw 0086eh ; pal ;//// filter coefficient of drum phase (ag) //// tdp_fag: dw 0f987h ; ntsc dw 0f815h ; pal ;//// filter coefficient of drum phase (-b) //// tdp_fb: dw 07fa5h ; ntsc dw 07f7bh ; pal ;//// 10% of maximum capstan speed error amount //// tcf_10per: dw 0458h ; ntsc 2.7778ms / 125ns * 0.1 = 2222.2 dw 0c60h ; pal 3.9602ms / 125ns * 0.1 = 3668.2
chapter 8 program list 160 ; ;//// capstan speed gain //// ; ;tcf_kv, tcp_kp are given in table per mode. ;//// maximum capstan speed error amount //// tcf_max: dw 1e79h ; ntsc 8386607 / 433(1075) = 7801.5...4.2 dw 1e79h ; pal 8386607 / 433(1075) = 7801.5 ;//// minimum capstan speed error amount //// tcf_min: dw 10000h - 1e79h ; ntsc dw 10000h - 1e79h ; pal ;//// filter coefficient of capstan speed phase composite (g) //// tcmx_fg: dw 0205fh ; ntsc dw 01478h ; pal dw 01796h ; lp ;//// filter coefficient of capstan speed phase composite (ag) //// tcmx_fag: dw 0e0a1h ; ntsc dw 0ecdch ; pal dw 0e9c0h ; lp ;//// filter coefficient of capstan speed phase composite (-b) //// tcmx_fb: dw 07efeh ; ntsc dw 07ea9h ; pal dw 07ea9h ; lp ;//// maximum capstan phase error amount //// tcp_max: dw 15a0h ; ntsc 8386607 / 0bd5 = 2768.8 dw 15a0h ; pal 8386607 / 0bd5 = 2768.8 ;//// minimum capstan phase error amount //// tcp_min: dw 10000h - 15a0h ; ntsc dw 10000h - 15a0h ; pal ;//// filter coefficient of capstan phase control (g) //// fcp_fg: dw 01264h ; 01164h %% ; ntsc dw 010d8h ; pal ;//// filter coefficient of capstan phase control (ag) //// fcp_fag: dw 0ee74h ; ntsc dw 0eff1h ; pal
chapter 8 program list 161 ;//// filter coefficient of capstan phase control (Cb) //// tcp_fb: dw 07f57h ; ntsc dw 07f35h ; pal ;------- data store subroutine --------------------- ; for debug save_ax: xch b,!save_cnt add b, #2 movw save_area[b], ax xch b,!save_cnt ret $ eject vdfg cseg unit ;---------------------------------------------------- ; intcpt2 drum fg interruption process routine ;---------------------------------------------------- ; ; vpt2_000 : interruption initial processing ; vpt2_100 : drum speed error calculation ; vpt2_200 : drum phase error x loop gain (kp) ; vpt2_300 : drum speed error x loop gain (kv) ; vpt2_400 : drum speed adjustment amount + drum phase adjustment degree + bias value ; vpt2_500 : save capture value (next cpt2n - 1) ; vpt2_600 : processing after interruption ; ;---------------------------------------------------- ; interruption initial process ;---------------------------------------------------- vpt2_000 :;v :///// register setting ///////// sel rb2 vpt2_010: ;///// highest order interruption enable /// movw ax,mk0 ; save mask register push ax movw ax,mk1 ;%save mask register nop ;%%% push ax ;% or mk0l,#11101111b ;%intcr00 enable or mk0h,#01111100b ;%intp2, intcr02, intcr11 enable or mk1l,#11110111b ;%intcr13 enable ;%ctl or mk1h,#11111110b ;%intp3 enable ei set1 fsdfg ; set dfg edge detection flag
chapter 8 program list 162 movg rvcpt22,whl ; for debug %%% movg tde,rvdfrf ; limit the maximum value addg tde,#7fffh ; subg tde,whl ; set the maximum value to 7fffh + target value bh $vpt2_101 ; addg whl,tde ; vpt2_101 : vpt2_110 : ;///// e dv calculation /////////// subg whl,rvdfef ; e dv = d ndf C ndfl ; drum speed error = measured speed C target speed vpt2_120 :;b ;///// get error amount ///////// movw ax,hl ; absolute value calculation bf a.7,$vpt2_128 ; movw hl,#0 ; subw hl,ax ; hl ? absolute value vpt2_128 : movw vp,ax ; vp ? error amount mov a,rvfsrv_2 and a,#00000011b ; read run mode mov b,#mode ntsc ; cmp a,#cvpal ; pal? bne $vpt2_129 ; no mov b,#mode pal ; vpt2_129 : mov ntsc pal,b ; store ntsc = 0/pal = 2 vpt2_130 :;b ;///// check error amount 5% /// movw ax, tdf_5per[b] ; ; dw 022ch ; ; dw 029ah ; cmpw hl,ax ; bc $vpt2_140 ; movw rverdp_1,#0000h ;% movw rverdp_y,#0000h ; drum phase error ? 0000h movw rverdp_by,#0000h ;%
chapter 8 program list 163 movw rverdp_by+2,#0000h ;% vpt2_140 :;b ;///// check error 10% /// movw ax,tdf_10per[b] ; ; dw 0458h ; ; dw 0535h ; vpt2_140_10 : cmpw ax,hl ; mov1 fvdfe10,cy ; set flag if drum speed error is 10% or more vpt2_150 :;b ;///// check maximum error value /// movw ax,tdf_max[b] ; limit maximum value of drum speed error ; dw 0735h ; ; dw 0735h ; cmpw ax,hl ; maximum value: drum speed error bnc $vpt2_160 ; >= cmpw vp,#8000h ; sign bc $vpt2_151 ; cy = 1 positive number ; cy = 0 negative number movw ax,tdf_min[b] ; minimum value: drum speed error ; dw 10000h-0735h ; ; dw 10000h-0735h ; vpt2_151 :;b movw vp,ax ; vpt2_160 :;b ;///// save speed error /////// xchw vp,rverdf ; rverdf ? error amount of this time movw rverdf_1,vp ; rverdf_1 ? error amount of last time
chapter 8 program list 164 ;--------------------------------------------------------------------------------- ; lag read filter processing ;--------------------------------------------------------------------------------- ; ; 0. set filter coefficient ; ; ntsc: ;f1= 8 ;f2= 56 calculation from ; dfg = 719.28hz ; ; mal a = C0.60695401 ; mbl b = C0.93247632 ; mgl g = 0.17179585 ; ; pal: ;f1= 6 ;f2= 42 calculation from ; dfg = 600.00hz ; ; mal a = C0.63946320 ; mbl b = C0.93908194 ; mgl g = 0.16896488 ; ; ---------------------------------------------------------------------------------- vpt2_170 : ;///// set filter coefficient /// mov b,ntsc_pal ; movw ax,tdf_fg[b] ; movw b_buf,ax ; movw ax,tdf_fag[b] ; movw b_buf+2,ax ; movw ax,tdf_fb[b] ; movw b_buf+4,ax ; ;///// filter calculation processing /// mov b,#low(b_buf) ; mov c,#low(rverdf) ; movw de,rverdf_by ; movw ax,rverdf_by+2 ; macsw 2 ; lag read filter processing movw rverdf_y,ax ; drum speed error amount (after filter calculation) movw de,b_buf+4 ; mulw de ; shlw de,1 ; rolc x,1 ; rolc a,1 ; movw rverdf_by,de ; (Cb)?y movw rverdf_by+2,ax ;
chapter 8 program list 165 ;--------------------------------------------------------------------------------- ; drum phase error x loop gain (kp) ;--------------------------------------------------------------------------------- ; ; 0. get kp (decimal fraction is ignored) ; ; ntsc kp = C3.75 real number : 0fc40h ; ; pal kp = C3.75 real number : 0fc40h ; ; 1. phase error x loop gain ; ; hl ? hl + ax ; ;--------------------------------------------------------------------------------- vpt2_200 : ;///// get kp /////////// mov b,ntsc_pal ; movw ax,tdp_kp[b] ; ; dw 11c2h ; ; dw 11c2h ; ;///// error x kp //////// movw de,rverdp_y ; drum phase error amount (after filter calculation) mulw de ; cmpw ax,#0ff80h ; zero check bnc $vpt2_230 ; cmp a,#80h ; bnc $vpt2_229 ; underflow cmpw ax,#0080h ; bc $vpt2_230 movw ax,#7fffh ; 7fffh ? overflow br vpt2_231 ; vpt2_229 : movw ax,#8000h ; 8000h ? underflow br vpt2_231 ; vpt2_230 : mov a,x ; a(xd)e mov x,d ; vpt2_231 : movw hl,ax ; hl ? drum phase error amount (after gain addition) vpt2_220 :
chapter 8 program list 166 ;--------------------------------------------------------------------------------- ; drum speed error x loop gain (kv) ;--------------------------------------------------------------------------------- ; ; 0. get kv (decimal fraction is ignored) ; ; ntsc kv = 17.76 real number : 11c2h ; ; pal kv = 17.76 real number : 08e1h ; ; 1. speed error x loop gain ; ; ax ? ax + de ; ;;-------------------------------------------------------------------------------- vpt2_300 :;b ;///// get kv /////////// mov b,ntsc_pal ; movw ax,tdf_kv[b] ; ;///// error x kv //////// movw de,rverdf_y ; drum speed error amount (after filter operation) mulw de ; ax ? drum speed error amount (after gain addition) mov a,x ; a(xd)e mov x,d ; ;--------------------------------------------------------------------------------- ; drum speed adjustment + drum phase adjustment + bias value ? pwm 0 ;--------------------------------------------------------------------------------- ; vpt2_400 :;b ;///// speed total + bias + phase total gain ///// addw ax,hl ; drum phase error addition bnv $vpt2_411 ; movw ax,#07fffh ; 7fffh ? overflow addc x,#0 ; addc a,#0 ; 8000h ? underflow vpt2_411 : bt a.7,$vpt2_412 ; addw ax,rvdbas ; bias addition (<7fff) br vpt2_420 ; vpt2_412 : addw ax,rvdbas ; bias addition (<7fff) bc $vpt2_420 ; movw ax,#0000h ; 0000h ? overflow
chapter 8 program list 167 vpt2_420 :;b ;///// pwm 0 output ////////// ;v% pwm limitation items cmpw ax,#0100h bc $vpt2_421 cmpw ax,#0ff00h bnh $vpt2_422 movw ax,#0ff00h br vpt2_422 vpt2_421 : movw ax,#0100h vpt2_422 : ;^% pwm limitation items movw pwm0,ax ; set drum pwm data ;--------------------------------------------------------------------------------- ; save capture value (next cpt2n - 1) ;--------------------------------------------------------------------------------- vpt2_500 : ;///// save cpt2 /////// movg rvcpt2,uup ; ;--------------------------------------------------------------------------------- ; processing after interrupt ;--------------------------------------------------------------------------------- vpt2_600 : ;///// multiple interrupt disable ///// di pop ax ; %return mask register movw mk1,ax ; %set mask register pop ax ; return mask register mov1 cy,crmk02 ; load intcr0 2 interrupt mask flag mov1 a.0,cy ; save intcr0 2 interrupt mask flag mov1 cy,pmk2 ; %load intp 2 interrupt mask flag mov1 a.7,cy ; %save intp 2 interrupt mask flag movw mk0,ax ; set mask register vpt2_ext : reti $ eject vdpgp cseg unit
chapter 8 program list 168 ;--------------------------------------------------------------------------------- ; intcr10 drum phase error detection interruption processing ;--------------------------------------------------------------------------------- ; ; vr10_000 : interrupt initial processing ; vp10_100 : calculation of phase control target value ; vp10_200 : calculation of drum phase error ; vp10_300 : lag read filter processing ; vp10_400 : processing after interrupt ; ;--------------------------------------------------------------------------------- ; interrupt initial processing ;--------------------------------------------------------------------------------- vr10_000 :;v ;///// register setting ///////// sel rb2 ; high-order interrupt vr10_010 : ;///// read cpt0 //// movw ax,cpt0l ; movw hl,ax ; mov a,cpt0h ; mov w,a ; movg uup,whl ; vr10_020 : ;///// drum on check /// bt fsdrmon,$vr10_030 reti vr10_030 :;b ;///// check speed error ///// bf fvdfe10,$vr10_040 ; 10% or more drum speed error? no reti ; yes interrupt end vr10_040 :;b ;///// high-order interrupt enable /// movw ax,mk0 ; save mask register push ax movw ax,mk1 ;%save mask register nop ; %%% push ax ;% or mk0l,#11101111b ;%intcr00 enable or mk0h,#01111100b ;%intp2, intcr02, intcr11 enable or mk1l,#11110111b ;%intcr13 enable ;%ctl or mk1h,#11111110b ;%intp3 enable ei
chapter 8 program list 169 ;--------------------------------------------------------------------------------- ; calculation of phase control target value ;--------------------------------------------------------------------------------- ; ; <1> digital value equal to hsw pulse delay amount ; ; cr00 x 4 times (difference between timer 0 and frc clock frequency) ; ; <2> delay amount for half cycle of frame ; ; cr10 value ; ; <3> delay amount for 6.5 hrs ; ; 6.5 hrs (0.41 msec) ? 125 ns (frc clock) = 616d ; ; <4> delay amount for vsync separation ; soft execution time ? 125 ns (frc clock) ; ;--------------------------------------------------------------------------------- vr10_100 : ;///// phase target value calculation /////// ; set minimum unit to 0.500 us movg whl,#0 ; movw hl,cr00 ; cr00*2 shlw hl,1 ; addw hl,cr10 ; + cr10 addg whl,#0355h ; + (<3> + <4>) 413.14 + 13.5 ; = 426.64 m s (853) movg vvp,whl ; vvp ? phase target value ;--------------------------------------------------------------------------------- ; drum phase error calculation ;--------------------------------------------------------------------------------- ; ; 0. phase error calculation ; ; edp = [(cpt0 value) C (cpt1 value)] C ndpl ; ; edp :drum phase error amount ; ndpl :phase control target value ; ; mcpt1 :capture value of internal hsw falling edge only ; mcpt0 :capture at cr10 match ; ; 1. check phase error maximum value ; ; assume ntsc error 3 06b1h ? error = 06b1h (maximum) ; ; assume pal error 3 06b1h ? error = 06b1h (maximum) ; ;---------------------------------------------------------------------------------
chapter 8 program list 170 vr10_200 : ;///// phase error calculation ///////// movg whl,uup ; (mcpt0 C mcpt1) movg rvcpt0,whl ; subg whl,rvcpt1 ; drum phase error mov a,w ; divide drum phase error into 1/2 and a,#03fh ; shr a,1 ; ;%% mov w,a ; rorc h,1 ; rorc l,1 ; shr a,1 ;%% mov w,a ;%% rorc h,1 ;%% rorc l,1 ;%% mov b,ntsc_pal ; limit maximum value movw ax,tdp_max[b] ; mov t,#0 ; movw de,ax ; addg tde,vvp ; set maximum value to target + maximum limitation value subg tde,whl ; bh $vr10_201 ; addg whl, tde ; vr10_201 : subg whl,vvp ; drum phase error C ; e dp (target value of drum phase error) bnc $vr10_220 ; is error amount negative value? ;///// check maximum error value /// ; negative value ;; mov b,ntsc_pal ; mov t,#0ffh ; less than minimum value? movw ax,tdp_min[b] ; movw de,ax ; subg tde,whl ; minimum value C error amount bc $vr10_220 ; movw hl,ax ; vr10_220 : xchw hl,rverdp ; rverdp ? drum phase error of this time movw rverdp_1,hl ; rverdp_1 ? drum phase error of last time
chapter 8 program list 171 ;--------------------------------------------------------------------------------- ; lag read filter processing ;--------------------------------------------------------------------------------- ; ; 0. set filter coefficient ; ; ntsc: ; f1 = 0.013hz ; f2 = 0.25 hz calculation from ; dpg = 30hz ; ; mal a = C0.94897592 ; mbl b = C0.99728098 ; mgl g = 0.05328881 ; ; pal: ; f1 = 0.016hz ; f2 = 0.25 hz calculation from ; dpg = 25hz ; ; mal a = C0.93908194 ; mbl b = C0.99598683 ; mgl g = 0.06587816 ; ;;-------------------------------------------------------------------------------- vr10_300 :;b ;///// set filter coefficient /// mov b,ntsc_pal ; movw ax,tdp_fg[b] ; movw b_buf,ax ; movw ax,tdp_fag[b] ; movw b_buf+2,ax ; movw ax,tdp_fb[b] ; movw b_buf+4,ax ; vr10_310 :;b ;///// filter calculation processing ///// mov b,#low(b_buf) ; mov c,#low(rverdp) ; movw de,rverdp_by ; movw ax,rverdp_by+2 ; macsw 2 ; movw rverdp_y,ax ; drum phase error amount (after filter calculation) movw de,b_buf+4 ; vr10_yl equ 13fh bt a.7,$vr10_312 ;;;;; maximum limitation processing yn C 1 cmpw ax,#vr10_yl ; positive number bc $vr10_314 ; movw ax,#vr10_yl ; br vr10_314
chapter 8 program list 172 vr10_312 : cmpw ax,#10000h - vr10_yl ; negative number bnc $vr10_314 ; movw ax,#10000h - vr10_yl ; vr10_314 : ;;;;; mulw de ; shlw de,1 ; rolc x,1 ; rolc a,1 ; movw rverdp_by,de ; (Cb)?y movw rverdp_by+2,ax ; ;--------------------------------------------------------------------------------- ; cr10 revision processing ;--------------------------------------------------------------------------------- vr10_320: movw ax,rvbcr10 ; cr10 ? cr10 data buffer area movw cr10,ax ; ; note: when write cr10, perform in ; intcr10 routine. (unless, tm1 ; may overflow depending on timing ; of writing!) ;--------------------------------------------------------------------------------- ; processing after interrupt ;--------------------------------------------------------------------------------- vr10_400 : ;///// multiple interrupt disable ///// di pop ax ; %return mask register movw mk1,ax ; %set mask register pop ax ; return mask register mov1 cy,crmk02 ; load intcr02 interrupt mask flag mov1 a.0,cy ; save intcr02 interrupt mask flag mov1 cy,pmk2 ; %load intp2 interrupt mask flag mov1 a.7,cy ; %save intp2 interrupt mask flag movw mk0,ax ; set mask register vr10_ext : reti $ eject vcfg cseg unit
chapter 8 program list 173 ;--------------------------------------------------------------------------------- ; intcpt3 capstan fg interrupt ;--------------------------------------------------------------------------------- ; ; vrt3_000 : interrupt initial processing ; vrt3_100 : pbctl signal missing detection ; vrt3_200 : capstan speed error calculation ; vrt3_300 : error amount calculation special processing ; vrt3_400 : speed error x loop gain (kv/kp) ; vrt3_500 : capstan speed adjustment amount + capstan phase ; adjustment amount ; vrt3_600 : mix error amount digital filter processing ; vrt3_700 : capstan speed/phase mix (yn) x gain adjustment ; vrt3_800 : capstan speed/phase mix adjustment value + bias value ; vpt3_900 : capstan pwm output ; vrt3_a00 : processing after interrupt ; ;--------------------------------------------------------------------------------- ; interrupt initial processing ;--------------------------------------------------------------------------------- vpt3_000 :;v ;///// register setting ///////// sel rb2 ; high order interrupt vpt3_010 : ;///// multiple interrupt enable //// movw ax,mk0 ; save mask register push ax movw ax,mk1 ;%save mask register nop ;%%% push ax ;% or mk0l,#11101111b ;%intcr00 enable or mk0h,#01111100b ;%intp2,intcr02, intcr11 enable or mk1l,#11110111b ;%intcr13 enable ;%ctl or mk1h,#11111110b ;%intp3 enable ei vpt3_015 : ;///// check cfg 90 pulse counter //// cmp rscfg90c,#00 bz $vpt3_100 dec rscfg90c ;--------------------------------------------------------------------------------- ; increment play run mode automatic judgment counter ; ; pbctl signal missing detection ;--------------------------------------------------------------------------------- vpt3_100 : inc rvcevfg ; cfg counter increment @@@ change
chapter 8 program list 174 vpt3_110 : bt fsmdchg,$vpt3_200 ; at transition? yes vpt3_130 : cmp rvcevfg,#40 ; pbctl signal missing? @@@ change bc $vpt3_200 ; no vpt3_140 : bt fvphfx,$vpt3_141 ;%ph fix on? yes (ff/rew) ;%ctl set1 fvflctl ; set pbctl signal missing flag vpt3_141 : ;%ctl mov rvcevfg,#00 ; clear play mode judgment counter ;@@@ ; change ;%ctl v ;% ;%% ctl amp gain inc(+5) ;% amplify ctl amp gain by +5 during pbctl signal missing mov a,ctlm ;% add a,#05h ;% cmp a,#1fh ;% bc $vpt3_150 ;% mov a,#1fh ;% vpt3_150 :;b ;% mov ctlm.a ;% ;%ctl ^ ;----------------------------------------------------------------------- ; calculate capstan speed error ;----------------------------------------------------------------------- ; ; d ncf = cpt3n C cpt3n-1 ; ; d ncf: capture value of this time C capture value of last time ; ; ecv = d ncf C ncfl ; ; ecv : capstan speed error amount ; ncfl : capstan speed target value ;----------------------------------------------------------------------- vpt3_200 :;b movw ax,cpt3l ; movw hl,ax ; mov a,cpt3h ; mov w,a ; movg uup,whl ; subg whl,rvcpt3 ; d ncf = cpt3n C cpt3n-1 mov a,w ; and a,#003fh ; mov w,a ; movg vvp,whl ; subg whl,#12c0h ; check capstan abnormal high speed rotating bnc $vpt3_201 ; cfg is within 600 m sec?
chapter 8 program list 175 movw ax,#1fffh ; yes br vpt3_820 ; to avoid occurring cfg frequent interrupt ; due to motor runaway, ; and micro controllers runaway vpt3_201 :;b movg whl,vvp ; movg tde,rvcfrf ; limit maximum value addg tde,#7fffh ; subg tde,whl ; set maximum value to 7fffh + target value bh $vpt3_202 ; addg whl,tde ; vpt3_202 : subg whl,rvcfrf ; ecv = d ncf C ncfl movw ax,hl ; calculation of absolute value bf a.7,$vpt3_203 ; negative value? movw hl,#0 ; subw hl,ax ; hl ? absolute value vpt3_203 : movw vp,ax ; vp ? error amount ;-------------------------------------------------------------------------- ; error amount calculation special processing ;-------------------------------------------------------------------------- ; ; when set capstan phase error amount to 0 ; ; ? when drum speed error amount is more than 10% ; ; flag more than 10%: fsdp10=1 ; ; ? when capstan speed error amount is more than 10% ; ; error amount is calculated by ntsc/pal play target value. ; ; ntsc5% : 56ceh x 0.10 = 0458h ; pal 5% : 7bc1h x 0.10 = 0c60h ; ; ? when pbctl signal missing is detected in play ; ? at ff/rew mode ; ? when capstan phase servo disabled (during loading) ; ;-------------------------------------------------------------------------- vpt3_300 :;b mov a,rvfsrv_2 and a,#00000011b ; read run mode mov b,#mode ntsc ; cmp a,#cvpal ; pal? bne $vpt3_321 ; no
chapter 8 program list 176 mov b,#mode pal ; vpt3_321 : mov ntsc_pal,b ; movw ax,tcf_max[b] ; less than maximum value? ; dw 1e79h ; dw 1e79h cmpw hl,ax ; error amount (absolute value): ; maximum value bc $vpt3_320 ; =< cmpw vp,#8000h ; sign bc $vpt3_311 ; cy=1 positive ; cy=0 negative movw ax,tcf_min[b] ; vpt3_311 : movw vp,ax ; set maximum value as speed error amount vpt3_320 :;b movw rvercf,vp ; capstan speed error movw ax,tcf_10per[b] ; ; dw 0458h ; ; dw 0c60h ; clr1 fvcfe05 ; cmpw ax,hl ; bnc $vpt3_330 ; set1 fvcfe05 ; br vpt3_340 ; vpt3_330 :;b bt fvphfx,$vpt3_340 ; ph fix on? yes(ff/rew) bt fvdfe10,$vpt3_340 ; is drum speed error more than 10%? yes bf fvflctl,$vpt3_400 ; pbctl signal missing? no vpt3_340 :;b ;///// phase error amount to 0 ////// movw rvercp_y,#0 ; capstan phase error ? 0000h movw rvercp,#0 ; movw rvercp_1,#0 ; movw rvercp_by,#0 ; capstan phase filter movw rvercp_by+2,#0 ; clear memory
chapter 8 program list 177 ;---------------------------------------------------------------------- ; capstan speed error x loop gain (kv/kp) ;---------------------------------------------------------------------- ; ; ax ? ax + de ;---------------------------------------------------------------------- vpt3_400 :;b movw ax,rvercf ; capstan speed error movw de,rvc_kvp ; speed phase error mix rate mulw de ; a(xd)e mov a,x ; 8 bits shift (set valid only 16 bits) mov x,d ; ;---------------------------------------------------------------------- ; capstan speed adjustment amount + capstan phase adjustment amount ;---------------------------------------------------------------------- movw de,rvercp_y ; capstan phase error shlw de,2 ; %%% 3 addw ax,de ; capstan speed error amount + capstan ; phase error bnv $vpt3_511 ; movw ax,#7fffh ; addc x,#0 ; 7fffh ? overflow addc a,#0 ; 8000h ? underflow vpt3_511 : xchw ax,rvercmx ; capstan speed phase mix error movw rvercmx_1,ax ; ;---------------------------------------------------------------------- ; speed/phase mix error amount digital filter processing ;---------------------------------------------------------------------- ; ; 0. set filter coefficient ; ; ntsc sp/ep ; f1 = 0.45 hz ; f2 = 1.8 hz calculation from ; cfg = 360 hz ; ; mal a = C0.96906992 ; mbl b = C0.99217674 ; mgl g = 0.25293372 ; ; ntsc lp ; f1 = 0.45 hz ; f2 = 2.5 hz calculation from ; cfg = 270 hz ; ; mal a = C0.94346684 ; mbl b = C0.98958257
chapter 8 program list 178 ; mgl g = 0.18427114 ; ; pal sp ; f1 = 0.42 hz ; f2 = 2.7 hz calculation from ; cfg = 252.51 hz ; mal a = C0.93499961 ; mbl b = C0.98960350 ; mgl g = 0.15994518 ; ; vpt3_600 :;b vpt3_610 : ;///// run mode judgment //////// mov b,ntsc_pal ; mov a,rvfsrv_2 ; and a,#00000011b ; read run mode cmp a,#cvlp ; lp? bne $cpt3_611 ; mov b,#mode lp ; ;b ? ntsc(0)/pal(2)/lp(4) cpt3_611 : movw ax,tcmx_fg[b] ; movw b_buf,ax ; movw ax,tcmx_fag[b] ; movw b_buf+2,ax ; movw ax,tcmx_fb[b] ; movw b_buf+4,ax ; mov b,#low(b_buf) ; mov c,#low(rvercmx) ; movw de,rvercmx_by ; movw ax,rvercmx_by+2 ; macsw 2 ; movw rvercmx_y,ax ; y movw de,b_buf+4 ; mulw de ; shlw de,1 ; rolc x,1 ; rolc a,1 ; movw rvercmx_by,de ; (Cb)?y movw rvercmx_by+2,ax ;
chapter 8 program list 179 ;---------------------------------------------------------------------- ; capstan speed/phase mix (yn) x gain adjustment ;---------------------------------------------------------------------- ; ; ax ? ax + de ;---------------------------------------------------------------------- vpt3_700: movw ax,rvc_kmp ; movw de,rvercmx_y ; mulw de ; a(xd)e cmpw ax,#0ff80h ; zero check bnc $vpt3_730 ; cmp a,#80h ; bnc $vpt3_729 ; underflow cmpw ax,#0080h ; bc $vpt3_730 movw ax,#7fffh ; 7fffh ? overflow br vpt3_731 ; vpt3_729 : movw ax,#8000h ; 8000h ? underflow br vpt3_731 ; vpt3_730 : mov a,x ; 8-bit shift (only for 16-bit) mov x,d ; vpt3_731 : ;---------------------------------------------------------------------- ; capstan speed/phase mix adjustment value + bias value ;---------------------------------------------------------------------- vpt3_800 :;b ; swbias8 equ 0 ; bias is less than 8000h swbias8 equ 1 ; bias is 8000h or more $_if(swbias8) ; add processing at bias (=> 8000h) bf a.7,$vpt3_812 ; addw ax,rvcbas ; negative number before adding br vpt3_820 ; vpt3_812 : addw ax,rvcbas ; when positive number before adding ; overflow may occur bnc $vpt3_820 ; movw ax,#0ffffh ; 0ffffh ? overflow
chapter 8 program list 180 $else ; add processing at bias (=< 7fffh) bf a.7,$vpt3_812 ; addw ax,rvcbas ; when negative number before adding ; underflow may occur bc $vpt3_820 ; movw ax,#0000h ; 0000h ? underflow br vpt3_820 ; vpt3_812 : addw ax,rvcbas ; positive number before adding $endif ;--------------------------------------------------------------------------------- ; capstan speed level judgment at ff/rew ;--------------------------------------------------------------------------------- vpt3_820 :;b movw bc,ax ; save pwm output data mov a,rvsrvcd and a,#11110000b ; clear low-order 4 bits cmp a,#cvffrew ; ff/rew? bne $vpt3_830 ; no mov a,rvercf ; capture high-order byte of capstan ; speed adjustment bt a.7,$vpt3_823 ; is capstan speed adjustment amount (C)? ;no ; %%% modification is required vpt3_821 : cmp a,#2 bc $vpt3_823 ; c-err 0h - 1ffh cmp a,#6 bc $vpt3_822 ; c-err 200h - 5ffh ; c-err 600h - max mov a,#0 ; level 0 br $vpt3_824 vpt3_822 : mov a,#1 ; level 1 br $vpt3_824 vpt3_823 : mov a,#2 ; level 2 vpt3_824 : mov rsfrsped,a ; capstan ff/rew speed level set movw bc,#0ffffh ; pwm output full vpt3_830 :;b movw ax,bc ; pwm output data return
chapter 8 program list 181 ;--------------------------------------------------------------------------------- ; capstan pwm suppression control at play ? review ;--------------------------------------------------------------------------------- vpt3_840 : movw bc,ax ; save pwm output data mov a,rvsrvcd and a,#11110000b ; clear low-order 4 bits cmp a,#cvfr6hvd ; 6hrs play? (at spin off rf gear) be $vpt3_841 ; yes cmp a,#cvrvs ; rvs play? (at reverse play) bne $vpt3_842 ; no vpt3_841 : movw ax,bc ; cmpw ax,#0b333h ; capstan pwm 0b333h (3.5 v) or higher? bc $vpt3_842 ; movw bc,#0b333h ; pwm output 3.5 v vpt3_842 : movw ax,bc ; pwm output data return ;--------------------------------------------------------------------------------- ; output capstan pwm ;--------------------------------------------------------------------------------- vpt3_900 :;b ;v%pwm limitations cmpw ax,#0100h bc $vpt3_901 cmpw ax,#0ff00h bnh $vpt3_902 movw ax,#0ff00h br vpt3_902 vpt3_901 : movw ax,#0100h vpt3_902 : ;^%pwm limitations movw pwm1,ax ; set capstan pwm data ;///// save cpt3 /////// movg rvcpt3,uup ; ;--------------------------------------------------------------------------------- ; multiple interruption prohibited ;--------------------------------------------------------------------------------- vpt3_a00 : di pop ax ; %return mask register movw mk1,ax ; %set mask register
chapter 8 program list 182 pop ax ; return mask register mov1 cy,crmk02 ; load intcr02 interrupt mask flag mov1 a.0,cy ; save intcr02 interrupt mask flag mov1 cy,pmk2 ; %load intp2 interrupt mask flag mov1 a.7,cy ; %save intp2 interrupt mask flag movw mk0,ax ; set mask register reti ; capstan fg interrupt processing end ;%%%ctl v $ nolist $ subtitle(srv0.asm : intcr13 routine ctl detection & output interruption) $ list $ eject vctl cseg unit ;--------------------------------------------------------------------------------- ; intcr13 ctl detection & output interrupt ;--------------------------------------------------------------------------------- ; vr13_000 : interrupt initial processing ; vr13_100 : ctl detection & output interrupt processing ;--------------------------------------------------------------------------------- ; interrupt initial processing ;--------------------------------------------------------------------------------- vr13_000 :;v ;///// register setting ///////// sel rb3 ; highest-order interrupt!! vr13_100 : ;********************************************************************************* ; gain control ;********************************************************************************* ; rewrite gain at play and cue/rev call !gainadj ; ctl amp gain adjust set1 crmk13 ; intcr13 interrupt disable reti ; ;*************************** ; gain adjust subroutine ;*************************** gainadj : mov a,ampmo ; set1 flgclr ; ctl flag clear mov1 cy,a.3
chapter 8 program list 183 xor1 cy,a.1 bc $gain_e ; mov x,ctlm and x,#00011111b ; bf a.3,$gain_up cmp x,#0 ;down bz $gain_e dec x br gainset gain_up : ;up cmp x,#1fh bz $gain_e inc x gainset : mov ctlm,x gain_e : ret ; ;%%%ctl ^ $eject vcpg cseg unit ;------------------------------------------------------ ; intcr12 capstan phase error detection interrupt ; at play: interrupt by pbctl signal ;------------------------------------------------------ ; vr12_000 : interrupt initial processing ; vr12_020 : viss signal detection processing ; vr12_200 : play run mode automatic judgment processing ; vr12_300 : capstan phase error calculation ; vr12_400 : lag read filter processing ; vr12_500 : pbctl signal missing check ; vr12_600 : processing after interrupt ; vr12_t00 : run mode judgment table ;------------------------------------------------------ ; interruption initial processing ;------------------------------------------------------ vr12_000 :;v ;///// register setting ///////// sel rb2 ; high-order interrupt vr12_010 : ;///// highest-order interrupt enable /// movw ax,mk0 ; save mask register push ax movw ax,mk1 ;%save mask register nop ; %%% push ax ;% or mk0l,#11101111b ;%intcr00 enable or mk0h,#01111100b ;%intp2, intcr02,
chapter 8 program list 184 ; intcr11 enable or mk1l,#11110111b ;%intcr13 enable ;%ctl or mk1h,#11111110b ;%intp3 enable ei ; vr12_020 : ;///// macro service //////// cmp rvmccr12,#00h ; is msc interrupting with 0? bne $vr12_032 ; no cmpw rvb2cr12,#dt_cmp ; are buffer 1 and 2 comparison area ; information? be $vr12_032 ; yes mov rvmccr12,rvcram ; set macro service counter value set1 crism12 ; set intcr12 macro service interrupt br vr12_120 ;% ; vr12_032 :;b mov rvmccr12,rvcram ; set macro service counter value set1 crism12 ; set intcr12 macro service interrupt vr12_040 : ; /// search mode check /// ;% bf fscapon,$vr12_111 ; capstan on? bf fnstena,$vr12_111 ; search detect di? (150 msec) ; mov a,rvsrvcd and a,#11110000b ; clear low-order 4 bits cmp a,#cvffrw6h ; at ff/rew start? bne $vr12_045 ; no br !vr12_111 ; disable viss! ; vr12_045 :;b cmp rsnow,#csmplay ; during play? be $vr12_050 ; yes ;no cmp rsnext,#csmplay ; bne $vr12_060 ;%a no br vr12_111 ;%a yes ; vr12_050 :;b bt fsvm0frq,$vr12_111 ; v_mute off?(1 pulse detection?) bf pqvd,$vr12_111 ; ;;no vr12_060 :;b bt fsvissi,$vr12_100 ; index search mode? bt fsvisso,$vr12_100 ; once more search mode? bf fsvissme,$vr12_111 ; mark/erase mode? ; yes vr12_100 :;b ; /// viss ok /// ;% set1 fsvissok ; set viss signal detection flag!! vr12_111 :;b ;% /// buffer area clear /// ;%
chapter 8 program list 185 movw rvb2cr12,#0ffffh ;%buffer area 1,2 clear ; (reverse/forward all 1 clear) vr12_120 :;b ; /// counter flag clear /// ;% bf fsvistr,$vr12_121 clr1 fsvistr ; clear viss signal detection start flag!! clr1 fsvissok ; clear viss signal detection flag!! movw rvb2cr12,#0ffffh ;%buffer area 1,2 clear ; (reverse/forward all 1 clear) ; /// set coefficient multiplied by cr30 at macro service /// ;% vr12_121 :;b mov a,#ptn_rew ;% (reverse) bt pcapfwd,$vr12_122 ;% capstan forward or reverse ? mov a,#ptn_ff ;% (forward) vr12_122 :;b ;% mov rvmkeisu,a ;% ;%viss ^ $ eject ;%%%ctl v ;-------------------------------------------------- ;-- determine ctl amp gain setting position ;-------------------------------------------------- vr12_a000: clr1 intm1.4 ;%a (reverse) pbctl: edge bt pcapfwd,$vr12_a00 ;%a capstan forward or reverse ? set1 intm1.4 ;%a (forward) pbctl: - edge vr12_a00 :;b ; bt fsmdchg,$vr12_a10 ; at transition? yes mov a,rvsrvcd and a,#11110000b ; clear low-order 4 bits cmp a,#cvffrew ; ff/rew ? bne $vr12_a01 ; no ; /// cr13 comparator update (ff/rew) /// ;% movw ax,cpt30 ; load pbctl capture data movw bc,#0133h ;%(reverse) cpt30 x 1.2 ; ...(256 x 1.2) bt pcapfwd,$vr12_a05 ; capstan forward or reverse ? movw bc,#01cdh ;%(forward) cpt30 x 1.8 ; ...(256 x 1.8) vp12_a05 :;b ; muluw bc ; cpt30 x *** mov a,x ; ax ? xb mov x,b ; br vr12_a04 ; ; ; ;
chapter 8 program list 186 ; /// cr13 comparator update (play, cue/rev) /// vr12_a01 :;b movw ax,cpt30 ; load pbctl capture data movw bc,#4ccdh ;%(reverse) cpt30 x 0.3 ; ...(65536 x 0.3) bt pcapfwd,$vr12_a02 ; capstan forward or reverse ? movw bc,#0b333h ;%(forward) cpt30 x 0.7 ; ...(65536 x 0.7) vr12_a02 :;b muluw bc ; cpt30 x *** vr12_a04 :;b addw ax,cr12 ; (cpt30 x ***) + cr12 cmpw ax,cr10 ; bc $vr12_a03 ; subw ax,cr10 ; vr12_a03 : movw cr13,ax ; cr13 update clr1 crif13 ; clear intcr13 interrupt request clr1 crmk13 ; enable intcr13 interrupt vr12_a10 :;b ;%%%ctl ;-------------------------------------------------- ;-- viss mark/erase ;-------------------------------------------------- call !sr12_000 ; viss mark/erase ;///// servo mode judgment /////// mov a,rvsrvcd and a,#11110000b ; clear low-order 4 bits bf fvphfx,$vr12_200 ; ph fix on? no br vr12_500 ; yes (ff/rew) $ eject ;-------------------------------------------------- ; play run mode automatic judgment processing ;-------------------------------------------------- ; ; run mode is judged by the count number ; of capstan fg signals after the event divider division ; that is input into one cycle of pbctl. ; ; vr12_200 :;b bf fvcfe05,$vr12_210 ; capstan speed error is more than 5%? br vr12_2b0 ; yes vr12_210 :;b movg whl,#vr12_t00 ; %refer to table
chapter 8 program list 187 mov a,rvcevfg ; run mode judgement cfg counter movw bc,#0900h ; counter initialization vr12_220 :;b cmp a,[hl] bnl $vr12_230 ; >= inc a ; +1 check cmp a,[hl] bne $vr12_2b0 ; not match vr12_230 :;b be $vr12_240 ; = incw hl ; set next data inc c ; set pulse type counter +1 dbnz b,$vr12_220 ; check complete? no br $vr12_2b0 ; yes vr12_240 :;b mov a,rvslpch ; judgment chattering counter and a,#0fh ; read back up data xch a,c cmp a,c ; match? be $vr12_250 ; yes mov rvslpch,a ; initialize br vr12_2c0 vr12_250 :;b add rvslpch,#10h ; judgment chattering counter ; h increment cmp rvslpch,#30h ; chattering absorption complete? bc $vr12_2c0 ; no ; yes vr12_260 : ;//// run mode set /////// xch a,c ; store pulse type counter mov a,rvfsrv_2 ; get run mode and a,#3 add a,a mov b,a movw ax,ttvr12_speed[b] mov b,#0 addw ax,bc movw hl,ax vr12_262 : mov a,[hl] cmp a,#03 ; change to pal mode
chapter 8 program list 188 bne $vr12_264 ; no bf fhifim,$vr12_264 ; pal mode ? yes br vr12_2b0 ; no mode change vr12_264 :;j mov a,rvfsrv_2 and a,#0fch or a,[hl] xch a,rvfsrv_2 ; set mode xor a,rvfsrv_2 and a,#03 be $vr12_2b0 ; no mode change vr12_270 : call !yvtbl_00 ; refer to set servo code & refer to table vr12_280 : callf !ysa01_r1 ; 1sec timer start for auto-tracking clr1 fsaend ; one auto-tracking end ; clear flag set1 fsspdchg ; set mark/erase release request flag vr12_2b0 :;b mov rvslpch,#00h ; run mode judgment chattering counter vr12_2c0 : mov rvcevfg,#00h ; run mode judgment cfg counter ; initialize br $vr12_300 $ eject ;---------------------------------------------------------------------- ; capstan phase error calculation ;---------------------------------------------------------------------- ; ; value of cr12 ; at play : capture value of tm1 by pbctl ; at record : capture value of tm1 by cfg division signal ; ; e cp = (cr12 value) C n cpl ; ; n cpl : capstan phase target value ; nf : internal reference timer value (cr10) ;---------------------------------------------------------------------- vr12_300 :;b ;///// internal reference timer value /////// movw de,cr10 ; internal reference timer value shrw de,1 ; set half cycle
chapter 8 program list 189 vr12_310 : ;///// phase error calculation //////// movw ax,cr12 ; load phase capture data subw ax,rvcprf ; e cp = np C n cpl movw hl,ax ; hl bc $vr12_321 ; is phase error (-)? ; when (+), subw ax,de ; subtract half cycle bc $vr12_322 ; when without carry, ; subtract half cycle again subw ax,de ; movw hl,ax ; br vr12_323 ; because sign is opposite, ; compare with minimum value vr12_321 : ; when (C), addw ax,de ; add half cycle bc $vr12_323 ; when without carry, ; add half cycle again addw ax,de ; movw hl,ax ; vr12_322 : mov b,ntsc_pal ; (+) ? compare with maximum value movw ax,tcp_max[b] ; cmpw ax,hl ; bnc $vr12_325 ; movw hl,ax ; br $vr12_325 ; vr12_323 : mov b,ntsc_pal ; (C) ? compare with minimum value movw ax,tcp_min[b] ; cmpw ax,hl ; bnh $vr12_325 ; movw hl,ax ; ;; br $vr12_325 ; vr12_325 : xchw hl,rvercp ; rverdp ? phase error amount of this time movw rvercp_1,hl ; rverdp_1 ? phase error amount of last time
chapter 8 program list 190 ;--------------------------------------------------------------------------------- ; lag read filter processing ;--------------------------------------------------------------------------------- ; ; 0. set filer coefficient ; ; ntsc ; ; f1 = 0.0245 hz ; f2 = 0.180 hz ; dpg = 30 hz ; ; mal a = C0.96299834 ; mbl b = C0.99488186 ; mgl g = 0.13832185 ; ; ; pal ; ; f1 = 0.0245 hz ; f2 = 0.190 hz ; dpg = 25 hz ; ; mal a = C0.95336134 ; mbl b = C0.99386137 ; mgl g = 0.13162089 ; vr12_400 :;b vr12_410 : ; *** clear filter memory when loading *** ; * because of inputting error information at loading cmp rsnext,#csmload ; loading? bne $vr12_420 ; no movw rvercp_y,#0 ; movw rvercp,#0 ; movw rvercp_1,#0 ; movw rvercp_by,#0 ; movw rvercp_by+2,#0 ; vr12_420 :;b ;///// run mode judgment //////// mov b,ntsc_pal ; movw ax,tcp_fg[b] ; movw b_buf,ax ; movw ax,tcp_fag[b] ; movw b_buf+2,ax ; movw ax,tcp_fb[b] ; movw b_buf+4,ax ; vr12_426 :;b mov b,#low(b_buf) ; mov c,#low(rvercp) ; movw de,rvercp_by ; movw ax,rvercp_by+2 ;
chapter 8 program list 191 macsw 2 ; movw rvercp_y,ax ; capstan phase error amount ; (after filter operation) movw de,b_buf+4 ; mulw de ; shlw de,1 ; rolc x,1 ; rolc a,1 ; movw rvercp_by,de ; movw rvercp_by+2,ax ; (Cb)?y ;--------------------------------------------------------------------------------- ; pbctl signal missing check counter initialize ;--------------------------------------------------------------------------------- vr12_500 :;b mov rvcevfg,#00h ; clear cfg counter clr1 fvflctl ; reset pbctl missing flag ;--------------------------------------------------------------------------------- ; multiple interruption disable ;--------------------------------------------------------------------------------- vr12_600 : di pop ax ; %return mask register mov1 cy,crmk13 ;% load intcr13 interrupt mask flag ;%ctl mov1 x.3,cy ;% save intcr13 interrupt mask flag ;%ctl movw mk1,ax ;%set mask register pop ax ; return mask register mov1 cy,crmk02 ; load intcr02 interrupt mask flag mov1 a.0,cy ; save intcr02 interrupt mask flag mov1 cy,pmk2 ;%load intp2 interrupt mask flag mov1 a.7,cy ;%save intp2 interrupt mask flag mov1 cy,crmk11 ; load intcr11 interrupt mask flag mov1 a.1,cy ; save intcr11 interrupt mask flag movw mk0,ax ; reti ; vsync or cr10 match ; interrupt processing end
chapter 8 program list 192 ;--------------------------------------------------------------------------------- ; run mode judgment table ;--------------------------------------------------------------------------------- ;//// number of cfg division //////// vr12_t00 : db 5,7,9,11,13,16,19,31,37 ; pulse data ;//// run mode conversion table /// ttvr12_speed: dw tvr12_t10_sp dw tvr12_t10_slp dw tvr12_t10_lp dw tvp12_t10_pal vr12_t10 : tvr12_t10_sp: db 1,2,0,3,0,0,0,0,0 ; sp mode tvr12_t10_slp: db 1,1,1,1,1,1,2,3,0 ; slp mode tvr12_t10_lp: db 2,1,2,2,2,3,0,2,2 ; lp mode tvr12_t10_pal: db 1,2,3,3,0,3,3,3,3 ; sp (pal) mode $ eject vcr00 cseg unit ;--------------------------------------------------------------------------------- ; intcr00 quasi vsync timing setting ;--------------------------------------------------------------------------------- ; vr00_000 : register setting processing ; vr00_100 : rfs level check ; vr00_200 : quasi vsync rising edge timing setting ; vr00_300 : drum start processing (interrupt enable condition judgment) ;--------------------------------------------------------------------------------- ; register setting processing ;--------------------------------------------------------------------------------- vr00_000 :;v ;///// register setting ///////// sel rb3 ; highest-order interrupt!! ;--------------------------------------------------------------------------------- ; rfs level check ;--------------------------------------------------------------------------------- vr00_100 : bf icr.6,$vr00_200 ; capture by rfs rising edge? no movw ax,cpt1l ; movw hl,ax ;
chapter 8 program list 193 mov a,cpt1h ; mov w,a ; movg rvcpt1,whl ; set1 fsafrq ; down edge set for auto-tracking ;--------------------------------------------------------------------------------- ; set quasi vsync rising timing ;--------------------------------------------------------------------------------- ; quasi vsync outputs during search mode ; (cue/rev), halt, and v.c mode. ; ; rising timing ; ; fixed value ; t d = hsw delay amount + 3 ; = (cr00 setting value) + 191 m sec ; = (cr00 setting value) + 191d ;% ; ; variable value: ch2 at still/frame ; t d = hsw delay amount + 2h to 4h (initial value) to 6h ; = (cr00 setting value) + 128 to 255 to 382 m sec ;% ; = (cr00 setting value) + 128d to 255d to 382d ;% ; ; falling edge timing ; ; 4h = 63.55 x 4 = 254.2 m sec ; = 254d ;% ; \ 1h = 63.55 m sec ; ; * timing match interrupt ? intcr02 ; ;--------------------------------------------------------------------------------- vr00_200 :;b bf fvdout,$vr00_300 ; quasi vsync output mode? no bt icr.6,$vr00_230 ; rfs rising edge? no vr00_210 : mov a,rvsrvcd and a,#11110000b ; clear low-order 4 bit cmp a,#cvstill ; servo code still? bne $vr00_230 ; no vr00_220 : ;///// variable value //////// movw ax,#00 ; clear buffer mov a,rvpsvcnt ; variable value (00-feh) xch a,x addw ax,#128d ; %basic value addw ax,cr00 ; rising timing movw cr02,ax ; set falling timing br vr00_240
chapter 8 program list 194 vr00_230 :;b ;///// fixed value //////// movw ax,cr00 ; rising timing addw ax,#191d ;%set data movw cr02,ax ; vr00_240 :;b set1 p8l.0 ;% clr1 crmk02 ; intcr02 enable set1 fvhqvdt ; set rising timing flag ;------------------------------------------------------------------ ; drum rising processing (interrupt enable conditions judgment) ;------------------------------------------------------------------ vr00_300 :;b bf fsdrmon,$vr00_400 ; drum on? no bf icr.6,$vr00_400 ; rfs falling edge input? no clr1 fseicpt2 ; clear intcpt2 interrupt enable ; request flag ;------------------------------------------------------------------ ; v-mute release rfs synchronization processing ;------------------------------------------------------------------ vr00_400 :;b bf fsvm0frq,$vr00_500 ; v-mute release request? no clr1 fsvm0frq ; clear request clr1 pqvd ; v-mute off clr1 fpqvd ; set port refresh flag set1 pmc8.0 ;%p80 pt0 output mode ;------------------------------------------------------------------ ; reverse brake at cue ? play rfs synchronization processing ;------------------------------------------------------------------ vr00_500 :;b bf fscrrfrq,$vr00_600 ; request capstan reverse rfs ; synchronization? clr1 fscrrfrq set1 pcapfwd ; capstan motor reverse start set1 pcapf_r set1 fpcapf_r ; set port refresh flag movg whl,#rnstim0 ;% mov a,rvfsrv_2 and a,#00000011b ; read run mode cmp a,#cvpal ; pal?
chapter 8 program list 195 be $vr00_510 ; yes cmp a,#cvsp ; ntsc sp? be $vr00_510 cmp a,#cvslp ; ntsc slp? be $vr00_520 mov a,#33h ; ntsc lp br $vr00_530 ; 70 msec timer set vr00_510 :;b ; pal sp, ntsc sp mov a,#50h ; 110 msec timer set br $vr00_530 vr00_520 :;b ; ntsc slp mov a,#2ch ; 60 msec timer set vr00_530 :;b mov [hl],a ; timer start clr1 fnsteno ; vr00_600 :;b reti ; intcr00 interrupt processing end $ eject vcr02 cseg unit ;--------------------------------------------------------------------------------- ; set intcr02 quasi vsync timing ;--------------------------------------------------------------------------------- ; vr02_000 : register set processing ; vr02_100 : set quasi vsync falling timing ; vr02_200 : intcr02 interrupt disable processing ;--------------------------------------------------------------------------------- ; register setting processing ;--------------------------------------------------------------------------------- vr02_000 :;v ;///// register setting ///////// sel rb3 ; highest-order interrupt!! ;--------------------------------------------------------------------------------- ; set quasi vsync falling edge timing ;--------------------------------------------------------------------------------- vr02_100 : btclr fvhqvdt,$vr02_110 ; rising timing interrupt? br $vr02_200 ; no
chapter 8 program list 196 vr02_110 :;b movw ax,cr02 ; falling edge timing addw ax,#254d ;%set data movw cr02,ax clr1 p8l.0 ;% (addition) br $vr02_300 ;-------------------------------------------------------------------- ; intcr02 interrupt disable processing ;-------------------------------------------------------------------- vr02_200 : set1 crmk02 ; intcr02 disable vr02_300 : reti ; intcr02 interrupt end $ eject ;-------------------------------------------------------------------- ; servo data table ;-------------------------------------------------------------------- ; ; ? table description ; ; ; db tmc0 (timer 0 control register setting value) ; db cptm (capture mode register setting value) ; db intm1 (external capture input mode register setting value) ; ; [sp/lp/slp/pal] ; ; db value of edvc ; db cr12 macro service counter ; dw ref30hz (cr10) ; dw drum speed target value (cpt2h) ; db drum speed target value (cpt2l) ; dw drum bias adding value ; dw capstan speed target value (cpt3) ; dw capstan bias adding value ; dw capstan gain adjustment value ; ;-------------------------------------------------------------------- ;------------------------------ ; play ;------------------------------ sdt_play : db 10001001b ; tmc0 count:en tm1:clr ; tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 ; cr12-trg:cti11,cpt1: - edge db 00010001b ;%intm1 pbctl:an_amp, ; pbctl: - edge cfg: - edge ; <-(01010001b)
chapter 8 program list 197 ;///// sp ///////////////// sdt_pls0 : db 03d ; edvc count sdt_pls1 : db 01h ; macro count sdt_pls2 : dw 8256h ; cr10 sdt_pls3 : dg 2b72h ; cpt2 sdt_pls5 : dw 66f0h ; drum bias sdt_pls6 : dg 56ceh ; cpt3 sdt_pls7 : dw 85e0h ; capstan bias sdt_pls8 : dw 600h ; loop gain sdt_pls9 : dw 433h ; capstan kv/kp sdt_plsa : db 17h ; ctl amp gain ;///// lp ///////////////// sdt_pll0 : db 02d ; edvc count sdt_pll1 : db 01h ; macro count sdt_pll2 : dw 8256h ; cr10 sdt_pll3 : dg 2b72h ; cpt2 sdt_pll5 : dw 66ffh ; drum bias sdt_pll6 : dg 73bdh ; cpt3 sdt_pll7 : dw 8595h ; capstan bias sdt_pll8 : dw 0540h ; loop gain sdt_pll9 : dw 0159h ; capstan kv/kp sdt_plla : db 1dh ;%% ctl amp gain ;///// slp ///////////////// sdt_ple0 : db 01d ; edvc count sdt_ple1 : db 01h ; macro count sdt_ple2 : dw 8256h ; cr10 sdt_ple3 : dg 2b72h ; cpt2 sdt_ple5 : dw 66ffh ; drum bias sdt_ple6: dg 56ceh ; cpt3
chapter 8 program list 198 sdt_ple7 : dw 86dfh ; capstan bias sdt_ple8 : dw 0420h ; loop gain sdt_ple9 : dw 0119h ; capstan kv/kp sdt_plea : db 1dh ;%% ctl amp gain ;///// pal /////////////// sdt_plp0 : db 03d ; edvc count sdt_plp1 : db 01h ; macro count sdt_plp2 : dw 9c40h ; cr10 sdt_plp3 : dg 3415h ; cpt2 sdt_plp5 : dw 66ffh ; drum bias sdt_plp6 : dg 7bc1h ; cpt3 sdt_plp7 : dw 863fh ; capstan bias sdt_plp8 : dw 0600h ; loop gain sdt_plp9 : dw 0166h ; capstan kv/kp sdt_plpa : db 1dh ;%% ctl amp gain ;------------------------------ ; rvs play ; sp/lp/slp/pal play ;------------------------------ sdt_rvs : db 10001001b ; tmc0 count:en tm1:clr tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 ; cr12-trg:cti11,cpt1: - edge db 00010001b ;%intm1 pbctl:an_amp,pbctl: - edge ; cfg: - edge <-(01010001b) ;///// sp /////////////// sdt_rps0 : db 03d ; edvc count sdt_rps1 : db 01h ; macro count sdt_rps2 : dw 83d3h ; cr10 sdt_rps3 : dg 2bf1h ; cpt2 sdt_rps5 : dw 66ffh ; drum bias sdt_rps6 : dg 56ceh ; cpt3 sdt_rps7 : dw 8678h ; capstan bias sdt_rps8 : dw 0600h ; loop gain
chapter 8 program list 199 sdt_rps9 : dw 0233h ; capstan kv/kp sdt_rpsa : db 17h ;%% ctl amp gain ;///// lp ///////////////// sdt_rpl0 : db 02d ; edvc count sdt_rpl1 : db 01h ; macro count sdt_rpl2 : dw 8314h ; cr10 sdt_rpl3: dg 2bb1h ; cpt2 sdt_rpl5 : dw 66ffh ; drum bias sdt_rpl6 : dg 73bdh ; cpt3 sdt_rpl7 : dw 8595h ; capstan bias sdt_rpl8 : dw 0540h ; loop gain sdt_rpl9 : dw 0159h ; capstan kv/kp sdt_rpla : db 1dh ;%% ctl amp gain ;///// slp ///////////////// sdt_rpe0 : db 01d ; edvc count sdt_rpe1 : db 01h ; macro count sdt_rpe2 : dw 82d5h ; cr10 sdt_rpe3 : dg 2b9ch ; cpt2 sdt_rpe5 : dw 66ffh ; drum bias sdt_rpe6 : dg 56ceh ; cpt3 sdt_rpe7 : dw 86dfh ; capstan bias sdt_rpe8 : dw 0420h ; loop gain sdt_rpe9 : dw 0119h ; capstan kv/kp sdt_rpea : db 1dh ;%% ctl amp gain ;///// pal ///////////////// sdt_rpp0 : db 03d ; edvc count sdt_rpp1 : db 01h ; macro count sdt_rpp2 : dw 9dc0h ; cr10 sdt_rpp3 :
chapter 8 program list 200 dg 3495h ; cpt2 sdt_rpp5 : dw 66ffh ; drum bias sdt_rpp6 : dg 7bc1h ; cpt3 sdt_rpp7 : dw 863fh ; capstan bias sdt_rpp8 : dw 0600h ; loop gain sdt_rpp9 : dw 0166h ; capstan kv/kp sdt_rppa : db 1dh ;%% ctl amp gain ;------------------------------ ; ff/rew (2h) ; ntsc play sp ;------------------------------ sdt_fr2h : db 10001001b ; tmc0 count:en tm1:clr tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 cr12-trg: ;cti11,cpt1; - edge db 00010001b ;%intm1 pbctl:an_amp,pbctl: - edge ; cfg: - edge <-(01010001b) ;///// sp ///////////////// sdt_2hs0: db 03d ; edvc count sdt_2hs1 : db 01h ; macro count sdt_2hs2 : dw 8256h ; cr10 sdt_2hs3 : dg 2b72h ; cpt2 sdt_2hs5 : dw 66ffh ; drum bias sdt_2hs6 : dg 56ceh ; cpt3 sdt_2hs7 : dw 8678h ; capstan bias sdt_2hs8 : dw 0600h ; loop gain sdt_2hs9 : dw 0233h ; capstan kv/kp sdt_2hsa : db 0eh ;%%ctl amp gain ;///// lp ///////////////// sdt_2hl0 : db 03d ; edvc count sdt_2hl1 : db 01h ; macro count sdt_2hl2 : dw 8256h ; cr10 sdt_2hl3 : dg 2b72h ; cpt2 sdt_2hl5 : dw 66ffh ; drum bias
chapter 8 program list 201 sdt_2hl6 : dg 56ceh ; cpt3 sdt_2hl7 : dw 8678h ; capstan bias sdt_2hl8 : dw 0600h ; loop gain sdt_2hl9 : dw 0233h ; capstan kv/kp sdt_2hla : db 0eh ;%% ctl amp gain ;///// slp ///////////////// sdt_2he0: db 03d ; edvc count sdt_2he1 : db 01h ; macro count sdt_2he2 : dw 8256h ; cr10 sdt_2he3 : dg 2b72h ; cpt2 sdt_2he5 : dw 66ffh ; drum bias sdt_2he6 : dg 56ceh ; cpt3 sdt_2h1e7 : dw 8678h ; capstan bias sdt_2he8 : dw 0600h ; loop gain sdt_2he9 : dw 0233h ; capstan kv/kp sdt_2hea : db 0eh ;%% ctl amp gain ;///// pal ///////////////// sdt_2hp0 : db 03d ; edvc count sdt_2hp1 : db 01h ; macro count sdt_2hp2 : dw 9c40h ; cr10 sdt_2hp3 : dg 3415h ; cpt2 sdt_2hp5 : dw 66ffh ; drum bias sdt_2hp6 : dg 7bc1h ; cpt3 sdt_2hp7 : dw 8678h ; capstan bias sdt_2hp8 : dw 0600h ; loop gain sdt_2hp9 : dw 0233h ; capstan kv/kp sdt_2hpa : db 0eh ;%% ctl amp gain
chapter 8 program list 202 ;------------------------------ ; ff/rew (6h) ; capstan initial speed ;------------------------------ sdt_fr6h : db 10001001b ; tmc0 count:en tm1:clr tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 cr12-trg: ;cti11,cpt1: - edge db 00010001b ;%intm1 pbctl:an_amp, pbctl: - edge ; cfg: - edge <-(01010001b) ;///// sp ///////////////// sdt_6hs0 : db 01d ; edvc count sdt_6hs1 : db 01h ; macro count sdt_6hs2 : dw 8256h ; cr10 sdt_6hs3 : dg 2b72h ; cpt2 sdt_6hs5 : dw 66ffh ; drum bias sdt_6hs6 : dg 56ceh ; cpt3 sdt_6hs7 : dw 86dfh ; capstan bias sdt_6hs8 : dw 00c0h ; loop gain sdt_6hs9 : dw 0119h ; capstan kv/kp sdt_6hsa : db 0eh ;%% ctl amp gain ;///// lp ///////////////// sdt_6hl0 : db 01d ; edvc count sdt_6hl1 : db 01h ; macro count sdt_6hl2 : dw 8256h ; cr10 sdt_6hl3 : dg 2b72h ; cpt2 sdt_6hl5 : dw 66ffh ; drum bias sdt_6hl6 : dg 56ceh ; cpt3 sdt_6hl7 : dw 86dfh ; capstan bias sdt_6hl8 : dw 00c0h ; loop gain sdt_6hl9 : dw 0119h ; capstan kv/kp sdt_6hla : db 0eh ;%% ctl amp gain ;///// slp ///////////////// sdt_6he0 : db 01d ; edvc count
chapter 8 program list 203 sdt_6he1 : db 01h ; macro count sdt_6he2 : dw 8256h ; cr10 sdt_6he3 : dg 2b72h ; cpt2 sdt_6he5 : dw 66ffh ; drum bias sdt_6he6 : dg 56ceh ; cpt3 sdt_6he7 : dw 86dfh ; capstan bias sdt_6he8 : dw 00c0h ; loop gain sdt_6he9 : dw 0119h ; capstan kv/kp sdt_6hea : db 0eh ;%% ctl amp gain ;///// pal ///////////////// sdt_6hp0 : db 01d ; edvc count sdt_6hp1 : db 01h ; macro count sdt_6hp2 : dw 9c40h ; cr10 sdt_6hp3 : dg 3415h ; cpt2 sdt_6hp5 : dw 66ffh ; drum bias sdt_6hp6 : dg 56ceh ; cpt3 sdt_6hp7 : dw 86dfh ; capstan bias sdt_6hp8 : dw 00c0h ; loop gain sdt_6hp9 : dw 0119h ; capstan kv/kp sdt_6hpa : db 0eh ;%% ctl amp gain ;------------------------------ ; ff/rew (6h) vd out ; capstan fg 90 pulses drive ;------------------------------ sdt_6hvd : db 10001001b ; tmc0 count:en tm1:clr tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 cr12-trg: ; cti11,cpt1: - edge db 00010001b ;%intm1 pbctl:an_amp,pbctl: - edge ; cfg: - edge <-(01010001b) ;///// sp ///////////////// sdt_6vs0 : db 01d ; edvc count sdt_6vs1 : db 01h ; macro count sdt_6vs2 : dw 8315h ; cr10
chapter 8 program list 204 sdt_6vs3 : dg 2bb1h ; cpt2 sdt_6vs5 : dw 66ffh ; drum bias sdt_6vs6 : dg 56ceh ; cpt3 sdt_6vs7 : dw 86dfh ; capstan bias sdt_6vs8 : dw 0420h ; loop gain sdt_6vs9 : dw 0119h ; capstan kv/kp sdt_6vsa : db 0eh ;%% ctl amp gain ;///// lp ///////////////// sdt_6vl0 : db 01d ; edvc count sdt_6vl1 : db 01h ; macro count sdt_6vl2 : dw 82b5h ; cr10 sdt_6vl3 : dg 2b91h ; cpt2 sdt_6vl5 : dw 66ffh ; drum bias sdt_6vl6 : dg 56ceh ; cpt3 sdt_6vl7 : dw 86dfh ; capstan bias sdt_6vl8 : dw 0420h ; loop gain sdt_6vl9 : dw 0119h ; capstan kv/kp sdt_6vla : db 0eh ;%% ctl amp gain ;///// slp ///////////////// sdt_6ve0 : db 01d ; edvc count sdt_6ve1 : db 01h ; macro count sdt_6ve2 : dw 8295h ; cr10 sdt_6ve3 : dg 2b91h ; cpt2 sdt_6ve5 : dw 66ffh ; drum bias sdt_6ve6 : dg 56ceh ; cpt3 sdt_6ve7 : dw 86dfh ; capstan bias sdt_6ve8 : dw 0420h ; loop gain sdt_6ve9 : dw 0119h ; capstan kv/kp sdt_6vea : db 0eh ;%% ctl amp gain
chapter 8 program list 205 ;///// pal ///////////////// sdt_6vp0 : db 01d ; edvc count sdt_6vp1 : db 01h ; macro count sdt_6vp2 : dw 9d00h ; cr10 sdt_6vp3 : dg 3455h ; cpt2 sdt_6vp5 : dw 66ffh ; drum bias sdt_6vp6 : dg 56ceh ; cpt3 sdt_6vp7 : dw 86dfh ; capstan bias sdt_6vp8 : dw 0420h ; loop gain sdt_6vp9 : dw 0119h ; capstan kv/kp sdt_6vpa : db 0eh ;%% ctl amp gain ;------------------------------ ; ff/rew (2h*3) ; ntsc slp cue/rev ;------------------------------ sdt_frx3 : db 10001001b ; tmc0 count:en tm1:clr tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 cr12-trg: ; cti11,cpt1: - edge db 00010001b ;%intm1 pbctl:an_amp,pbctl: - edge ; cfg: - edge <-(01010001b) ;///// sp ///////////////// sdt_x3s0: db 03d*3 ; edvc count sdt_x3s1 : db 09d ; macro count sdt_x3s2 : dw 8315h ; cr10 sdt_x3s3 : dg 2bb1h ; cpt2 sdt_x3s5 : dw 66ffh ; drum bias sdt_x3s6 : dg 56ceh ; cpt3 sdt_x3s7 : dw 8678h ; capstan bias sdt_x3s8 : dw 0600h ; loop gain sdt_x3s9 : dw 034ch ; capstan kv/kp sdt_x3sa : db 0eh ;%% ctl amp gain
chapter 8 program list 206 ;///// lp ///////////////// sdt_x3l0: db 03d*3 ; edvc count sdt_x3l1 : db 09d ; macro count sdt_x3l2 : dw 82b5h ; cr10 sdt_x3l3 : dg 2b91h ; cpt2 sdt_x3l5 : dw 66ffh ; drum bias sdt_x3l6 : dg 56ceh ; cpt3 sdt_x3l7 : dw 8595h ; capstan bias sdt_x3l8 : dw 0600h ; loop gain sdt_x3l9 : dw 034ch ; capstan kv/kp sdt_x3la : db 0eh ;%% ctl amp gain ;///// slp ///////////////// sdt_x3e0 : db 03d*3 ; edvc count sdt_x3e1 : db 09d ; macro count sdt_x3e2 : dw 8295h ; cr10 sdt_x3e3 : dg 2bb7h ; cpt2 sdt_x3e5 : dw 66ffh ; drum bias sdt_x3e6 : dg 56ceh ; cpt3 sdt_x3e7 : dw 86dfh ; capstan bias sdt_x3e8 : dw 0600h ; loop gain sdt_x3e9 : dw 034ch ; capstan kv/kp sdt_x3ea : db 0eh ;%%ctl amp gain ;///// pal ///////////////// sdt_x3p0 : db 03d*3 ; edvc count sdt_x3p1 : db 09d ; macro count sdt_x3p2 : dw 9d00h ; cr10 sdt_x3p3 : dg 3455h ; cpt2 sdt_x3p5 : dw 66ffh ; drum bias sdt_x3p6 : dg 56ceh ; cpt3 sdt_x3p7 : dw 863fh ; capstan bias
chapter 8 program list 207 sdt_x3p8 : dw 0600h ; loop gain sdt_x3p9 : dw 034ch ; capstan kv/kp sdt_x3pa : db 0eh ;%% ctl amp gain ;------------------------------ ; ff/rew ; ntsc sp play ;------------------------------ sdt_ffrw : db 10001001b ; tmc0 count:en tm1:clr tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 cr12-trg: ; cti11,cpt1: - edge db 00010001b ;%intm1 pbctl:an_amp,pbctl: - edge ; cfg: - edge <-(01010001b) ;///// sp ///////////////// sdt_frs0 : db 40d ; edvc count sdt_frs1 : db 08d ; macro count sdt_frs2 : dw 8256h ; cr10 sdt_frs3 : dg 2b72h ; cpt2 sdt_frs5 : dw 66ffh ; drum bias sdt_frs6 : dg 56ceh ; cpt3 sdt_frs7 : dw 8678h ; capstan bias sdt_frs8 : dw 0600h ; loop gain sdt_frs9 : dw 0233h ; capstan kv/kp sdt_frsa : db 0ehh ;%% ctl amp gain ;///// lp ///////////////// sdt_frl0: db 40d ; edvc count sdt_frl1 : db 08d ; macro count sdt_frl2 : dw 8256h ; cr10 sdt_frl3 : dg 2b72h ; cpt2 sdt_frl5 : dw 66ffh ; drum bias sdt_frl6 : dg 56ceh ; cpt3 sdt_frl7 : dw 8595h ; capstan bias sdt_frl8 : dw 0600h ; loop gain sdt_frl9 : dw 0233h ; capstan kv/kp
chapter 8 program list 208 sdt_frla : db 0eh ;%% ctl amp gain ;///// slp ///////////////// sdt_fre0 : db 40d ; edvc count sdt_fre1 : db 08d ; macro count sdt_fre2 : dw 8256h ; cr10 sdt_fre3 : dg 2b72h ; cpt2 sdt_fre5 : dw 66ffh ; drum bias sdt_fre6 : dg 56ceh ; cpt3 sdt_fre7 : dw 86dfh ; capstan bias sdt_fre8 : dw 0600h ; loop gain sdt_fre9 : dw 0233h ; capstan kv/kp sdt_frea : db 0eh ;%% ctl amp gain ;///// pal ///////////////// sdt_frp0 : db 40d ; edvc count sdt_frp1 : db 08d ; macro count sdt_frp2 : dw 9c40h ; cr10 sdt_frp3 : dg 3415h ; cpt2h sdt_frp5 : dw 66ffh ; drum bias sdt_frp6 : dg 7bc1h ; cpt3 sdt_frp7 : dw 863h ; capstan bias sdt_frp8 : dw 0600h ; loop gain sdt_frp9 : dw 0233h ; capstan kv/kp sdt_frpa : db 0eh ;%% ctl amp gain ;------------------------------ ; cue ;------------------------------ sdt__cue : db 10001001b ; tmc0 count:en tm1:clr tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 cr12-trg: ; cti11,cpt1: - edge db 00010001b ;%intm1 pbctl:an_amp,pbctl: - edge ; cfg: - edge <-(01010001b)
chapter 8 program list 209 ;///// sp ///////////////// sdt_cus0 : db 15d ; edvc count sdt_cus1 : db 05d ; macro count sdt_cus2 : dw 7f5ch ; cr10 sdt_cus3 : dg 2a74h ; cpt2 sdt_cus5 : dw 66ffh ; drum bias sdt_cus6 : dg 54e8h ; cpt3 sdt_cus7 : dw 8678h ; capstan bias sdt_cus8 : dw 0600h ; loop gain sdt_cus9 : dw 0433h ; capstan kv/kp sdt_cusa : db 11h ;%% ctl amp gain ;///// lp ///////////////// sdt_cul0 : db 09d*2 ; edvc count sdt_cul1 : db 09d ; macro count sdt_cul2 : dw 7f5eh ; cr10 sdt_cul3 : dg 2a74h ; cpt2 sdt_cul5 : dw 66ffh ; drum bias sdt_cul6 : dg 54e9h ; cpt3 sdt_cul7 : dw 8595h ; capstan bias sdt_cul8 : dw 0600h ; loop gain sdt_cul9 : dw 034ch ; capstan kv/kp sdt_cula : db 12h ;%% ctl amp gain ;///// slp ///////////////// sdt_cue0 : db 09d ; edvc count sdt_cue1 : db 09d ; macro count sdt_cue2 : dw 805ch ; cr10 sdt_cue3 : dg 2ac9h ; cpt2 sdt_cue5 : dw 66ffh ; drum bias sdt_cue6 : dg 5592h ; cpt3
chapter 8 program list 210 sdt_cue7 : dw 86dfh ; capstan bias sdt_cue8 : dw 0600h ; loop gain sdt_cue9 : dw 034ch ; capstan kv/kp sdt_cuea : db 12h ;%% ctl amp gain ;///// pal ///////////////// sdt_cup0 : db 21d ; edvc count sdt_cup1 : db 07d ; macro count sdt_cup2 : dw 97c0h ; cr10 sdt_cup3 : dg 3295h ; cpt2 sdt_cup5 : dw 66ffh ; drum bias sdt_cup6 : dg 652ah ; cpt3 sdt_cup7 : dw 863fh ; capstan bias sdt_cup8 : dw 0600h ; loop gain sdt_cup9 : dw 034ch ; capstan kv/kp sdt_cupa : db 12h ;%% ctl amp gain ;------------------------------ ; cue ? play ;------------------------------ sdt_cupl : db 10001001b ; tmc0 count:en tm1:clr tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 cr12-trg: ; cti11,cpt1: - edge db 00010001b ;%intm1 pbctl:an_amp,pbctl: - edge ; cfg: - edge <-(01010001b) ;///// sp ///////////////// sdt_cps0 : db 15d ; edvc count sdt_cps1 : db 05d ; macro count sdt_cps2 : dw 80d9h ; cr10 sdt_cps3 : dg 2af3h ; cpt2 sdt_cps5 : dw 66ffh ; drum bias sdt_cps6 : dg 54e8h ; cpt3 sdt_cps7 : dw 8678h ; capstan bias sdt_cps8 : dw 0600h ; loop gain
chapter 8 program list 211 sdt_cps9 : dw 0433h ; capstan kv/kp sdt_cpsa : db 17h ;%% ctl amp gain ;///// lp ///////////////// sdt_cpl0 : db 09d*2 ; edvc count sdt_cpl1 : db 09d ; macro count sdt_cpl2 : dw 80d9h ; cr10 sdt_cpl3 : dg 2af3h ; cpt2 sdt_cpl5 : dw 66ffh ; drum bias sdt_cpl6 : dg 7137h ; cpt3 sdt_cpl7 : dw 8595h ; capstan bias sdt_cpl8 : dw 0600h ; loop gain sdt_cpl9 : dw 034ch ; capstan kv/kp sdt_cpla : db 1dh ;%% ctl amp gain ;///// slp ///////////////// sdt_cpe0 : db 09d ; edvc count sdt_cpe1 : db 09d ; macro count sdt_cpe2 : dw 8159h ; cr10 sdt_cpe3 : dg 2b1dh ; cpt2 sdt_cpe5 : dw 66ffh ; drum bias sdt_cpe6 : dg 55e7h ; cpt3 sdt_cpe7 : dw 86dfh ; capstan bias sdt_cpe8 : dw 0600h ; loop gain sdt_cpe9 : dw 034ch ; capstan kv/kp sdt_cpea : db 1dh ;%% ctl amp gain ;///// pal ///////////////// sdt_cpp0 : db 21d ; edvc count sdt_cpp1 : db 07d ; macro count sdt_cpp2 : dw 9940h ; cr10 sdt_cpp3 :
chapter 8 program list 212 dg 3315h ; cpt2 sdt_cpp5 : dw 66ffh ; drum bias sdt_cpp6 : dg 652ah ; cpt3 sdt_cpp7 : dw 863fh ; capstan bias sdt_cpp8 : dw 0600h ; loop gain sdt_cpp9 : dw 034ch ; capstan kv/kp sdt_cppa : db 1dh ;%% ctl amp gain ;------------------------------ ; review ;------------------------------ sdt__rev : db 10001001b ; tmc0 count:en tm1:clr tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 cr12-trg: ; cti11,cpt1: - edge db 00010001b ;%intm1 pbctl:an_amp,pbctl: - edge ; cfg: - edge <-(01010001b) ;///// sp ///////////////// sdt_rvs0 : db 15d ; edvc count sdt_rvs1 : db 05d ; macro count sdt_rvs2 : dw 86ceh ; cr10 sdt_rvs3 : dg 2cefh ; cpt2 sdt_rvs5 : dw 66ffh ; drum bias sdt_rvs6 : dg 59dfh ; cpt3 sdt_rvs7 : dw 8678h ; capstan bias sdt_rvs8 : dw 0600h ; loop gain sdt_rvs9 : dw 0433h ; capstan kv/kp sdt_rvsa : db 11h ;%% ctl amp gain ;///// lp ///////////////// sdt_rvl0 : db 09d*2 ; edvc count sdt_rvl1 : db 09d ; macro count sdt_rvl2 : dw 860dh ; cr10 sdt_rvl3 : dg 2cafh ; cpt2 sdt_rvl5 : dw 66ffh ; drum bias
chapter 8 program list 213 sdt_rvl6 : dg 7728h ; cpt3 sdt_rvl7 : dw 8595h ; capstan bias sdt_rvl8 : dw 0600h ; loop gain sdt_rvl9 : dw 034ch ; capstan kv/kp sdt_rvla : db 12h ;%% ctl amp gain ;///// slp /////////////// sdt_rve0 : db 09d ; edvc count sdt_rve1 : db 09d ; macro count sdt_rve2 : dw 84cfh ; cr10 sdt_rve3 : dg 2c45h ; cpt2 sdt_rve5 : dw 66ffh ; drum bias sdt_rve6 : dg 588ah ; cpt3 sdt_rve7 : dw 86dfh ; capstan bias sdt_rve8 : dw 0600h ; loop gain sdt_rve9 : dw 034ch ; capstan kv/kp sdt_rvea : db 12h ;%% ctl amp gain ;///// pal /////////////// sdt_rvp0 : db 21d ; edvc count sdt_rvp1 : db 07d ; macro count sdt_rvp2 : dw 0a240h ; cr10 sdt_rvp3 : dg 3615h ; cpt2 sdt_rvp5 : dw 66ffh ; drum bias sdt_rvp6 : dg 6c2ah ; cpt3 sdt_rvp7 : dw 863fh ; capstan bias sdt_rvp8 : dw 0600h ; loop gain sdt_rvp9 : dw 034ch ; capstan kv/kp sdt_rvpa : db 12h ;%% ctl amp gain
chapter 8 program list 214 ;------------------------------ ; still ; sp/lp/slp/pal play ;------------------------------ sdt_stil : db 10001001b ; tmc0 count:en tm1:clr tm0:clr db 00110000b ;%cptm cpt0-trg:tm1=cr10 cr12-trg: ; cti11,cpt1: - edge db 00010001b ;%intm1 pbctl:an_amp,pbctl: - edge ; cfg: - edge <-(01010001b) ;///// sp ///////////////// sdt_sts0 : db 03d ; edvc count sdt_sts1 : db 01h ; macro count sdt_sts2 : dw 8315h ; cr10 sdt_sts3 : dg 2bb1h ; cpt2 sdt_sts5 : dw 66ffh ; drum bias sdt_sts6 : dg 56ceh ; cpt3 sdt_sts7 : dw 8678h ; capstan bias sdt_sts8 : dw 0600h ; loop gain sdt_sts9 : dw 0233h ; capstan kv/kp sdt_stsa : db 17h ;%% ctl amp gain ;///// lp ///////////////// sdt_stl0 : db 02d ; edvc count sdt_stl1 : db 01h ; macro count sdt_stl2 : dw 8265h ; cr10 sdt_stl3 : dg 2b91h ; cpt2 sdt_stl5 : dw 66ffh ; drum bias sdt_stl6 : dg 73bdh ; cpt3 sdt_stl7 : dw 8595h ; capstan bias sdt_stl8 : dw 0540h ; loop gain sdt_stl9 : dw 0159h ; capstan kv/kp sdt_stla : db 1dh ;%% ctl amp gain ;///// slp ///////////////// sdt_ste0 : db 01d ; edvc count
chapter 8 program list 215 sdt_ste1 : db 01h ; macro count sdt_ste2 : dw 8295h ; cr10 sdt_ste3 : dg 2bb7h ; cpt2 sdt_ste5 : dw 66ffh ; drum bias sdt_ste6 : dg 56ceh ; cpt3 sdt_ste7 : dw 86dfh ; capstan bias sdt_ste8 : dw 0420h ; loop gain sdt_ste9 : dw 0119h ; capstan kv/kp sdt_stea : db 1dh ;%% ctl amp gain ;///// pal /////////////// sdt_stp0 : db 03d ; edvc count sdt_stp1 : db 01h ; macro count sdt_stp2 : dw 9d00h ; cr10 sdt_stp3 : dg 3455h ; cpt2 sdt_stp5 : dw 66ffh ; drum bias sdt_stp6 : dg 7bc1h ; cpt3 sdt_stp7 : dw 863fh ; capstan bias sdt_stp8 : dw 0600h ; loop gain sdt_stp9 : dw 0166h ; capstan kv/kp sdt_stpa : db 1dh ;%% ctl amp gain $ eject servosub cseg fixed ;--------------------------------------------------------------------------------- ; servo data setting sub ;--------------------------------------------------------------------------------- ; ; ; ? tmc0 (timer 0 control register) ; ? cptm (capture mode register) ; ? intm1 (external capture input mode register) ; ? edvc (event divider control register) ; ? cr12 macro service counter ; ? ref30hz (cr10) ; ? drum speed target value (cpt2h) ; ? drum speed target value (cpt2l)
chapter 8 program list 216 ; ? drum bias adding value ; ? capstan speed target value (cpt3) ; ? capstan bias adding value ; ? loop gain ; ? clear filter ; ? clear capstan error amount ; ;--------------------------------------------------------------------------------- yvtbl_00 :;c ;///// interrupt control ///////// di ; to be referred at servo relation control yvtbl_10 : ;///// address setting ///////// mov a,rvsrvcd and a,#0f0h ; servo code low-order mask movg whl,#sdt_play ;%set play cmp a,#cvffrw2hrs ; ff/rew(2hrs)? bne $yvtbl_11 ; no movg whl,#sdt_fr2hrs ;% yes yvtbl_11 :;b cmp a,#cvffrw6hrs ; ff/rew(6hrs)? bne $yvtbl_12 ; no movg whl,#sdt_fr6hrs :% yes yvtbl_12 :;b cmp a,#cvffrwx3 ; ff/rew(2hrs*3)? bne $yvtbl_13 ; no movg whl,#sdt_frx3 ;% yes yvtbl_13 :;b cmp a,#cvffrew ; ff/rew? bne $yvtbl_14 ; no movg whl,#sdt_ffrw ;% yes yvtbl_14 :;b cmp a,#cvcue ; cue? bne $yvtbl_15 ; no movg whl,#sdt_ _cue ;% yes yvtbl_15 :;b cmp a,#cvrev ; review? bne $yvtbl_16 ; no movg whl,#sdt_ _rev ;% yes yvtbl_16 :;b cmp a,#cvstill ; still? bne $yvtbl_17 ; no movg whl,#sdt_stil ;% yes yvtbl_17 :;b cmp a,#cvrvs ; rvs play? bne $yvtbl_18 ; no
chapter 8 program list 217 movg whl_#sdt_rvs ;% yes yvtbl_18 :;b cmp a,#cvcupl : cue ? play? bne $yvtbl_19 ; no play movg whl,#sdt_cupl ;% yes yvtbl_19 :;b cmp a,#cvfr6hvd ; 6hrs play vd out ? bne $yvtbl_20 ; no play movg whl,#sdt_6hvd ;% yes yvtbl_20 : ;///// tmc0 read ///// mov a,[hl+] mov tmc0,a yvtbl_30 : ;///// cptm read ///// mov a,[hl+] mov cptm,a yvtbl_40 : ;///// intm1 read ///// mov a,[hl+] mov intm1,a yvtbl_50 : ;///// address adjustment ///////// mov a,rvfsrv_2 ; and a,#00000011b ; read running mode movw bc,#00h ; set address adding value (sp) cmp a,#cvlp ; lp? bne $yvtbl_51 ; no movw bc,#sdt_pll0-sdt_pls0 ;% yes (number of table byte x 1) yvtbl_51 :;b cmp a,#cvslp ; slp? bne $yvtbl_52 ; no movw bc,#sdt_ple0-sdt_pls0 ;% yes (number of table byte x 2) yvtbl_52 :;b cmp a,#cvpal ; pal? bne $yvtbl_53 ; no movw bc,#sdt_plp0-sdt_pls0 ;% yes (number of table byte x 3) yvtbl_53 :;b movw de,bc ;% address adding mov t,#0 ;% addg whl,tde ;%
chapter 8 program list 218 yvtbl_60 :;b ;///// edvc ///////////// mov a,[hl+] dec a ; ;add%% mov edvc,a yvtbl_70 : ;///// cr12 ///////////// mov a,[hl+] mov rvmccr12,a mov rvcram,a yvtbl_80 : ;///// cr10 ///////////// movw ax,[hl+] ; write into cr10 is performed in ; intcr10 routine. movw rvbcr10,ax ; (tm1 may overflow depending on write ; timing!) call !ypgadchg ; set pg value yvtbl_90 : ;///// cpt2 /////////// movg tde,whl movg whl,[tde+] movg rvdfrf,whl movg whl,tde yvtbl_b0 : ;///// d-bias ///////// movw ax,[hl+] movw rvdbas,ax yvtbl_c0 : ;///// cpt3 ///////////// movg tde,whl movg whl,[tde+] movg rvcfrf,whl movg whl,tde yvtbl_d0 : ;///// c-bias ///////// movw ax,[hl+] movw rvcbas,ax yvtbl_e0 : ;///// c-gain adjustment ///// movw ax,[hl+] movw rvc_kmp,ax
chapter 8 program list 219 yvtbl_f0 : ;///// c-kv/kp /////// movw ax,[hl+] movw rvc_kvp,ax ; yvtbl_f1 : ;///// pb_ctl gain /////// mov a,[hl] ; mov ctlm,a ; yvtbl_g0 : = ;///// clear filter ///// ; capstan speed/phase movw rvercmx,#0 ; movw rvercmx_1,#0 ; movw rvercmx_by,#0 ; movw rvercmx_by+2,#0 ; movw rvercp,#0 ; capstan phase filter movw rvercp_1,#0 ; movw rvercp_by,#0 ; movw rvercp_by+2,#0 ; yvtbl_h0 : ;///// clear c-error /////// movw rvercp_y,#0 ; capstan phase error movw rvercmx_y+2,#0 ; capstan speed error yvtbl_i0 : ;///// interrupt control ///////// ei ret end
chapter 8 program list 220 [memo]
221 appendix revision history appendix revision history the history of revisions hitherto made is shown as follows. edition revisions chapter second addition of m pd784915a throughout addition of related document number introduction the following figures are changed. chapter 3 ? figure 3-4 use of event counter (ec) is corrected. examples of ? figure 3-5 event counter (ec) operation timing is corrected. stationary type ? figure 3-6 use of timer 0 is corrected. vcr servo control ? figure 3-7 head switching signal (v-hsw) timing (pto00) is corrected. ? figure 3-19 timer 1 peripheral circuit is corrected. ? figure 3-27 use of timer for drum phase control (for recording) is corrected. ? figure 3-28 drum phase control timing (for recording) is corrected. third the m pd784928, 784928y subseries and the m pd784915b, 784916b are added. throughout document numbers of related documents are added or corrected. introduction chapter 1 outline of nec vcr servo microcontroller chapter 1 products is added. outline of nec vcr servo microcontroller products table 2-1 differences among m pd784915 subseries products is added. chapter 2 outline of m pd784915 subseries chapter 3 outline of m pd784928, 784928y subseries is added. chapter 3 outline of m pd784928, 784928y subseries
222 appendix revision history [memo]
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