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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1999 mos integrated circuit m m m m pd464318al, 464336al 4m-bit bi-cmos synchronous fast static ram 256k-word by 18-bit / 128k-word by 36-bit h s tl interfa c e / re g i s ter-re g i s ter / late write data sheet document no. m13508ej2v0dsj1 (2nd edition) date published december 2000 ns cp(k) printed in japan the mark ? ? ? ? shows major revised points. description the m pd464318al is a 262,144 words by 18 bits, and the m pd464336al is a 131,072 words by 36 bits synchronous static ram fabricated with advanced bi-cmos technology using n-channel memory cell. this technology and unique peripheral circuits make the m pd464318al and m pd464336al a high-speed device. the m pd464318al and m pd464336al are suitable for applications which require high-speed, low voltage, high- density memory and wide bit configuration, such as cache and buffer memory. these are packaged in a 119-pin plastic bga (ball grid array). features fully synchronous operation hstl input / output levels fast clock access time : 2.0 ns / 250 mhz, 2.3 ns / 225 mhz, 2.5 ns / 200 mhz asynchronous output enable control : /g byte write control : /sba (dqa1-9), /sbb (dqb1-9), /sbc (dqc1-9), /sbd (dqd1-9) common i/o using three-state outputs internally self-timed write cycle late write with 1 dead cycle between read-write user-configurable outputs : controlled impedance outputs or push-pull outputs boundary scan (jtag) ieee 1149.1 compatible 3.3 v (chip) / 1.5v (i/o) supply 119 bump bga package, 1.27 mm pitch, 14 mm x 22 mm sleep mode : zz(enables sleep mode, active high) ordering information part number access time clock frequency package m pd464318als1-a4 2.0 ns 250 mhz 119-pin plastic bga m pd464318als1-a44 2.3 ns 225 mhz m pd464318als1-a5 2.5 ns 200 mhz m pd464336als1-a4 2.0 ns 250 mhz m pd464336als1-a44 2.3 ns 225 mhz m pd464336als1-a5 2.5 ns 200 mhz
2 m m m m pd464318al, 464336al data sheet m13508ej2v0ds pin configurations /xxx indicates active low si gnal. 119-pin plastic bga (256k words by 18 bits pin assignment) [ m m m m pd464318als1 ] 7 654321 1234567 v dd q sa2 sa6 nc sa9 sa12 v dd qa v dd q sa12 sa9 nc sa6 sa2 v dd q nc nc sa16 nc sa17 nc nc b nc nc sa17 nc sa16 nc nc nc sa3 sa7 v dd sa10 sa13 nc c nc sa13 sa10 v dd sa7 sa3 nc nc dqa9 v ss zq v ss nc dqb1 d dqb1 nc v ss zq v ss dqa9 nc dqa8 nc v ss /ss v ss dqb2 nc e nc dqb2 v ss /ss v ss nc dqa8 v dd qdqa7 v ss /g v ss nc v dd qf v dd qnc v ss /g v ss dqa7 v dd q dqa6 nc v ss nc /sbb dqb3 nc g nc dqb3 /sbb nc v ss nc dqa6 nc dqa5 v ss nc v ss nc dqb4 h dqb4 nc v ss nc v ss dqa5 nc v dd qv dd v ref v dd v ref v dd v dd qj v dd qv dd v ref v dd v ref v dd v dd q dqa4 nc v ss kv ss dqb5 nc k nc dqb5 v ss kv ss nc dqa4 nc dqa3 /sba /k v ss nc dqb6 l dqb6 nc v ss /k /sba dqa3 nc v dd qnc v ss /sw v ss dqb7 v dd qm v dd qdqb7 v ss /sw v ss nc v dd q nc dqa2 v ss sa1 v ss nc dqb8 n dqb8 nc v ss sa1 v ss dqa2 nc dqa1 nc v ss sa0 v ss dqb9 nc p nc dqb9 v ss sa0 v ss nc dqa1 nc sa4 m2 v dd m1 sa14 nc r nc sa14 m1 v dd m2 sa4 nc zz sa5 sa8 nc sa11 sa15 nc t nc sa15 sa11 nc sa8 sa5 zz v dd q nc tdo tck tdi tms v dd qu v dd q tms tdi tck tdo nc v dd q 1 2 3 4 5 6 7 l n m r p t u d f e h g j k b c a 7 6 5 4 3 2 1 bottom view top view
3 m m m m pd464318al, 464336al data sheet m13508ej2v0ds pin name and functions [ m m m m pd464318als1] pin name description function v dd core power supply supplies power for ram core v ss ground v dd q output power supply supplies power for output buffers v ref input reference k, /k main clock input sa0 to sa17 synchronous address input dqa1 to dqb9 synchronous data input / output /ss synchronous chip select logically selects sram /sw synchronous byte write enable write command /sba synchronous byte "a" write enable write dqa1 to dqa9 /sbb synchronous byte "b" write enable write dqb1 to dqb9 /g asynchronous output enable asynchronous input zz asynchronous sleep mode enables sleep mode, active high zq output impedance control m1, m2 mode select selects operation mode note nc no connection tms test mode select (jtag) tdi test data input (jtag) tck test clock input (jtag) tdo test data output (jtag) note this device only supports single differential clock, r/r mode. (r/r stands for registered input/registered output.)
4 m m m m pd464318al, 464336al data sheet m13508ej2v0ds 119-pin plastic bga (128k words by 36 bits pin assignment) [ m m m m pd464336als1 ] 7 654321 1234567 v dd q sa2 sa5 nc sa9 sa12 v dd qa v dd q sa12 sa9 nc sa5 sa2 v dd q nc nc sa15 nc sa16 nc nc b nc nc sa16 nc sa15 nc nc nc sa3 sa6 v dd sa10 sa13 nc c nc sa13 sa10 v dd sa6 sa3 nc dqb8 dqb9 v ss zq v ss dqc9 dqc8 d dqc8 dqc9 v ss zq v ss dqb9 dqb8 dqb6 dqb7 v ss /ss v ss dqc7 dqc6 e dqc6 dqc7 v ss /ss v ss dqb7 dqb6 v dd qdqb5 v ss /g v ss dqc5 v dd qf v dd qdqc5 v ss /g v ss dqb5 v dd q dqb3 dqb4 /sbb nc /sbc dqc4 dqc3 g dqc3 dqc4 /sbc nc /sbb dqb4 dqb3 dqb1 dqb2 v ss nc v ss dqc2 dqc1 h dqc1 dqc2 v ss nc v ss dqb2 dqb1 v dd qv dd v ref v dd v ref v dd v dd qj v dd qv dd v ref v dd v ref v dd v dd q dqa1 dqa2 v ss kv ss dqd2 dqd1 k dqd1 dqd2 v ss kv ss dqa2 dqa1 dqa3 dqa4 /sba /k /sbd dqd4 dqd3 l dqd3 dqd4 /sbd /k /sba dqa4 dqa3 v dd qdqa5 v ss /sw v ss dqd5 v dd qm v dd qdqd5 v ss /sw v ss dqa5 v dd q dqa6 dqa7 v ss sa1 v ss dqd7 dqd6 n dqd6 dqd7 v ss sa1 v ss dqa7 dqa6 dqa8 dqa9 v ss sa0 v ss dqd9 dqd8 p dqd8 dqd9 v ss sa0 v ss dqa9 dqa8 nc sa4 m2 v dd m1 sa14 nc r nc sa14 m1 v dd m2 sa4 nc zz nc sa7 sa8 sa11 nc nc t nc nc sa11 sa8 sa7 nc zz v dd q nc tdo tck tdi tms v dd qu v dd q tms tdi tck tdo nc v dd q 1 2 3 4 5 6 7 l n m r p t u d f e h g j k b c a 7 6 5 4 3 2 1 bottom view top view
5 m m m m pd464318al, 464336al data sheet m13508ej2v0ds pin name and functions [ m m m m pd464336als1] pin name description function v dd core power supply supplies power for ram core v ss ground v dd q output power supply supplies power for output buffers v ref input reference k, /k main clock sa0 to sa16 synchronous address input dqa1 to dqd9 synchronous data input / output /ss synchronous chip select logically selects sram /sw synchronous byte write enable write command /sba synchronous byte "a" write enable write dqa1 to dqa9 /sbb synchronous byte "b" write enable write dqb1 to dqb9 /sbc synchronous byte "c" write enable write dqc1 to dqc9 /sbd synchronous byte "d" write enable write dqd1 to dqd9 /g asynchronous output enable asynchronous input zz asynchronous sleep mode enables sleep mode, active high zq output impedance control m1, m2 mode select selects operation mode note nc no connection tms test mode select (jtag) tdi test data input (jtag) tck test clock input (jtag) tdo test data output (jtag) note this device only supports single differential clock, r/r mode. (r/r stands for registered input/registered output.)
6 m m m m pd464318al, 464336al data sheet m13508ej2v0ds late write block diagram k /sba k /k /ss /sw /sba /sbb /sbc /sbd data in register write control logic address register write address register read comp. memory array data in data out mux output register /sw /sbc /sbb dq /sbd /g /k /ss sa0 to sa17 mux zz write clock genelator /g zz
7 m m m m pd464318al, 464336al data sheet m13508ej2v0ds programmable impedance / power up requirements an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow for the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a tolerance of 10 % is between 175 ohm and 350 ohm. periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. one evaluation occurs every 8 clock cycles and each evaluation may move the output driver impedance level only one step at a time towards the optimum level. the output driver has 64 discrete binary weighted steps. the impedance update of the output driver occurs when the sram is in hi-z. write and deselect operations will synchronously switch the sram into and out of hi-z, therefore, triggering an update. power up requirements for the sram are that v dd must be powered before or simultaneously with v dd q followed by v ref ; inputs should be powered last. the limitation on v dd q is that it must not exceed v dd by more than 0.4 v during power up. in order to guarantee the optimum internally regulated supply voltage, the sram requires 4 m s of power-up time after v dd reaches its operating range. to guarantee optimum output driver impedance after power up, the sram needs 520 clock cycles followed by a single low-z to hi-z transition at the end of 520 cycles.
8 m m m m pd464318al, 464336al data sheet m13508ej2v0ds synchronous truth table zz /ss /sw /sba /sbb /sbc /sbd mode dqa1 C 9dqb1 C 9dqc1 C 9dqd1 C 9 power lh not selected hi-z hi-z hi-z hi-z active llh read dout dout dout dout active lllllll write dindindindinactive l l l l h h h write din hi-z hi-z hi-z active l l l h l l l write hi-z din din din active hxxxxxxsl eep mode hi-z hi-z hi-z hi-z standby remark : dont care output enable truth table mode /g dq read l dout read h hi-z sleep (zz=h) x hi-z write (/sw=l) x hi-z deselect (/ss=h) x hi-z mode select (i/o) note1 m1 m2 mode v ss v dd single differential clock (k,/k), r/r mode note2 notes 1. this device only supports single differential clock, r/r mode. mode select pins(m1,m2) are to be tied to either v dd or v ss 2. r/r : registered input / registered output mode select (output buffer) zq mode notes izq rq controlled impedance push-pull output buffer mode 1 v dd push-pull output buffer mode 2 notes 1. see figure. 2. see figure. zq v dd zq rq (175 w rq 350 w)
9 m m m m pd464318al, 464336al data sheet m13508ej2v0ds electrical specifications absolute maximum ratings parameter symbol condition min. typ. max. unit note supply voltage v dd C0.5 +4 v 1 output supply voltage v dd q C0.5 +4 v 1 input voltage v in C0.5 v dd + 0.3 v 1 input / output voltage v i/o C0.5 v dd q + 0.3 v 1 operating temperature t j 5 110 c 2 storage temperature t stg C55 +125 c notes 1. C1.0 v min. (pulse width 10% tcyc) 2. t j = junction temperature caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t j = 5 to 110 c) parameter symbol conditions min. typ. max. unit core supply voltage v dd 3.15 3.3 3.45 v output buffer supply voltage v dd q 1.4 1.5 1.6 v input reference voltage v ref 0.60.750.9 v low level input voltage v il C0.3 note v ref C0.1 v high level input voltage v ih v ref +0.1 v dd q+0.3 v note C1.0 v min. (pulse width 10% tcyc) recommended ac operating conditions (t j = 5 to 110 c) parameter symbol conditions min. typ. max. unit input reference voltage v ref (rms) C5% +5% v low level input voltage v il C0.3 v ref C0.2 v high level input voltage v ih v ref +0.2 v dd q+0.3 v capacitance (t a = 25 c, f = 1 mhz) parameter note symbol test conditions max. unit input capacitance c in v in = 0 v 6 pf input / output capacitance c i/o v i/o = 0 v 7 pf note these parameters are sampled and not 100% tested.
10 m m m m pd464318al, 464336al data sheet m13508ej2v0ds dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol conditions min. typ. max. unit input leakage current i li v in = 0 to v dd C5 +5 m a dq leakage current i lo v i/o = 0 to v dd q, /ss = v ih or /g = v ih C5 +5 m a operating supply current i cc v in = v ih or v il , /ss = v il , zz = v il , m pd464318al 550 ma cycle = 250 mhz, idq = 0 ma m pd464336al 750 quiescent active power i cc2 v in = v ih or v il , /ss = v il , zz = v il , 200 ma supply current cycle = 4 mhz, idq = 0 ma sleep mode power supply i sbzz zz = v ih , all other inputs = v ih or v il 55 ma current cycle = dc, i dq = 0 ma power supply standby current i sbss v in = v ih or v il , /ss = v ih , zz = v il , m pd464318al 530 ma cycle=250 mhz, idq = 0 ma m pd464336al 730 output voltage on controlled impedance push-pull output buffer mode (vzq = izq rq) parameter symbol conditions min. typ. max. unit low level output voltage v ol i ol = (v dd q/2) / (rq/5) 10% v ss v dd q/2 v @v ol = v dd q / 2 (175 w < rq < 350 w ) high level output voltage v oh i oh = (v dd q/2) / (rq/5) 10% v dd q/2 v dd qv @v oh = v dd q / 2 (175 w < rq < 350 w ) output voltage on push-pull output buffer mode (vzq = v dd ) parameter symbol conditions min. typ. max. unit low level output voltage v ol i ol = +4 ma C 0.3 v high level output voltage v oh i oh = C 4 ma v dd qC0.3 C v ? ? ?
11 m m m m pd464318al, 464336al data sheet m13508ej2v0ds ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions input waveform (rise and fall time = 0.5 ns (20 to 80%)) v tt or v dd q / 2 0.25 v 1.25 v remarks 1. clock input differential voltage 2. clock input common mode voltage range output waveform v tt or v dd q / 2
12 m m m m pd464318al, 464336al data sheet m13508ej2v0ds single differential clock, registered input / registered output mode parameter symbol Ca4 (250 mhz) Ca44 (225 mhz) Ca5 (200 mhz) unit notes min. max. min. max. min. max. clock cycle time t khkh 4.0 C 4.4 C 5.0 C ns clock phase time t khkl / t klkh 1.5 C 1.5 C 1.5 C ns setup times address t avkh 0.5 C 0.5 C 0.5 C ns write data t dvkh write enable t wvkh chip select t svkh hold times address t khax 0.75 C 0.75 C 1.0 C ns write data t khdx write enable t khwx chip select t khsx clock access time t khqv C2.0C2.3C2.5ns1 k high to q change t khqx 0.7 C 0.7 C 0.7 C ns 2 /g low to q valid t glqv C2.0C2.3C2.5ns1 /g low to q change t glqx 0.7 C 0.7 C 0.7 C ns 2 /g high to q hi-z t ghqz 1.0 2.0 1.0 2.3 1.0 2.5 ns 2 k high to q hi-z (/sw) t khqz 1.0 2.5 1.0 2.8 1.0 3.0 ns 2 k high to q hi-z (/ss) t khqz2 1.0 2.5 1.0 2.8 1.0 3.0 ns 2 k high to q lo-z t khqx2 0.7 C 0.7 C 0.7 C ns /g high pulse width t ghgl 4.0 C 4.4 C 5.0 C ns 3 /g high to k high t ghkh 1.0 C 1.0 C 1.0 C ns 3 k high to /g low t khgl 2.5 C 2.5 C 2.5 C ns 3 sleep mode recovery t zzr 4.0 C 4.4 C 5.0 C ns 4 sleep mode enable t zze C4.0C4.4C5.0ns4 notes 1. see figure. (v tt =0.75 v, rq=250 w ) dq (output) z0 = 50 w 20 pf 50 w v tt 2. see figure. (v tt =0.75 v, rq=250 w ) dq (output) 5 pf 50 w v tt 3. controlled impedance push-pull output buffer mode only. 4. /ss must be high before sleep mode entry.
13 m m m m pd464318al, 464336al data sheet m13508ej2v0ds a qa qc qe qf qg bcde f gh i j k qi t khax t avkh t khkh t khkl t klkh t khsx t svkh t wvkh t khwx t ghqz t ghgl t glqx t glqv t khqz2 t khqv t khqx t khqx2 single differential clock, registered input / registered output mode (read operation) /k k address /ss /sw /g dq qb
14 m m m m pd464318al, 464336al data sheet m13508ej2v0ds l ql qo qp qq mnopq r s t uv t khax t avkh t khkh t khkl t klkh t khsx t svkh t wvkh t khwx t glqx t ghkh t glqv t khqz t khdx t dvkh t khqx2 single differential clock, registered input / registered output mode (write operation) /k k address /ss /sw /g dq dn qt ds t ghqz t khgl
15 m m m m pd464318al, 464336al data sheet m13508ej2v0ds a qa qc bcde f gh i j k t zze t zzr sleep mode /k k address /ss /zz dq qb l qj
16 m m m m pd464318al, 464336al data sheet m13508ej2v0ds jtag specifications the m pd464318al and m pd464336al support a limited set of jtag functions as in ieee standard 1149.1. test access port (tap) pins pin name pin assignments description tck 4 u test clock input. all input are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms 2 u test mode select. this is the command input for the tap controller state machine. tdi 3 u test data input. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is deter-mined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction. tdo 5 u test data output. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. remark the device does not have trst (tap reset). the test-logic reset state is entered while tms is held high for five rising edges of tck. the controller state is also reset on the sram power-up. jtag dc characteristics (t j = 5 to 110 c) parameter symbol conditions min. typ. max. unit notes jtag input high voltage v ih 2.2 v dd +0.3 v jtag input low voltage v il C0.3 +0.8 v jtag output high voltage v oh i oh = C8 ma 2.4 C v jtag output low voltage v ol i ol = 8 ma C0.4v
17 m m m m pd464318al, 464336al data sheet m13508ej2v0ds jtag ac test conditions (t j = 5 to 110 c) input waveform (rise / fall time = 1 ns (20 to 80 %)) output waveform output load (v tt =1.5 v) tdo z0 = 50 w 50 w v tt test points 1.5 v 1.5 v 0 v 3.0 v test points 1.5 v 1.5 v
18 m m m m pd464318al, 464336al data sheet m13508ej2v0ds jtag ac characteristics (t j = 5 to 110 c) parameter symbol conditions min. typ. max. unit note clock cycle time (tck) t thth 100 C ns clock phase time (tck) t thtl / t tlth 40 C ns setup time (tms / tdi) t mvth / t dvth 10 C ns hold time (tms / tdi) t thmx / t thdx 10 C ns tck low to tdo valid (tdo) t tlqv C20ns jtag timing diagram t thth t tlqv t tlth t thtl t mvth t thdx t dvth t thmx tck tms tdi tdo
19 m m m m pd464318al, 464336al data sheet m13508ej2v0ds scan register definition (1) register name description instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run-test/idle or the various data register state. the register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the rams tap to another device in the scan chain with as little delay as possible. id register the id register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. boundary register the boundary register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. several tap instructions can be used to activate the boundary register. the scan exit order tables describe which device bump connects to each boundary register location. the first column defines the bits position in the boundary register. the shift register bit nearest tdo (i.e., first to be shifted out) is defined as bit 1. the second column is the name of the input or i/o at the bump and the third column is the bump number. scan register definition (2) register name m pd464318al m pd464336al unit instruction register 3 3 bit bypass register 1 1 bit id register 32 32 bit boundary register 51 70 bit id register definition part number organization id [31:28] vendor revision no. id [27:12] part no. id [11:1] vendor id no. id [0] fix bit m pd464318al 256k x 18 xxxx 0110001011 000000 00010010000 1 m pd464336al 128k x 36 xxxx 0110101100 000000 00010010000 1
20 m m m m pd464318al, 464336al data sheet m13508ej2v0ds scan exit order [ m m m m pd464318al (256k words by 18 bits) ] [ m m m m pd464336al (128k words by 36 bits) ] bit no. signal name bump id bit no. signal name bump id bit no. signal name bump id bit no. signal name bump id 1 m2 5r 26 sa17 3b 1 m2 5r 36 sa16 3b 2 sa5 6t 27 nc 2b 37 nc 2b 3 sa0 4p 28 sa9 3a 2 sa0 4p 38 sa9 3a 29 sa10 3c 3 sa8 4t 39 sa10 3c 4 sa4 6r 30 sa13 2c 4 sa4 6r 40 sa13 2c 5 sa8 5t 31 sa12 2a 5 sa7 5t 41 sa12 2a 6 zz 7t 6 zz 7t 42 dqc9 2d 32 dqb1 1d 7 dqa9 6p 43 dqc8 1d 7 dqa1 7p 33 dqb2 2e 8 dqa8 7p 44 dqc7 2e 8 dqa2 6n 9 dqa7 6n 45 dqc6 1e 10 dqa6 7n 46 dqc5 2f 34 dqb3 2g 11 dqa5 6m 47 dqc4 2g 9 dqa3 6l 12 dqa4 6l 48 dqc3 1g 13 dqa3 7l 49 dqc2 2h 35 dqb4 1h 14 dqa2 6k 50 dqc1 1h 10 dqa4 7k 36 /sbb 3g 15 dqa1 7k 51 /sbc 3g 11 /sba 5l 37 zq 4d 16 /sba 5l 52 zq 4d 12 /k 4l 38 /ss 4e 17 /k 4l 53 /ss 4e 13 k 4k 39 nc 4g 18 k 4k 54 nc 4g 14 /g 4f 40 nc 4h 19 /g 4f 55 nc 4h 41 /sw 4m 20 /sbb 5g 56 /sw 4m 21 dqb1 7h 57 /sbd 3l 15 dqa5 6h 22 dqb2 6h 58 dqd1 1k 16 dqa6 7g 42 dqb5 2k 23 dqb3 7g 59 dqd2 2k 43 dqb6 1l 24 dqb4 6g 60 dqd3 1l 17 dqa7 6f 25 dqb5 6f 61 dqd4 2l 18 dqa8 7e 44 dqb7 2m 26 dqb6 7e 62 dqd5 2m 45 dqb8 1n 27 dqb7 6e 63 dqd6 1n 28 dqb8 7d 64 dqd7 2n 19 dqa9 6d 29 dqb9 6d 65 dqd8 1p 20 sa2 6a 46 dqb9 2p 30 sa2 6a 66 dqd9 2p 21 sa3 6c 47 sa11 3t 31 sa3 6c 67 sa11 3t 22 sa7 5c 48 sa14 2r 32 sa6 5c 68 sa14 2r 23 sa6 5a 49 sa1 4n 33 sa5 5a 69 sa1 4n 24 nc 6b 50 sa15 2t 34 nc 6b 25 sa16 5b 51 m1 3r 35 sa15 5b 70 m1 3r
21 m m m m pd464318al, 464336al data sheet m13508ej2v0ds jtag instructions instructions description extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. extest is not implemented in this device. therefore this device is not 1149.1 compliant. nevertheless, this rams tap does respond to an all zeros instruction, as follows. with the extest (000) instruction loaded in the instruction register the ram responds just as it does in response to the sample instruction, except the ram output are forced to hi-z any time the instruction is loaded. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. bypass the bypass instruction is loaded in the instruction register when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample sample is a standard 1149.1 mandatory public instruction. when the sample instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable input will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. this functionality is not standard 1149.1 compliant. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (hi-z) and the boundary register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. jtag instruction cording ir2 ir1 ir0 instruction note 0 0 0 extest 1 0 0 1 idcode 0 1 0 sample-z 1 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 bypass 1 1 1 bypass note 1. tristate all data drivers and capture the pad values into a serial scan latch.
22 m m m m pd464318al, 464336al data sheet m13508ej2v0ds tap controller state diagram disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a 1 k resistor. tdo should be left unconnected. test-logic-reset run-test / idle select-dr-scan capture-dr capture-ir shift-dr exit1-dr pause-dr exit2-dr update-dr update-ir exit2-ir pause-ir exit1-ir shift-ir select-ir-scan 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 10 10 11 1 0 1 1 0 1 0 11
23 m m m m pd464318al, 464336al data sheet m13508ej2v0ds test logic operation (instruction scan) tck controller state tdi tms tdo test-logic-reset run-test/idle select-dr-scan select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir shift-ir exit1-ir update-ir run-test/idle idcode instruction register state new instruction output inactive output from instruction register output from instruction register
24 m m m m pd464318al, 464336al data sheet m13508ej2v0ds test logic operation (data scan) tck controller state tdi tms tdo run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr shift-dr exit1-dr update-dr test-logic-reset instruction instruction register state idcode output inactive output from instruction register output from instruction register run-test/idle select-dr-scan select-ir-scan
25 m m m m pd464318al, 464336al data sheet m13508ej2v0ds package drawing 119 pin plastic bga item millimeters inches p119s1-r4 a 22.00.2 0.8660.008 b 19.5 0.768 g 0.60.1 0.024 +0.004 C0.005 h 0.56 0.022 i 1.460.1 0.057 c 12.0 0.472 d 14.00.2 0.5510.008 e 0.84 0.033 f 1.27 (t.p.) 0.05 (t.p.) j 2.30 max. 0.091 k 0.15 0.006 l 0.780.1 0.031 p c0.7 c0.028 r25 25 s 1.25 0.049 t 1.0 0.039 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u c a b s t d j i h g e f k l r +0.005 C0.004 +0.004 C0.005 p
26 m m m m pd464318al, 464336al data sheet m13508ej2v0ds recommended soldering conditions please consult with our sales offices for soldering conditions of the m pd464318al and m pd464336al. type of surface mount device m pd464318als1: 119-pin plastic bga m pd464336als1: 119-pin plastic bga
27 m m m m pd464318al, 464336al data sheet m13508ej2v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd464318al, 464336al m8e 00. 4 the information in this document is current as of december, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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