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QLU22108-PT280C device data sheet 1 ? ? QLU22108-PT280C device data sheet utopia level 2 to 1 multiplexer 1.0 utopia level 2/1 multiplexer core features implements an utopia l2 slave and two to four utopia l1 masters providing a solution to aggregate utopia level 1 slave devices to a level 2 master compliant with atm-forum af-phy-0039.000 (l evel 2) and af-phy-0017.000 (level 1) implements 8-bit data busses level 2 interface implements mphy mo de with direct status indication round robin port arbitration independent for egress (tx) and ingress (rx) data pathes level 2 interface meets 50mhz performance offering up to 400mbps cell rate transfers level 1 interface meets 25mhz performance o ffering up to 200mbps cell rate transfers per port single chip solution with up to 3 east ports for improved system integration supports cell level transfer mode cell and clock rate decoup ling with on chip fifos up to 1 kbyte of on chip fifo per data direction integrated management interface and built-in errored cell discard atm cell size programmable via external pins from 16 to 128 bytes level 2 mphy address programmable via external pins optional utopia parity generation/che cking enable/disable via external pin built in jtag port (ieee1149 compliant) simulation model available for sy stem level verification (contact quicklogic for details) solution also available as fl exible soft-ip core, delivered with a full device modelization and verification testbenches
2 www.quicklogic.com ? 2001 quicklogic corporation QLU22108-PT280C device data sheet 2.0 utopia overview the utopia (universal test & operations phy interface for atm) interface is defined by the atm forum to provide a standard inte rface between atm devices and atm phy or sar (segmentation and re-assembly) devices. figure 1: utopia reference model the utopia standard defines a full duplex bus interface with a master/slave paradigm. the slave interface responds to the requests from the master. the master performs phy arbitration and initiates data transf ers to and from the slave device. the atm forum has standardized the utopia le vels 1 (l1) to 3 (l3). each level extends the maximum supported interface speed from oc3, 155mbps (l1) over oc12, 622mbps (l2) to 3.2gbit/s (l3). the following table 1 gives an overview of the main differences in these three levels. utopia level 1 implements an 8-bit interfac e running at up to 25mhz. level 2 adds a 16 bit interface and increases the speed to 50mhz . level 3 extends the interface further by a 32 bit word-size and speeds up to 104mhz pr oviding rates up to 3.2 gbit/s over the interface. table 1: utopia level differences utopia level interface width max. interface speed theoretic (typical) throughput 1 8-bit 25 mhz 200 mbps (typ. oc3 155 mbps) 2 8-bit, 16-bit 50 mhz 800 mbps (typ. oc12 622 mbps) 3 8-bit, 32-bit 104 mhz 3.2 gbps (typ. oc48 2.5 gbps)
QLU22108-PT280C device data sheet 3 QLU22108-PT280C device data sheet in addition to the diffe rences in throughput, utopia level 2 uses a shared bus offering to physically share a single interface bus between one master and up to 31 slave devices (multi-phy or mphy operation). this allows the implementation of aggregation units that multiplex several slave devices to a single ma ster device. the level 1 and level 3 are point- to-point only, whereas level 1 has no notion of multiple slaves. level 3 still has the notion of multiple slaves, but they must be implemen ted in a single physical device connected to the utopia interface. 3.0 utopia l2 slave to l1 master multiplexer application utopia level 2 offers the notion of multiple phys (mphy) and a shared bus topology to connect several phy devices to a single at m layer device, or use phy devices with multiple ports. the l2 slave to l1 master multiplexer implem ents the necessary interfaces enabling to connect multiple level 1 phy devices to a level 2 topology. the multiplexer itself implements two or more ports and aggr egates them on the level 2 interface. as utopia level 2 allows for higher speed, at least two level 1 devices can be aggregated into a single level 2 interface without exc eeding bandwidth. a bus extension to 16 bit on the l2 side can enable up to four level 1 devices without exceedin g the level 2 interface bandwidth. figure 2: utopia 2 port multiplexer example
4 www.quicklogic.com ? 2001 quicklogic corporation QLU22108-PT280C device data sheet 4.0 application figure 3: l2 to l1 multiplexer data flows from the west side tx interface to the corresponding tx port on the east side of the multiplexer and the rx port s to the rx interface accordingly. all ports are served in a round-robin fashion, whereas the tx and rx sides are decoupled.
QLU22108-PT280C device data sheet 5 QLU22108-PT280C device data sheet 5.0 core pinout on the utopia interfaces, the core implements all the required utopia signals and provides all the utopia optional signals (indicated by an 'o' in the following tables). the optional utopia signals are activated during the core configuration and inactive utopia signals should be left unconnected (outpu ts) or tied to a zero logic le vel (inputs) as specified in the following tables. in addition to the utopia interface signals, error indication signals are available for error monitoring or statistics. an e rror indication always shows that a cell has been discarded by the multiplexer. possible errors are parity or cell-length errors on th e receive interface of the corresponding utopia interfaces. all utopia interfaces work in the same tran sfer mode (cell level). a mix is not possible. to identify the sides of the core the noti on "west" and "east" for the corresponding interfaces is used. figure 4: l2 to l1 multiplexer top entity 5.1 signal descriptions table 2: global signal pin mode description reset in active high chip reset
6 www.quicklogic.com ? 2001 quicklogic corporation QLU22108-PT280C device data sheet note: wtx_.. signals are sampled with west tran smit clock (wtxclk). etx_.. signals are sampled with west receive clock (wrxclk). note: (o) indicates optional signals. table 3: device management interface pin mode description wtx_err out transmit error indication on west interface. when driven high, indicates that an errored cell (wrong parity or wrong length) was received from the device connected to the west interface and is discarded. wtx_err_stat(1:0) out transmit error status information for west interface. when wtx_err is driven, indicates the error status of the discarded cell: ? wtx_err_stat(0) : when set to '1' indica tes that a cell is discarded because of a parity error. wtx_err_stat(1) : when set to '1' indicates that a cell is discarded because it has a wrong length (consecutive assertion of ut_tx_soc on the utopia interface within less than a complete cell time). erx_err(n) out receive error indication on east interf ace port n (n=0..3). when driven high, indicates that an errored cell (wrong par ity or wrong length) was received from the device connected to the corresponding east interface port. erx_err_stat (2n+1:2n)) out receive error status information for east receive interface port n (n=0..3). when etx_err is driven, indicates the er ror status of the discarded cell: etx_err_stat(2n) : when set to '1' indica tes that a cell is discarded because of a parity error. etx_err_stat(2n+1) : when set to '1' indi cates that a cell is discarded because it has a wrong length (consecutive assertion of ut_tx_soc on the utopia interface within less than a complete cell time). table 4: west utopia level 2 slave transmit interface pin mode description wtxclk in 50mhz transmit byte clock. the core samples all utopia transmit signals on txclk rising edge. wtxdata[7:0] in transmit data bus. the width of the data bus is be 8 bit. n is the msb. wtxprty(o) in transmit data bus parity. standard odd or non-standard even parity can be optionally checked by the connected slave. when the parity check is disabled during t he core configuration, or not used in the design, the pin txpr ty should be tied to '0'. wtxsoc in transmit start of cell. asserted by the mast er to indicate that the current word is the first word of a cell. wtxenb in active low transmit data transfer enable. wtxclav[0] out cell buffer available. asserted in octet level transfers to indicate to the master that the fifo is almost full (active low) or, in cell level transfers, to indicate to the master that the phy port fifo has space to accept one cell. wtxclav[3:1] out extra fifo full / cell buffer available. in mphy mode and when direct status indication is selected during the core configuration, one txclav signal is implemented per phy port. the maximum nu mber of clav signals is limited to four. wtxaddr[4:0] in utopia transmit address. when the core operates in mphy mode, address bus used during polling and slave port selection. bit 4 is the msb.
QLU22108-PT280C device data sheet 7 QLU22108-PT280C device data sheet note: (o) indicates optional signals. table 5: west utopia level 2 slave receive interface pin mode description wrxclk in 50mhz receive byte clock. the core sa mples all utopia rece ive signal s on rxclk rising edge. wrxdata[7:0] out receive data bus. wrxprty (o) out receive data bus parity. standard odd or non standard even parity can be optionally generated by the utopia slave core. when the parity generation is disabled during the core configuration, the pin rxprty can be let unconnected. wrxsoc out receive start of cell. asserted to indicate that the current word is the first word of a cell. wrxenb in active low transmit data transfer enable. wrxclav[0] out cell buffer available. asserted in octet level transfers to indicate to the master that the fifo is almost empty (active low) or, in cell level transfers, to indicate to the master that the phy port fifo has space one cell available in the fifo. wrxclav[3:1] out extra fifo full / cell buffer available. in mphy mode and when direct status indication is selected, one rxclav si gnal is implemented per phy port. the maximum number of clav signals is limited to four. not used and not available. wrxaddr(4:0) in utopia receive address. when the core operates in mphy mode, address bus used during polling and slave port selection. bit 4 is the msb. table 6: east utopia level 1 master transmit interface (per port, n=0..3) pin mode description etxclk(n) in 25mhz transmit byte clock. the core samples all utopia transmit signals on txclk rising edge. etxdata(n)[7:0] out transmit data bus. erxprty(n) (o) out transmit data bus parity. standard odd or non-standard even parity can be optionally checked by the connected slave. when the parity check is disabled during t he core configuration, or not used in the design, the pin txprty should be left open. erxsoc(n) out transmit start of cell. asserted by the mast er to indicate that the current word is the first word of a cell. etxenb(n) out active low transmit data transfer enable. etxclav(n) in cell buffer available. asserted in octet level transfers to indicate to the master that the fifo is almost full (active low) or, in cell level transfers, to indicate to the master that the phy port fifo has space to accept one cell.
8 www.quicklogic.com ? 2001 quicklogic corporation QLU22108-PT280C device data sheet the configuration pins are not intended for change during operation. they are usually board wired to configure the device for operation. table 7: east utopia level 1 master receive interface (per port, n=0..3) pin mode description erxclk(n) in 25mhz receive byte clock. the core samples all utopia receive signals on rxclk rising edge. erxdata(n)[7:0] in receive data bus. erxprty(n) (o) in receive data bus parity. standard odd or non standard even parity can be optionally generated by the utopia slave core. when the parity generation is disabled dur ing the core configuration, the pin rxprty can be let unconnected. erxsoc(n) in receive start of cell. asserted to indicate that the current word is the first word of a cell. erxenb(n) out active low transmit data transfer enable. erxclav(n) in cell buffer available. asserted in octet level transfers to indicate to the master that the fifo is almost empty (active low) or, in cell level transfers, to indicate to the master that the phy port fifo has space one cell available in the fifo. table 8: device configuration pins pin mode description waddr[4:0] in programs the utopia l2 slave address used on the west interfaces (tx and rx). prty_en in enable parity checking on the utopia interface. if disabled (tied to 0), the wrx_err_st at(0) signal can be ignored and left open and the rx parity input should be tied to 0. also the tx parity pins can be left open. cellsize[7:0] in define cellsize: sets the size in bytes of a cell. binary value to be set usually by board wiring
QLU22108-PT280C device data sheet 9 QLU22108-PT280C device data sheet 6.0 global signal distribution the externally provided utopia transmit and receive clocks are connected to global resources to provide low skew and fast chip le vel distribution. in both data directions, the two corresponding utopia interfaces are decoupled by asynchronous fifos. therefore each interface runs completely independently each at its own tx and rx clocks which typically are up to 50 mhz on the west and up to 25 mhz on the east interface. the error indications of the two receive interfaces are always sampled within the west clock domains. the errors of the east rx interface is available on the erx_err signal, which is handled using the west clock domain (wrxclk). the west tx (receiving) error is directly derived from the west tx block (wtxclk). figure 5: slave/master mu ltiplexer clock distribution (one east port shown)
10 www.quicklogic.com ? 2001 quicklogic corporation QLU22108-PT280C device data sheet 7.0 functional description ? utopia interface the utopia multiplexer implements a single port on the west and separate single-phy interfaces on the east. the west interface (utopia l2) operates in mp hy mode with direct status indication. it implements a single clav signal per direction and port (t/rxclav[x]) and the address bus to select the device within a shared bus topology. the east interface (l1) has no notion of mphy. it has a single clav signal and no address bus. 7.1 utopia interface single phy transmit interface (l1) the transmit interface is controlled by the master. the transmit interface has data flowing in the same direction as the atm enable ut_tx_enb . the atm transmit block generates all outp ut signals on the rising edge of the ut_txclk . transmit data is transferred from the master to slave via the following procedure. the slave indicates it can accept data using the ut_txclav signal, then the master drives data onto u t_txdat and asserts ut_txenb . the slave controls the flow of data via the ut_txclav signal. 7.1.1 cell level transfer - single cell the slave asserts ut_txclav 1 when it is capable of accepting the transfer of a whole cell. the master asserts ut_txenb (low) to indicates that it drives valid data to the slave 2 . together with the first octet of a cell, the master device asserts ut_txsoc for one clock cycle 3 . to ensure that the master does not cause transmit overrun, the slave deasserts ut_txclav at least 4 cycles before the end of a cell if it cannot accept the immediate transfer of the subsequent cell 4 . the master can pause the cell transfer by de-asserting ut_txenb 5 . to complete the transfer to the slave, the master de-asserts ut_tx_enb 6 . figure 6: single cell transfer ? cell level transfer
QLU22108-PT280C device data sheet 11 QLU22108-PT280C device data sheet 7.1.2 cell level transfer ? back to back cells when, during a cell transfer, the slave is able to receive a subsequent cell, the master can keep ut_txenb asserted between two cells 1 and asserts ut_txsoc , to start a new cell transfer, immediately after the la st octet of the previous cell 2 . figure 7: back to back cell transfer ? cell level transfer 7.2 utopia interface single phy receive interface (l1) the receive interface is controlled by the master. the receive interface has data flowing in the opposite direction to the master enable ut_rxenb . receive data is transferred from the slave to master via the following procedure. the slave indicates it has valid data, then the master asserts ut_rxenb to read this data from the slave. the slave indicates valid data (the reby controlling the data flow) via the ut_rxclav signal. 7.2.1 cell level transfer - single cell the slave asserts ut_rx_clav when it is ready to send a complete cell to the master device 1 . the master interface asserts ut_rxenb to start the cell transfer. the slave samples ut_rxenb and starts driving data 2 . the slave asserts ut_rxsoc together with the cell first word to indicate the start of a cell 3 . the master can pause a transfer by de-asserting ut_rxenb 4 . the slave samples high ut_rxenb and stops driving data 5 . to resume the transfer, the master re-asserts ut_rxenb 6 . the slave samples low ut_rxenb and starts driving valid data 7 . the master drives ut_txenb high one before the expected end of the current cell if the slave has no more cell to transfer 8 . the slave de-asserts ut_rxclav to indicate that no new cell is available 9 .
12 www.quicklogic.com ? 2001 quicklogic corporation QLU22108-PT280C device data sheet figure 8: single cell transfer - cell level transfer 7.2.2 cell level transfer - back to back cells if the master keeps ut_rxenb asserted at the end of a cell transfer 1 and if the slave has a new cell to send, the slave keeps ut_rxclav asserted 2 and immediately drives the new cell asserting ut_rxsoc to indicate the start of a new cell 3 . figure 9: back to back cells transfer - cell level transfer note: if the master keeps ut_rxenb asserted at the end of a packet and if the slave does not have a new cell available, the slave de-asserts ut_rxclav and the data of the bus ut_rxdat are invalid.
QLU22108-PT280C device data sheet 13 QLU22108-PT280C device data sheet 7.3 utopia interface mphy transmit (l2) when operating in mphy mode, the master ch ecks, (typically in a round robin fashion) the status of all the slave ports. two options are defined by the utopia standard: polled status indication with all the phy ports using a shar ed single clav signal to report their status to the master direct status indication with one clav implemented per phy port or per utopia group. in mphy mode only one transmit phy port is selected at a time for data transfers but the master continuously polls the stat us of the slave's other phy ports. the bridge implements the second approach, using di rect status indication. 7.3.1 mphy operation with direct status for each phy port, a status signal ut_txclav is permanently available. the utopia bus then supports up to four phy ports, ea ch using one clav signal (slave port ut_txclav_dir(n) ). for each port independently, ut_txclav_dir(n) is asserted when enough space is available for a complete ce ll in the port fifo 1 and ut_txclav_dir(n) is de-asserted when the corresponding port fifo cannot receive the subsequent cell 2 . status signals and cell transfers are independen t of each other for each port. no address information is needed to obtain status inform ation. address information must be valid only for selecting a phy port prior to one or multiple cell transfers. to select a port, the master de-asserts ut_txenb 3 , puts address port on ut_txaddr(4:0) 4 , the port is selected by the slave when ut_txenb goes low (re-asserted by the master) 5 . figure 10: mphy transmit - direct status indication as defined for single clav utopia transmit, th e master can pause a transfer and implicitly re-select a phy port.
14 www.quicklogic.com ? 2001 quicklogic corporation QLU22108-PT280C device data sheet 7.4 utopia interface mphy receive (l2) when operating in mphy mode, the master ch ecks, (typically in a round robin fashion) the status of all the slave ports. two options are defined by the utopia standard: polled status indication with al l the phy ports using a signal clav signal to report their status to the master direct status indication with one clav implemented per phy port or per utopia group. in mphy mode only one receive phy port is selected at a time for data transfers but the master can continuously polls th e status of the slave phy ports. 7.4.1 mphy operation with direct status for each phy port, a status signal ut_rxclav_dir(n) is permanently available. for each port independently, ut_rxclav_dir(n) is asserted when the corresponding phy port has a cell available in its fifo 1 and ut_rxclav_dir(n) is de-asserted when the corresponding port fifo cannot transm it a complete cell to the master 2 . status signals and cell transfers are independent of each other for each port. no address information is needed to obtain status inform ation. address information must be valid only for selecting a phy port prior to one or multiple cell transfers. to select a port, the master de-asserts ut_rxenb 3 , puts address port on ut_rxaddr(4:0) 4 , the port is selected by the slave when ut_rxenb goes low (re-asserted by the master) 5 . figure 11: mphy receive - direct status indication
QLU22108-PT280C device data sheet 15 QLU22108-PT280C device data sheet 8.0 core management and error handling on egress, the core is designed to handle and report utopia errors su ch as parity error or wrong cell length. errored cells are discarded with an error status indication provided to the user phy application. when an errored cell is received on the utopia interface, the core discards the complete cell and provides a cell discard indication to the user phy application (signal eg_err(n) asserted) 1 together with a cell discard status (signal eg_err_stat(1:0) ) 2 . note: eg_err is routed to the corresponding wtx_err and etx_err respectively (see figure 4). figure 12: cell discard indication the signals are sampled on the corresponding clocks from the west interface: erx_... sampled with wrxclk (west receive clock) wtx_... sampled with wtxclk (west transmit clock) table 9: error status word bit coding error status bit name description 0 parity_err valid when wtx/etx_err is asserted. if set to one indicates that a cell is discarded wi th a parity error decoded by the core. 1 length_err valid when wtx/etx_err is asserted. if set to one indicates that a cell is discarded with a cell length error detected on the utopia interface.
16 www.quicklogic.com ? 2001 quicklogic corporation QLU22108-PT280C device data sheet 9.0 complexity and performance summary 9.1 timing parameters definition figure 13: tco timing parameter definition figure 14: tsu timing parameter definition
QLU22108-PT280C device data sheet 17 QLU22108-PT280C device data sheet note: timing model "worst" case is used. 10.0 device pinout 10.1 signals overview the table summarizes all signals. if less than 4 ports are implemented, the port numbers n vary from 0 to maximum port available. table 10: 8-bit utopia interface timing characteristics parameter typ max unit tco 7.5 7.0 ns tsu 2.5 2.4 ns wrxclk 66 mhz wtxclk 69 mhz erxclk 62 mhz etxclk 62 mhz minimum reset time 50 ns table 11: signal overview table signals description wrxclk, wrxclav, wrxenb*, wrxdat, wrxsoc, wrxaddr west utopia l2 receive interface. wtxclk, wtxclav, wtxenb*, wtxdata, wtxsoc, wtxaddr west utopia l2 transmit interface. wtx_err, wtx_err_stat west interface error indication (sam pled with wtxclk). erxclk[n], erxclav[n], erxenb[n]*, erxsoc[n], erxdatan[7:0] east utopia l1 receive interface. port n (n=0..3)note: the data port names are not indexed, instead, explicitly named erxdata0.. erxdata3 each consisting of 8 pins. etxclk[n], etxclav[n], etxenb[n]*, etxsoc[n], etxdatan[7:0] east utopia l1 transmit interface. port n (n=0..3) note: the data port names are not indexed, instead, explicitly named erxdata0.. erxdata3 each consisting of 8 pins. unused etxdatn[] signals of non- existing ports should be left open. erx_err[0], erx_err_stat[1:0] east interface er ror indication port 0 (sampled with wrxclk). erx_err[1], erx_err_stat[3:2] east interface error indication port 1 (sampled with wrxclk). erx_err[2], erx_err_stat[5:4] east interface er ror indication port 2 (sampled with wrxclk). erx_err[3], erx_err_stat[7:6] east interface error indication port 3 (sampled with wrxclk). prty_en, cellsize, waddr configuration pins to be board wired. usual values for waddr are between 0 and 3. reset active high device reset
18 www.quicklogic.com ? 2001 quicklogic corporation QLU22108-PT280C device data sheet *: active low signal gnd ground vcc device power 2.5 v clk(x) unused clock inputs should be tied to gnd ioctrl(x) vccio(x) io power 3.0 v inref(x) connect to gnd pllrst(x) connect to gnd or vcc pllout(x) connect to gnd or vcc vccpll(x) gndpll(x) tck, trstb jtag signals. connect to gnd tms, tdi jtag signals. connect to vcc tdo jtag signal. leave open iov nc not connected. should be left open table 11: signal overview table (continued) signals description
QLU22108-PT280C device data sheet 19 QLU22108-PT280C device data sheet 10.2 280 pin fpbga device diagram figure 15: 280 pin bottom view qlu22108 -pt280c
20 www.quicklogic.com ? 2001 quicklogic corporation QLU22108-PT280C device data sheet 10.3 280 pin fpbga pinout table table 12: 280 pin fpbga pinout table pin function pin function pin function pin function pin function a1 pllout3 c19 cellsize[1] g17 etxdat1[4] n4 i/o u2 wtxclav[0] a2 gndpll0 d1 i/o g18 etxdat1[5] n5 vcc u3 vccpll3 a3 cellsize[7] d2 i/o g19 etxdat1[6] n15 vcc u4 wtxclav[1] a4 reset d3 etxdat3[6] h1 i/o n16 etxprty[0] u5 vccio a5 etxdat2[0] d4 etxdat3[7] h2 i/o n17 etxsoc[0] u6 inref a6 ioctl d5 prty_en h3 i/o n18 ioctl u7 wtxdat[0] a7 etxdat2[1] d6 i/o h4 i/o n19 ioctl u8 wtxdat[1] a8 etxdat2[2] d7 i/o h5 vcc p1 i/o u9 vccio a9 etxdat2[3] d8 i/o h15 vcc p2 i/o u10 wtxclk a10 etxclk[1] d9 etxclk[0] h16 vcc p3 ioctl u11 vccio a11 erxdat1[1] d10 cellsize[2] h17 etxdat1[7] p4 inref u12 wrxdat[2] a12 erxdat1[2] d11 cellsize[3] h18 etxclav[1] p5 vcc u13 wrxdat[3] a13 erxdat1[3] d12 cellsize[4] h19 etxenb[1] p15 gnd u14 ioctl a14 ioctl d13 inref j1 i/o p16 erxdat0[0] u15 vccio a15 erxdat1[4] d14 cellsize[5] j2 i/o p17 erxdat0[1] u16 wrxdat[4] a16 erxdat1[5] d15 cellsize[6] j3 vccio p18 erxdat0[2] u17 (floating) a17 erxdat1[6] d16 erxdat0[7] j4 i/o p19 erxdat0[3] u18 pllrst2 a18 pllrst1 d17 erxclav[0] j5 gnd r1 i/o u19 wrxdat[5] a19 gnd d18 erxenb[0] j15 vcc r2 i/o v1 pllout2 b1 pllrst0 d19 erxprty[0] j16 etxdat0[1] r3 vccio v2 gndpll3 b2 gnd e1 i/o j17 vccio r4 i/o v3 gnd b3 etxdat2[4] e2 i/o j18 etxprty[1] r5 gnd v4 wtxdat[2] b4 etxdat2[5] e3 vccio j19 etxsoc[1] r6 gnd v5 wtxdat[3] b5 etxdat2[6] e4 i/o k1 vcc r7 vcc v6 ioctl b6 inref e5 gnd k2 tck r8 vcc v7 wtxdat[4] b7 etxdat2[7] e6 vcc k3 i/o r9 gnd v8 wtxdat[5] b8 etxdat3[0] e7 vcc k4 i/o r10 gnd v9 wtxdat[6] b9 tms e8 vcc k5 gnd r11 vcc v10 clk(1) b10 erxclk[1] e9 vcc k15 gnd r12 vcc v11 wrxclk b11 erxdat1[7] e10 gnd k16 etxdat0[2] r13 vcc v12 wrxdat[6] b12 erxclav[1] e11 gnd k17 erxdat1[0] r14 vcc v13 wrxdat[7] b13 ioctl e12 vcc k18 etxdat0[3] r15 gnd v14 inref b14 erxenb[1] e13 vcc k19 trstb r16 erxdat0[4] v15 wrxenb b15 erxprty[1] e14 gnd l1 i/o r17 vccio v16 wrxprty b16 erxsoc[1] e15 gnd l2 i/o r18 erxdat0[5] v17 wrxsoc b17 vccpll1 e16 erxsoc[0] l3 vccio r19 erxdat0[6] v18 gndpll2 b18 gndpll1 e17 vccio l4 i/o t1 i/o v19 gnd b19 pllout0 e18 inref l5 vcc t2 i/o w1 gnd c1 etxdat3[1] e19 ioctl l15 gnd t3 wtx_err w2 pllrst3 c2 vccpll0 f1 inref l16 etxdat0[4] t4 wtx_err_stat[0] w3 wtxdat[7] c3 etxdat3[2] f2 ioctl l17 vccio t5 wtx_err_stat[1] w4 wtxenb c4 etxdat3[3] f3 i/o l18 etxdat0[5] t6 ioctl w5 wtxprty c5 vccio f4 i/o l19 etxdat0[6] t7 wtxaddr[0] w6 wtxsoc c6 ioctl f5 gnd m1 i/o t8 wtxaddr[1] w7 wrxaddr[0] c7 etxdat3[4] f15 vcc m2 i/o t9 wtxaddr[2] w8 wrxaddr[1] c8 etxdat3[5] f16 ioctl m3 i/o t10 wtxaddr[3] w9 tdi c9 vccio f17 etxdat1[0] m4 i/o t11 pllin1 w10 pllin2 c10 erxclk[0] f18 etxdat1[1] m5 vcc t12 wrxaddr[2] w11 erx_err[0] c11 vccio f19 etxdat1[2] m15 vcc t13 wrxaddr[3] w12 erx_err_stat[0] c12 waddr[0] g1 i/o m16 inref t14 wrxaddr[4] w13 erx_err_stat[1] c13 waddr[1] g2 i/o m17 etxdat0[7] t15 wrxclav[0] w14 ioctl c14 waddr[2] g3 ioctl m18 etxclav[0] t16 wrxclav[1] w15 erx_err[1] c15 vccio g4 i/o m19 etxenb[0] t17 vccpll2 w16 erx_err_stat[2] c16 waddr[3] g5 vcc n1 ioctl t18 wrxdat[0] w17 erx_err_stat[3] c17 waddr[4] g15 vcc n2 i/o t19 wrxdat[1] w18 etxdat0[0] c18 cellsize[0] g16 etxdat1[3] n3 i/o u1 wtxaddr[4] w19 pllout1
QLU22108-PT280C device data sheet 21 QLU22108-PT280C device data sheet 11.0 references atm forum, utopia level 1, af-phy-0017.000, 1994 atm forum, utopia level 2, af-phy-0039.000, 1995 12.0 contact quicklogic corp. tel : 408 990 4000 (us) : + 44 1932 57 9011 (europe) : + 49 89 930 86 170 (germany) : + 852 8106 9091 (asia) : + 81 45 470 5525 (japan) e-mail : info@quicklogic.com internet : www.quicklogic.com

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