hy5dv651622t 4 banks x 1m x 16bit double data rate sdram this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.1/apr.01 description the hynix hy5dv651622 is a 67,108,864-bit cmos double data rate(ddr) synchronous dram, ideally suited for the point to point applications which require high bandwidth. hy5dv651622 is organized as 4 banks of 1,048,576x16. hy5dv651622 offers fully synchronous operations referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on the rising edges of the clock(falling edges of the clk ), data(dq), data strobes(ldqs/udqs) and write data masks(ldm/udm) inputs are sampled on both rising and falling edges of it. the data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. mode register set options include the length of pipeline ( cas latency of 2 / 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 2 / 4 / 8), and the burst count sequence(sequential or interleave). because data rate is doubled through reading and writing at both rising and falling edges of the clock, 2x higher data bandwidth can be achieved than that of traditional (single data rate) synchronous dram. features ? 3.3v for v dd and 2.5v for v ddq power supply ? all inputs and outputs are compatible with sstl_2 interface ? jedec standard 400mil 66pin tsop-ii with 0.65mm pin pitch ? fully differential clock operations(clk & clk ) ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? data(dq) and write masks(ldm/udm) latched on both rising and falling edges of the data strobe ? data outputs on ldqs/udqs edges when read (edged dq) ? data inputs on ldqs/udqs centers when write (centered dq) ? data strobes synchronized with output data for read and input data for write ? delay locked loop(dll) installed with dll reset mode ? write mask byte controls by ldm and udm ? programmable cas latency 2 / 3 supported ? write operations with 1 clock write latency ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? internal 4 bank operations with single pulsed ras ? auto refresh and self refresh supported ordering information part no. power supply clock frequency organization interface package HY5DV651622TC-G55 v dd =3.3v v ddq =2.5v 183mhz 4banks x 1mbit x 16 sstl_2 400mil 66pin tsop ii hy5dv651622tc-g6 166mhz hy5dv651622tc-g7 143mhz
hy5dv651622t rev. 1.1/ apr.01 2 pin configuration 400 mil x 875mil 66 pin tsop -ii 0.65mm pin pitch top view v dd dq0 vddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc v ddq ldqs nc v dd nc ldm / we / cas / ras / cs nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 nc v ssq udqs nc v ref v ss udm / clk clk cke nc nc a11 a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 pin description pin pin name description clk, clk differential clock input the system clock input. all of the inputs are latched on the rising edges of the clock except dqi, ldqs/udqs and ldm/udm that are sampled on the both. cke clock enable controls internal clock signal. when deactivated, the ddr sdram will be one of the states among power down or self refresh. cs chip select enables or disables all inputs except clk/ clk , cke, ldqs/udqs and ldm/udm. ba0, ba1 bank select address selects bank to be activated during either ras or cas activity. selects bank to be read/written during either ras or cas activity. a0 ~ a11 address row address : a0 ~ a11, column address : a0 ~ a7 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the command being issued. refer function truth table for details. ldm, udm write mask masks input data in write mode. ldqs, udqs data input/output strobe active on the both edges for data input and output. dq0 ~ dq15 data input/output bidirectional data input / output pin. v dd /v ss power supply/ground power supply for internal circuits and input buffers. v ddq /v ssq data output power/ground power supply for output buffers for noise immunity. v ref reference voltage reference voltage for inputs for sstl interface. nc no connection no connection.
hy5dv651622t rev. 1.1/ apr.01 3 functional block diagram 4banks x 1mbit x 16 i/o double data rate synchronous dram command decoder clk / clk cke / cs / ras / cas / we ldm address buffer a0 ~ a11 bank control 1 mx16/bank0 column decoder column address counter sense amp 2 - bit prefetch unit 1 mx16/bank1 1 mx16/bank2 1 mx16/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver ldqs, udqs clk ds write data register 2 - bit prefetch unit ds dq[0:15] 32 16 16 32 clk_dll udm ba0, ba1
hy5dv651622t rev. 1.1/ apr.01 4 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability. dc operating conditions (ta=0 to 70 o c , voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with 5ns of duration. 3. the value of v ref is approximately equal to 0.5*v ddq . ac operating test conditions (ta=0 to 70 o c , voltage referenced to v ss = 0v) parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -1.0 ~ 4.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 1 w soldering temperature , time t solder 260 , 10 o c , sec parameter symbol min typ. max unit note power supply voltage v dd 3.15 3.3 3.6 v power supply voltage v ddq 2.3 2.5 2.7 v 1 input high voltage v ih v ref + 0.18 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.18 v 2 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 1.15 1.25 1.35 v 3 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.35 v ac input low level voltage (v il , max) v ref - 0.35 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v
hy5dv651622t rev. 1.1/ apr.01 5 ac operating test conditions (ta=0 to 70 o c , voltage referenced to v ss = 0v) - continued capacitance (t a =25 o c , f=1mhz) output load circuit parameter value unit input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t ) 50 w output load capacitance for access time measurement (c l ) 30 pf parameter pin symbol min max unit input capacitance a0 ~ a11, ba0 ~ ba1, cke, cs , ras , cas , we c in 2.5 3.5 pf clock capacitance clk, clk c clk 2.5 3.5 pf data input / output capacitance dq0 ~ dq15, ldqs, udqs, ldm, udm c io 4.0 5.5 pf v ref v tt r t =50 w zo =50 w c l =30pf output
hy5dv651622t rev. 1.1/ apr.01 6 dc characteristics i (ta=0 to 70 o c , voltage referenced to v ss = 0v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 2.7v dc characteristics ii (ta=0 to 70 o c , voltage referenced to v ss = 0v) note : 1. i dd1, idd4 and i dd5 depend on output loading and cycle rates. specified values are measured with the output open. 2. min. of t rfc (auto refresh row cycle time) is shown at ac characteristics. parameter symbol min. max unit note input leakage current i li -5 5 m a 1 output leakage current i lo -5 5 m a 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma output low voltage v ol - v tt - 0.76 v i ol = +15.2ma parameter symbol test condition speed unit note g55 g6 g7 operating current i dd1 burst length=2, one bank active t rc 3 t rc (min), i ol =0ma 160 150 140 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 20 ma precharge standby current in non power down mode i dd2n cke 3 v ih (min), cs 3 v ih (min), t ck = min input signals are changed one time during 2clks 40 ma active standby current in power down mode i dd3p cke v il (max), t ck = min 25 ma active standby current in non power down mode i dd3n cke 3 v ih (min), cs 3 v ih (min), t ck = min input signals are changed one time during 2clks 50 ma burst mode operating current i dd4 t ck 3 t ck (min), i ol =0ma all banks active cl=3 280 260 240 ma 1 auto refresh current i dd5 t rc 3 t rfc (min), all banks active 210 200 190 ma 1,2 self refresh current i dd6 cke 0.2v 2 ma
hy5dv651622t rev. 1.1/ apr.01 7 ac characteristics note : 1. data sampled at the rising edges of the clock : a0~a11, ba0~ba1, cke, cs , ras , cas , we . 2. data letched at both rising and falling edges of data strobes(ldqs/udqs) : dq, ldm/udm. 3. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to complete self refresh exit and lock the internal dll circuit of ddr sdram. parameter symbol -g55 -g6 -g7 unit note min max min max min max row cycle time trc 55 - 60 - 62 - ns auto refresh row cycle time trfc 66 - 72 - 77 - ns row active time tras 38.5 120k 42 120k 42 120k ns row address to column address delay trcd 16.5 - 18 - 20 - ns row prechage time trp 16.5 - 18 - 20 - ns row active to row active delay trrd 2 - 2 - 2 - clk column address to column address delay tccd 1 - 1 - 1 - clk write recovery time twr 2 - 2 - 2 - clk last data-in to read command delay tdrl 1 - 1 - 1 - clk auto precharge write recovery + precharge time tdal 27.5 - 30 - 34 - ns system clock cycle time cl = 3 tck 5.5 12 6 15 7 15 ns clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 clk clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 clk dqs-out edge to clock edge skew tdqsck -0.4 0.1 -0.4 0.1 -0.4 0.1 clk data-out edge to clock edge skew tac -0.4 0.1 -0.4 0.1 -0.4 0.1 clk dqs-out edge to data-out edge skew tdqsq -0.4 0.4 -0.4 0.4 -0.5 0.5 ns data/dqs-out valid window tdv 0.35 - 0.35 - 0.35 - clk dqs-out preamble time trpre 0.8 1.1 0.8 1.1 0.8 1.1 clk dqs-out postamble time trpst 0.4 0.6 0.4 0.6 0.4 0.6 clk clk to first rising edge of dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 clk dqs-in preamble setup time twpres 0 - 0 - 0 - clk dqs-in preamble hold time twpreh 0.25 - 0.25 - 0.25 - clk dqs-in last falling edge to hi-z delay twpst 0.4 0.6 0.4 0.6 0.4 0.6 clk dqs-in high level width tdsh 0.4 0.6 0.4 0.6 0.4 0.6 clk dqs-in low level width tdsl 0.4 0.6 0.4 0.6 0.4 0.6 clk input setup time to clk (addr & control) tis 1.1 - 1.1 - 1.1 - ns 1 input hold time to clk (addr & control) tih 1.1 - 1.1 - 1.1 - ns 1 data-in setup time to dqs-in (dq & dm) tds 0.5 - 0.5 - 0.5 - ns 2 data-in hold time to dqs-in (dq & dm) tdh 0.5 - 0.5 - 0.5 - ns 2 dqs-in pulse width tdipw 1.6 - 1.6 - 1.7 - ns mode register set cycle time tmrd 2 - 2 - 2 - clk power down exit time tpdex 10 - 10 - 10 - ns exit self refresh to non-read command txsnr 66 - 72 - 75 - ns exit self refresh to read command txsrd 200 - 200 - 200 - clk 3 average periodic refresh interval trefi - 15.6 - 15.6 - 15.6 us
hy5dv651622t rev. 1.1/ apr.01 8 simplified command truth table note : 1. ldm/udm states are ?don?t care?. refer to below write mask truth table. 2. op code(operand code) consists of a 0 ~a 11 and ba 0 ~ba 1 used for mode registering duing extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in clk(n), then there will be no command presented to activated bank until clk(n+bl/2+t rp ). 4. if a write with autoprecharge command is detected by memory compoment in clk(n), then there will be no command presented to activated bank until clk(n+bl/2+1+t dpl +t rp ). last data-in to prechage delay(t dpl ) which is also called write recovery time (twr) is needed to guarantee that the last data has been completely written. 5. if a 10 /ap is ?high? when row precharge command being issued, ba 0 /ba 1 are ignored and all banks are selected to be precharged. 6. the speed grade with g code will not be guaranteed the read and write with autoprecharge function. command cken-1 cken cs ras cas we addr a10/ ap ba note extended mode register set h x l l l l op code 1,2 mode register set h x l l l l op code 1,2 device deselect h x h x x x x 1 no operation l h h h bank active h x l l h h ra v 1 read h x l h l h ca l v 1 read with autoprecharge h 1,3,6 write h x l h l l ca l v 1 write with autoprecharge h 1,4,6 precharge all banks h x l l h l x h x 1,5 precharge selected bank l v 1 read burst stop h x l h h l x 1 auto refresh h h l l l h x 1 self refresh entry h l l l l h x 1 exit l h h x x x 1 l h h h precharge power down mode entry h l h x x x x 1 l h h h 1 exit l h h x x x 1 l h h h 1 active power down mode (clock suspend) entry h l h x x x x 1 l v v v 1 exit l h x 1 ( h=logic high level, l=logic low level, x=don?t care, v=valid data input, op code=operand code, nop=no operation )
hy5dv651622t rev. 1.1/ apr.01 9 write mask truth table note : 1. write mask command masks burst write data with reference to ldqs/udqs(data strobes) and it is not related with read data. 2. in case of x16 data i/o, ldm and udm control lower byte(dq0~7) and upper byte(dq8~15) respectively. package information 400mil 66pin thin small outline package function cken-1 cken cs , ras , cas , we ldm udm addr a10/ ap ba note data write h x x l l x 1,2 data-in mask h x x h h x 1,2 lower byte write / upper byte-in mask h x x l h x 1,2 upper byte write / lower byte-in mask h x x h l x 1,2 10.26 (0.404) 10.05 (0.396) 11.94 (0.470) 11.79 (0.462) 22.33 (0.879) 22.12 (0.871) 1.194 (0.0470) 0.991 (0.0390) 0.65 (0.0256) bsc 0.35 (0.0138) 0.25 (0.0098) 0.15 (0.0059) 0.05 (0.0020) base plane seating plane 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 0 ~ 5 deg. unit : mm(inch) ( h=logic high level, l=logic low level, x=don?t care )
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