tm april 2007 FDMS9620S dual n-channel powertrench ? mosfet ?2007 fairchild semiconductor corporation FDMS9620S rev.d www.fairchildsemi.com 1 FDMS9620S dual n-channel powertrench ? mosfet q1: 30v, 16a, 21.5m q2: 30v, 18a, 13m features q1: n-channel ? max r ds(on) = 21.5m at v gs = 10v, i d = 7.5a ? max r ds(on) = 29.5m at v gs = 4.5v, i d = 6.5a q2: n-channel ? max r ds(on) = 13m at v gs = 10v, i d = 10a ? max r ds(on) = 17m at v gs = 4.5v, i d = 8.5a ? low qg high side mosfet ? low r ds(on) low side mosfet ? thermally efficient dual power 56 package ? pinout optimized for simple pcb design ? rohs compliant general description this device includes two specialized mosfets in a unique dual power 56 package. it is designed to provide an optimal synchronous buck power stage in terms of efficiency and pcb utilization. the low switchi ng loss "high side" mosfet is complemented by a low conduction loss "low side" syncfet. application synchronous buck converter for: ? notebook system power ? general purpose point of load mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 30 30 v v gs gate to source voltage 20 20 v i d drain current -continuous (package limited) t c = 25c 16 18 a -continuous (silicon limited) t c = 25c 21 44 -continuous t a = 25c (note 1a) 7.5 10 -pulsed 60 60 p d power dissipation for single operation t a = 25c (note 1a) 2.5 w t a = 25c (note 1b) 1 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient (note 1a) 50 c/w r ja thermal resistance, junction to ambient (note 1b) 120 r jc thermal resistance, junction to case 8.2 3.1 device marking device package reel size tape width quantity FDMS9620S FDMS9620S power 56 13? 12mm 3000 units g1 d1 d1 d1 s1/d2 g2 s2 s2 s2 d1 g1 d1 d1 d1 s1/d2 g2 s2 s2 s2 d1 4 3 2 1 5 6 7 8 q 1 q 2 power 56
FDMS9620S dual n-channel powertrench ? mosfet ?2007 fairchild semiconductor corporation FDMS9620S rev.d www.fairchildsemi.com electrical characteristics t j = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics symbol parameter test conditions type min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0v i d = 1ma, v gs = 0v q1 q2 30 30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c q1 q2 23 23 mv/ c i dss zero gate voltage drain current v ds = 24v, v gs = 0v q1 q2 1 500 a i gss gate to source leakage current v gs = 20v, v ds = 0v q1 q2 100 100 na na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a v gs = v ds , i d = 1ma q1 q2 1 1 1.6 1.6 3 3 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 1ma, referenced to 25 c q1 q2 -4 -4 mv/ c r ds(on) drain to source on resistance v gs = 10v, i d = 7.5a v gs = 4.5v, i d = 6.5a v gs = 10v, i d = 7.5a , t j = 125 c q1 18 23 25 21.5 29.5 32 m v gs = 10v, i d = 10a v gs = 4.5v, i d = 8.5a v gs = 10v, i d = 10a , t j = 125 c q2 9 13 14 13 17 22 g fs forward transconductance v ds = 10v, i d = 7.5a v ds = 10v, i d = 10a q1 q2 25 27 s c iss input capacitance q1: v ds = 15v, v gs = 0v, f = 1mhz q2: v ds = 15v, v gs = 0v, f = 1mhz q1 q2 500 700 665 935 pf c oss output capacitance q1 q2 100 500 135 665 pf c rss reverse transfer capacitance q1 q2 65 100 100 150 pf r g gate resistance f = 1mhz q1 q2 0.9 1.8 t d(on) turn-on delay time q1: v dd = 15v, i d = 1a, r gen = 6 q2: v dd = 15v, i d = 1a, r gen = 6 q1 q2 11 15 20 27 ns t r rise time q1 q2 7 13 14 24 ns t d(off) turn-off delay time q1 q2 23 27 37 44 ns t f fall time q1 q2 2.3 7 10 14 ns q g total gate charge q1 v dd = 15v, v gs = 10v ,i d = 7.5a q2 v dd = 15v, v gs = 10v ,i d = 10a q1 q2 10 18 14 25 nc q gs gate to source gate charge q1 q2 0.7 1.5 nc q gd gate to drain ?miller? charge q1 q2 1.7 2.6 nc
FDMS9620S dual n-channel powertrench ? mosfet ?2007 fairchild semiconductor corporation FDMS9620S rev.d www.fairchildsemi.com electrical characteristics t j = 25c unless otherwise noted drain-source diod e characteristics symbol parameter test conditions type min typ max units i s maximum continuous drain-source diode forward current q1 q2 2.1 3.5 a v sd source to drain diode forward voltage v gs = 0v, i s = 2.1a (note 2) v gs = 0v, i s = 3.5a (note 2) q1 q2 0.7 0.5 1.2 1.0 v t rr reverse recovery time q1 i f = 7.5a, di/dt = 100a/ s q2 i f = 10a, di/dt = 300a/ s q1 q2 13 14 ns q rr reverse recovery charge q1 q2 4 9 nc notes: 1: r ja is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2: pulse test: pulse width < 30 0 s, duty cycle < 2.0%. a.50c/w when mounted on a 1 in 2 pad of 2 oz copper b. 120c/w when mounted on a minimum pad of 2 oz copper
FDMS9620S dual n-channel powertrench ? mosfet ?2007 fairchild semiconductor corporation FDMS9620S rev.d www.fairchildsemi.com typical characteristics (q1 n-channel) t j = 25c unless otherwise noted figure 1. on region characteristics figure 2. n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e vs junction temperature figure 4. o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics figure 6. s o u r c e t o d r a i n d i o d e forward voltage vs source current 01234 0 10 20 30 40 50 60 v gs = 4.5v v gs = 4.0v v gs = 3.5v v gs = 10v pulse duration = 300 s duty cycle = 2.0%max v gs = 3v v gs = 6v i d , drain current (a) v ds , drain to source voltage ( v ) 0 102030405060 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 v gs = 10v v gs = 6.0v v gs = 4.0v pulse duration = 300 s duty cycle = 2.0%max normalized drain to source on-resistance i d , drain current(a) v gs =3.5v v gs = 3v v gs = 4.5v -50 -25 0 25 50 75 100 125 150 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 i d = 7.5a v gs =10v normalized drain to source on-resistance t j , junction temperature ( o c ) 246810 10 20 30 40 50 60 70 pulse duration = 300 s duty cycle = 2.0%max t j = 125 o c t j = 25 o c i d = 3.8a r ds(on) , drain to source on-resistance ( m ) v gs , gate to source voltage (v) 12345 0 10 20 30 40 v ds = 5v pulse duration = 300 s duty cycle = 2.0%max t j =125 o c t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.001 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0v i s , reverse drain current (a) v sd , body diode forward voltage (v) 40
FDMS9620S dual n-channel powertrench ? mosfet ?2007 fairchild semiconductor corporation FDMS9620S rev.d www.fairchildsemi.com figure 7. gate charge characteristics figure 8. c a p a c i t a n c e v s d r a i n to source voltage figure 9. f o r w a r d b i a s s a f e operating area figure 10. s i n g l e p u l s e m a x i m u m p o w e r d i s s i p a t i o n figure 11. transient thermal response curve typical characteristics (q1 n-channel) t j = 25c unless otherwise noted 024681012 0 2 4 6 8 10 i d = 7.5a v dd = 20v v dd = 15v v dd =10v q g , gate charge(nc) v gs , gate to source voltage(v) 0.1 1 10 100 1000 30 f = 1mhz v gs = 0v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 30 0.1 1 10 100 0.01 0.1 1 10 100 dc 10s 1s 100ms 10ms 1ms single pulse t j = max rate r ja = 120 o c t a = 25 o c this area is limited by r ds(on) v ds , drain to source voltage (v) i d , drain current (a) 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 1 10 100 0.5 v gs = 10v single pulse r ja = 120 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (s) 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 0.01 0.1 1 duty cycle-descending order normalized thermal impedance, z ja t, rectangular pulse duration (s) d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse r ja = 120 o c/w 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a
FDMS9620S dual n-channel powertrench ? mosfet ?2007 fairchild semiconductor corporation FDMS9620S rev.d www.fairchildsemi.com typical characteristics (q2 syncfet) figure 12. on-region characteristics figure 13. normalized on-resistance vs drain current and gate voltage figure 14. normalized on-resistance vs junction temperature figure 15. on-resistance vs gate to source voltage figure 16. transfer characteristics figure 17. source to drain diode forward voltage vs source current 0.0 0.5 1.0 1.5 2.0 2.5 0 10 20 30 40 50 60 v gs = 3v v gs = 4.5v v gs = 4.0v v gs = 3.5v v gs = 10v pulse duration = 300 s duty cycle = 2.0%max v gs = 6v i d , drain current (a) v ds , drain to source voltage (v) 0 102030405060 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 v gs = 10v v gs = 6.0v v gs = 4.0v pulse duration = 300 s duty cycle = 2.0%max normalized drain to source on-resistance i d , drain current(a) v gs =3.5v v gs = 4.5v -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 i d = 10a v gs =10v normalized drain to source on-resistance t j , junction temperature ( o c ) 246810 0 10 20 30 40 50 60 pulse duration = 300 s duty cycle = 2.0%max t j = 125 o c t j = 25 o c i d = 5a r ds(on) , drain to source on-resistance ( m ) v gs , gate to source voltage (v) 12345 0 10 20 30 40 50 60 v ds = 5v pulse duration = 300 s duty cycle = 2.0%max t j =125 o c t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.0 0.2 0.4 0.6 0.8 0.001 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0v i s , reverse drain current (a) v sd , body diode forward voltage (v)
FDMS9620S dual n-channel powertrench ? mosfet ?2007 fairchild semiconductor corporation FDMS9620S rev.d www.fairchildsemi.com typical characteristics figure 18. gate ch arge characteristics figure 19. capacitance vs drain to source voltage 048121620 0 2 4 6 8 10 i d = 10a v dd = 20v v dd = 15v v dd =10v q g , gate charge(nc) v gs , gate to source voltage(v) 0.1 1 10 100 1000 2000 50 f = 1mhz v gs = 0v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 30
FDMS9620S dual n-channel powertrench ? mosfet ?2007 fairchild semiconductor corporation FDMS9620S rev.d www.fairchildsemi.com dimensional outlin e and pad layout
FDMS9620S dual n-channel powertrench ? mosfet trademarks the following are registered and unregistered trademarks fairchil d semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. disclaimer fairchild semiconductor reserves the right to make chang es without further notice to any products herein to improve reliability, funct ion or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described he rein; neither does it convey any lice nse under its patent rights, nor the rights of others. these specifications do not expand th e terms of fairchild?s worldwide terms and conditions, specifically the warranty ther ein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expe cted to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose fail ure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms acex ? across the board. around the world? activearray? bottomless? build it now? coolfet? crossvolt ? ctl? current transfer logic? dome? e 2 cmos? ecospark ? ensigna? fact quiet series? fact ? fast ? fastr? fps? frfet ? globaloptoisolator ? gto ? i-lo ? implieddisconnect? intellimax? isoplanar? microcoupler? micropak? microwire? motion-spm? msx? msxpro? ocx? ocxpro? optologic ? optoplanar ? pacman? pdp-spm? pop? power220 ? power247 ? poweredge? powersaver? power-spm? powertrench ? programmable active droop? qfet ? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? scalarpump? smart start? spm ? stealth? superfet? supersot?-3 supersot?-6 supersot?-8 syncfet? tcm? the power franchise ? ? tinyboost? tinybuck? tinylogic ? tinyopto? tinypower? tinywire? trutranslation? serdes? uhc ? unifet? vcx? wire? datasheet identification product status definition advance information formative or in design this datasheet contains the desi gn specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet c ontains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any ti me without notice to improve design. no identification needed full production this dat asheet contains final s pecifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. obsolete not in production this datasheet contains specific ations on a product that has been discontinued by fairchild semic onductor.the datasheet is printed for reference information only. rev. i26 tm tm hisec ? ?2007 fairchild semiconductor corporation FDMS9620S rev.d www.fairchildsemi.com
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