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utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? revision history revision description date preliminary rev. 0.1 original. jun 7,2001 rev. 1.0 1.truth table 2.dc electrical characteristics jul 19,2001 rev. 1.1 add order information for lead free product may15,2003
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? features access time : 35/70ns (max.) low power consumption: operating : 40 ma (typical.) standby : 3ma (typical) normal 2ua (typical) l-version 1ua (typical) ll-version single 5v power supply all inputs and outputs are ttl compatible fully static operation three state outputs data retention voltage : 2v (min.) package : 28-pin 600 mil pdip 28-pin 330 mil sop 28-pin 8mmx13.4mm stsop functional block diagram decoder i/o data circuit control circuit 32k x 8 memory array column i/o a0-a14 vcc vss i/o1-i/o8 ce we ce2 pin description symbol description a0 - a14 address inputs i/o1 - i/o8 data inputs/outputs ce ?b ce2 chip enable inputs we write enable input v cc power supply v ss ground general description the UT62257C is a 262,144-bit low power cmos static random access memory organized as 32,768 words by 8 bits. it is fabricated using high performance, high reliability cmos technology. the UT62257C is designed for high-speed and low power application. with 2 chip controls ( ce ?b ce2 ), it is easy to design memory systems with power-down and capacity expansion in the application circuits. it is particularly well suited for battery back-up nonvolatile memory application. the UT62257C operates from a single 5v power supply and all inputs and outputs are fully ttl compatible. pin configuration a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 vcc a8 a9 a11 a10 i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 vss UT62257C pdip/sop 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 ce 5?5u a13 a14 ce2 i/o4 a11 a9 a8 a13 i/o3 a10 a14 a12 a7 a6 a5 vcc i/o8 i/o7 i/o6 i/o5 vss i/o2 i/o1 a0 a1 a2 a4 a3 UT62257C stsop 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 we ce ce2
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? absolute maximum ratings * parameter symbol rating unit terminal voltage with respect to v ss v term -0.5 to +7.0 v operating temperature t a 0 to +70 j storage temperature t stg -65 to +150 j power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 sec) tsolder 260 j *stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating only and functional operation of the dev ice or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity. truth table mode ce ce2 we i/o operation supply current h x x high - z i sb , i sb1 standby x l x high - z i sb , i sb1 read l h h d out i cc , i cc 1, i cc 2 write l h l d in i cc , i cc 1, i cc 2 note: h = vih, l=vil, x = don't care. dc electrical characteristics (v cc = 5v10%, t a = 0 j to 70 j ) parameter symbol test condition min. typ. max. unit input high voltage v ih *1 2.2 - v cc +0.5 v input low voltage v il *2 - 0.5 - 0.8 v input leakage current i li v ss ?? v in ?? v cc - 1 - 1 a output leakage current i lo v ss ?? v i/o ?? v cc ce =v ih or ce2 = v il - 1 - 1 a output high voltage v oh i oh = - 1ma 2.4 - - v output low voltage v ol i ol = 4ma - - 0.4 v - 35 - 40 50 ma i cc cycle time=min., i i/o = 0ma , ce =v il , ce2 = v ih - 70 - 30 40 ma i cc 1 cycle time=1 s,100%duty,i i/o =0ma, ce = 0.2v ; ce2 = v cc -0.2v , other pins at 0.2v or v cc -0.2v - - 10 ma operating power supply current i cc 2 cycle time=500ns,100%duty,i i/o =0ma, ce = 0.2v ; ce2 = v cc -0.2v , other pins at 0.2v or v cc -0.2v - - 20 ma i sb ce =v ih or ce2 = v il 1 10 ma i sb1 ce ? v cc -0.2v ce2 ? v cc -0.2v normal - 0.3 5 ma i sb ce =v ih or ce2 = v il -l/-ll - - 3 ma i sb1 ce ? v cc -0.2v -l - 2 100 a standby power supply current ce2 ? v cc -0.2v -ll - 1 40 a notes: 1. overshoot : vcc+2.0v fo r pulse width less than 10ns. 2. undershoot : vss-2.0v fo r pulse width less than 10ns. 3. overshoot and undershoot ar e sampled, not 100% tested.
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? capacitance (ta=25 j , f=1.0mhz) parameter symbol min. max unit input capacitance c in - 8 pf input/output capacitance c i/o - 10 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0v to 3.0v input rise and fall times 5ns input and output timing reference levels 1.5v output load c l = 100pf, i oh /i ol = -1ma/4ma ac electrical characteristics (v cc = 5v10% , t a = 0 j to 70 j ) (1) read cycle parameter symbol UT62257C-35 UT62257C-70 unit min. max. min. max. read cycle time t rc 35 - 70 - ns address access time t aa - 35 - 70 ns chip enable access time t ace - 35 - 70 ns output enable access time t oe - 25 - 35 ns chip enable to output in low z t clz* 10 - 10 - ns output enable to output in low z t olz* 5 - 5 - ns chip disable to output in high z t chz* - 25 - 35 ns output disable to output in high z t ohz* - 25 - 35 ns output hold from address change t oh 5 - 5 - ns (2) write cycle parameter symbol UT62257C-35 UT62257C-70 unit min. max. min. max. write cycle time t wc 35 - 70 - ns address valid to end of write t aw 30 - 60 - ns chip enable to end of write t cw 30 - 60 - ns address set-up time t as 0 - 0 - ns write pulse width t wp 25 - 50 - ns write recovery time t wr 0 - 0 - ns data to write time overlap t dw 20 - 30 - ns data hold from end of write time t dh 0 - 0 - ns output active from end of write t ow* 5 - 5 - ns write to output in high z t whz* - 15 - 25 ns *these parameters are guaranteed by device char acterization, but not production tested.
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? timing waveforms read cycle 1 (address controlled) (1,2) t rc t aa data valid address dout t oh t oh previous data valid read cycle 2 ( ce and ce2 controlled) (1,3,4,5) t rc t aa t ace t clz t oh high-z data valid high-z t chz address ce2 dout ce notes : 1. we is high for read cycle. 2. device is continuously selected ce =low , ce2=high . 3. address must be valid prior to or coincident with ce =low , ce2=high ; otherwise t aa is the limiting parameter. 4. t clz , t olz , t chz and t ohz are specified with c l =5pf. transition is measured ? 500mv from steady state. 5. at any given temperature and voltage condition, t chz is less than t clz .
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? write cycle 1 ( we controlled) (1,2,3,5,6) t wc t aw t cw t as t wp t whz t ow t wr high-z (4) (4) address ce2 ce we dout din data valid t dw t dh write cycle 2 ( ce and ce2 controlled) (1,2,5,6) t wc t aw t cw t as t wr t wp t whz t dw t dh data valid high-z (4) address ce2 ce we dout din
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? notes : 1. we , ce must be high or ce2 must be low during all address transitions. 2. a write occurs during the overlap of a low ce , high ce2, low we . 3. during a we controlled write cycle, t wp must be greater than t whz +t dw to allow the drivers to turn off and data to be placed on the bus. 4. during this period, i/o pins are in the out put state, and input signals must not be applied. 5. if the ce low transition and ce2 high transition o ccurs simultaneously with or after we low transition, the outputs remain in a high impedance state. 6. t ow and t whz are specified with c l = 5pf. transition is measured ? 500mv from steady state. data retention characteristics (t a = 0 j to 70 j ) parameter symbol test condition min. typ. max. unit vcc for data retention v dr ce ? v cc -0.2v or ce2 0.2v 2.0 - 5.5 v data retention current i dr vcc=3v, ce2 0.2v - l - 1 50 a or ce ? v cc -0.2v - ll - 0.5 20 a chip disable to data t cdr see data retention 0 - - ns retention time waveforms (below) recovery time t r t rc* - - ns t rc* = read cycle time data retention waveform low vcc data retention waveform (1) ( ce controlled) vdr ? 2v ce ? v cc -0.2v v cc(min.) v cc(min.) v ih v ih v cc t r t cdr ce low vcc data retention waveform (2) (ce2 controlled) vdr ? 2v v cc(min.) v cc t r t cdr ce2 ?? 0.2v v il ce2 v cc(min.) v il
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? package outline dimension 28 pin 600 mil pdip package outline dimension unit symbol inch(base) mm(ref) a1 0.010(min) 0.254(min) a2 0.150 ? 0.001 3.810 ? 0.254 b 0.018 ? 0.005 0.457 ? 0.127 c 0.010 ? 0.004 0.254 ? 0.102 d 1.460 ? 0.005 37.084 ? 0.127 e 0.600 ? 0.010 15.240 ? 0.254 e 0.100 (typ) 2.540(typ) eb 0.640 ? 0.03 16.256 ? 0.762 l 0.130 ? 0.010 3.302 ? 0.254 c 0 o ~15 o 0 o ~15 o
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? 28 pin 330 mil sop package outline dimension unit symbol inch(base) mm(ref) a 0.112 (max) 2.845 (max) a1 0.004(min) 0.102(min) a2 0.098 ? 0.005 2.489 ? 0.127 b 0.016 (typ) 0.406(typ) c 0.010 (typ) 0.254(typ) d 0.713 ? 0.005 18.110 ? 0.127 e 0.331 ? 0.005 8.407 ? 0.127 e1 0.465 ? 0.012 11.811 ? 0.305 e 0.050 (typ) 1.270(typ) l 0.0404 ? 0.008 1.0255 ? 0.203 l1 0.067 ? 0.008 1.702 ? 0.203 s 0.047 (max) 1.194 (max) y 0.003(max) 0.076(max) c 0 o ?? 10 o 0 o ?? 10 o
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? 28 pin 8x13.4mm stsop package outline dimension 1 14 15 28 c l hd d "a" e e seating plane y 28 15 14 1 c a2 a1 a 0 seating plane "a" datail view l1 unit symbol inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.004 ? 0.002 0.10 ? 0.05 a2 0.039 ? 0.002 1.00 ? 0.05 d 0.465 ? 0.004 11.800 ? 0.100 e 0.315 ? 0.004 8.000 ? 0.100 e 0.022 (typ) 0.55 (typ) hd 0.528 ? 0.008 13.40 ? 0.20. l1 0.0315 ? 0.004 0.80 ? 0.10 y 0.003 (max) 0.076 (max) k 0 o ?? 5 o 0 o ?? 5 o
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 11 ? ordering information part no. access time (ns) standby current ( a) package UT62257Cpc-70 70 5 ma 28 pin pdip UT62257Cpc-70l 70 100 a 28 pin pdip UT62257Cpc-70ll 70 40 a 28 pin pdip UT62257Csc-35 35 5 ma 28 pin sop UT62257Csc-35l 35 100 a 28 pin sop UT62257Csc-35ll 35 40 a 28 pin sop UT62257Csc-70 70 5 ma 28 pin sop UT62257Csc-70l 70 100 a 28 pin sop UT62257Csc-70ll 70 40 a 28 pin sop UT62257Cls-35l 35 100 a 28 pin stsop UT62257Cls-35ll 35 50 a 28 pin stsop UT62257Cls-70l 70 100 a 28 pin stsop UT62257Cls-70ll 70 40 a 28 pin stsop ordering information (for lead free product) part no. access time (ns) standby current ( a) package UT62257Cpcl-70 70 5 ma 28 pin pdip UT62257Cpcl-70l 70 100 a 28 pin pdip UT62257Cpcl-70ll 70 40 a 28 pin pdip UT62257Cscl-35 35 5 ma 28 pin sop UT62257Cscl-35l 35 100 a 28 pin sop UT62257Cscl-35ll 35 40 a 28 pin sop UT62257Cscl-70 70 5 ma 28 pin sop UT62257Cscl-70l 70 100 a 28 pin sop UT62257Cscl-70ll 70 40 a 28 pin sop UT62257Clsl-35l 35 100 a 28 pin stsop UT62257Clsl-35ll 35 50 a 28 pin stsop UT62257Clsl-70l 70 100 a 28 pin stsop UT62257Clsl-70ll 70 40 a 28 pin stsop
utron UT62257C rev. 1.1 32k x 8 bit low power cmos sram utron technology inc. p80062 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 12 ? this page is left blank intentionally.

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