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revisions ltr description date ( yr-mo-da ) approved rev sheet 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 rev sheet 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 rev rev status of sheets sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pmic n/a prepared by charles f. saffle checked by charles f. saffle defense supply center columbus columbus, ohio 43216 http://www.d scc.dla.mil approved by thomas m. hess drawing approval date 03-08-14 microcircuit, digital, 32-bit sparc low voltage processor, monolithic silicon size a cage code 67268 5962-03246 standard microcircuit drawing this drawing is available for use by all departments and agencies of the department of defense amsc n/a revision level - sheet 1 of 52 dscc form 2233 apr 97 5962-e509-03 distribution statement a . approved for public release; distribution is unlimited.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 2 dscc form 2234 apr 97 1. scope 1.1 scope . this drawing documents two product assurance class le vels consisting of high reliability (device classes q and m) and space application (device class v). a choice of case outlines and lead finishes are available and are reflected in the part or identifying number (pin). when available, a choice of radiation hardness assurance (rha ) levels are reflected in the pin. 1.2 pin . the pin is as shown in the following example: 5962 - 03246 01 q x c federal rha device device case lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) \ / (see 1.2.3) \/ drawing number 1.2.1 rha designator . device classes q and v rha marked devices meet the mil-prf-38535 specified rha levels and are marked with the appropriate rha designator. device class m rha marked devices meet the mil-prf-38535, appendix a specified rha levels and are marked with the appropriate rha designator. a dash (-) indicates a non-rha device. 1.2.2 device type(s) . the device type(s) identify the circuit function as follows: device type generic number circuit function frequency 01 tsc695fl 32-bit sparc low voltage 15 mhz processor 1.2.3 device class designator . the device class designator is a single letter identifying the product assurance level as follows: device class device requirements documentation m vendor self-certification to the requirements for mil-std-883 compliant, non-jan class level b microcircuits in accordance with mil-prf-38535, appendix a q or v certification and qualification to mil-prf-38535 1.2.4 case outline(s) . the case outline(s) are as designated in mil-std-1835 and as follows: outline letter descriptive designator terminals package style x see figure 1 256 ceramic quad flat package 1.2.5 lead finish . the lead finish is as specified in mil-pr f-38535 for device classes q and v or mil-prf-38535, appendix a for device class m.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 3 dscc form 2234 apr 97 1.3 absolute maximum ratings . 1 / supply voltage range (v dd ).......................................................................... -0.5 v dc to +7.0 v dc 2 / input voltage range (v in ).............................................................................. -0.5 v dc to v dd +0.5 v dc 3 / output current (i out ) .................................................................................... 50 ma 4 / maximum power dissipation (continuous) (p d ) ............................................ 1.5 w storage temperature range (t stg ) ............................................................... -65 c to +150 c lead temperature (solderi ng, 10 seconds ) .................................................. +265 c 5 / thermal resistance, junction-to-case ( jc )................................................... 3 c/w junction temperature (t j ) ............................................................................ +165 c 1.4 recommended operating conditions . operating supply voltage range (v dd ) .......................................................... +3.15 v dc to +3.45 v dc case operating temperature range (t c ) ...................................................... -55 c to +125 c storage conditions for packaged devic es .................................................... 30 c, 20 to 65%rh, dust free, original packing 1.5 radiation features . maximum total dose (dose rate = 0.1 rads (si)/s)........................................ 1.0 x 10 5 rads (si) single event phenomenon (sep) effective linear energy threshold (let) with no upset............................................................................................. error rate 5e-5/dev ice/day (worst case) with no latchup .......................................................................................... > 80 mev-cm 2 /mg 2. applicable documents 2.1 government specification, standards, and handbooks . the following specification, standards, and handbooks form a part of this drawing to the extent specified herein. unless ot herwise specified, the issues of these documents are those liste d in the issue of the department of defense i ndex of specifications and standards (dodi ss) and supplement thereto, cited in the solicitation. specification department of defense mil-prf-38535 - integrated circuits, m anufacturing, general specification for. standards department of defense mil-std-883 - test method standard microcircuits. mil-std-1835 - interface standard elec tronic component case outlines. handbooks department of defense mil-hdbk-103 - list of standard microcircuit drawings. mil-hdbk-780 - standard microcircuit drawings. (unless otherwise indicated, copies of the specificat ion, standards, and handbooks are ava ilable from the standardization document order desk, 700 robbins avenue, building 4d, philadelphia, pa 19111-5094.) ____________ 1 / stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. 2 / device is functional from +3.15 v to +3.45 v with reference to ground. 3 / (v dd + 0.5 v) should not exceed +7.0 v. 4 / this is the maximum current of any single output. 5 / duration 10 seconds maximum at a distance not less than 1.5 mm from the device body, and the same lead shall not be resoldered until 3 minutes have elapsed.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 4 dscc form 2234 apr 97 2.2 non-government publications . the following document(s) form a part of this document to the extent specified herein. unless otherwise specified, the issues of the documents which are dod adopted are t hose listed in the issue of the dodiss cited in the solicitation. unless otherwise specified, the issues of documents not lis ted in the dodiss are the issues of the documents cited in the solicitation. institute of electrical a nd electronics engineers (ieee) ieee standard 1149.1 - ieee standard test a ccess port and boundary scan architecture. (applications for copies should be addressed to the inst itute of electrical and elec tronics engineers, 445 hoes lane, piscataway, nj 08854-4150.) (non-government standards and other publicat ions are normally available from the organizations that prepare or distribute the documents. these documents may also be available in or through libraries or other informational services.) 2.3 order of precedence . in the event of a conflict between the text of th is drawing and the references cited herein, the text of this drawing takes precedence. nothing in this docum ent, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. requirements 3.1 item requirements . the individual item requirements for device classes q and v shall be in accordance with mil-prf-38535 and as specified herein or as modified in the device manufacturer's quality management (qm) plan. the modification in the qm plan shall not affect the form, fit, or function as described herein. the individual item requirements for device class m shall be in accordance with mil-prf-38535, appendix a for non-jan class level b devices and as specified herein. 3.1.1 microcircuit die . for the requirements of microcircu it die, see appendix a of this document. 3.2 design, construction, and physical dimensions . the design, construction, and physica l dimensions shall be as specified in mil-prf-38535 and herein for device classes q and v or mil-prf-38535, appendix a and herein for device class m. 3.2.1 case outline . the case outline shall be in accordanc e with 1.2.4 herein and figure 1 herein. 3.2.2 terminal connections . the terminal connections sha ll be as specified on figure 2. 3.2.3 block diagram . the block diagram shall be as specified on figure 3. 3.2.4 boundary scan instruction codes . the boundary scan instruction codes shall be as specified on figure 4. 3.2.5 timing waveforms . the timing waveforms shall be as specified on figure 5. 3.2.6 radiation exposure connections . the radiation exposure connections shall be as specified on figure 6. 3.3 electrical performanc e characteristics and postirr adiation parameter limits . unless otherwise specified herein, the electrical performance characteristics and pos tirradiation parameter limits are as spec ified in table ia and shall apply over t he full case operating temperature range. 3.4 electrical test requirements . the electrical test requirements shall be the subgroups specified in tabl e iia. the electrical tests for each subgroup are defined in table ia. 3.5 marking . the part shall be marked with the pin listed in 1.2 her ein. in addition, the manufacturer's pin may also be marked as listed in mil-hdbk-103. for pa ckages where marking of the entire smd pi n number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. for rha product using this option, the rha designator shall still be marked. marking for device cl asses q and v shall be in accordance with mil-prf-38535. marking for device class m shall be in accordance with mil-prf-38535, appendix a. 3.5.1 certification/compliance mark . the certification mark for device classes q and v shall be a "qml" or "q" as required in mil-prf-38535. the compliance mark for device class m shall be a "c" as required in mil-prf-38535, appendix a.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 5 dscc form 2234 apr 97 3.6 certificate of compliance . for device classes q and v, a certificate of compliance shall be required from a qml-38535 listed manufacturer in order to supply to t he requirements of this drawing (see 6.6.1 herein). for device class m, a certifica te of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in mil-hdbk-103 (see 6.6.2 herein). the certificate of compliance submitted to ds cc-va prior to listing as an approv ed source of supply for this drawing shall affirm that the manufactu rer's product meets, for device classes q and v, the requirements of mil-prf-38535 and herein or for device class m, the requi rements of mil-prf-38535, appendix a and herein. 3.7 certificate of conformance . a certificate of conformance as required for device classes q and v in mil-prf-38535 or for device class m in mil-prf-38535, appendix a shall be provided wi th each lot of microcircuits delivered to this drawing. 3.8 notification of change for device class m . for device class m, notification to dscc-va of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in mil-prf-38535, appendix a. 3.9 verification and review for device class m . for device class m, dscc, dscc's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. offs hore documentation shall be made available onshore at the option of the reviewer. 3.10 microcircuit group assignment for device class m . device class m devices covered by this drawing shall be in microcircuit group number 132 (see mil-prf-38535, appendix a).
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 6 dscc form 2234 apr 97 table ia. electrical per formance characteristics . limits test symbol conditions 1 / -55 c t c +125 c +3.15 v v dd +3.4.5 v unless otherwise specified group a subgroups device type min max unit high level input voltage v ih v dd = 3.45 v 2 / 3 / 4 / 1, 2, 3 all 2.0 v low level input voltage v il v dd = 3.45 v 2 / 3 / 4 / 1, 2, 3 all 0.8 v v oh v dd =3.15 v, i oh = -2.0 ma 5 / minimum and maximum values recorded 1, 2, 3 all 2.4 high level output voltage v ohb v dd =3.15 v, i oh = -6.0 ma 6 / minimum and maximum values recorded 1, 2, 3 all 2.4 v v ol v dd =3.15 v, i ol = 3.0 ma 5 / minimum and maximum values recorded 1, 2, 3 all 0.4 low level output voltage v olb v dd =3.15 v, i ol = 9.0 ma 6 / minimum and maximum values recorded 1, 2, 3 all 0.4 v high level input current i ih v dd = 3.45 v, v in = v dd 7 / 1, 2, 3 all 10 a i il v dd = 3.45 v, v in = 0.0 v 8 / 1, 2, 3 all 10 low level input current i ilt v dd = 3.45 v, v in = 0.0 v 9 / 1, 2, 3 all 350 a three-state leakage current i ozh v dd = 3.45 v, v in = v dd 10 / 1, 2, 3 all 10 a three-state leakage current i ozl v dd = 3.45 v, v in = 0.0 v 10 / 1, 2, 3 all 10 a supply current (idle) iv dd pins i ddidle v dd = 3.45 v, f = 15 mhz 1, 2, 3 all 10 ma supply current (internal) iv dd pins i ddin v dd = 3.45 v, f = 15 mhz 1, 2, 3 all 100 ma input capacitance c in v in = 2.5 v t c = 25 c f in = 1.0 mhz see 4.4.1c 4 all 7 pf functional test v il = 0.0 v, v ih = 3.0 v v ol = 1.45 v, v oh = 1.55 v v dd = 3.15 v, 3.3 v, and 3.45 v f = 15 mhz see 4.4.1b 7, 8 all see footnotes at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 7 dscc form 2234 apr 97 table ia. electrical per formance characteristics - continued. limits test symbol conditions 1 / -55 c t c +125 c +3.15 v v dd +3.45 v unless otherwise specified group a subgroups device type min max unit clk2 period 11 / t 1 9, 10, 11 all 33 ns sysclk period 11 / t 2 9, 10, 11 all 66 ns clk2 high and low pulse width 11 / t 3 9, 10, 11 all 16 ns ra[31:0], rapar, rsize, rldsto output delay 12 / t 4-1 9, 10, 11 all 10 ns lock output delay 12 / t 4-2 9, 10, 11 all 16 ns 0] : memcs[9 , romcs , exmcs output delay 11 / 12 / t 5 9, 10, 11 all 18 ns ddir, ddir output delay 11 / 12 / t 6 9, 10, 11 all 18 ns memwr and iomwr output delay 12 / 13 / t 7 9, 10, 11 all 36.5 ns oe (hl) output delay 12 / t 8 v dd = 3.15 v sysclk frequency = 15 mhz see figure 5 9, 10, 11 all 31.5 ns v dd = 3.15 v 11 / sysclk frequency = 15 mhz see figure 5 16 data setup time during load 12 / t 9 v dd = 3.15 v sysclk frequency = 15 mhz nopar = 0 rpa = rec = either 0 or 1 see figure 5 9, 10, 11 all 13 ns data hold time during load 11 / 12 / t 10 9, 10, 11 all 7 ns data output delay 13 / t 11 9, 10, 11 all 44 ns data output valid 11 / 12 / t 12 9, 10, 11 all 18 ns cb output delay 11 / 12 / t 13 9, 10, 11 all 30 ns ale output delay 11 / 13 / t 14 9, 10, 11 all 25 ns buffen (hl) output delay 11 / 12 / t 15 9, 10, 11 all 32.5 ns mhold output delay 11 / 12 / t 16 9, 10, 11 all 20 ns mds , drdy output delay 11 / 12 / t 17 9, 10, 11 all 20 ns mexc output delay 11 / 13 / t 20 9, 10, 11 all 20 ns rasi[3:0], rsize[1:0], raspar setup time 11 / 12 / t 21 v dd = 3.15 v sysclk frequency = 15 mhz see figure 5 9, 10, 11 all 15 ns see footnotes at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 8 dscc form 2234 apr 97 table ia. electrical per formance characteristics - continued. limits test symbol conditions 1 / -55 c t c +125 c +3.15 v v dd +3.4.5 v unless otherwise specified group a subgroups device type min max unit rasi[3:0], rsize[1:0], raspar hold time 11 / 12 / t 22 9, 10, 11 all 0 ns boot prom address output delay 11 / 12 / t 23 9, 10, 11 all 20 ns busrdy setup time 11 / 12 / t 24 9, 10, 11 all 15 ns busrdy hold time 11 / 12 / t 25 9, 10, 11 all 0 ns iosel output delay 11 / 12 / t 27 9, 10, 11 all 20 ns dmaas setup time 11 / 12 / t 28 9, 10, 11 all 15 33 ns dmaas hold time 11 / 13 / t 29 9, 10, 11 all 0 33 ns dmareq setup time 11 / 12 / t 30 9, 10, 11 all 15 ns dmagnt output delay 11 / 12 / t 31 9, 10, 11 all 20 ns ra[31:0], rapar, cpar setup time 11 / 12 / t 32 9, 10, 11 all 15 ns ra[31:0], rapar, cpar hold time 11 / 12 / t 33 9, 10, 11 all 0 ns tck period 11 / t 36 9, 10, 11 all 100 ns tms setup time 11 / 14 / t 37 9, 10, 11 all 10 ns tms hold time 11 / 14 / t 38 9, 10, 11 all 4 ns tdi setup time 11 / 14 / t 39 9, 10, 11 all 10 ns tdi hold time 11 / 14 / t 40 9, 10, 11 all 10 ns tdo output delay 11 / 15 / t 41 9, 10, 11 all 20 ns inull output delay 11 / 12 / t 46 9, 10, 11 all 35 ns reset , cpuhalt output delay 11 / 12 / t 48 9, 10, 11 all 35 ns syserr , sysav output delay 11 / 12 / t 49 9, 10, 11 all 20 ns iuerr output delay 11 / 12 / t 50 9, 10, 11 all 35 ns extint[4:0] setup time 11 / 13 / t 52 9, 10, 11 all 15 ns extint[4:0] hold time 11 / 12 / t 53 9, 10, 11 all 0 ns extintack output delay 11 / 12 / t 54 v dd = 3.15 v sysclk frequency = 15 mhz see figure 5 9, 10, 11 all 20 ns see footnotes at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 9 dscc form 2234 apr 97 table ia. electrical per formance characteristics - continued. limits test symbol conditions 1 / -55 c t c +125 c +3.15 v v dd +3.45 v unless otherwise specified group a subgroups device type min max unit oe (lh) output delay (no dma mode) 11 / 12 / t 56 9, 10, 11 all 14 ns buffen (lh) output delay 11 / 12 / t 57 9, 10, 11 all 15 ns inst output delay 11 / 12 / t 60 9, 10, 11 all 35 ns data output delay to low-z 11 / 12 / t 61 v dd = 3.15 v sysclk frequency = 15 mhz see figure 5 9, 10, 11 all 30.5 ns 1/ rha devices supplied to this drawing are characterized at all le vels m, d, p, l, and r of irradiation. however, this device is only tested at the ?r? level. pre and post irradiation val ues are identical unless otherwise specified in table ia. when performing post irradiation electrical measurements for any rha level, t a = +25 c. 2 / not recorded ? tested go/no-go during functional test. 3 / applies to ra[31:0], rapar, rasi[3:0], rsize[1:0], r aspar, cpar, d[31:0], cb[6:0], d par, rldsto, dxfer, lock, rd, we , wrt, prom8 , romwrt , busrdy , buserr , dmareq , dmaas, syshalt , nopar , iwde, wdclk, clk2, tmode[1:0], debug, tck, trst , tms, tdi. 4 / applies to rxa, rxb, gpi[7:0], extint[4:0], ewdint, sysreset . 5 / applies to rapar, rasi[3:0], rsize[1:0], raspar, cpar, d[31:0], cb[6:0], dpar, rldsto, ale , dxfer, lock, rd, we , wrt, mhold , mds , mexc , ba[1:0], romcs , buffen , ddir, ddir , 0] : iosel[3 , iowr , exmcs , dmagnt , drdy , iuerr , cpuhalt , syserr , sysav, inull, inst, flush, dia, rtc, txa, txb, gpiint, extintack, sysclk, reset , tdo. 6 / applies to ra[31:0], memwr , oe , 0] : memcs[9 7 / applies to prom8 , romwrt , busrdy , buserr , dmareq , dmaas, syshalt , nopar , rxa, rxb, extint[4:0], iwde, ewdint, wdclk, clk2, sysreset , tmode[1:0], debug, tck, trst , tms, tdi. 8 / applies to prom8 , romwrt , busrdy , buserr , dmareq , dmaas, syshalt , nopar , rxa, rxb, extint[4:0], iwde, ewdint, wdclk, clk2, sysreset , tmode[1:0], debug tck. 9 / applies to tms, tdi, trst 10 / applies to ra[31:0], rapar, rasi[3:0], rsize[1:0], r aspar, cpar, d[31:0], cb[6:0], d par, rldsto, dxfer, lock, rd, we , wrt, gpi[7:0]. 11 / tested during ac tests but not recorded. 12 / with reference edge of sysclk+. 13 / with reference edge of sysclk-. 14 / with reference edge of tck+. 15 / with reference edge of tck-.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 10 dscc form 2234 apr 97 case outline x millimeters inches symbol min max min max a 2.41 3.18 .095 .125 a1 2.06 2.56 .081 .101 a2 0.05 0.36 .002 .014 b 0.15 0.25 .006 .010 c 0.10 0.20 .004 .008 d/e 53.23 55.74 2.095 2.195 d1/e1 36.83 37.34 1.450 1.470 e 0.508 bsc .020 bsc l 8.20 9.20 .323 .362 n1/n2 64 64 figure 1. case outline .
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 11 dscc form 2234 apr 97 case x pin number pin name pin number pin name pin number pin name pin number pin name 1 gpiint 33 d[20] 65 d[0] 97 ra[18] 2 gpi[7] 34 d[19] 66 rsize[1] 98 v ddo 3 v ddo 35 d[18] 67 rsize[0] 99 v sso 4 v sso 36 v ddo 68 rasi[3] 100 ra[17] 5 gpi[6] 37 v sso 69 v ddo 101 ra[16] 6 gpi[5] 38 d[17] 70 v sso 102 ra[15] 7 gpi[4] 39 d[16] 71 rasi[2] 103 v ddo 8 gpi[3] 40 v cci 72 rasi[1] 104 v sso 9 v ddo 41 v ssi 73 rasi[0] 105 ra[14] 10 v sso 42 d[15] 74 ra[31] 106 v ddi 11 gpi[2] 43 d[14] 75 ra[30] 107 v ssi 12 gpi[1] 44 v ddo 76 v ddo 108 ra[13] 13 gpi[0] 45 v sso 77 v sso 109 ra[12] 14 d[31] 46 d[13] 78 ra[29] 110 v ddo 15 d[30] 47 d[12] 79 ra[28] 111 v sso 16 v ddo 48 d[11] 80 ra[27] 112 ra[11] 17 v sso 49 d[10] 81 v ddo 113 ra[10] 18 d[29] 50 v ddo 82 v sso 114 ra[9] 19 d[28] 51 v sso 83 ra[26] 115 v ddo 20 v ddi 52 d[9] 84 ra[25] 116 v sso 21 v ssi 53 d[8] 85 ra[24] 117 ra[8] 22 d[27] 54 d[7] 86 v ddi 118 ra[7] 23 d[26] 55 d[6] 87 v ssi 119 ra[6] 24 v ddo 56 v ddo 88 v ddo 120 v ddo 25 v sso 57 v sso 89 v sso 121 v sso 26 d[25] 58 d[5] 90 ra[23] 122 ra[5] 27 d[24] 59 d[4] 91 ra[22] 123 ra[4] 28 d[23] 60 d[3] 92 ra[21] 124 ra[3] 29 d[22] 61 d[2] 93 v ddo 125 v ddo 30 v ddo 62 v ddo 94 v sso 126 v sso 31 v sso 63 v sso 95 ra[20] 127 ra[2] 32 d[21] 64 d[1] 96 ra[19] 128 ra[1] figure 2. terminal connections .
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 12 dscc form 2234 apr 97 case x pin number pin name pin number pin name pin number pin name pin number pin name 129 ra[0] 161 syserr 193 dxfer 225 memcs[3] 130 v ddo 162 sysav 194 mexc 226 v ddo 131 v sso 163 extint[4] 195 v ddo 227 v sso 132 rapar 164 extint[3] 196 v sso 228 memcs[2] 133 raspar 165 extint[2] 197 reset 229 memcs[1] 134 dpar 166 extint[1] 198 sysreset 230 memcs[0] 135 v ddo 167 extint[0] 199 ba[1] 231 v ddi 136 v sso 168 v ddi 200 ba[0] 232 v ssi 137 sysclk 169 v ssi 201 cb[6] 233 oe 138 tdo 170 extintack 202 cb[5] 234 v ddo 139 trst 171 iuerr 203 v ddo 235 v sso 140 tms 172 v ddo 204 v sso 236 memwr 141 tdi 173 v sso 205 cb[4] 237 buffen 142 tck 174 cpar 206 cb[3] 238 ddir 143 clk2 175 txa 207 cb[2] 239 v ddo 144 drdy 176 rxa 208 cb[1] 240 v sso 145 dmaas 177 rxb 209 v ddo 241 ddir 146 v ddo 178 txb 210 v sso 242 mhold 147 v sso 179 iowr 211 cb[0] 243 mds 148 dmagnt 180 iosel[3] 212 ale 244 wdclk 149 exmcs 181 v ddo 213 v ddi 245 iwde 150 v ddi 182 v sso 214 v ssi 246 ewdint 151 v ssi 183 iosel[2] 215 prom8 247 tmode[1] 152 dmareq 184 iosel[1] 216 romcs 248 tmode[0] 153 buserr 185 iosel[0] 217 memcs[9] 249 debug 154 busrdy 186 wrt 218 v ddo 250 inull 155 romwrt 187 we 219 v sso 251 dia 156 nopar 188 v ddo 220 memcs[8] 252 v ddo 157 syshalt 189 v sso 221 memcs[7] 253 v sso 158 cpuhalt 190 rd 222 memcs[6] 254 flush 159 v ddo 191 rldsto 223 memcs[5] 255 inst 160 v sso 192 lock 224 memcs[4] 256 rtc figure 2. terminal connections ? continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 13 dscc form 2234 apr 97 figure 3. block diagram . device type 01 instruction name instruction code bypass 11.1111 extest 00.0000 sample/preload 00.0001 intest 00.0011 id code 10.0000 reserved for emulation 01.1000 reserved for emulation 01.1001 reserved for emulation 01.1010 reserved for emulation 01.1100 reserved for emulation 01.1101 reserved for emulation 01.1110 figure 4. boundary scan instruction codes .
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 14 dscc form 2234 apr 97 figure 5. timing waveforms .
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 15 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 16 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 17 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 18 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 19 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 20 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 21 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 22 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 23 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 24 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 25 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 26 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 27 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 28 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 29 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 30 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 31 dscc form 2234 apr 97 case outline v dd = 3.3 0.15 v ground other x 1 - 3, 5 - 9, 11 - 16, 20, 23, 24, 28, 30, 33, 34, 36, 40, 44, 50, 53, 56, 58, 62, 66 - 69, 71 - 76, 78 - 81, 83 - 86, 88, 90 - 93, 95 - 98, 100 - 103, 105, 106, 108 - 110, 112 - 115, 117 - 120, 122 - 125, 127 - 130, 132 - 135, 137, 138, 140 - 142, 144, 146, 148 - 150, 152 - 155, 157 - 159, 161 - 168, 170 - 172, 174 - 181, 183 - 188, 190 - 195, 197, 199, 200, 203, 206, 208, 209, 212, 213, 215 - 218, 220 - 226, 228 - 231, 233, 234, 236 - 239, 241 - 243, 250 - 252, 254 - 256 4, 10, 17 - 19, 21, 22, 25 - 27, 29, 31, 32, 35, 37 - 39, 41 - 43, 45 - 49, 51, 52, 54, 55, 57, 59 - 61, 63 - 65, 70, 77, 82, 87, 89, 94, 99, 104, 107, 111, 116, 121, 126, 131, 136, 139, 145, 147, 151, 156, 160, 169, 173, 182, 189, 196, 198, 201, 202, 204, 205, 207, 210, 211, 214, 219, 227, 232, 235, 240, 244 - 249, 253 143 notes: 1. pin 138 (tdo) is in the high-impedance (high z) state. 2. pin 143 (clk2) is activated at low frequency (below 100 hz). 3. the product is set in reset mode. 4. the following pins have serial resistors with the specified value attached: 1 k ? : 2, 5 ? 8, 11 ? 15, 18, 19, 22, 23, 26 ? 29, 32 ? 35, 38, 39, 42, 43, 46 ? 49, 52 ? 55, 58 ? 61, 64, 65, 134, 139 ? 143, 145, 152 ? 157, 163 ? 167, 176, 177, 198, 201, 202, 205 ? 208, 211, 215, and 244 ? 249. 5.6 k ? : 1, 66 ? 68, 71 ? 75, 78 ? 80, 83 ? 85, 90 ? 92, 95 ? 97, 100 ? 102, 105, 108, 109, 112 ? 114, 117 ? 119, 122 ? 124, 127 ? 129, 132, 133, 137, 138, 144, 148, 149, 158, 161, 162, 170, 171, 174, 175, 178 ? 180, 183 ? 187, 190 ? 194, 197, 199, 200, 212, 216, 217, 220 ? 225, 228 ? 230, 233, 236 ? 238, 241 ? 243, 250, 251, and 254 ? 256. for all other pins, no serial resistor is attached. 5. the following output pins have output buffer c apacitors with the specified value attached: 400 pf: 74, 75, 78 ? 80, 83 ? 85, 90 ? 92, 95 ? 97, 100 ? 102, 105, 108, 109, 112 ? 114, 117 ? 119, 122 ? 124, 127 ? 129, 233, and 236. for all other output pins, output buffers are 150 pf. 6. the following i/o pins are input at reset: 2, 5 ? 8, 11 ? 13, 134, 201, 202, 205 ? 208, and 211. 7. v ddo /v sso = output buffers. 8. v ddi /v ssi = internal logic. figure 6. radiation exposure connections . table ib. sep test limits . 1 / 2 / v dd = 3.15 v device type ta = temperature 10 c 3 / effective let no upsets [mev/(mg/cm 2 )] maximum device cross section (let = 80) (cm 2 ) bias for latch-up test v dd = 3.45 v no latch-up let 3 / all +25 c 8 2e-5 >80 1 / devices that contain cross coupled re sistance must be tested at the maximum rated t a . for sep test condition, see 4.4.4 herein. 2 / technology characterization and model verification supplemented by in-line data may be used in lieu of end-of-line. test plan must be approved by trb and qualifying activity. 3 / worst case temperature t a = +125 c.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 32 dscc form 2234 apr 97 4. quality assurance provisions 4.1 sampling and inspection . for device classes q and v, sampling and inspection procedures shall be in accordance with mil-prf-38535 or as modified in the device manufacturer's qua lity management (qm) plan. the modification in the qm plan shall not affect the form, fit, or function as described herein. for device class m, sampling and inspection procedures shall be in accordance with mil-prf-38535, appendix a. 4.2 screening . for device classes q and v, screening shall be in accordance with mil-prf-38535, and shall be conducted on all devices prior to qualification and technology conform ance inspection. for device class m, screening shall be in accordance with method 5004 of mil-std-883, and shall be conduct ed on all devices prior to qua lity conformance inspection. 4.2.1 additional criteria for device class m . a. burn-in test, method 1015 of mil-std-883. (1) test condition d. the test circuit shall be main tained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring ac tivity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (2) t a = +125 c, minimum. b. interim and final electrical test paramet ers shall be as specified in table iia herein. 4.2.2 additional criteria for device classes q and v . a. the burn-in test duration, test condition and test tem perature, or approved alternatives shall be as specified in the device manufacturer's qm plan in accordance with mil-prf- 38535. the burn-in test circuit shall be maintained under document revision level control of the device manufacture r's technology review board (trb) in accordance with mil-prf-38535 and shall be made available to the acquiring or preparing activity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of mil-std-883. b. interim and final electrical test paramet ers shall be as specified in table iia herein. c. additional screening for device class v beyond the requi rements of device class q shall be as specified in mil-prf-38535, appendix b. 4.3 qualification inspection for device classes q and v . qualification inspection for device classes q and v shall be in accordance with mil-prf-38535. inspections to be perform ed shall be those specified in mil-prf-38535 and herein for groups a, b, c, d, and e inspec tions (see 4.4.1 through 4.4.4). 4.4 conformance inspection . technology conformance inspection for cl asses q and v shall be in accordance with mil-prf-38535 including groups a, b, c, d, and e inspections and as specified herein. qualit y conformance inspection for device class m shall be in accordance with mil-prf-38535, appendi x a and as specified herein. inspections to be performed for device class m shall be those specified in method 5005 of mi l-std-883 and herein for groups a, b, c, d, and e inspections (see 4.4.1 through 4.4.4). 4.4.1 group a inspection . a. tests shall be as specified in table iia herein. b. for device class m, subgroups 7 and 8 tests shall verify the instruction set. the instruction set forms a part of the vendor?s test tape and shall be maintained and available for re view from the approved sources of supply. for device classes q and v, subgroups 7 and 8 shall include verifying the functionality of the device. c. subgroup 4 (c in measurement) shall be measured only for the initia l test and after process or design changes which may affect input capacitance. a minimum sample of 3 devices with zero rejects shall be required. 4.4.2 group c inspection . the group c inspection end-point electrical paramet ers shall be as specified in table iia herein.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 33 dscc form 2234 apr 97 4.4.2.1 additional criteria for device class m . steady-state life test conditions, method 1005 of mil-std-883: a. test condition d. the test circuit shall be mainta ined by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in acco rdance with the intent specified in test method 1005 of mil-std-883. b. t a = +125 c, minimum. c. test duration: 1,000 hours, except as permitted by method 1005 of mil-std-883. 4.4.2.2 additional criteria for device classes q and v . the steady-state life test duration, test condition and test temperature, or approved alternatives s hall be as specified in the device manuf acturer's qm plan in accordance with mil-prf-38535. the test circuit shall be maintained under docum ent revision level control by the device manufacturer's trb in accordance with mil-prf-38535 and shall be made available to the acquiring or preparing activity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissi pation, as applicable, in accordance with the intent specifie d in test method 1005 of mil-std-883. 4.4.3 group d inspection . the group d inspection end-point electrical paramet ers shall be as specified in table iia herein. 4.4.4 group e inspection . group e inspection is required only for par ts intended to be marked as radiation hardness assured (see 3.5 herein). a. end-point electrical par ameters shall be as specified in table iia herein. b. for device classes q and v, the devices or test vehicl e shall be subjected to radiation hardness assured tests as specified in mil-prf-38535 for the rha level being tested. for device class m, the devices shall be subjected to radiation hardness assured tests as specified in mil- prf-38535, appendix a for the rha level being tested. all device classes must meet the postirradiation end-point elec trical parameter limits as defined in table ia at t a = +25 c 5 c, after exposure, to the subgroups specified in table iia herein. c. when specified in the purchase or der or contract, a copy of the rha delta limits shall be supplied. 4.4.4.1 total dose irradiation testing . total dose irradiation testing shall be per formed in accordance with mil-std-883, test method 1019 (condition b) and as specified herein. 4.4.4.1.1 accelerated aging test . accelerated aging tests shall be performed on all devices requiring a rha level greater than 5k rads (si). the post-anneal end-point electrical parameter limits shall be as specified in table ia herein and shall be the pre-irradiation end-point electr ical parameter limit at 25 c 5 c. testing shall be performed at initial qualification and after any design or process changes which may affe ct the rha response of the device. 4.4.4.2 dose rate induced latchup testing . dose rate induced latchup testing shall be performed in accordance with test method 1020 of mil-std-883 and as specified herein (see paragr aph 1.5). tests shall be performed on devices, the standard evaluation circuit (sec), or approved test structures at tec hnology qualification and after any design or process changes which may effect the rha capability of the process. 4.4.4.3 dose rate upset testing . dose rate upset testing shall be performed in accordance with mil-std-883, test method 1021 and herein (see paragraph 1.5). a. transient dose rate upset testing shall be performed at initial qualification and after any design or process changes which may effect the rha performance of the devices. test 10 devices with 0 defects unless otherwise specified. b. transient dose rate upset testing for class q and v devices shall be performed as specified by a trb approved radiation hardness assur ance plan and mil-prf-38535.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 34 dscc form 2234 apr 97 table iia. electrical test requirements . subgroups (in accordance with mil-std-883, method 5005, table i) subgroups (in accordance with mil-prf-38535, table iii) test requirements device class m device class q device class v interim electrical parameters (see 4.2) --- --- 1, 7, 9 final electrical parameters (see 4.2) 1, 2, 3, 7, 8, 9, 10, 11 1 / 1, 2, 3, 7, 8, 9, 10, 11 1 / 1, 2, 3, 7, 8, 9, 10, 11 2/ 3 / group a test requirements (see 4.4) 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 group c end-point electrical parameters (see 4.4) 2, 8a, 10 2, 8a, 10 2, 8a, 10 3 / group d end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 group e end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 1 / pda applies to subgroup 1. 2 / pda applies to subgroups 1 and 7. 3 / delta limits are as specified in table iib herei n and shall be required where specified in table i. table iib. delta limits . parameter 1 / limit unit v oh 0.1 v v ol 0.1 v i ih 0.1 a i il 0.1 a i ozh 0.1 a i ozl 0.1 a 1 / the parameters shall be recorded before and after the required burn-in and life test to determine the delta limits.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 35 dscc form 2234 apr 97 4.4.4.4 single event phenomena (sep) . sep testing shall be required on class v devices (see paragraph 1.5). sep testing shall be performed on the sec or alternate sep test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may effect the upset or latchup characteristics. the recommended test conditions for sep are as follows: a. the ion beam angle of incidence shall be between normal to the die surface and 60 to the normal, inclusive (i.e. 0 angle 60 ). no shadowing of the ion beam due to fixturing or package related effects is allowed. b. the fluence shall be 100 errors or 10 6 ions/cm 2 . c. the flux shall be between 10 2 and 10 5 ions/cm 2 /s. the cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. the particle range shall be 20 microns in silicon. e. the upset test temperature shall be +25 c and the latchup test temperature is maximum rated operating temperature 10 c. f. bias conditions shall be defined by t he manufacturer for la tchup measurements. g. test four devices with zero failures. h. for sep test limits, see table ib herein. 5. packaging 5.1 packaging requirements . the requirements for packaging shall be in accordance with mil-prf-38535 for device classes q and v or mil-prf-38535, appendix a for device class m. 6. notes 6.1 intended use . microcircuits conforming to this drawing are intended for use for gove rnment microcircuit applications (original equipment), design applic ations, and logistics purposes. 6.1.1 replaceability . microcircuits covered by this drawing w ill replace the same generic device covered by a contractor-prepared specif ication or drawing. 6.1.2 substitutability . device class q devices will replace device class m devices. 6.2 configuration control of smd's . all proposed changes to existing smd's will be coordinated with the users of record for the individual documents. this coordination will be accomplished using dd form 1692, engineering change proposal. 6.3 record of users . military and industrial users should inform de fense supply center columbus when a system application requires configuration control and which smd's are applic able to that system. dscc will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. users of drawings covering microelectronic devices (fsc 5962) shoul d contact dscc-va, telephone (614) 692-0544. 6.4 comments . comments on this drawing should be directed to dscc-va , columbus, ohio 43216-5000, or telephone (614) 692-0547. 6.5 abbreviations, symbols, and definitions . the abbreviations, symbols, and definitions used herein are defined in mil-prf-38535, mil-hdbk-1331, and table iii herein. 6.6 sources of supply . 6.6.1 sources of supply for device classes q and v . sources of supply for device classes q and v are listed in qml-38535. the vendors listed in qml-38535 have submitted a certificate of compliance (see 3.6 herein) to dscc-va and have agreed to this drawing.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 36 dscc form 2234 apr 97 6.6.2 approved sources of supply for device class m . approved sources of supply for cl ass m are listed in mil-hdbk-103. the vendors listed in mil-hdbk-103 have agreed to this drawi ng and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by dscc-va. 6.7 additional information . a copy of the following additional data shall be maintained and available from the device manufacturer: a. rha upset levels. b. test conditions (sep). c. number of upsets (sep). d. number of transients (sep). e. occurrence of latchup (sep).
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 37 dscc form 2234 apr 97 table iii. terminal descriptions . pin name type 1 / description iu and fpu signals ra[31:0] i/o registered address bus. the address bus for the device is an output bus. inside the processor, the iu address bus is used to per form decoding, to generate select signals and to check against the memory access protection schem e. it is also used to address the system registers. to save board space, the address bus is sent out regi stered for external resources. this means that internal d-type flip-flop's ar e implemented inside the device to memorize the iu address bus at each rising edge of sysclk enabled by ale signal. this registered address bus is always driven by the devic e even during system registers accesses. in case of dma session, the address bus for the device is an input bus. the dma unit must drives itself the registered addr ess bus for the available parts of the processor during a dma session and for the external resources (sram's, rom's, i/o's ....). organization and addressing of data in memory fo llows the "big-endian" convention wherein lower addresses contain the higher-order byte s. attempting to access misaligned data will generate a memory-address- not-aligned trap (tt = 7). rapar i/o registered address bus parity. this output is the odd parit y over the 32-bit iu address bus. to save board space, this signal is sent out r egistered and has the same timing as ra[31:0]. in case of dma session, this signal must be driven by the dma unit if dma parity is enabled. this input requires the same timing as ra[31:0]. rasi[3:0] i/o 4-bit registered address space identifier. these four bits constitute the address space identifier (asi), which identifies the memory address space to which the instruction or data access is being directed. the asi bits are provided to detect supervisor or user mode, instruction or data access. inside the processor, these identifiers are used to control accesses to on-chip peripherals. to save board space, these outputs are sent out registered and has the same timing as ra[31:0]. in case of dma session, these signals must be driven by the dma unit. these inputs require the same timing as ra[31:0]. rsize[1:0] i/o 2-bit registered bus transaction size. t he coding on these pins specifies the size of the data being transferred during an instruction or a data fe tch. to save board space, these outputs are sent out registered and has the same timing as ra[31:0]. raspar i/o registered asi and size parity. this output is the odd parity ov er the rasi[3:0] and the rsize[1:0] signals. to save board space, this output is sent out registered and has the same timing as ra[31:0]. in case of dma session, this signal must be driven by the dma unit if dma parity is enabled. this input requires the same timing as ra[31:0]. cpar i/o control bus parity. this output is the odd parity over the rldsto, dxfer, lock, wrt, rd and we signals. this signal is sent out unregist ered and must be latched externally before it is used. in case of dma session, this signal must be driven by the dma unit if dma parity is enabled. see footnote at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 38 dscc form 2234 apr 97 table iii. terminal descriptions - continued. pin name type 1 / description iu and fpu signals ? continued d[31:0] i/o 32-bit data bus. these signals form a 32-bit bidirectional data bus that serves as the interface between the device and external memory. the data bus is not driven by the device during system registers accesses, it is only driven during the executi on of integer and floating-point store instructions and the store cycle of atomic-load-store instructions on external memory. store data is valid during the second data cycle of a store single access, the second and third data cycle of a store double access, and the thir d data cycle of an atomic-load-store access. alignment for load and store instructions is per formed by the processor. doublewords are aligned on 8-byte boundaries, words on 4-by te boundaries, and halfwords on 2-byte boundaries. if a doubleword, word, or halfwor d load or store instruction generates an improperly aligned address, a memory address not aligned trap will occur. instructions and operands are always expected to reside in a 32- bit wide memory. d[31] corresponds to the most significant bit of the most significant by te of a 32-bit word going to or from memory. cb[6:0] i/o 7-bit check-bit bus. cb [6:0] is the edac checkword over the 33-bit data bus consisting of d[31:0] and the parity bit (dpar). when the dev ice performs a write operation to the main memory, it will assert the edac checkword on the cb[6:0]. during read access from the main memory, cb[6:0] are input signals and will be used for checking and correction of the data word and the parity bit. during read access to areas which do not generate a parity bit, the device will latch the data from the accessed address and drive the correct parity bit on the dpar pin. dpar i/o data bus parity. this pin is used by the device to check and generate the odd parity over the 32-bit data bus during write cycles. dpar = not (d[31] xor d[30] xor .... xor d[1] xor d[0]) in case of dma session, this signal must be driven by the dma unit if dma parity is enabled. rldsto i/o registered atomic load-store. this signal is used to identify an atomic load-store to the system and is asserted by the iu during all the data cy cles (the load cycle and both store cycles) of atomic load-store instructions. to save board space, ldsto is sent out registered. in case of dma session, this signal must be driven unlatched by the dma unit. ale o address latch enable. this output is asserted w hen the internal address bus from the iu is to be latched. this latch operation is assumed by the internal latch. in case of dma session, this signal is intended to be used to enable the clock input (sysclk) of an external flip-flop used to la tch the generated address from dma unit. dxfer i/o data transfer. dxfer is used to di fferentiate between the addresses being sent out for instruction fetches and the addresses of data fe tches. dxfer is asserted by the processor during the address cycles of all bus data transfe r cycles, including both cycles of store single and all three cycles of store double and atomic l oad-store. dxfer is sent out unregistered and must be latched externally before it is used. a dma unit must supply this signal during a dma session. lock i/o bus lock. lock is asserted by the processor when it needs to retain control of the bus (address and data) for multiple cycle transac tions (load double, store single and double, atomic load-store). the bus will not be granted to another bus master as long as lock is asserted. note that mhold , when it reflects the internal signal "bus hold", should not be asserted in the processor clock cycle which follows a cycle in which lock is asserted. lock is sent out unregistered and must be la tched externally before it is used. a dma unit must supply this signal during a dma session. see footnote at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 39 dscc form 2234 apr 97 table iii. terminal descriptions - continued. pin name type 1 / description iu and fpu signals ? continued rd i/o read access. rd is sent out during the addre ss portion of an access to specify whether the current memory access is a read (rd = "1") or a write (rd = "0") operation. rd is set low only during the address cycles of stor e instructions. for atomic l oad-store instructions, rd is set high during the load address cycle and set low dur ing the two store address cycles. rd may be used, in conjunction with size[1:0], asi[7 :0], and ldsto, to determine the type and to check the read/write access rights of bus transacti ons in the extended general area. it is sent out unregistered and must be latched ex ternally before it is used. a dma unit must supply this signal during a dma session. mhold o memory bus hold. the signal is asserted when a ?memory hold? (mhold), or a ?floating point hold? (fhold) or a ?floating point condition c odes valid? (fccv) or a bus hold (bhold) is internally generated. note that mhold must be driven high while reset is low. ? "memory hold" "memory hold" is used to freeze the pipeline to both the iu and fpu accessing a slow memory or during memory exception. the iu and fpu in ternal outputs return to and stay at the value they had on the rising edge of sysclk in the cycle in which "memory hold" was asserted. "memory hold" is tested on the falling edge (midpoint of cycle) of sysclk. the memory wait state controller of the device inserts, in this way, wait states during external accesses. ? "floating-point hold" "floating-point hold" is asserted by the fpu if a situation arises in which the fpu cannot continue execution. the fpu checks all dependencies in the decode stage of the instruction and asserts a "floating-point hold" (if necessary) in the next cycle. if the iu receives a "floating-point hold", it freezes the instruction pipeline in the same cycle. once the conditions causing the "floating-point hold" are resolved, the fpu deasserts its command, releasing the instruction pipeline. a "floating-point hold" is asserted if: - the fpu encounters an stfsr instruction wi th one or more fpops pending in the queue, - either a resource or operand dependency ex ists between the fpop being decoded and any fpops already being executed, - the floating-point queue is full. ? "floating-point condition codes valid" "floating-point condition codes valid" is a s pecialized hold used to synchronize fpu compare instructions with floating-point branch instru ctions. it is asserted (the normal condition) whenever the "floating-point condition codes" bi ts (fcc[1:0]) are valid. the fpu deasserts these bits (= "0") as soon as a floating-point compare instruction ent ers the floating-point queue, unless an exception is detected. deassert ing the "floating-point condition codes" bits freezes the iu pipeline, preventing any further compares from entering the pipeline. the "floating-point condition codes" bits are rea sserted when the compare is completed and the condition codes are valid, thus ensuring that the condition codes match the proper compare instruction. ? "bus hold" "bus hold" is asserted during dma accesses. assertion of this hold signal will freeze the processor pipeline, so after deassertion of "bus hold", external logic must guarantee that the data at all inputs to the device is the same as it was before "bus hold" was asserted. this hold signal is tested on the falling edge (midpoint of cycle) of sysclk. see footnote at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 40 dscc form 2234 apr 97 table iii. terminal descriptions - continued. pin name type 1 / description iu and fpu signals ? continued we i/o write enable. we is asserted by the iu during the cycl e in which the store data is on the data bus. for a store single instruction, this is during the second store addr ess cycle, the second and third store address cycles of store double instructions and the third load-store address cycle of atomic load-store instructions. to av oid writing to memory during memory exceptions, we must be externally qualified by the mhold , when this holding reflects the internal signal "memory hold". it is sent out unregistered and must be latched externally before it is used. a dma unit must supply this signal during a dma session, asserted low for write and deasserted high for read accesses. wrt i/o advanced write. wrt is an early write signal , asserted by the processor during the first store address cycle of integer single or double store instructions, t he first store address cycle of floating-point single or double store instructi ons, and the second load-store address cycle of atomic load-store instructions. wrt is sent out unregistered and must be latched externally before it is used. a dma unit must supply this signal during a dma session, deasserted low for read and asserted high for write accesses. mds o memory data strobe. mds is asserted by the memory access controller of the device to enable the clock to the iu's instruction register ( during an instruction fetch) or to the load result register (during a data fetch) wh ile the pipeline is frozen with an mhold . in a system with slow memories, mds tells the processor when the read data is available on the bus. mds is also used to strobe in the mexc memory exception signal. mds is only asserted when the pipeline is frozen with mhold . mexc o memory exception. assertion of this signal by the memory access controller of the device initiates a memory exception and indicates to the iu that the memory system was unable to supply a valid instruction or data. if mexc is asserted during an instruction fetch cycle, it generates an instruction access exception trap ( tt=1). if asserted during a data cycle, it generates a data access exception trap (tt=9). it denotes a parity error, uncorrectable edac error, access violation, bus time-out or system bus error is detected. mexc is used as a qualifier for the mds signal, and is asserted when both mhold and mds are already asserted. if mds is applied without mexc , the device accepts the contents of the data bus as valid. if mexc accompanies mds , an exception is generated and the data bus content is ignored. mexc is latched in the iu on the rising edge of sysclk and is used in the following cycle. mexc is deasserted in the same clock cycle in which mhold is deasserted. if this signal is asserted during a dma transfe r, the dma must withdraw its dma request and end the dma cycle. see footnote at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 41 dscc form 2234 apr 97 table iii. terminal descriptions - continued. pin name type 1 / description memory and system interface signals prom8 i select 8-bit wide prom. this input indicate s that only 8-bit wide prom is connected to the device. the eight data lines from the prom is to be connected to the d[7:0] signals. the processor will perform an 8-bit to 32-bit conv ersion when the iu reads from the prom (the conversion is not visible on data bus). there is no edac or parity checking on accesses to the prom when prom8 is asserted, and edac and parity bits must be supplied by the prom when prom8 is deasserted. ba[1:0] o latched address used for 8-bit wide boot prom. these outputs are used when 8-bit wide prom is connected to the device. during a fetch or 32-bit load access to the prom , the ba[1:0] will be asserted four times in order to get the four bytes needed to generate a 32-bit word. romcs o prom chip select. this output is asserted whenever there is an access to the boot rom and extended prom areas. it can be connected dire ctly to the prom chip select pins. romwrt i rom write enable. assertion of this signal will enable the pwr bit of the memory configuration register (mcnfr). this logic allows the on- board programming (write operations) of the boot prom when eeprom or flash devices are used. 0] : memcs[9 o memory chip select. 0] : memcs[9 is asserted during an access to the main memory. 8] : memcs[9 are redundant signals, used to substitute any of the nominal memory banks when memory connected to any of 0] : memcs[7 malfunctions. memwr o memory write. memwr is asserted during write access (store) to boot prom area, extended prom area, ram area and extended ram area. it is intended to be used as write strobe to the memory devices. oe o memory output enable. oe is asserted during fetch or load accesses to the main memory. it is intended to be used to control memory devices with output enable features. buffen o data buffer enable. buffen is asserted during memory accesses excepted in ram area (ram area does not needs data buffers). it is intended to be used as buffer enable for data, check and parity bit buffers in the boot prom area, extended prom area, exchange memory area, extended ram area, i/o area, extended i/o area and extended general area if these areas share the same buffers. ddir o data buffer direction. ddir is used for det ermining the direction of the data buffers enabled by buffen . it is valid during all memory accesses. the ddir is asserted high during store operations. ddir o data buffer direction. ddir is used for determining the direction of the data buffers enabled by buffen . it is valid during all memory accesses. the ddir is asserted high during fetch or load operations. 0] : iosel[3 o i/o chip select. these four select signals are used to enable one of four possible i/o address areas. iowr o i/o and exchange memory write strobe. iowr is asserted during write operations to the i/o area, extended i/o area and the exchange memory area. see footnote at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 42 dscc form 2234 apr 97 table iii. terminal descriptions - continued. pin name type 1 / description memory and system interface signals - continued exmcs o exchange memory chip select. exmcs is asserted when the exchange memory is accessed. busrdy i bus ready. busrdy is to be generated by a unit in the i/o area, exchange memory area or in the extended areas, which requires extended time when accessed in addition to the preprogrammed number of wait states. (not e however that wait states can not be preprogrammed for units in the extended general area, only for extended i/o, boot prom and ram). error, dma, halt, and check signals buserr i bus error. buserr is to be generated together with busrdy by a unit in the i/o area, exchange memory area or in the extended areas if an error is detected by the accessed unit during an access. dmareq i dma request. dmareq is to be issued by a unit requesting the access to the processor bus as a master. the device can include a dma se ssion timeout function preventing the dma unit to lockout the iu/fpu by asserting dma request for a long time. dmagnt o dma grant. dmagnt is generated by the device as a response to a dmareq . dmagnt is sent after that the device has asserted a "bus ho ld". a memory cycle started by the processor is not interrupted by a dma access before it is finished. the dma unit has access to all system registers and all integrated peripherals of the device. it has also access to the memory controlled by the memory access controller of the device. dmaas i dma address strobe. during dma transfers (when the external dma is bus master) this input is used to inform the device that the address from the dma is valid and that the access cycle shall start. dmaas can be asserted multiple times during dma grant. drdy o data ready during dma access. during dma read transfers (when the external dma is bus master) this output is used to inform the dma unit that the data are valid. during dma write transfers this signal indicates that data have been written into memory. iuerr o iu error. this signal is asserted when the (m aster) iu enters the "error mode" state. this happens if a synchronous trap occurs while traps are disabled (the %psr's et bit = 0). before it enters the error mode state, the device saves t he %pc and %npc and sets the trap type (tt) for the trap causing the error mode into the %tbr. it then asserts the error signal and halts. the only way to restart a processor which is in the e rror mode state is to trigger a reset by asserting the reset signal. cpuhalt o processor (iu & fpu) halt and freeze. this output informs that the iu and the fpu are in "halt" mode. it can be used to halt other units in the system. cpuhalt signal is also used to advise the "freeze" mode generated by the ocd. syserr o system error. this signal is asserted whenever an unmasked error is set in the error and reset status register (errrsr). it stays asserted until the errrsr is cleared. the error can originate from either the iu (iu error ar iu hardware error) or the sy stem registers (system hardware error). syserr and iuerr are used to signal to the application system. see footnote at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 43 dscc form 2234 apr 97 table iii. terminal descriptions - continued. pin name type 1 / description error, dma, halt, and check signals - continued syshalt i system halt. assertion of this pin will halt t he device, freezing iu/fpu execution. sysclk and internal clk2 are running but all the timers and watchdog are halted and the uart operation is stopped. dma accesses are allowed during halt mode. when syshalt is deasserted, the previous mode is entered. sysav o system availability. this signal is assert ed whenever the system is available, i.e. when the sysav bit in the errrsr is set and the cpuhalt and syserr signals are deasserted. the sysav bit is cleared by reset and is programmable by software. nopar i no parity. assertion of this signal will disabl e the parity checking of all signals related to the device internal buses. the parity generation on the data bus (towards and io units) is not affected by this signal, but note that parity checking is disabled if nopar is asserted. this is a static signal and shall not change when running. when this signal is asserted (no parity), it disables the epa and rpa bits of the memory configuration register (mcnfr) and the pa3, pa2, pa1, and pa0 bits of the i/o configuration register. inull o integer unit nullify cycle. the processor a sserts inull to indicate that the current memory access is being nullified. it is asserted at t he beginning of the cycle in which the address being nullified is active. inull is used to disabl e memory exception generation for the current memory access. this means that mds and mexc is not be asserted for a memory access in which inull = 1. inull is asserted under the following conditions: - during the second data cycle of any store inst ruction (including atomic load-store) to nullify the second occurrence of the store address, - on all traps, to nullify the third instruction fe tch after the trapped instruction. for reset, it nullifies the error-producing address, - on a load in which the hardware interlock is activated, - on jmpl and rett instructions. inst o instruction fetch. the inst signal is asserted by the iu whenever a new instruction is being fetched. it is used by the fpu to latch the inst ruction currently on the internal data bus into an fpu instruction buffer. the fpu have two instruction buffers (d1 and d2) to save the last two fetched instructions. when inst is asserted, a new instruction enters buffer d1 and the instruction that was in d1 moves to buffer d2. flush o fpu instruction flush. this signal is asse rted by the iu whenever it takes a trap. flush is used by the fpu to flush the instructions in its in struction buffers. these instructions, as well as the instructions annulled in the iu pipeline, are re started after the trap handler is finished. if the trap was not caused by a floating-point exception, instructions already in the floating-point queue may continue their execution. if the trap wa s caused by a floating-point exception, the fpqueue must be emptied before the fpu can resume execution. dia o delay instruction annulled. this signal is asserted when the delay instruction is annulled (c.f. delayed control transfer). this signal is used to trace the iu execution pipe. see footnote at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 44 dscc form 2234 apr 97 table iii. terminal descriptions - continued. pin name type 1 / description interrupt, clock, uart, gpi, timer, tap, and test signals rtc o real time clock counter output. this signal is generated when the delay time has elapsed in the "real time clock timer". this output is asserted high for one sysclk period. rxa/rxb i receive data uart "a" and "b". rxa is the serial data input for channel a of the uart. rxb is the serial data input for channel b of the uart. txa/txb o transmit data uart "a" and "b". txa is the serial data output for channel a of the uart. txb is the serial data output for channel b of the uart. gpi[7:0] i/o general purpose interface. each pin of the gpi is programmable as input or output gpiint o general purpose interface interrupt. an edge detection (rising or falling) is made on each gpi input pin configured as input. gpiint is the resu lt of a logical or of these detections. this output is asserted high for two sysclk periods. extint[4:0] i external interrupt. the five external interrupt inputs are programmable to be level or edge sensitive, and active high (rising) or active low (falling). extintack o external interrupt acknowledge. extint ack is used for giving acknowledge to an interrupting unit which requires such a signal. it is programm able to which of the five external interrupt inputs it is associated. it is issued as soon as the iu has recognized the interrupt. iwde i internal watch dog enable. this static signal commands the multiplexer placed in front of the watch dog timeout interrupt of the "interrupt pendi ng register". to use the internal watch dog, iwde must set to high. this input set to lo w enables the input ewdint for an external watch dog and disables entirely the internal watch dog (not running). the value of iwde is copied into the "system control register" bit 15. ewdint i external watch dog input interrupt. this input enabled by iwde receives an external watch dog timeout. another usage of this input can be an nmi. this input must asserted high for a minimum of two sysclk periods. wdclk i watch dog clock. wdclk is the wd clock input but this clock can also be used as a clock input for the uart interface. the clock frequency of wdclk must be less than the clock frequency of sysclk, i.e. f wdclk < f sysclk . clk2 i double frequency clock. clk2 is the input clock to the device. the frequency of this clock must be twice the clock frequency f sysclk used to drive the iu and the fpu. note that some external timings of the device can be affected by the duty cycle of clk2. sysclk o system clock. sysclk is a nominally 50% duty-cycle clock generated by the device from clk2 and is used for clocking the iu and the fpu as well as other system logic. note that the timing of the device is referenced by sysclk. reset o output reset. reset will be asserted when the device is to be synchronously reset. this occurs when either sysreset is asserted or the device initiates a reset due to an error or a programming command. the minimum pulse width of reset is 1024 sysclk periods to authorize the implementation of flash memories in the application. sysreset i system input reset. assertion of this pin w ill reset the device. following this assertion, reset is generated for a minimum of 1024 sysclk periods. sysreset must be asserted for a minimum of 4 sysclk periods. see footnote at end of table.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 45 dscc form 2234 apr 97 table iii. terminal descriptions - continued. pin name type 1 / description interrupt, clock, uart, gpi, timer, tap, and test signals ? continued tmode[1:0] i factory test mode. this test mode is onl y dedicated for factory test mode. the user functional mode is: tmode[1:0] = "00". debug i software debug mode. debug directly enables the setting of halt bits of the "timer control register" to freeze in tegrated peripherals. - debug + phlt freeze the internal watch dog and the 2 internal timers, - debug + phlt + ahlt freeze the channel a of the internal uart, - debug + phlt + bhlt freeze the channel b of the internal uart. for final application, this pin must be grounded. this allows to keep software included debug facilities. tck i test (jtag) clock. test clock for scan registers. trst i test (jtag) reset. asynchronous reset for the tap controller. for final application, this pin must be grounded. tms i test (jtag) mode select. sele cts test mode of the tap controller. tdi i test (jtag) data input. test scan register data input. tdo o test (jtag) data output. test scan register data output. power signals v ddo /v ddi power. v ddo pins supply the output and bidirectional pins of the device. v ddi pins supply the input and the main internal circuitry of the device. v sso /v ssi ground. v sso pins provide ground return for the output and bidirectional pins of the device. v ssi pins provide ground return for the input and the main internal circuitry of the device. 1 / i = input; o = ouput.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 46 dscc form 2234 apr 97 appendix a appendix a forms a part of smd 5962-03246 a.1 scope a.1.1 scope . this appendix establishes minimum requirements for microcircuit die to be supplied under the qualified manufacturers list (qml) program. qml microcircuit die meeting the requirem ents of mil-prf-38535 and the manufacturers approved qm plan for use in monolithic microc ircuits, multi-chip modules (mcms), hybr ids, electronic modules, or devices using chip and wire designs in accordance with mil-prf-38534 are spec ified herein. two product assurance classes consisting of military high reliability (device class q) and space application (dev ice class v) are reflected in the part or identification n umber (pin). when available a choice of radiation hardine ss assurance (rha) levels are reflected in the pin. a.1.2 pin . the pin is as shown in the following example: 5962 - 03246 01 v 9 a federal stock class designator rha designator (see a.1.2.1) device type (see a.1.2.2) device class designator die code die details (see a.1.2.4) \ / (see a.1.2.3) \/ drawing number a.1.2.1 rha designator . device classes q and v rha identified die sha ll meet the mil-prf-38535 specified rha levels. a dash (-) indicates a non-rha die. a.1.2.2 device type(s) . the device type(s) shall identify the circuit function as follows: device type generic number circuit function frequency 01 tsc695fl 32-bit sparc low voltage 15 mhz processor a.1.2.3 device class designator . device class device requirements documentation q or v cert ification and qualification to the die requirements of mil-prf-38535 a.1.2.4 die details . the die details designation shall be a unique lette r which designates the die's physical dimensions, bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for ea ch product and variant supplied to this appendix. a.1.2.4.1 die physical dimensions . figure a-1 a.1.2.4.2 die bonding pad locations and electrical functions . figure a-1 a.1.2.4.3 interface materials . figure a-1 a.1.2.4.4 assembly related information . figure a-1
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 47 dscc form 2234 apr 97 appendix a appendix a forms a part of smd 5962-03246 a.1.3 absolute maximum ratings . see paragraph 1.3 herein for details. a.1.4 recommended operating conditions . see paragraph 1.4 herein for details. a.2 applicable documents. a.2.1 government specif ications, standards, and handbooks . unless otherwise specified, the following specification, standard, and handbook of the issue listed in that issue of the department of defense index of specifications and standards specified in the solicitation, form a part of this drawing to the extent specified herein. specification department of defense mil-prf-38535 - integrated circuits , manufacturing, general specification for. standards department of defense mil-std-883 - test method standard microcircuits. handbook department of defense mil-hdbk-103 - list of standard microcircuit drawings. (copies of the specification, standard, and handbook required by manufacturers in connection with specific acquisition functions should be obtained from the c ontracting activity or as direct ed by the contracting activity). a.2.2 order of precedence . in the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. a.3 requirements a.3.1 item requirements . the individual item requirements for device classes q and v shall be in accordance with mil-prf-38535 and as specified herein or as modified in the device manufacturer?s quality management (qm) plan. the modification in the qm plan shall not effect the form, fit or function as described herein. a.3.2 design, construction and physical dimensions . the design, construction and phy sical dimensions shall be as specified in mil-prf-38535 and the manufacturer?s qm plan, for device classes q and v and herein. a.3.2.1 die physical dimensions . the die physical dimensions shall be as specified in a.1.2.4.1 and on figure a-1. a.3.2.2 die bonding pad locations and electrical functions . the die bonding pad locations and electrical functions shall be as specified in a.1.2.4.2 and on figure a-1. a.3.2.3 interface materials . the interface materials for the die shall be as specified in a.1.2.4.3 and on figure a-1. a.3.2.4 assembly related information . the assembly related information shall be as specified in a.1.2.4.4 and figure a-1. a.3.2.5 radiation exposure connections . the radiation exposure connections sha ll be as defined in paragraph 3.2.6 herein. a.3.3 electrical performanc e characteristics and post-i rradiation parameter limits . unless otherwise specified herein, the electrical performance characteristics and pos t-irradiation parameter limit s are as specified in table ia of the body of this document. a.3.4 electrical test requirements . the wafer probe test requirements shall include functional and parametric testing sufficient to make the packaged die capable of meeting the electrical performance requirements in table ia.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 48 dscc form 2234 apr 97 appendix a appendix a forms a part of smd 5962-03246 a.3.5 marking . as a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a customer, shall be identified with the wafer lot number, the ce rtification mark, the manufactu rer?s identification and the pin listed in a.1.2 herein. the certification mark s hall be a ?qml? or ?q? as required by mil-prf-38535. a.3.6 certification of compliance . for device classes q and v, a certificate of compliance shall be required from a qml- 38535 listed manufacturer in order to supply to the requirements of this drawing (s ee a.6.4 herein). the certificate of compliance submitted to dscc-va prior to listing as an approved source of supply for this appendix shall affirm that the manufacturer?s product meets, for device classes q and v, t he requirements of mil-prf-38535 and the requirements herein. a.3.7 certificate of conformance . a certificate of conformance as requi red for device classes q and v in mil-prf-38535 shall be provided with each lot of microc ircuit die delivered to this drawing. a.4 quality assurance provisions a.4.1 sampling and inspection . for device classes q and v, die sampling and inspection procedures shall be in accordance with mil-prf-38535 or as modified in the dev ice manufacturer?s quality management (qm) plan. the modifications in the qm plan shall not effect the form, fit or function as described herein. a.4.2 screening . for device classes q and v, screening shall be in accordance with mil-prf-38535, and as defined in the manufacturer?s qm plan. as a minimum it shall consist of: a) wafer lot acceptance for class v product using the criteria defined in mil-std-883 test method 5007. b) 100% wafer probe (see paragraph a.3.4 herein). c) 100% internal visual inspection to the applicable cla ss q or v criteria defined in mil-std-883 test method 2010 or the alternate procedures allowed in mil-std-883 test method 5004. a.4.3 conformance inspection . a.4.3.1 group e inspection . group e inspection is required only for parts in tended to be identified as radiation assured (see a.3.5 herein). rha levels for device classes q and v shall be as specified in mil-prf-38535. end point electrical testing of packaged die shall be as specified in table ii herein. group e tests and conditions are as spec ified in paragraphs 4.4.4 herei n. a.5 die carrier a.5.1 die carrier requirements . the requirements for the die carrier shall be accordance with the manufacturer?s qm plan or as specified in the purchase order by the acquiring activity. the die carrier shall provide adequate physical, mechanical and electrostatic protection. a.6 notes a.6.1 intended use . microcircuit die conforming to th is drawing are intended for use in micr ocircuits built in accordance with mil-prf-38535 or mil-prf-38534 for government microcircuit applications (origi nal equipment), design applications and logistics purposes. a.6.2 comments . comments on this appendix should be directed to dscc-va, columbus, ohio, 43216-5000 or telephone (614)-692-0547. a.6.3 abbreviations, symbols and definitions . the abbreviations, symbols, and definitions used herein are defined in mil-prf-38535 and mil-hdbk-1331. a.6.4 sources of supply for device classes q and v . sources of supply for device classes q and v are listed in qml-38535. the vendors listed within qml-38535 have submitted a certific ate of compliance (see a.3.6 herein) to dscc-va and have agreed to this drawing.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 49 dscc form 2234 apr 97 appendix a appendix a forms a part of smd 5962-03246 due to the complexity of the device, a graphical representation of the pad locations is not available. this figure shall be maintained and available from the device manufacturer. see subsequent pages for a table of pad locations. die bonding pad locations and electrical functions - mask number 5186 die physical dimensions . die size: 11,010 x 11,170 microns (with scribe line) die thickness: 475 microns interface materials . top metallization: al cu backside metallization: si (bare) glassivation . type: oxinitride thickness: 21 k? substrate : single crystal silicon assembly related information . substrate potential: not connected special assembly instructions: none figure a-1. die bonding pad locations and electrical functions .
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 50 dscc form 2234 apr 97 appendix a appendix a forms a part of smd 5962-03246 die bonding pad locations. pad x center y center pad x c enter y center pad x center y center pad x center y center 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4807.1 4655.1 4503.1 4351.1 4199.1 4047.1 3895.1 3743.1 3591.1 3439.1 3287.1 3135.1 2983.1 2831.1 2679.1 2527.1 2375.1 2223.1 2071.1 1919.1 1767.1 1615.1 1463.1 1311.1 1159.1 1007.1 855.1 703.1 551.1 399.1 247.1 95.1 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 -75.8 -227.8 -379.8 -531.8 -683.8 -835.8 -987.8 -1139.8 -1291.8 -1443.8 -1595.8 -1747.8 -1899.8 -2051.8 -2203.8 -2355.8 -2507.8 -2659.8 -2811.8 -2963.8 -3115.8 -3267.8 -3419.8 -3571.8 -3723.8 -3875.8 -4027.8 -4179.8 -4331.8 -4483.8 -4635.8 -4787.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 96 87 88 89 90 91 92 93 94 95 96 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 4807.1 4655.1 4503.1 4351.1 4199.1 4047.1 3895.1 3743.1 3591.1 3439.1 3287.1 3135.1 2983.1 2831.1 2679.1 2527.1 2375.1 2223.1 2071.1 1919.1 1767.1 1615.1 1463.1 1311.1 1159.1 1007.1 855.1 703.1 551.1 399.1 247.1 95.1 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -75.8 -227.8 -379.8 -531.8 -683.8 -835.8 -987.8 -1139.8 -1291.8 -1443.8 -1595.8 -1747.8 -1899.8 -2051.8 -2203.8 -2355.8 -2507.8 -2659.8 -2811.8 -2963.8 -3115.8 -3267.8 -3419.8 -3571.8 -3723.8 -3875.8 -4027.8 -4179.8 -4331.8 -4483.8 -4635.8 -4787.8 see notes at end of figure. figure a-1. die bonding pad locations and electrical functions - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 51 dscc form 2234 apr 97 appendix a appendix a forms a part of smd 5962-03246 die bonding pad locations - continued. pad x center y center pad x c enter y center pad x center y center pad x center y center 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 -4807.1 -4655.1 -4503.1 -4351.1 -4199.1 -4047.1 -3895.1 -3743.1 -3591.1 -3439.1 -3287.1 -3135.1 -2983.1 -2831.1 -2679.1 -2527.1 -2375.1 -2223.1 -2071.1 -1919.1 -1767.1 -1615.1 -1463.1 -1311.1 -1159.1 -1007.1 -855.1 -703.1 -551.1 -399.1 -247.1 -95.1 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 75.8 227.8 379.8 531.8 683.8 835.8 987.8 1139.8 1291.8 1443.8 1595.8 1747.8 1899.8 2051.8 2203.8 2355.8 2507.8 2659.8 2811.8 2963.8 3115.8 3267.8 3419.8 3571.8 3723.8 3875.8 4027.8 4179.8 4331.8 4483.8 4635.8 4787.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 -4807.1 -4655.1 -4503.1 -4351.1 -4199.1 -4047.1 -3895.1 -3743.1 -3591.1 -3439.1 -3287.1 -3135.1 -2983.1 -2831.1 -2679.1 -2527.1 -2375.1 -2223.1 -2071.1 -1919.1 -1767.1 -1615.1 -1463.1 -1311.1 -1159.1 -1007.1 -855.1 -703.1 -551.1 -399.1 -247.1 -95.1 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 75.8 227.8 379.8 531.8 683.8 835.8 987.8 1139.8 1291.8 1443.8 1595.8 1747.8 1899.8 2051.8 2203.8 2355.8 2507.8 2659.8 2811.8 2963.8 3115.8 3267.8 3419.8 3571.8 3723.8 3875.8 4027.8 4179.8 4331.8 4483.8 4635.8 4787.8 see notes at end of figure. figure a-1. die bonding pad locations and electrical functions - continued.
size a 5962-03246 standard microcircuit drawing defense supply center columbus columbus, ohio 43216-5000 revision level sheet 52 dscc form 2234 apr 97 appendix a appendix a forms a part of smd 5962-03246 die bonding pad locations - continued. notes: 1. the die center is the coordinate origin (0,0). 2. coordinates are in microns. 3. numbering of pad is not the numbering of the package pin. it differs as follows: package pin 1 = die pad 256 package pin 2 = die pad 255 package pin 3 = die pad 254 ? ? ? package pin 256 = die pad 1 figure a-1. die bonding pad locations and electrical functions - continued.
standard microcircuit drawing bulletin date: 03-08-14 approved sources of supply for smd 5962-03246 are listed below for immediate acquisition information only and shall be added to mil-hdbk-103 and qml-38535 during the next revision. mil-hdbk-103 and qml-38535 will be revised to include the addition or deletion of sources. the vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accept ed by dscc-va. this bulletin is superseded by the next dated revision of mil-hdbk-103 and qml-38535. standard microcircuit drawing pin 1 / vendor cage number vendor similar pin 2 / 5962-0324601qxc f7400 tsc695fl-15mamq 5962-0324601vxc f7400 tsc695fl-15sasv 5962r0324601vxc f7400 ts c695fl-15sasr 5962-0324601q9a f7400 tsc695fl-15mbmq 5962-0324601v9a f7400 tcs695fl-15sbsv 1 / the lead finish shown for each pin representing a hermetic package is the most readily available from the manufacturer listed for that part. if the desired lead finish is not listed contact the vendor to determine its availability. 2 / caution . do not use this number for item acquisition. items acquired to this number may not satisfy the performance requirements of this drawing. vendor cage vendor name number and address f7400 atmel nantes sa bp70602 44306 nantes cedex 3, france the information contained herein is disseminated for convenience only and the government assumes no liability whatsoever for any inaccuracies in the information bulletin.

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