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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADSP-2188M one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 dsp microcomputer functional block diagram arithmetic units shifter mac alu program memory address data memory address program memory data data memory data power-down control memory program memory 48k 24 bit data memory 56k 16 bit external address bus external data bus byte dma controller full memory mode sport0 serial ports sport1 programmable i/o and flags timer host mode or external data bus internal dma port dag1 data address generators dag2 program sequencer adsp-2100 base architecture ice-port is a trademark of analog devices, inc. features performance 13.3 ns instruction cycle time @ 2.75 v (internal), 75 mips sustained performance single-cycle instruction execution single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle multifunction instructions power-down mode featuring low cmos standby power dissipation with 200 clkin cycle recovery from power-down condition low power dissipation in idle mode integration adsp-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions 256k bytes of on-chip ram, configured as 48k words program memory ram 56k words data memory ram dual-purpose program memory for both instruction and data storage independent alu, multiplier/accumulator, and barrel shifter computational units two independent data address generators powerful program sequencer provides zero overhead looping conditional instruction execution programmable 16-bit interval timer with prescaler 100-lead lqfp and 144-ball mini-bga system interface flexible i/o structure allows 2.75 v or 3.3 v operation; all inputs tolerate up to 3.6 v regardless of mode 16-bit internal dma port for high-speed access to on-chip memory (mode selectable) 4 mbyte memory interface for storage of data tables and program overlays (mode selectable) 8-bit dma to byte memory for transparent program and data memory transfers (mode selectable) i/o memory interface with 2048 locations supports parallel peripherals (mode selectable) programmable memory strobe and separate i/o memory space permits glueless system design programmable wait state generation two double-buffered serial ports with companding hardware and automatic data buffering automatic booting of on-chip program memory from byte-wide external memory, e.g., eprom, or through internal dma port six external interrupts 13 programmable flag pins provide flexible system signaling uart emulation through software sport reconfiguration ice-port? emulator interface supports debugging in final systems
rev. 0 C2C ADSP-2188M table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 3 development system . . . . . . . . . . . . . . . . . . . . . . . 3 additional information . . . . . . . . . . . . . . . . . . . . . . . . . . 3 architecture overview . . . . . . . . . . . . . . . . . . . . 4 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 common-mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 memory interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 full memory mode pins (mode c = 0) . . . . . . . . . . . . . . 7 host mode pins (mode c = 1) . . . . . . . . . . . . . . . . . . . . 7 terminating unused pins . . . . . . . . . . . . . . . . . . . . . . . . 8 pin terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 low power operation . . . . . . . . . . . . . . . . . . . . . . . 9 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 slow idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . 10 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 modes of operation . . . . . . . . . . . . . . . . . . . . . . . 11 setting memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11 passive configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 active configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 iack configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 memory architecture . . . . . . . . . . . . . . . . . . . . . 12 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 memory mapped registers (new to the ADSP-2188M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i/o space (full memory mode) . . . . . . . . . . . . . . . . . . . 14 composite memory select ( cms ) . . . . . . . . . . . . . . . . . 14 byte memory select ( bms ) . . . . . . . . . . . . . . . . . . . . . . 14 byte memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 byte memory dma (bdma, full memory mode) . . . . 14 internal memory dma port (idma port; host memory mode) . . . . . . . . . . . . . . 15 bootstrap loading (booting) . . . . . . . . . . . . . . . . . . . . . 16 idma port booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 bus request and bus grant . . . . . . . . . . . . . . . . . . . . . . 16 flag i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 instruction set description . . . . . . . . . . . . . . . . . . . . . . 17 designing an ez-ice-compatible system . . . 17 target board connector for ez-ice probe . . . . . . . . . . 18 target memory interface . . . . . . . . . . . . . . . . . . . . . . . . 18 pm, dm, bm, iom, and cm . . . . . . . . . . . . . . . . . . . . 18 target system interface signals . . . . . . . . . . . . . . . . . . . 18 recommended operating conditions . . . . . 19 electrical characteristics . . . . . . . . . . . . . . . 19 absolute maximum ratings . . . . . . . . . . . . . . . 20 timing specifications . . . . . . . . . . . . . . . . . . . . . 20 general notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 timing notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 memory timing specifications . . . . . . . . . . . . 20 frequency dependency for timing specifications . . . . . . . . . . . . . . . . . . . . 21 environmental conditions . . . . . . . . . . . . . . . 21 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 21 output drive currents . . . . . . . . . . . . . . . . . . . . . . . . . . 21 capacitive loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 output disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 output enable time . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 clock signals and reset . . . . . . . . . . . . . . . . . . . . . . . . . 24 interrupts and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 bus request?us grant . . . . . . . . . . . . . . . . . . . . . . . . . 26 memory read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 memory write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 idma address latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 idma write, short write cycle . . . . . . . . . . . . . . . . . . 31 idma write, long write cycle . . . . . . . . . . . . . . . . . . . 32 idma read, long read cycle . . . . . . . . . . . . . . . . . . . 33 idma read, short read cycle . . . . . . . . . . . . . . . . . . . 34 idma read, short read cycle in short read only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 100-lead lqfp pin configuration . . . . . . . . . . 36 lqfp package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 144-ball mini-bga package pinout . . . . . . . . . . . . . . . . . 38 mini-bga package pinout . . . . . . . . . . . . . . . . . . . . . . . . 39 outline dimensions 100-lead metric thin plastic quad flatpack (lqfp) (st-100) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 outline dimensions 144-ball mini-bga (ca-144) . . . . . . . . . . . . . . . . . . . . 40 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 tables table i. interrupt priority and interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table ii. modes of operation . . . . . . . . . . . . . . . . . . . . . . 11 table iii. pmovlay bits . . . . . . . . . . . . . . . . . . . . . . . . 12 table iv. dmovlay bits . . . . . . . . . . . . . . . . . . . . . . . . 13 table v. wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table vi. data formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14
rev. 0 ADSP-2188M C3C general description the ADSP-2188M is a single-chip microcomputer optimized for digital signal processing (dsp) and other high-speed numeric processing applications. the ADSP-2188M combines the adsp-2100 family base archi- tecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, exten- sive interrupt capabilities, and on-chip program and data memory. the ADSP-2188M integrates 256k bytes of on-chip memory configured as 48k words (24-bit) of program ram, and 56k words (16-bit) of data ram. power-down circuitry is also pro- vided to meet the low power needs of battery-operated portable equipment. the ADSP-2188M is available in a 100-lead lqfp package and 144 ball mini-bga. in addition, the ADSP-2188M supports new instructions, which include bit manipulations?it set, bit clear, bit toggle, bit test new alu constants, new multiplication instruction ( squared), biased rounding, result-free alu operations, i/o memory trans- fers, and global interrupt masking, for increased flexibility. fabricated in a high-speed, low-power, cmos process, the ADSP-2188M operates with a 13.3 ns instruction cycle time. every instruction can execute in a single processor cycle. the ADSP-2188M? flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel. in one processor cycle, the ADSP-2188M can: generate the next program address fetch the next instruction perform one or two data moves update one or two data address pointers perform a computational operation this takes place while the processor continues to: receive and transmit data through the two serial ports receive and/or transmit data through the internal dma port receive and/or transmit data through the byte dma port decrement timer development system the adsp-2100 family development software, a complete set of tools for software and hardware system development, supports the ADSP-2188M. the system builder provides a high-level method for defining the architecture of systems under develop- ment. the assembler has an algebraic syntax that is easy to program and debug. the linker combines object files into an executable file. the simulator provides an interactive instruction- level simulation with a reconfigurable user interface to display different portions of the hardware environment. the ez-kit lite is a hardware/software kit offering a complete evaluation environment for the adsp-218x family: an adsp- 2189m-based evaluation board with pc monitor software plus assembler, linker, simulator, and prom splitter software. the adsp-2189m ez-kit lite is a low cost, easy to use hardware platform on which you can quickly get started with your dsp software design. the ez-kit lite includes the following features: 75 mhz adsp-2189m full 16-bit stereo audio i/o with ad73322 codec rs-232 interface ez-ice connector for emulator control dsp demo programs evaluation suite of visualdsp the adsp-218x ez-ice emulator aids in the hardware debugging of an ADSP-2188M system. the ADSP-2188M integrates on-chip emulation support with a 14-pin ice-port interface. this interface provides a simpler target board connec- tion that requires fewer mechanical clearance considerations than other adsp-2100 family ez-ices. the ADSP-2188M device need not be removed from the target system when using the ez-ice, nor are any adapters needed. due to the small footprint of the ez-ice connector, emulation can be supported in final board designs. the ez-ice performs a full range of functions, including: in-target operation up to 20 breakpoints single-step or full-speed operation registers and memory values can be examined and altered pc upload and download functions instruction-level emulation of program booting and execution complete assembly and disassembly of instructions c source-level debugging see designing an ez-ice-compatible target system in the adsp-2100 family ez-tools manual (adsp-2181 sections) as well as the designing an ez-ice-compatible system section of this data sheet for the exact specifications of the ez-ice target board connector. additional information this data sheet provides a general overview of ADSP-2188M functionality. for additional information on the architecture and instruction set of the processor, refer to the adsp-2100 family user? manual . for more information about the development tools, refer to the adsp-2100 family development tools data sheet. ez-ice is a registered trademark of analog devices, inc.
rev. 0 C4C ADSP-2188M architecture overview the ADSP-2188M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every instruction can be executed in a single processor cycle. the ADSP-2188M assembly language uses an algebraic sy ntax for ease of coding and readability. a compre- hensive set of development tools supports program development. figure 1 is an overall block diagram of the ADSP-2188M. the processor contains three independent computational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add, and multiply/subtract opera- tions with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. the shifter can be used to efficiently implement numeric format control, including multiword and block flo ating-point representations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computa- tional units. the sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. with internal loop counters and loop stacks, the ADSP-2188M executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. efficient data transfer is achieved with the use of five internal buses: program memory address (pma) bus program memory data (pmd) bus data memory address (dma) bus data memory data (dmd) bus result (r) bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/o memory space also share the external buses. program memory can store both instructions and data, permit- ting the ADSP-2188M to fetch two operands in a single cycle, one from program memory and one from data memory. the ADSP-2188M can fetch an operand from program memory and the next instruction in the same cycle. in lieu of the address and data bus for external memory connec- tion, the ADSP-2188M may be configured for 16-bit internal dma port (idma port) connection to external systems. the idma port is made up of 16 data/address pins and five control pins. the idma port provides transparent, direct access to the dsps on-chip program and data ram. an interface to low-cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the byte memory and i/o memory space interface supports slow memories and i/o memory-mapped peripherals with program- mable wait state generation. external devices can gain control of arithmetic units shifter mac alu program memory address data memory address program memory data data memory data power-down control memory program memory 48k 24 bit data memory 56k 16 bit external address bus external data bus byte dma controller full memory mode sport0 serial ports sport1 programmable i/o and flags timer host mode or external data bus internal dma port dag1 data address generators dag2 program sequencer adsp-2100 base architecture figure 1. functional block diagram
rev. 0 ADSP-2188M C5C external buses with bus request/grant signals ( br , bgh , and bg ). one execution mode (go mode) allows the ADSP-2188M to continue running from on-chip memory. normal execution mode requires the processor to halt while buses are granted. the ADSP-2188M can respond to eleven interrupts. there can be up to six external interrupts (one edge-sensitive, two level- sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (sports), the byte dma port, and the power-down circuitry. there is also a master reset signal. the two serial ports provide a complete synchro- nous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the ADSP-2188M provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) decrements every n pro- cessor cycle, where n is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the ADSP-2188M incorporates two complete synchronous serial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the ADSP-2188M sports. for additional information on serial ports, refer to the adsp-2100 family user? manual . sports are bidirectional and have a separate, double- buffered transmit and receive section. sports can use an external serial clock or generate their own serial clock internally. sports have independent framing for the receive and trans- mit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulsewidths and timings. sports support serial data word lengths from 3 to 16 bits and provide optional a-law and -law companding according to ccitt recommendation g.711. sport receive and transmit sections can generate unique interrupts on completing a data word transfer. sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. an interrupt is generated after a data buffer transfer. sport0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time- division multiplexed, serial bitstream. sport1 can be configured to have two external interrupts ( irq0 and irq1 ) and the fi and fo signals. the internally generated serial clock may still be used in this configuration. pin descriptions the ADSP-2188M is available in a 100-lead lqfp package and a 144-ball mini-bga package. in order to maintain maxi- mum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. the external bus pins are configured during reset only, while serial port pins are soft- ware configurable during program execution. flag and interrupt functionality is retained concurrently on multiplexed pins. in cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.
rev. 0 C6C ADSP-2188M common-mode pins pin name # of pins i/o function reset 1 i processor reset input br 1 i bus request input bg 1 o bus grant output bgh 1 o bus grant hung output dms 1 o data memory select output pms 1 o program memory select output ioms 1 o memory select output bms 1 o byte memory select output cms 1 o combined memory select output rd 1 o memory read enable output wr 1 o memory write enable output irq2 1 i edge- or level-sensitive interrupt request 1 pf7 i/o programmable i/o pin irql1 1 i level-sensitive interrupt requests 1 pf6 i/o programmable i/o pin irql0 1 i level-sensitive interrupt requests 1 pf5 i/o programmable i/o pin irqe 1 i edge-sensitive interrupt requests 1 pf4 i/o programmable i/o pin mode d 1 i mode select input?hecked only during reset pf3 i/o programmable i/o pin during normal operation mode c 1 i mode select input?hecked only during reset pf2 i/o programmable i/o pin during normal operation mode b 1 i mode select input?hecked only during reset pf1 i/o programmable i/o pin during normal operation mode a 1 i mode select input?hecked only during reset pf0 i/o programmable i/o pin during normal operation clkin, xtal 2 i clock or quartz crystal input clkout 1 o processor clock output sport0 5 i/o serial port i/o pins sport1 5 i/o serial port i/o pins irq1:0, fi, fo edge- or level-sensitive interrupts, fi, fo 2 pwd 1 i power-down control input pwdack 1 o power-down control output fl0, fl1, fl2 3 o output flags v ddint 2 i internal v dd (2.75 v) power (lqfp) v ddext 4 i external v dd (2.75 v or 3.3 v) power (lqfp) gnd 10 i ground (lqfp) v ddint 4 i internal v dd (2.75 v) power (mini-bga) v ddext 7 i external v dd (2.75 v or 3.3 v) power (mini-bga) gnd 20 i ground (mini-bga) ez-port 9 i/o for emulation use notes 1 interrupt/flag pins retain both functions concurrently. if imask is set to enable the corresponding interrupts, then the dsp wi ll vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2 sport configuration determined by the dsp system control register. software configurable.
rev. 0 ADSP-2188M C7C memory interface pins the ADSP-2188M processor can be used in one of two modes: full memory mode, which allows bdma operation with full exter- nal overlay memory and i/o capability, or host mode, which allows idma operation with limited external addressing capabilities. the operating mode is determined by the state of the mode c pin during reset and cannot be changed while the processor is running. the following tables list the active signals at specific pins of the dsp during either of the two operating modes (full memory or host). a signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set . for the shared pins and their alternate signals (e.g., a4/iad3), refer to the package pinout tables. full memory mode pins (mode c = 0) pin name # of pins i/o function a13:0 14 o address output pins for program, data, byte, and i/o spaces d23:0 24 i/o data i/o pins for program, data, byte, and i/o spaces (8 msbs are also used as byte memory addresses.) host mode pins (mode c = 1) pin name # of pins i/o function iad15:0 16 i/o idma port address/data bus a0 1 o address pin for external i/o, program, data, or byte access 1 d23:8 16 i/o data i/o pins for program, data, byte, and i/o spaces iwr 1 i idma write enable ird 1 i idma read enable ial 1 i idma address latch pin is 1 i idma select iack 1 o idma port acknowledge configurable in mode d; open drain note 1 in host mode, external peripheral addresses can be decoded using the a0, cms , pms , dms , and ioms signals.
rev. 0 C8C ADSP-2188M terminating unused pins the following table shows the recommendations for terminating unused pins. pin terminations i/o 3-state reset hi-z * pin name (z) state caused by unused configuration xtal i i float clkout o o float a13:1 or o (z) hi-z br , ebr float iad 12:0 i/o (z) hi-z is float a0 o (z) hi-z br , ebr float d23:8 i/o (z) hi-z br , ebr float d7 or i/o (z) hi-z br , ebr float iwr i i high (inactive) d6 or i/o (z) hi-z br , ebr float ird ii br , ebr high (inactive) d5 or i/o (z) hi-z float ial i i low (inactive) d4 or i/o (z) hi-z br , ebr float is i i high (inactive) d3 or i/o (z) hi-z br , ebr float iack float d2:0 or i/o (z) hi-z br , ebr float iad15:13 i/o (z) hi-z is float pms o (z) o br , ebr float dms o (z) o br , ebr float bms o (z) o br , ebr float ioms o (z) o br , ebr float cms o (z) o br , ebr float rd o (z) o br , ebr float wr o (z) o br , ebr float br i i high (inactive) bg o (z) o ee float bgh o o float irq2 / pf7 i/o (z) i input = high (inactive) or program as output, set to 1, let float irql1 / pf6 i/o (z) i input = high (inactive) or program as output, set to 1, let float irql0 / pf5 i/o (z) i input = high (inactive) or program as output, set to 1, let float irqe / pf4 i/o (z) i input = high (inactive) or program as output, set to 1, let float sclk0 i/o i input = high or low, output = float rfs0 i/o i high or low dr0 i i high or low tfs0 i/o i high or low dt0 o o float sclk1 i/o i input = high or low, output = float rfs1/ irq0 i/o i high or low dr1/fi i i high or low tfs1/ irq1 i/o i high or low dt1/fo o o float ee i i float ebr i i float ebg o o float ereset i i float ems o o float eint i i float eclk i i float elin i i float elout o o float notes * hi-z = high impedance. 1. if the clkout pin is not used, turn it off, using clkodis in sport0 autobuffer control register. 2. if the interrupt/programmable flag pins are not used, there are two options: option 1: when these pins are configured as inpu ts at reset and function as inter- rupts and input flag pins, pull the pins high (in active). option 2: program the unused pins as outputs, set them to 1, prior to enabling interrupts, and let pins float. 3. all bidirectional pins have three-stated outputs. when the pin is configured as an output, the output is hi-z (high impedance ) when inactive. 4. clkin, reset , and pf3:0/mode d:a are not included in the table because these pins must be used.
rev. 0 ADSP-2188M C9C interrupts the interrupt controller allows the processor to respond to the 11 possible interrupts and reset w ith minimum overhe ad. the ADSP-2188M provides four dedicated external interrupt input pins: irq2 , irql0 , irql1 , and irqe (shared with the pf7:4 pins). in addition, sport1 may be reconfigured for irq0 , irq1 , fi and fo, for a total of six external interrupts. the ADSP-2188M also supports internal interrupts from the timer, the byte dma port, the two serial ports, software, and the power- down control circuit. the interrupt levels are internally prioritized and individually maskable (except power- down and reset). the irq2 , irq0 , and irq1 input pins can be programmed to be either level- or edge-sensitive. irql0 and irql1 are level- sensitive and irqe is edge-sensitive. the priorities and vector addresses of all interrupts are shown in table i. table i. interrupt priority and interrupt vector addresses interrupt vector source of interrupt address (hex) reset (or power-up with pucr = 1) 0000 (highest priority) power-down (nonmaskable) 002c irq2 0004 irql1 0008 irql0 000c sport0 transmit 0010 sport0 receive 0014 irqe 0018 bdma interrupt 001c sport1 transmit or irq1 0020 sport1 receive or irq0 0024 timer 0028 (lowest priority) interrupt routines can either be nested with higher priority inter- rupts taking precedence or processed sequentially. interrupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected. the power-down interrupt is nonmaskable. the ADSP-2188M masks all interrupts for one instruction cycle following the execution of an instruction that modifies the imask register. this does not affect serial port autobuffering or dma transfers. the interrupt control register, icntl, controls interrupt nest- ing and defines the irq0 , irq1 , and irq2 external interrupts to be either edge- or level-sensitive. the irqe pin is an exter- nal edge sensitive interrupt and can be forced and cleared. the irql0 and irql1 pins are external level sensitive interrupts. the ifc register is a write-only register used to force and clear interrupts. on-chip stacks preserve the processor status and are automatically maintained during interrupt handling. the stacks are twelve levels deep to allow interrupt, loop, and subroutine nesting. the following instructions allow global enable or disable servicing of the interrupts (including power down), regardless of the state of imask. disabling the interrupts does not affect serial port autobuffering or dma. ena ints; dis ints; when the processor is reset, interrupt servicing is enabled. low power operation the ADSP-2188M has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. these modes are: power-down ?dle slow idle the clkout pin may also be disabled to reduce external power dissipation. power-down the ADSP-2188M processor has a low power feature that lets the processor enter a very low-power dormant state through hardware or software control. following is a brief list of power- down features. refer to the adsp-2100 family user? manual , ?ystem interface?chapter, for detailed information about the power-down feature. quick recovery from power-down. the processor begins executing instructions in as few as 200 clkin cycles. support for an externally generated ttl or cmos processor clock. the external clock can continue running during power- down without affecting the lowest power rating and 200 clkin cycle recovery. support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approximately 4096 clkin cycles for the crystal oscillator to start or stabi- lize), and letting the oscillator run to allow 200 clkin cycle start-up. power-down is initiated by either the power-down pin ( pwd ) or the software powe r-down force bit. interrupt support allows an unlimited number of instructions to be executed before optionally powering down. the power-down interrupt also can be used as a nonmaskable, edge-sensitive interrupt. context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. the reset pin also can be used to terminate power-down. power-down acknowledge pin indicates when the processor has entered power-down. idle when the ADSP-2188M is in the idle mode, the processor waits indefinitely in a low-power state until an interrupt occurs. when an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the idle instruc- tion. in idle mode idma, bdma and autobuffer cycle steals still occur. slow idle the idle instruction is enhanced on the ADSP-2188M to let the processor? internal clock signal be slowed, further reducing power consumption. the reduced clock frequency, a program- mable fraction of the normal clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is: idle (n); where n = 16, 32, 64, or 128. this instruction keeps the proces- sor fully functional, but operating at the slower clock rate. while it is in this state, the processor? other internal clock signals, such
rev. 0 C10C ADSP-2188M as sclk, clkout, and timer clock, are reduced by the same ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruction. when the idle (n) instruction is used, it effectively slows down the processor? internal clock and thus its response time to incom- ing interrupts. the one-cycle response time of the standard idle state is increased by n, the clock divisor. when an enabled inter- rupt is received, the ad sp-2188m will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processor? reduced internal clock rate. under these conditions, interrupts must not be generated at a faster than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). system interface figure 2 shows typical basic system configurations with the ADSP-2188M, two serial devices, a byte-wide eprom, and optional external program and data overlay memories (mode- selectable). programmable wait state generation allows the processor to connect easily to slow peripheral devices. the adsp -2188m also provides four external interrupts and two serial ports or six e xternal interrupts and one serial port. host memory mode allows access to the full external data bus, but limits addressing to a single address bit (a0). through the use of external hardware, additional system peripherals can be added in this mode to generate and latch address signals. clock signals the ADSP-2188M can be clocked by either a crystal or a ttl-compatible clock signal. the clkin input cannot be halted, changed during op era- tion, nor operated below the specified frequency during normal operation. the only exception is while the processor is in the power-down state. for additional information, refer to chap- ter 9, adsp-2100 family user? manual, for detailed information on this power-down feature. if an external clock is used, it should be a ttl-compatible signal running at half the instruction rate. the signal is connected to the processor? clkin input. when an external clock is used, the xtal input must be left unconnected. the ADSP-2188M uses an input clock with a frequency equal to half the instruction rate; a 37.50 mhz input clock yields a 13 ns processor cycle (which is equivalent to 75 mhz). normally, instructions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. because the ADSP-2188M includes an on-chip oscillator circuit, an external crystal may be used. the crystal should be connected across the c lkin and xtal pins, with two ca pacitors con- nected as shown in figure 3. capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. a parallel-resonant, fundamental frequency, microprocessor- grade crystal should be used. a clock output (clkout) signal is generated by the processor at the processor? cycle rate. this can be enabled and disabled by the clkodis bit in the sport0 autobuffer control register. clkin xtal clkout dsp figure 3. external crystal connections 1/2x clock or crystal fl0? clkin xtal serial device sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or f i sport1 serial device a0?21 data byte memory i/o space (peripherals) data addr data addr 2048 locations overlay memory two 8k pm segments two 8k dm segments d 23? a 13? d 23? a 10? d 15? d 23?6 a 13? 14 24 sclk0 rfs0 tfs0 dt0 dr0 sport0 addr13? data23? ADSP-2188M cs cs 1/2x clock or crystal clkin xtal fl0? serial device sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport1 16 idma port ird /d6 iwr /d7 is /d4 ial/d5 iack /d3 iad15? serial device sclk0 rfs0 tfs0 dt0 dr0 sport0 1 16 a0 data23? ioms ADSP-2188M bms pms dms cms br bg bgh pwd pwdack host memory mode full memory mode mode d/ pf3 mode c/ pf2 mode b/ pf1 mode a/ pf0 irq2 / pf7 irqe / pf4 irql0 / pf5 irql1 / pf6 mode d/ pf3 mode c/ pf2 mode b/ pf1 mode a/ pf0 wr rd system interface or controller irq2 / pf7 irqe / pf4 irql0 / pf5 irql1 / pf6 ioms bms pms dms cms br bg bgh pwd pwdack wr rd ADSP-2188M figure 2. basic system interface
rev. 0 ADSP-2188M C11C reset the reset signal initiates a master reset of the ADSP-2188M. the reset signal must be asserted during the power-up sequence to assure proper initialization. reset during initial power-up must be held long enough to allow the internal clock to stabilize. if reset is activated any time after power-up, the clock continues to run and does not require stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is applied to the processor, and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 clkin cycles ensures that the pll has locked but does not include the crystal oscillator start-up time. during this power-up sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the minimum pulsewidth specifi- cation, t rsp . the reset input contains some hysteresis; however, if an rc circuit is used to generate the reset signal, the use of an external schmidt trigger is recommended. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the mstat register. when reset is released, if there is no pending bus request and the chip is configured for booting, the boot-loading se quence is performed. the first instruction is fetched from on-chip pro- gram memory location 0x0000 once boot loading completes. power supplies the ADSP-2188M has separate power supply connections for the internal (v ddint ) and external (v ddext ) power supplies. the internal supply must meet the 2.75 v requirement. the external supply can be connected to either a 2.75 v or 3.3 v supply. all external supply pins must be connected to the same supply. all input and i/o pins can tolerate input voltages up to table ii. modes of operation mode d mode c mode b mode a booting method x 0 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in full memory mode. 1 x010no automatic boot operations occur. program execution starts at external memory location 0. chip is configured in full memory mode. bdma can still be used, but the processor does not automatically use or wait for these operations. 0100 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in host mode. iack has active pull-down. (requires additional hardware). 0101i dma feature is used to load any internal memory as desired. program execution is held off until internal program memory location 0 is written to. chip is configured in host mode. iack has active pull-down. 1 1100 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in host mode; iack requires exter- nal pull down. (requires additional hardware) 1101i dma feature is used to load any internal memory as desired. program execution is held off until internal program memory location 0 is written to. chip is configured in host mode. iack requires external pull-down. 1 note 1 considered as standard operating settings. using these configurations allows for easier design and better memory management. 3.6 v, regardless of the external supply voltage. this feature pro- vides maximum flexibility in mixing 2.75 v and 3.3 v components. modes of operation setting memory mode memory mode selection for the ADSP-2188M is made during chip reset through the use of the mode c pin. this pin is multi- plexed with the dsp? pf2 pin, so care must be taken in how the mode selection is made. the two methods for selecting the value of mode c are active and passive. passive configuration passive configuration involves the use a pull-up or pull-down resistor connected to the mode c pin. to minimize power con- sumption, or if the pf2 pin is to be used as an output in the dsp application, a weak pull-up or pull-down, on the order of 10 k ? , can be used. this value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor? output driver. for minimum power consumption during power-down, re con- figure pf2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will not sw itch. active configuration active configuration involves the use of a three-statable external driver connected to the mode c pin. a driver? output enable should be connected to the dsp? reset signal such that it only drives the pf2 pin when reset is active (low). when reset is deasserted, the driver should three-state, thus allow- ing full use of the pf2 pin as either an input or output. to minimize power consumption during power-down, configure the programmable flag as an output when connected to a three- stated buffer. this ensures that the pin will be held at a constant level, and will not oscillate should the three-state driver? level hover around the logic switching point.
rev. 0 C12C ADSP-2188M iack configuration mode d = 0 and in host mode: iack is an active, driven signal and cannot be ?ire or?. mode d = 1 and in host mode: iack is an open drain and requires an external pull-down, but multiple iack pins can be ?ire or??together. memory architecture the ADSP-2188M provides a variety of memory and peripheral interface options. the key functional groups are program memory, data memory, byte memory, and i/o. refer to the following figures and tables for pm and dm memory allocations in the ADSP-2188M. program memory program memory (full memory mode) is a 24-bit-wide space for storing both instruction opcodes and data. the adsp- 2188m has 48k words of program memory ram on chip, and the capability of accessing up to two 8k external memory over- lay spaces using the external data bus. program memory (host mode) allows access to all internal memory. external overlay access is limited by a single external address line (a0). external program execution is not available in host mode due to a restricted data bus that is 16 bits wide only. accessible when pmovlay = 2 0 x 2000 0 x 3fff 2 0 x 2000 0 x 3fff 2 external memory accessible when pmovlay = 1 0x2000 0x3fff pm mode b = 0 internal memory accessible when pmovlay = 7 accessible when pmovlay = 6 accessible when pmovlay = 5 accessible when pmovlay = 4 accessible when pmovlay = 0 always accessible at address 0x0000 0x1fff 0x2000 0x3fff 0x2000 0x3fff 0x2000 0x3fff 0x2000 0x3fff pm (mode b = 1) 1 0 x 0000 0 x 1fff 2 0 x 0000 0 x 1fff 2 external memory accessible when pmovlay = 0 0x2000 0x3fff internal memory accessible when pmovlay = 0 reserved reserved reserved reserved reserved reserved notes 1 when mode b = 1, pmovlay must be set to 0 2 see table iii for pmovlay bits 0 x 3fff 8k internal 0 x 0000 0 x 1fff 0 x 2000 program memory mode b = 0 address 8k internal pmovlay = 0, 4, 5, 6, 7 or 8k external pmovlay = 1, 2 0 x 3fff 8k internal 0 x 0000 0 x 1fff 0 x 2000 program memory mode b = 1 address 8k internal pmovlay = 0 figure 4. program memory table iii. pmovlay bits pmovlay memory a13 a12:0 0, 4, 5, 6, 7 internal not applicable not applicable 1 external overlay 1 0 13 lsbs of address between 0x2000 and 0x3fff 2 external overlay 2 1 13 lsbs of address between 0x2000 and 0x3fff
rev. 0 ADSP-2188M C13C table iv. dmovlay bits dmovlay memory a13 a12:0 0, 4, 5, 6, 7, 8 internal not applicable not applicable 1 external overlay 1 0 13 lsbs of address between 0x2000 and 0x3fff 2 external overlay 2 1 13 lsbs of address between 0x2000 and 0x3fff accessible when dmovlay = 2 0 x 0000 0 x 1fff 0 x 0000 0 x 1fff external memory accessible when dmovlay = 1 0x0000 0x1fff 0x0000 0x1fff accessible when dmovlay = 8 0x0000 0x1fff data memory 0x0000 0x1fff accessible when dmovlay = 7 0x0000 0x1fff internal memory accessible when dmovlay = 6 accessible when dmovlay = 5 accessible when dmovlay = 4 accessible when dmovlay = 0 always accessible at address 0x2000 0x3fff 0x0000 0x1fff 0 x 3fff 0 x 0000 0 x 1fff 0 x 2000 data memory address 8k internal dmovlay = 0, 4, 5, 6, 7, 8 or 8k external dmovlay = 1, 2 32 memory mapped registers internal 8160 words 0 x 3fe0 0 x 3fdf figure 5. data memory map data memory data memory (full memory mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. the ADSP-2188M has 56k words on data memory ram on-chip. part of this space is used by 32 memory- mapped registers. support also exists for up to two 8k external memory overlay spaces through the external data bus . all internal accesses complete in one cycle. accesses to external memory are timed using the wait states specified by the dwait register and the wait state mode bit. data memory (host mode) allows access to all internal memory. external overlay access is limited by a single external address line (a0). memory mapped registers (new to the ADSP-2188M) the ADSP-2188M has three memory mapped registers that differ from other adsp-21xx family dsps. the slight modifications to these registers (wait state control, programmable flag and composite select control, and system control) provide the ADSP-2188M? wait state and bms control features. default bit values at reset are shown; if no value is shown, the bit is unde- fined at reset. reserved bits are shown on a grey field. these bits should always be written with zeros. dwait iowait3 iowait2 iowait1 iowait0 dm(0x3ffe) waitstate control 1111111111111111 1514131211109876543210 wait state mode select 0 = normal mode (pwait, dwait, iowait0 3 = n wait states, ranging from 0 to 7) 1 = 2n + 1 mode (pwait, dwait, iowait0 3 = 2n + 1 wait states, ranging from 0 to 15 ) figure 6. wait state control register bmwait cmssel 0 = disable cms 1 = enable cms dm(0x3fe6) pftype 0 = input 1 = output (where bit: 11-iom, 10-bm, 9-dm, 8-pm) 1111101100000000 1514131211109876543210 programmable flag and composite select control figure 7. programmable flag and composite control register reserved, always set to 0 sport0 enable 0 = disable 1 = enable dm(0x3fff) system control sport1 enable 0 = disable 1 = enable sport1 configure 0 = fi, fo, irq0 , irq1 , sclk 1 = sport1 disable bms 0 = enable bms 1 = disable bms , except when memory strobes are three-stated pwait program memory wait states 0000010000000111 1514131211109876543210 note: reserved bits are shown on a gray field. these bits should always be written with zeros. reserved set to 0 &
- 2 1

rev. 0 C14C ADSP-2188M i/o space (full memory mode) the ADSP-2188M supports an additional external memory space called i/o space. this space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface asic data registers. i/o space sup- ports 2048 locations of 16-bit wide data. the lower eleven bits of the external address bus are used; the upper three bits are undefined. two instructions were added to the core adsp-2100 family instruction set to read from and write to i/o memory space. the i/o space also has four dedicated three-bit wait state registers, iowait0?, which in combination with the wait state mode bit, specify up to 15 wait states to be automatically gener- ated for each of four regions. the wait states act on address ranges as shown in table v. table v. wait states address range wait state register 0x000?x1ff iowait0 and wait state mode select bit 0x200?x3ff iowait1 and wait state mode select bit 0x400?x5ff iowait2 and wait state mode select bit 0x600?x7ff iowait3 and wait state mode select bit composite memory select ( cms ) the ADSP-2188M has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. the cms signal is gener- ated to have the same timing as each of the individual memory select signals ( pms , dms , bms , ioms ) but can combine their functionality. each bit in the cmssel register, when set, causes the cms signal to be asserted when the selected memory select is asserted. for example, to use a 32k word memory to act as both program and data memory, set the pms and dms bits in the cmssel register and use the cms pin to drive the chip select of the memory, and use either dms or pms as the additional address bit. the cms pin functions like the other memory select signals with the same timing and bus request logic. a 1 in the enable bit causes the assertion of the cms signal at the same time as the selected memory select signal. all enable bits default to 1 at reset, except the bms bit. byte memory select ( bms ) the ADSP-2188M? bms disable feature combined with the cms pin allows use of multiple memories in the byte memory space. for example, an eprom could be attached to the bms select, and an sram could be connected to cms . because at reset bms is enabled, the eprom would be used for booting. after booting, software could disable bms and set the cms signal to respond to bms , enabling the sram. byte memory the byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. byte memory is accessed using the bdma feature. the byte memory space con- sists of 256 pages, each of which is 16k 8. the byte memory space on the ADSP-2188M supports read and write operations as well as four different data formats. the byte memory uses data bits 15:8 for data. the byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. this allows up to a 4 meg 8 (32 megabit) rom or ram to be used without glue logic. all byte memory accesses are timed by the bmwait register and the wait state mode bit. byte memory dma (bdma, full memory mode) the byte memory dma controller allows loading and storing of program instructions and data using the byte memory space. the bdma circuit is able to access the byte memory space while the processor is operating normally and steals only one dsp cycle per 8-, 16- or 24-bit word transferred. bdma control bmpage btype bdir 0 = load from bm 1 = store to bm bcr 0 = run during bdma 1 = halt during bdma 0000000000001000 1514131211109876543210 dm (0x3fe3) bdma overlay bits figure 9. bdma control register the bdma circuit supports four different data formats that are selected by the btype register field. the appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. table vi shows the data formats sup- ported by the bdma circuit. table vi. data formats btype internal memory space word size alignment 00 program memory 24 full word 01 data memory 16 full word 10 data memory 8 msbs 11 data memory 8 lsbs unused bits in the 8-bit data memory formats are filled with 0s. the biad register field is used to specify the starting address for the on-chip memory involved with the transfer. the 14-bit bead register specifies the starting address for the external byte memory space. the 8-bit bmpage register specifies the start- ing page for the external byte memory space. the bdir register field selects the direction of the transfer. finally, the 14-bit bwcount register specifies the number of dsp words to transfer and initiates the bdma circuit transfers. bdma accesses can cross page boundaries during sequential addressing. a bdma interrupt is generated on the completion of the number of transfers specified by the bwcount register. the bwcount register is updated after each transfer so it can be used to check the status of the transfers. when it reaches zero, the transfers have finished and a bdma interrupt is generated. the bmpage and bead registers must not be accessed by the dsp during bdma operations. the source or destination of a bdma transfer will always be on-chip program or data memory.
rev. 0 ADSP-2188M C15C when the bwcount register is written with a nonzero value the bdma circuit starts executing byte memory accesses with wait states set by bmwait. these accesses continue until the count reaches zero. when enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. the transfer takes one dsp cycle. dsp accesses to external memory have priority over bdma byte memory accesses. the bdma context reset bit (bcr) controls whether the processor is held off while the bdma accesses are occurring. setting the bcr bit to 0 allows the processor to continue opera- tions. setting the bcr bit to 1 causes the processor to stop execution while the bdma accesses are occurring, to clear the context of the processor, and start execution at address 0 when the bdma accesses have completed. the bdma overlay bits specify the ovlay memory blocks to be accessed for internal memory. the bmwait field, which has 4 bits on ADSP-2188M, allows selection up to 15 wait states for bdma transfers. internal memory dma port (idma port; host memory mode) the idma port provides an efficient means of communication between a host system and the ADSP-2188M. the port is used to access the on-chip program memory and data memory of the dsp with only one dsp cycle per word overhead. the idma port cannot, however, be used to write to the dsp? memory- mapped control registers. a typical idma transfer process is described as follows: 1. host starts idma transfer 2. host checks iack control line to see if the dsp is busy 3. host uses is and ial control lines to latch either the dma starting address (idmaa) or the pm/dm ovlay selection into the dsp? idma control registers. if bit 15 = 1, the value of bits 7:0 represent the idma overlay: bits 14:8 must be set to 0. if bit 15 = 0, the value of bits 13:0 represent the starting address of internal memory to be accessed and bit 14 reflects pm or dm for access. 4. host uses is and ird (or iwr ) to read (or write) dsp inter- nal memory (pm or dm). 5. host checks iack line to see if the dsp has completed the previous idma operation. 6. host ends idma transfer. the idma port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. the idma port is com- pletely asynchronous and can be written while the ADSP-2188M is operating at full speed. the dsp memory address is latched and then automatically in cre- mented af ter each idma transaction. an external device can ther efore access a block of sequentially addressed memory by specifying only the starting address of the block. this increases throughput as the address does not have to be sent for each memory access. idma port access occurs in two phases. the first is the idma address latch cycle. when the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. the address specifies an on-chip memory location, the destination type specifies whether it is a dm or pm access. the falling edge of the idma address latch signal (ial) or the missing edge of the idma select signal ( is ) latches this value into the idmaa register. once the address is stored, data can be read from, or written to, the ADSP-2188M? on-chip memory. asserting the select line ( is ) and the appropriate read or write line ( ird and iwr respectively) signals the ADSP-2188M that a particular transac- tion is required. in either case, there is a one-processor-cycle delay for synchronization. the memory access consumes one additional processor cycle. once an access has occurred, the latched address is automati- cally incremented, and another access can occur. through the idmaa register, the dsp can also specify the starting address and data format for dma operation. asserting the idma port select ( is ) and address latch enable (ial) directs the ADSP-2188M to write the address onto the iad0?4 bus into the idma control register. if bit 15 is set to 0, idma latches the address. if bit 15 is set to 1, idma latches into the ovlay register. this register, shown below, is memory mapped at address dm (0x3fe0). note that the latched address (idmaa) cannot be read back by the host. when bit 14 in 0x3fe7 is set to 1, timing in figure 31 applies for short reads. w hen bit 14 in 0x3fe7 is set to zero, short reads use the timing shown in fig- ure 32. refer to the following figures for more information on idma and dma memory maps. idma overlay dm (0x3fe7) reserved set to 0 iddmovlay idpmovlay 000000000000000 1514131211109876543210 short read only 0 = enable 1 = disable idma control (u = undefined at reset) dm (0x3fe0) idmaa address uuuuuuuuuuuuuuu 1514131211109876543210 idmad destination memory type 0 = pm 1 = dm note: reserved bits are shown on a gray field. these bits should always be written with zeros. 0 reserved set to 0 0 reserved set to 0 figure 10. idma control/ovlay registers
rev. 0 C16C ADSP-2188M 0x2000 0x3fff 0x2000 0x3fff 0x2000 0x3fff accessible when pmovlay = 7 0x2000 0x3fff accessible when pmovlay = 6 accessible when pmovlay = 5 accessible when pmovlay = 4 accessible when pmovlay = 0 always accessible at address 0x0000 0x1fff 0x2000 0x3fff dma program memory ovlay dma data memory ovlay 0x0000 0x1fff 0x0000 0x1fff accessible when dmovlay = 8 0x0000 0x1fff 0x0000 0x1fff accessible when dmovlay = 7 0x0000 0x1fff accessible when dmovlay = 6 accessible when dmovlay = 5 accessible when dmovlay = 4 accessible when dmovlay = 0 always accessible at address 0x2000 0x3fff 0x0000 0x1fff note: idma and bdma have separate dma control registers. figure 11. direct memory accesspm and dm memory maps bootstrap loading (booting) the ADSP-2188M has two mechanisms to allow automatic load- ing of the internal program memory after reset. the method for booting is controlled by the mode a, b, and c configuration bits. when the mode pins specify bdma booting, the ADSP-2188M initiates a bdma boot sequence when reset is released. the bdma interface is set up during reset to the following defaults when bdma booting is specified: the bdir, bmpage, biad, and bead registers are set to 0, the btype register is set to 0 to specify program memory 24-bit words, and the bwcount register is set to 32. this causes 32 words of on-chip program memory to be loaded from byte mem ory. these 32 words are used to set up the bdma to load in the remaining program code. the bcr bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. execution then begins at address 0. the adsp-2100 family development software (revision 5.02 and later) fully supports the bdma booting feature and can generate byte memory space compatible boot code. the idle instruction can also be used to allow the processor to hold off execution while booting continues through the bdma interface. for bdma accesses while in host mode, the addresses to boot memory must be constructed externally to the ADSP-2188M. the only memory address bit provided by the processor is a0. idma port booting the ADSP-2188M can also boot programs through its internal dma port. if mode c = 1, mode b = 0, and mode a = 1, the ADSP-2188M boots from the idma port. idma feature can load as much on-chip memory as desired. program execution is held off until on-chip program memory location 0 is written to. bus request and bus grant the ADSP-2188M can relinquish control of the data and address buses to an external device. when the external device requires access to memory, it asserts the bus request ( br ) signal. if the ADSP-2188M is not performing an external memory access, it responds to the active br input in the following processor cycle by: three-stating the data and address buses and the pms , dms , bms , cms , ioms , rd , wr output drivers, asserting the bus grant ( bg ) signal, and halting program execution. if go mode is enabled, the ADSP-2188M will not halt program execution until it encounters an instruction that requires an external memory access. if the ADSP-2188M is performing an external memory access when the external device asserts the br signal, it will not three- state the memory interfaces nor assert the bg signal until the processor cycle after the access completes. the instruction does not need to be completed when the bus is granted. if a single instruction requires two external memory accesses, the bus will be granted between the two accesses. when the br signal is released, the processor releases the bg signal, re-enables the output drivers, and continues program execution from the point at which it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. the bgh pin is asserted when the ADSP-2188M requires the external bus for a memory or bdma access, but is stopped. the other device can release the bus by deasserting bus request. once the bus is released, the ADSP-2188M deasserts bg and bgh and executes the external memory access. flag i/o pins the ADSP-2188M has eight general purpose programmable input/output flag pins. they are controlled by two memory mapped registers. the pftype register determines the direc- tion, 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin configured as an input is synchronized to the ADSP-2188Ms clock. bits that are programmed as outputs will read the value being output. the pf pins default to input during reset.
rev. 0 ADSP-2188M C17C in addition to the programmable flags, the ADSP-2188M has five fixed-mode flags, fi, fo, fl0, fl1, and fl2. fl0?l2 are dedicated output flags. fi and fo are available as an alternate configuration of sport1. note: pins pf0, pf1, pf2, and pf3 are also used for device configuration during reset. instruction set description the ADSP-2188M assembly language instruction set has an algebraic syntax that was designed for ease of coding and read- ability. the assembly language, which takes full advantage of the processor? unique architecture, offers the following benefits: the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. the syntax is a superset adsp-2100 family assembly lan- guage and is completely source and object code compatible with other family members. programs may need to be relocated to utilize on-chip memory and conform to the ADSP-2188M? interrupt vector and reset vector map. sixteen condition codes are available. for conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruc- tion cycle. multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. designing an ez-ice-compatible system the ADSP-2188M has on-chip emulation support and an ice-port, a special set of pins that interface to the ez-ice. these features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the ez-ice. target systems must have a 14-pin connector to accept the ez-ice? in-circuit probe, a 14-pin plug. issuing the chip reset command during emulation causes the dsp to perform a full chip reset, including a reset of its memory mode. therefore, it is vital that the mode pins are set correctly prior to issuing a chip reset command from the emulator user interface. if a passive method of maintaining mode information is being used (as discussed in setting memory modes), it does not matter that the mode information is latched by an emulator reset. however, if the reset pin is being used as a method of setting the value of the mode pins, the effects of an emulator reset must be taken into consideration. one method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in figure 12. this circuit forces the value located on the mode a pin to logic high; regardless of whether it is latched via the reset or ereset pin. programmable i/o mode a/pfo reset ereset 1k ADSP-2188M figure 12. mode a pin/ez-ice circuit see the adsp-2100 family ez-tools data sheet for complete information on ice products. the ice-port interface consists of the following ADSP-2188M pins: ebr , eint , ee, ebg , eclk, ereset , elin, ems , and elout these ADSP-2188M pins must be connected only to the ez-ice connector in the target system. these pins have no function except during emulation, and do not require pull-up or pull-down resistors. the traces for these signals between the ADSP-2188M and the connector must be kept as short as possible, no longer than 3 inches. the following pins are also used by the ez-ice: br , bg , reset , and gnd. the ez-ice uses the ee (emulator enable) signal to take con- trol of the adsp-2185m in the target system. this causes the processor to use its ereset , ebr , and ebg pins instead of the reset , br , and bg pins. the bg output is three-stated. these signals do not need to be jumper-isolated in your system. the ez-ice connects to your target system via a ribbon cable and a 14-pin female plug. the female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. target board connector for ez-ice probe the ez-ice connector (a standard pin strip header) is shown in figure 13. you must add this connector to your target board design if you intend to use the ez-ice. be sure to allow enough room in your system to fit the ez-ice probe onto the 14-pin connector. 1 2 3 4 56 78 910 11 12 13 14 gnd key (no pin) reset br bg top view ebg ebr elout ee eint elin eclk ems ereset figure 13. target board connector for ez-ice
rev. 0 C18C ADSP-2188M the 14-pin, 2-row pin strip header is keyed at the pin 7 loca- tion?ou must remove pin 7 from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spac- ing should be 0.1 0.1 inches. the pin strip header must have at least 0.15 inch clearance on all sides to accept the ez- ice probe plug. pin strip headers are available from vendors such as 3m, mckenzie, and samtec. target memory interface for your target system to be compatible with the ez-ice emulator, it m ust comply with the memory interface guidelines listed below. pm, dm, bm, iom, and cm design your program memory (pm), data memory (dm), byte memory (bm), i/o memory (iom), and composite memory (cm) external interfaces to comply with worst case device tim- ing requirements and switching characteristics as specified in this data sheet. the performance of the ez- ice may approach published worst case specification for some memory access timing requirements and switching characteristics. note: if your target does not meet the worst-case chip specifica- tion for memory access parameters, you may not be able to emulate your circuitry at the desired clkin frequency. depend- ing on the severity of the specification violation, you may have trouble manufacturing your system as dsp components statisti- cally vary in switching characteristic and timing requirements within published limits. restriction: all memory strobe signals on the ADSP-2188M ( rd , wr , pms , dms , bms , cms , and ioms ) used in your target system must have 10 k ? pull-up resistors connected when the ez-ice is being used. the pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical ez-ice debugging sessions. these resistors may be removed at your option when the ez-ice is not being used. target system interface signals when the ez-ice board is installed, the performance on some system signals change. design your system to be compatible with the following system interface signal changes introduced by the ez-ice board: ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the dsp on the reset signal. ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the dsp on the br signal. ez-ice emulation ignores reset and br when single- stepping. ez-ice emulation ignores reset and br when in emulator space (dsp halted). ez-ice emulation ignores the state of target br in certain modes. as a result, the target system may take control of the dsp? external memory bus only if bus grant ( bg ) is asserted by the ez- ice board? dsp.
rev. 0 C19C ADSP-2188M recommended operating conditions k grade b grade parameter min max min max unit v ddint 2.61 2.89 2.25 2.75 v v ddext 2.61 3.6 2.25 3.6 v v input 1 v il = ?.3 v ih = +3.6 v il = ?.3 v ih = +3.6 v t amb 0 +70 ?0 +85 c notes 1 the ADSP-2188M is 3.3 v tolerant (always accepts up to 3.6 v max v ih ), but voltage compliance (on outputs, v oh ) depends on the input v ddext ; because v oh (max) v ddext (max). this applies to bidirectional pins (d0?23, rfs0, rfs1, sclk0, sclk1, tfs 0, tfs1, a1?13, pf0?f7) and input only pins (clkin, reset , br , dr0, dr1, pwd ). specifications subject to change without notice. electrical characteristics k/b grades parameter test conditions min typ max unit v ih hi-level input voltage 1, 2 @ v ddint = max 1.5 v v ih hi-level clkin voltage @ v ddint = max 2.0 v v il lo-level input voltage 1, 3 @ v ddint = min 0.7 v v oh hi-level output voltage 1, 4, 5 @ v ddext = min, i oh = ?.5 ma 2.0 v @ v ddext = 3.0 v, i oh = ?.5 ma 2.4 v @ v ddext = min, i oh = ?00 a 6 v ddext ?0.3 v v ol lo-level output voltage 1, 4, 5 @ v ddext = min, i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v ddint = max, v in = 3.6 v 10 a i il lo-level input current 3 @ v ddint = max, v in = 0 v 10 a i ozh three-state leakage current 7 @ v ddext = max, v in = 3.6 v 8 10 a i ozl three-state leakage current 7 @ v ddext = max, v in = 0 v 8 10 a i dd supply current (idle) 9 @ v ddint = 2.75, t ck = 15 ns 9 ma i dd supply current (idle) 9 @ v ddint = 2.75, t ck = 13.3 ns 10 ma i dd supply current (dynamic) 10 @ v ddint = 2.75, t ck = 15 ns 11 , t amb = 25 c44ma i dd supply current (dynamic) 10 @ v ddint = 2.75, t ck = 13.3 ns 11 , t amb = 25 c42ma i dd supply current (power-down) 12 @ v ddint = 2.75, t amb = 25 c in lowest 100 a power mode c i input pin capacitance 3, 6 @ v in = 2.75 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 6, 7, 12, 13 @ v in = 2.75 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 bidirectional pins: d0?23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1?13, pf0?f7. 2 input only pins: reset , br , dr0, dr1, pwd . 3 input only pins: clkin, reset , br , dr0, dr1, pwd . 4 output pins: bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2?, bgh . 5 although specified for ttl outputs, all ADSP-2188M outputs are cmos-compatible and will drive to v ddext and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: a0?13, d0?23, pms , dms , bms , ioms , cms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rfs1, pf0?f7. 8 0 v on br . 9 idle refers to ADSP-2188M state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 10 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11 v in = 0 v and 3 v. for typical figures for supply currents, refer to power dissipation section. 12 see chapter 9 of the adsp-2100 family user? manual for details. 13 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. specifications
rev. 0 C20C ADSP-2188M absolute maximum ratings 1 value parameter min max internal supply voltage (v ddint ) ?.3 v +3.0 v external supply voltage (v ddext ) ?.3 v +4.0 v input voltage 2 ?.5 v +4.0 v output voltage swing 3 ?.5 v v ddext + 0.5 v operating temperature range ?0 c +85 c storage temperature range ?5 c +150 c lead temperature (5 sec) lqfp 280 c notes 1 stresses greater than those listed may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specifi- cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 applies to bidirectional pins (d0?23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1?13, pf0?f7) and input only pins (clkin, reset , br , dr0, dr1, pwd ). 3 applies to output pins ( bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2?, bgh ). timing specifications general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an indiv idual device, the values given in this data sh eet reflect statistical variations and worst cases. consequently, you cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timing?ircuitry external to the proc essor must be designed for compat ibility with these signal characteristics. switching characteristics tell you what the processor will do in a given circumstance. you can also use switching characteristics to ensure that any timing require- ment of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the proces- sor operates correctly with other devices. memory timing specifications the table below shows common memory device specifications and the corresponding ADSP-2188M timing parameters, for your convenience. memory timing device parameter specification parameter definition 1 address setup to t asw a0?13, xms setup before write start wr low address setup to t aw a0?13, xms setup before write end wr deasserted address hold time t wra a0?13, xms hold before wr low data setup time t dw data setup before wr high data hold time t dh data hold after wr high oe to data valid t rdd rd low to data valid address access time t aa a0?13, xms to data valid note 1 xms = pms , dms , bms , cms or ioms . esd sensitivity esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADSP-2188M features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 ADSP-2188M C21C each address and data pin has a 10 pf total load at the pin. the application operates at v ddext = 3.3 v and t ck = 30 ns. total power dissipation = p int + ( c v ddext 2 f ) p int = internal power dissipation from power vs. frequency graph (figure 15). ( c v ddext 2 f ) is calculated for each output: # of c v ddext 2 fpd parameters pins pf v mhz mw address 7 10 3.3 2 16.67 12.7 data output, wr 9 10 3.3 2 16.67 16.3 rd 1 10 3.3 2 16.67 1.8 clkout, dms 2 10 3.3 2 33.3 7.2 38.0 total power dissipation for this example is p int + 38.0 mw. output drive currents figure 14 shows typical i-v characteristics for the output drivers on the ADSP-2188M. the curves represent the current drive capability of the output drivers as a function of output voltage. v oh v ol source voltage v 0 0.5 1.0 source current ma 60 0 20 40 60 40 20 v ddext = 3.6v @ 40 c v ddext = 3.3v @ +25 c v ddext = 2.5v @ +85 c v ddext = 2.5v @ +85 c v ddext = 3.3v @ +25 c v ddext = 3.6v @ 40 c 80 80 1.5 2.0 2.5 3.0 3.5 4.0 figure 14. typical output driver characteristics frequency dependency for timing specifications t ck is defined as 0.5 t cki . the ADSP-2188M uses an input clock with a frequency equal to half the instruction rate. for example, a 37.50 mhz input clock (which is equivalent to 26.6 ns) yields a 13.3 ns processor cycle (equivalent to 75 mhz). t ck values within the range of 0.5 t cki period should be substituted for all relevant timing parameters to obtain the specification value. example: t ckh = 0.5 t ck ?2 ns = 0.5 (15 ns) ?2 ns = 5.5 ns environmental conditions 1 rating description symbol lqfp mini-bga thermal resistance ca 48 c/w 63.3 c/w (case-to-ambient) thermal resistance ja 50 c/w 70.7 c/w (junction-to-ambient) thermal resistance jc 2 c/w 7.4 c/w (junction-to-case) note 1 where the ambient temperature rating (t amb ) is: t amb = t case ?(pd ca ) t case = case temperature in c pd = power dissipation in w power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: external data memory is accessed every cycle with 50% of the address pins switching. external data memory writes occur every other cycle with 50% of the data pins switching.
rev. 0 C22C ADSP-2188M 15 power (p idle n ) mw 24mw 19mw 18mw 19mw 21mw 32mw power, idle n modes 2 1/t ck mhz 50 75 20 25 30 35 40 55 60 70 65 10 idle (16) idle (128) idle 15 power (p idle ) mw 28mw 36mw 24mw 32mw 20mw 28mw power, idle 1, 2, 4 1/t ck mhz 50 20 25 30 35 40 45 55 60 65 70 75 v ddint = 2.9v v ddint = 2.75v v d d in t = 2.6v 1/t ck mhz 50 45 75 101mw 88mw 78mw 129mw 111mw power, internal 1, 2, 3 145mw power (p int ) mw 70 55 60 65 70 75 100 105 110 115 120 125 130 135 140 145 150 85 80 95 90 v ddint = 2.9v v ddint = 2.75v v ddint = 2.6v notes: valid for all temperature grades. 1 power reflects device operating with no output loads. 2 typical power dissipation at 2.75v v ddint and 25 c, except where specified. 3 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 4 idle refers to state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. figure 15. power vs. frequency capacitive loading figure 16 and figure 17 show the capacitive loading character- istics of the ADSP-2188M. c l pf rise time (0.4v 2.4v) ns 30 300 0 50 100 150 200 250 25 15 10 5 0 20 t = 85 c v dd = 0v to 2.0v figure 16. typical output rise time vs. load capacitance (at maximum ambient operating temperature) c l pf 14 0 valid output delay or hold ns 50 100 150 250 200 12 4 2 2 10 8 nominal 16 18 6 4 6 figure 17. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature)
rev. 0 ADSP-2188M C23C test conditions output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the output disable time (t dis ) is the difference of t measured and t decay , as shown in the output enable/disable diagram. the time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitive load, c l , and the current load, i l , on the output pin. it can be approximated by the following equation: t c i decay l l = 05 . v from which t dis = t measured t decay is calculated. if multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. 1.5v output input 1.5v 2.0v 0.8v figure 18. voltage reference levels for ac measure- ments (except output enable/disable) output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a refer- ence signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown figure 19. if multiple pins (such as the data bus) are enabled, the mea- surement value is that of the first pin to start driving. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) 0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 19. output enable/disable to output pin 50pf 1.5v i oh i ol figure 20. equivalent loading for ac measurements (including all fixtures)
rev. 0 C24C ADSP-2188M parameter min max unit clock signals and reset timing requirements: t cki clkin period 26.6 80 ns t ckil clkin width low 8 ns t ckih clkin width high 8 ns switching characteristics: t ckl clkout width low 0.5t ck 2ns t ckh clkout width high 0.5t ck 2ns t ckoh clkin high to clkout high 0 13 ns control signals timing requirements : t rsp reset width low 5t ck 1 ns t ms mode setup before reset high 2 ns t mh mode hold after reset high 5 ns note 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable c lkin (not including crystal oscillator start-up time). t ckoh t cki t ckih t ckil t ckh t ckl t mh t ms clkin clkout pf(3:0) * reset * pf3 is mode d, pf2 is mode c, pf1 is mode b, pf0 is mode a t rsp figure 21. clock signals
rev. 0 ADSP-2188M C25C parameter min max unit interrupts and flags timing requirements: t ifs irqx , fi, or pfx setup before clkout low 1, 2, 3, 4 0.25t ck + 10 ns t ifh irqx , fi, or pfx hold after clkout high 1, 2, 3, 4 0.25t ck ns switching characteristics: t foh flag output hold after clkout low 5 0.5t ck 5ns t fod flag output delay from clkout low 5 0.5t ck + 4 ns notes 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (refer to interrupt controller operation in the program control chapter of the adsp-2100 family user s manual for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 , irq1 , irq2 , irql0 , irql1 , irqle . 4 pfx = pf0, pf1, pf2, pf3, pf4, pf5, pf6, pf7. 5 flag outputs = pfx, fl0, fl1, fl2, fo. t fod t foh t ifh t ifs clkout flag outputs irqx fi pfx figure 22. interrupts and flags
rev. 0 C26C ADSP-2188M parameter min max unit bus request?us grant timing requirements: t bh br hold after clkout high 1 0.25t ck + 2 ns t bs br setup before clkout low 1 0.25t ck + 10 ns switching characteristics: t sd clkout high to xms , rd , wr disable 0.25t ck + 8 ns t sdb xms , rd , wr disable to bg low 0 ns t se bg high to xms , rd , wr enable 0 ns t sec xms , rd , wr enable to clkout high 0.25t ck 3ns t sdbh xms , rd , wr disable to bgh low 2 0ns t seh bgh high to xms , rd , wr enable 2 0ns notes xms = pms , dms , cms , ioms , bms . 1 br is an asynchronous signal. if br meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recogniz ed on the following cycle. refer to the adsp-2100 family user s manual for br / bg cycle relationships. 2 bgh is asserted when the bus is granted and the processor or bdma requires control of the bus to continue. clkout t sd t sdb t se t sec t sdbh t seh t bs br t bh clkout pms , dms bms , rd wr bg bgh figure 23. bus requestCbus grant
rev. 0 ADSP-2188M C27C parameter min max unit memory read timing requirements: t rdd rd low to data valid 0.5t ck 5 + w ns t aa a0 a13, xms to data valid 0.75t ck 6 + w ns t rdh data hold from rd high 0 ns switching characteristics: t rp rd pulsewidth 0.5t ck 3 + w ns t crd clkout high to rd low 0.25t ck 2 0.25t ck + 4 ns t asr a0 a13, xms setup before rd low 0.25t ck 3ns t rda a0 a13, xms hold after rd deasserted 0.25t ck 3ns t rwr rd high to rd or wr low 0.5t ck 3ns notes w = wait states x t ck . xms = pms , dms , cms , ioms , bms . clkout a0 a13 d0 d23 t rda t rwr t rp t asr t crd t rdd t aa t rdh dms , pms , bms , ioms , cms rd wr figure 24. memory read
rev. 0 C28C ADSP-2188M parameter min max unit memory write switching characteristics: t dw data setup before wr high 0.5t ck 4 + w ns t dh data hold after wr high 0.25t ck 1ns t wp wr pulsewidth 0.5t ck 3 + w ns t wde wr low to data enabled 0 ns t asw a0 a13, xms setup before wr low 0.25t ck 3ns t ddr data disable before wr or rd low 0.25t ck 3ns t cwr clkout high to wr low 0.25t ck 2 0.25 t ck + 4 ns t aw a0 a13, xms , setup before wr deasserted 0.75t ck 5 + w ns t wra a0 a13, xms hold after wr deasserted 0.25t ck 1ns t wwr wr high to rd or wr low 0.5t ck 3ns notes w = wait states x t ck. xms = pms , dms , cms , ioms , bms . clkout a0 a13 d0 d23 t wp t aw t cwr t dh t wde t dw t asw t wwr t wra t ddr dms , pms, bms , cms, ioms rd wr figure 25. memory write
rev. 0 ADSP-2188M C29C serial ports parameter min max unit serial ports timing requirements: t sck sclk period 26.6 ns t scs dr/tfs/rfs setup before sclk low 4 ns t sch dr/tfs/rfs hold after sclk low 7 ns t scp sclkin width 12 ns switching characteristics : t cc clkout high to sclkout 0.25t ck 0.25t ck + 6 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 12 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 12 ns t scdh dt hold after sclk high 0 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 12 ns t scdd sclk high to dt disable 12 ns t rdv rfs (multichannel, frame delay zero) to dt valid 12 ns clkout sclk tfs out rfs out dt alternate frame mode t cc t cc t scs t sch t rh t scde t scdh t scdd t tde t rdv multichannel mode, frame delay 0 (mfd = 0) dr tfs in rfs in rfs out tfs out t tdv t scdv t rd t scp t sck t scp tfs in rfs in alternate frame mode t rdv multichannel mode, frame delay 0 (mfd = 0) t tdv t tde figure 26. serial ports
rev. 0 C30C ADSP-2188M parameter min max unit idma address latch timing requirements: t ialp duration of address latch 1, 2 10 ns t iasu iad15 0 address setup before address latch end 2 5ns t iah iad15 0 address hold after address latch end 2 3ns t ika iack low before start of address latch 2, 3 0ns t ials start of write or read after address latch end 2, 3 3ns t iald address latch start after address latch end 1, 2 2ns notes 1 start of address latch = is low and ial high. 2 end of address latch = is high or ial low. 3 start of write or read = is low and iwr low or ird low. iack ial is iad15 0 ird or iwr t ika t ialp t iald t iasu t iah t iasu t ials t iah t ialp figure 27. idma address latch
rev. 0 ADSP-2188M C31C parameter min max unit idma write, short write cycle timing requirements: t ikw iack low before start of write 1 0ns t iwp duration of write 1, 2 10 ns t idsu iad15 0 data setup before end of write 2, 3, 4 3ns t idh iad15 0 data hold after end of write 2, 3, 4 2ns switching characteristic : t ikhw start of write to iack high 10 ns notes 1 start of write = is low and iwr low. 2 end of write = is high or iwr high. 3 if write pulse ends before iack low, use specifications t idsu , t idh . 4 if write pulse ends after iack low, use specifications t iksu , t ikh . iad15 0 data t ikhw t ikw t idsu iack t iwp t idh is iwr figure 28. idma write, short write cycle
rev. 0 C32C ADSP-2188M parameter min max unit idma write, long write cycle timing requirements: t ikw iack low before start of write 1 0ns t iksu iad15 0 data setup before end of write 2, 3, 4 0.5 t ck + 5 ns t ikh iad15 0 data hold after end of write 2, 3, 4 0ns switching characteristics : t iklw start of write to iack low 4 1.5 t ck ns t ikhw start of write to iack high 10 ns notes 1 start of write = is low and iwr low. 2 if write pulse ends before iack low, use specifications t idsu , t idh . 3 if write pulse ends after iack low, use specifications t iksu , t ikh . 4 this is the earliest time for iack low from start of write. for idma write cycle relationships, please refer to the adsp-2100 family user s manual . iad15 0 data t ikhw t ikw iack is iwr t iklw t ikh t iksu figure 29. idma write, long write cycle
rev. 0 ADSP-2188M C33C parameter min max unit idma read, long read cycle timing requirements: t ikr iack low before start of read 1 0ns t irk end of read after iack low 2 2ns switching characteristics: t ikhr iack high after start of read 1 10 ns t ikds iad15 0 data setup before iack low 0.5t ck 2ns t ikdh iad15 0 data hold after end of read 2 0ns t ikdd iad15 0 data disabled after end of read 2 10 ns t irde iad15 0 previous data enabled after start of read 0 ns t irdv iad15 0 previous data valid after start of read 11 ns t irdh1 iad15 0 previous data hold after start of read (dm/pm1) 3 2t ck 5ns t irdh2 iad15 0 previous data hold after start of read (pm2) 4 t ck 5ns notes 1 start of read = is low and ird low. 2 end of read = is high or ird high. 3 dm read or first half of pm read. 4 second half of pm read. t irk t ikr previous data read data t ikhr t ikds t irdv t ikdd t irde t ikdh iad15 0 iack is ird t irdh1 or t irdh2 figure 30. idma read, long read cycle
rev. 0 C34C ADSP-2188M parameter min max unit idma read, short read cycle 1, 2 timing requirements: t ikr iack low before start of read 3 0ns t irp1 duration of read (dm/pm1) 4 10 2t ck 5ns t irp2 duration of read (pm2) 5 10 t ck 5ns switching characteristics : t ikhr iack high after start of read 3 10 ns t ikdh iad15 0 data hold after end of read 6 0ns t ikdd iad15 0 data disabled after end of read 6 10 ns t irde iad15 0 previous data enabled after start of read 0 ns t irdv iad15 0 previous data valid after start of read 10 ns notes 1 short read only must be disabled in the idma overlay memory mapped register. 2 consider using the short read only mode, instead, because short read mode is not applicable at high clock frequencies. 3 start of read = is low and ird low. 4 dm read or first half of pm read. 5 second half of pm read. 6 end of read = is high or ird high. t irp t ikr previous data t ikhr t irdv t ikdd t irde t ikdh iad15 0 iack is ird figure 31. idma read, short read cycle
rev. 0 ADSP-2188M C35C parameter min max unit idma read, short read cycle in short read only mode 1 timing requirements: t ikr iack low before start of read 2 0ns t irp duration of read 3 10 ns switching characteristics: t ikhr iack high after start of read 2 10 ns t ikdh iad15 0 previous data hold after end of read 3 0ns t ikdd iad15 0 previous data disabled after end of read 3 10 ns t irde iad15 0 previous data enabled after start of read 0 ns t irdv iad15 0 previous data valid after start of read 10 ns notes 1 short read only is enabled by setting bit 14 of the idma overlay register to 1 (0x3fe7). short read only can be enabled by the processor core writing to the register or by an external host writing to the register. disabled by default. 2 start of read = is low and ird low. previous data remains until end of read. 3 end of read = is high or ird high. t irp t ikr previous data t ikhr t irdv t ikdd t irde t ikdh iad15 0 iack is ird figure 32. idma read, short read only cycle
rev. 0 C36C ADSP-2188M 100-lead lqfp pin configuration 5 4 3 2 7 6 9 8 1 d19 d18 d17 d16 irqe +pf4 irql0 +pf5 gnd irql1 +pf6 dt0 tfs0 sclk0 v ddext dt1/fo tfs1/i rq1 dr1/fi gnd sclk1 ereset reset d15 d14 d13 d12 gnd d11 d10 d9 v ddext gnd d8 d7/ iwr d6/ ird d5/ial d4/ is gnd v ddint d3/ iack d2/iad15 d1/iad14 d0/iad13 bg ebg br ebr a4/iad3 a5/iad4 gnd a6/iad5 a7/iad6 a8/iad7 a9/iad8 a10/iad9 a11/iad10 a12/iad11 a13/iad12 gnd clkin xtal v ddext clkout gnd v ddint wr rd bms dms pms ioms cms 71 72 73 74 69 70 67 68 65 66 75 60 61 62 63 58 59 56 57 54 55 64 52 53 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pin 1 identifier top view (not to scale) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 ADSP-2188M irq2 +pf7 rfs0 dr0 ems ee elout eclk elin eint a3/iad2 a2/iad1 a1/iad0 a0 pwdack bgh fl0 fl1 fl2 d23 d22 d21 d20 gnd pf1 [mode b] gnd pwd v ddext pf0 [mode a] pf2 [mode c] pf3 [mode d] rfs1/ irq0
rev. 0 ADSP-2188M C37C the lqfp package pinout is shown in the table below. pin names in bold text replace the plain text named functions when mode c = 1. a + sign separates two functions when either function can be active for either major i/o mode. signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of reset . the multiplexed pins dt1/fo, tfs1/ irq1 , rfs1/ irq0 , and dr1/fi, are mode selectable by setting bit 10 (sport1 configure) of the system control register. if bit 10 = 1, these pins have serial port functionality. if bit 10 = 0, these pins are the ext ernal inter- rupt and flag pins. this bit is set to 1 by default upon reset. lqfp package pinout pin pin pin pin no. pin name no. pin name no. pin name no. pin name 1 a4/ iad3 26 irqe + pf4 51 ebr 76 d16 2 a5/ iad4 27 irql0 + pf5 52 br 77 d17 3 gnd 28 gnd 53 ebg 78 d18 4a6 /iad5 29 irql1 + pf6 54 bg 79 d19 5 a7/ iad6 30 irq2 + pf7 55 d0/ iad13 80 gnd 6 a8/ iad7 31 dt0 56 d1/ iad14 81 d20 7 a9/ iad8 32 tfs0 57 d2/ iad15 82 d21 8 a10/ iad9 33 rfs0 58 d3/ iack 83 d22 9 a11/ iad10 34 dr0 59 v ddint 84 d23 10 a12/ iad11 35 sclk0 60 gnd 85 fl2 11 a13/ iad12 36 v ddext 61 d4/ is 86 fl1 12 gnd 37 dt1/fo 62 d5/ ial 87 fl0 13 clkin 38 tfs1/ irq1 63 d6/ ird 88 pf3 [mode d] 14 xtal 39 rfs1/ irq0 64 d7/ iwr 89 pf2 [mode c] 15 v ddext 40 dr1/fi 65 d8 90 v ddext 16 clkout 41 gnd 66 gnd 91 pwd 17 gnd 42 sclk1 67 v ddext 92 gnd 18 v ddint 43 ereset 68 d9 93 pf1 [mode b] 19 wr 44 reset 69 d10 94 pf0 [mode a] 20 rd 45 ems 70 d11 95 bgh 21 bms 46 ee 71 gnd 96 pwdack 22 dms 47 eclk 72 d12 97 a0 23 pms 48 elout 73 d13 98 a1/ iad0 24 ioms 49 elin 74 d14 99 a2/ iad1 25 cms 50 eint 75 d15 100 a3/ iad2
rev. 0 C38C ADSP-2188M 144-ball mini-bga package pinout (bottom view) irql0 + pf5 irq2 + pf7 nc cms gnd dt1/fo dr1/fi gnd nc ems ee eclk irqe + pf4 nc irql1 + pf6 ioms gnd pms dr0 gnd reset elin elout eint nc nc nc bms dms rfs0 tfs1/ irq1 sclk1 ereset ebr br ebg clkout v ddint nc v ddext v ddext sclk0 d0/iad13 rfs1/ irq0 bg d1/iad14 v ddint v ddint clkin gnd gnd gnd v ddint dt0 tfs0 d2/iad15 d3/ iack gnd nc gnd xtal nc gnd a10/iad9 nc nc nc d6/ ird d5/ial nc nc d4/ is a13/iad12 nc a12/iad11 a11/iad10 fl1 nc nc d7/ iwr d11 d8 nc d9 v ddext v ddext a8/iad7 fl0 pf0 [mode a] fl2 pf3 [mode d] gnd gnd v ddext gnd d10 nc wr nc bgh a9/iad8 pf1 [mode b] pf2 [mode c] nc d13 d12 nc gnd pwdack a6/iad5 rd a5/iad4 a7/iad6 pwd v ddext d21 d19 d15 nc d14 a4/iad3 a3/iad2 gnd nc nc gnd v ddext d23 d20 d18 d17 d16 a2/iad1 a1/iad0 gnd a0 nc gnd nc nc nc d22 gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 m l k j h g f e d c b a
rev. 0 ADSP-2188M C39C the mini-bga package pinout is shown in the table below. pin names in bold text replace the plain text named functions when mode c = 1. a + sign separates two functions when either function can be active for either major i/o mode. signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of reset . the multiplexed pins dt1/fo, tfs1/ irq1 , rfs1/ irq0 , and dr1/fi, are mode selectable by setting bit 10 (sport1 configure) of the system control register. if bit 10 = 1, these pins have serial port functionality. if bit 10 = 0, these pins are the extern al interrupt and flag pins. this bit is set to 1 by default upon reset. mini-bga package pinout ball # pin name ball # pin name ball # pin name ball # pin name a01 a2/ iad1 d01 nc g01 xtal k01 nc a02 a1/ iad0 d02 wr g02 nc k02 nc a03 gnd d03 nc g03 gnd k03 nc a04 a0 d04 bgh g04 a10/ iad9 k04 bms a05 nc d05 a9/ iad8 g05 nc k05 dms a06 gnd d06 pf1 [mode b] g06 nc k06 rfs0 a07 nc d07 pf2 [mode c] g07 nc k07 tfs1/ irq1 a08 nc d08 nc g08 d6/ ird k08 sclk1 a09 nc d09 d13 g09 d5/ ial k09 ereset a10 d22 d10 d12 g10 nc k10 ebr a11 gnd d11 nc g11 nc k11 br a12 gnd d12 gnd g12 d4/ is k12 ebg b01 a4/ iad3 e01 v ddext h01 clkin l01 irqe + pf4 b02 a3/ iad2 e02 v ddext h02 gnd l02 nc b03 gnd e03 a8/ iad7 h03 gnd l03 irql1 + pf6 b04 nc e04 fl0 h04 gnd l04 ioms b05 nc e05 pf0 [mode a] h05 v ddint l05 gnd b06 gnd e06 fl2 h06 dt0 l06 pms b07 v ddext e07 pf3 [mode d] h07 tfs0 l07 dr0 b08 d23 e08 gnd h08 d2/ iad15 l08 gnd b09 d20 e09 gnd h09 d3/ iack l09 reset b10 d18 e10 v ddext h10 gnd l10 elin b11 d17 e11 gnd h11 nc l11 elout b12 d16 e12 d10 h12 gnd l12 eint c01 pwdack f01 a13/ iad12 j01 clkout m01 irql0 + pf5 c02 a6/ iad5 f02 nc j02 v ddint m02 irql2 + pf7 c03 rd f03 a12/ iad11 j03 nc m03 nc c04 a5/ iad4 f04 a11/ iad10 j04 v ddext m04 cms c05 a7/ iad6 f05 fl1 j05 v ddext m05 gnd c06 pwd f06 nc j06 sclk0 m06 dt1/fo c07 v ddext f07 nc j07 d0/ iad13 m07 dr1/fi c08 d21 f08 d7/ iwr j08 rfs1/ irq0 m08 gnd c09 d19 f09 d11 j09 bg m09 nc c10 d15 f10 d8 j10 d1/ iad14 m10 ems c11 nc f11 nc j11 v ddint m11 ee c12 d14 f12 d9 j12 v ddint m12 eclk
rev. 0 C40C c01629C2.5C9/00 (rev. 0) printed in u.s.a. ADSP-2188M outline dimensions dimensions shown in millimeters. 100-lead metric thin plastic quad flatpack (lqfp) (st-100) seating plane 0.75 0.60 typ 0.50 1.60 max 12 typ 0.15 0.05 6 4 0 7 0.08 max lead coplanarity top view (pins down) 1 25 26 51 50 75 100 76 0.27 0.22 typ 0.17 16.20 16.00 typ sq 15.80 0.50 bsc lead pitch 14.05 14.00 typ sq 13.95 12.00 bsc lead width note: the actual position of each lead is within 0.08 from its ideal position when measured in the lateral direction. 144-ball mini-bga (ca-144) seating plane 1.00 0.85 detail a 0.55 0.50 0.45 ball diameter 0.12 max 0.40 0.25 1.40 max detail a 0.80 bsc 8.80 bsc 0.80 bsc 8.80 bsc a b c d e f g h j k l m 12 11 10 9 8 7 6 5 4 3 2 1 top view 10.10 10.00 sq 9.90 10.10 10.00 sq 9.90 notes: the actual position of the ball population is within 0.150 of its ideal position relative to the package edges. the actual position of each ball is within 0.08 of its ideal position relative to the ball population. 1. 2. ordering guide ambient temperature instruction package package part number range rate description * option ADSP-2188Mkst-300 0 c to 70 c 75 100-lead lqfp st-100 ADSP-2188Mbst-266 40 c to +85 c 66 100-lead lqfp st-100 ADSP-2188Mkca-300 0 c to 70 c 75 144-ball mini-bga ca-144 ADSP-2188Mbca-266 40 c to +85 c 66 144-ball mini-bga ca-144 * in 1998, jedec reevaluated the specifications for the tqfp package designation, assigning it to packages 1.0 mm thick. previous ly labeled tqfp packages (1.6 mm thick) are now designated as lqfp.

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