hy514404a 1mx4, extended data out mode this family is a 4m bit dynamic ram organized 1,048,576 x 4- bit configuration with extended data out mode cmos drams . extended data out mode is a kind of page mode which is useful for the read operation. the circuit and process design allow this device to achieve high performance and low power dissipation. optional features are access time(50, 60 or 70ns) and package type(soj, tsop-ii) and power consumption (normal or low power with self refresh). hyundai ? s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. description features ? extended data out operation ? read-modify-write capability ? ttl compatible inputs and outputs ? /cas-before-/ras , /ras-only, hidden and self refresh capability ? max. active power dissipation speed 50 power 605 mw ? fast access time and cycle time speed 50 60 trac 50 ns 60 ns tcac 13 ns 15 ns thpc 20 ns 25 ns ? refresh cycle part number hy514404a refresh 1 k normal 16 ms sl-part 128 ms this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licences are implied rev.10 / jan.97 ordering information part name hy514404aj refresh 1 k power package 20/26 pin soj hy514404alj 1 k l-part 20/26 pin soj hy514404at 1 k 20/26 pin tsop-ii hy514404alt 1 k l-part 20/26 pin tsop-ii 60 495 mw hyundai semiconductor ? jedec standard pinout ? 20/26-pin soj (300mil ) 20/26- pin tsop -ii (300mil ) ? single power supply of 5v 10% ? early write or output enable controlled write 1 * sl : low power with self refresh 70 412 mw 70 70 ns 20 ns 30 ns
hy514404a functional block diagram we cas oe data input buffer data output buffer cas clock generator cloumn predecoder (10) refresh controller refresh counter (10) column decoder sense amp i/o gate memory array 1,048,576 x 4 row decoder row predecoder (10) ras clock generator substrate bias generator v cc v ss address buffer ras dq0 ~ dq3 10 10 4 8 4 4 a0 a1 a2 2 a3 a4 a5 a6 a7 a8 4 a9 1 mx4, edo dram rev.10 / jan.97
hy514404a pin configuration (marking side) pin description / ras / cas row address strobe column address strobe / we write enable / oe output enable a0 ~a9 address input dq0 ~dq3 data in/out vcc power (5v) vss ground 20/26 pin plastic tsop- ii (300mil ) pin name parameter 3 20/26 pin plastic soj (300mil ) dq0 dq1 ras a9 a0 a1 a2 a3 vcc 1 2 3 4 5 9 10 11 12 13 26 25 24 23 22 18 17 16 15 14 v ss dq3 dq2 cas oe a8 a7 a6 a5 a4 we dq0 dq1 ras a9 a0 a1 a2 a3 vcc 1 2 3 4 5 9 10 11 12 13 26 25 24 23 22 18 17 16 15 14 v ss dq3 dq2 cas oe a8 a7 a6 a5 a4 we 1 mx4, edo dram rev.10 / jan.97
hy514404a absolute maximum ratings symbol t a parameter ambient temperature rating 0 to 70 unit c t stg storage temperature -55 to 150 c v in, v out voltage on any pin relative to v ss -1.0 to 7.0 v v cc voltage on v cc relative to v ss -1.0 to 7.0 v i os short circuit output current 50 ma p d power dissipation 0.9 w t solder soldering temperature ? time 260 ? 10 c ? sec note : operation at or above absolute maximum ratings can adversely affect device reliability symbol i li parameter input leakage current (any input) unit m a min -10 max 10 test condition v ss v in v cc + 1.0 all other pins not under test = v ss dc operating characteristics i lo output leakage current (any input) m a -10 10 v ss v out v cc /ras & /cas at v ih v ol output low voltage v - 0.4 i ol = 4.2 ma v oh output high voltage v 2.4 - i oh = -5.0 ma 4 recommended dc operating conditions symbol v cc parameter power supply voltage unit v max 5.5 typ 5.0 min 4.5 v ih input high voltage v v cc+ 1.0 - 2.4 v il input low voltage v 0.8 - -1.0 note : all voltages are referenced to v ss . ( t a = 0 c to 70 c ) 1 mx4, edo dram rev.10 / jan.97
hy514404a dc characteristics symbol i cc1 parameter operating current speed 50 60 70 unit ma ( t a = 0 c to 70 c , v cc = 5v 10% , v ss = 0v, unless otherwise noted.) note 100 90 75 test condition / ras, /cas cycling t rc = t rc (min) max. i cc2 ttl standby current ma 2 / ras, /cas 3 v ih(min) other inputs 3 v ss i cc3 / ras-only refresh current 50 60 70 ma 110 90 75 / ras cycling,/cas = v ih t rc = t rc (min) i cc4 edo mode current 50 60 70 ma 115 90 75 / cas cycling, /ras = v il t hpc = t hpc (min) i cc5 cmos standby current sl-part ma m a 1 200 / ras = /cas 3 v cc - 0.2v i cc6 / cas-before-/ras refresh current 50 60 70 ma 95 80 65 / ras & /cas = 0.2v t rc = t rc (min.) i cc7 battery back-up current (l -part) m a trc =125 s /cas = cbr cycling or 0.2v /oe & /we = v cc - 0.2v address = vcc -0.2v or 0.2v dq0 ~dq9 = vcc -0.2, 0.2v or open 1. i cc1 , i cc3 , i cc4 , i cc6 and i cc6 depend on output loading and cycle rates( t rc and t hpc ). 2. specified values are obtained with output unloaded. 3. i cc is specified as an average current. in i cc1 , i cc3 , i cc6 , address can be changed only once while /ras=v il . in i cc4 , address can be changed maximum once while /cas=v ih withen one edo mode cycle time t hpc . 4. only tras (max) = 1 s is applied to refresh of battery backup but tras (max) = 10 s is to applied to normal functional operation. 5. icc5(max.), icc7 are applied to l -part only. 5 1 mx4, edo dram rev.10 / jan.97 tras 300ns 300 tras e 1 s 400
t rc random read or write cycle time 105 ns symbol parameter min max min max unit note 60 ns 70 ns ac characteristics ( t a = 0 c to 70 c , v cc = 5 v 10% , v ss = 0v, unless otherwise noted.) hy514404a read-modify-write cycle time 142 edo mode cycle time 25 edo mode read-modify-write cycle time 73 access time from /ras - access time from /cas - access time from column address - access time from /cas precharge - / cas to output low impedance transition time(rise and fall) / ras precharge time / ras pulse width / ras pulse width(edo mode) / ras hold time / cas hold time / cas pulse width / ras to /cas delay time / ras to column address delay time / cas to /ras precharge time / cas precharge time row address set-up time row address hold time column address set-up time column address hold time column address to /ras lead time read command set-up time read command hold time referenced to /cas t rwc t hpc t hprwc t rac t cac t aa t cpa t clz t t t rp t ras t rasp t rsh t csh t cas t rcd t rad t crp t cp t asr t rah t asc t cah t ral t rcs t rch 0 2.5 40 60 60 15 40 10 20 15 5 10 0 10 0 10 30 0 0 - - - - 60 15 30 35 - 50 - 10 k 100 k - - 10 k 45 30 - - - - - - - - - 125 167 30 85 - - - - 0 2.5 50 70 70 13 50 15 20 15 5 10 0 10 0 15 35 0 0 - - - - 70 20 35 35 - 50 - 10 k 100 k - - 10 k 50 35 - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 4,9,10 4,9 4,10 4,15 4 3 9 10 15 17 14 14 14 6,14 1 mx4, edo dram rev.10 / jan.97 read command hold time referenced to /ras t rrh 0 - 0 - ns 6 write command hold time write command pulse width t wch t wp 10 10 - - 15 10 - - ns ns 14 50 ns 85 min max 120 20 62 - - - - 0 2.5 30 50 50 13 40 8 20 15 5 7 0 10 0 8 25 0 0 - - - - 50 13 25 30 - 50 - 10 k 100 k - - 10 k 37 25 - - - - - - - - - 0 - 8 10 - - write command to /ras lead time t rwl 15 - 15 - ns 13 -
symbol parameter min max min max unit note 60 ns 70 ns ac characteristics continued hy514404a data-in set-up time data-in hold time refresh period (1024 cycles) refresh period (l -part) write command set-up time / cas to /we delay time / ras to /we delay time column address to /we delay time / cas set-up time(cbr cycle) / cas hold time(cbr cycle) / ras to /cas precharge time / cas precharge time(cbr counter test) / ras hold time referenced to /oe / oe access time / oe to data delay output buffer turn-off delay time from /oe / oe command hold time / we delay time from /cas precharge / ras hold time from /cas precharge / we to /ras precharge time (cbr cycle) t ds t dh t ref t wcs t cwd t rwd t awd t csr t chr t rpc t cpt t roh t oea t oed t oez t oeh t cpwd t rhcp t wrp 0 10 16 128 0 37 80 50 5 10 5 30 10 - 15 0 15 55 35 10 - - - - - - - - - - - - - 15 - 15 - - - - 0 15 16 128 0 45 95 60 5 10 5 35 10 - 20 0 20 65 40 10 - - - - - - - - - - - - - 20 - 15 - - - - ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 7 7 12 11 8,14 8 8 8 14 15 14 17 5 8 1 mx4, edo dram rev.10 / jan.97 output data hold time output buffer turn off delay time from /ras / oe pulse width t wrh t rps t doh t rez t wez t oep 10 105 5 0 0 10 - - - 15 15 - 10 125 5 0 0 10 - - - 15 15 - ns ns ns ns ns ns t och t cho / we to /ras hold time(cbr cycle) / ras precharge time output buffer turn off delay time from /we / oe to /cas hold time 0 - 0 - ns / cas hold time to /oe 5 - 7 - ns min max 0 8 16 128 0 33 70 45 5 10 5 25 10 - 13 0 13 50 30 10 - - - - - - - - - - - - - 13 - 13 - - - - 10 85 5 0 3 10 - - - 13 13 - 0 - 5 - 50 ns / we to data delay time t wed 15 - 15 - ns 13 - / we pulse width for output dsiable when /cass high t wpe 10 - 10 - ns 10 - t cwl write command to /cas lead time ns 10 - 15 - 16 8 -
hy514404a note 8 1 mx4 edo dram rev.10 / jan.97 capacitance symbol c in1 parameter input capacitance (a0~a8) max 5 unit pf c in2 input capacitance (/ras, /cas , /we, /oe) 7 pf c dq data input / output capacitance (dq0 ~dq3) 7 pf ( t a = 25 c, v cc = 5v 10%, v ss = 0v and f=1mhz, unless otherwise noted.) typ . - - - 1. an initial pause of 200 m s is required after power-up followed by 8 /ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cbr refresh cycles instead of 8 /ras-only refresh cycles are required. 2. if /ras= vss during power-up,the hy514404a could begin an active cycle. this condition results in higher current than necessary current which is demanded from the power supply during power-up. it is recommended that /ras and /cas track with vcc during power-up or be held at a valid vih in other to minimize the power-up current. 3. vih(min.) and vil(max.) are reference levels for measuring timing of input signals. transition times are measured between vih(min.) and vil(max.),and are assumed to be 5ns for all inputs. 4. measured at v oh =2.0v and v ol =0.8v with a load equivalent to 2ttl loads and 100pf. 5. toff(max.) and toez define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 6. either trch or trrh must be satisfied for a read cycle. 7. t cez and t oez define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs(min.) , the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min) , and t cpwd 3 t cpwd (min.) , the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. operation within the t rcd(max.) limit ensures that t rac(max.) can be met. t rcd(max.) is specified as a reference point only. if t rcd is greater than the specified t rcd(max.) limit, then access time is controlled by t cac . 10.operation within the t rad(max.) limit ensures that t rac(max.) can be met. t rad(max.) is specified as a reference point only. if t rad is greater than the specified t rad(max.) limit, then access time is controlled by t aa . 11 . tref (max.)=128ms is applied to l -parts only. 12.a burst of 1024 cbr refresh cycles must be executed within 16ms (128ms for sl-part) after exiting self refresh. 13.when cas goes low at the same time, 4bits data are written into the device. 14.these parameters are determined by the earlier falling edge of /cas . 15.these parameters are determined by the later rising edge of /cas . 16. tcwl must be satisfied by /cas for 4bits access cycle. 17. tcp and tcpt are measured when /cas and is high state.
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