amd a 29k ? family technical bulletin arbiter solution for shared-bus systems using the am29030 ? or am29035 ? microprocessor epd systems engineering september 2, 1993 purpose assistance is available in the u.s. from 9:00 a . m . to 6:00 p . m . central time, monday through friday (except major holidays). in europe assistance is available during u.k. business hours. contact us at one of the following numbers: the revision d am29030 and am29035 microprocessors inappropriately assert the req CCC signal after bgrt CCCC is deasserted. in doing so, they create the potential for a bus collision in shared-bus systems . this bulletin includes the pal equations for a state machine used in an eb29030 ? board to prevent bus collisions. these equations may be revised to suit a particular arbiter design. to reach the u.s. from call u.s. 1-800-2929-amd u.k. 0-800-89-1455 affected parts japan 0031-11-1163 the information in this bulletin affects the following parts: any other location +1-512-462-4118 = = toll applies. device revision am29030 microprocessor b, d to reach the u.k. am29035 microprocessor b, d from call u.k. (0)256-811101 if you need assistance france 0590-8621 product support for the 29k family processors is available from our embedded processor division (epd) technical support hotlines located in the u.s. and in the u.k. germany 0130-813875 italy 1678-77224 any other location +44-(0)256-811101 = = toll applies. pid no. 18012 1 of 6
example pal equations for the eb29030 board arbiter (in plpl) "definitions" "030 = am29030 or am29035 microprocessor" "at = pc at" "eb29030 = am29030 execution board" "note" "these pal equations were designed for a state machine used in an eb29030" "board. these equations may be revised to suit a particular arbiter" "design." "u17 performs arbitration of 030 and at access requests to eb29030 memory," "as well as freeing memory for refresh when posted by the at." "rev 11 removes *breq from the arbitration, using *req and *bgrt only." "rev 12 implements pseudo-arbitration. it relies on the 030 to relinquish" "the bus by deasserting *req. this is the only arbitration scheme for" "rev d in the eb29030 board." device arbitrat (p22v10) pin "the pal pin names and architectural features follow." "input pin definitions" memclk = 1 (clock) /ataccplt = 2 (input combinatorial) "at access complete" /atacrdy = 3 (input combinatorial) "at access ready" /breq = 4 (input combinatorial) "030 bus request" /atacreq = 5 (input combinatorial) "at access request" /refreq = 6 (input combinatorial) "at refresh request" /refecplt = 7 (input combinatorial) "even bank refresh complete" /refocplt = 8 (input combinatorial) "odd bank refresh complete" /reset = 9 (input combinatorial) "hardware reset" /casodd = 10 (input combinatorial) "odd bank access complete" /caseven = 11 (input combinatorial) "even bank access complete" /req = 13 (input combinatorial) "030 request" exrefcplt = 14 (input combinatorial) "eb29030 board refresh complete" /erlya = 23 (input combinatorial) "030 early address mode" pid no. 18012 2 of 6
"output pin definitions" /state[4] = 22 (output registered active_low) "sv4 and atacgrnt" /state[5] = 21 (output registered active_low) "sv5 and atacack" /state[0] = 20 (output registered active_low) "sv0" /state[1] = 19 (output registered active_low) "sv1" /state[2] = 18 (output registered active_low) "sv2" /state[3] = 17 (output registered active_low) "sv3" /state[7] = 16 (output registered active_low) "sv7 and bgrt" /state[6] = 15 (output registered active_low); "sv6 and refact" begin "the logic definition and operation of the state machine is" "contained within this begin-end construct." enable(/state[7]); enable(/state[6]); enable(/state[5]); enable(/state[4]); enable(/state[3]); enable(/state[2]); enable(/state[1]); enable(/state[0]); if (reset) then begin "bgrt = 0" /state [7:0] = 126; end; else case (/state [7:0]) begin 126 ) begin "bgrt = 0" "let 030 have the bus upon reset or if no refresh" "nor at access request is outstanding." if (refreq * /erlya) then /state [7:0] = 127; "refresh request arrives." else if (/refreq * atacreq * /erlya) then /state [7:0] = 124; "at host access request arrives." else /state [7:0] = 126; "stay 126 if there is no request." end; pid no. 18012 3 of 6
127 ) begin "bgrt = 0" "synchronize a refresh request from the at with" "arbitration logic in this device." if (/refreq) then /state [7:0] = 126; "refreq set-up time missed this cycle." else if (/req) then /state [7:0] = 255; "move to 255 when *req deasserts." else /state [7:0] = 127; "wait until 030 relinquishes bus." end; 255 ) begin /state [7:0] = 243; " *bgrt is deasserted in this cycle." end; 243 ) begin if (/req) then /state [7:0] = 242; else /state [7:0] = 243; end; 242 ) begin "work-around for 030 bug found 8-25-91 where 030" "asserts *req even after *req deassert from *bgrt" "deassertion." if (req) then /state [7:0] = 243; else /state [7:0] = 191; end; 191 ) begin "refact = 0" "refresh active is now asserted indicating that a" "refresh can begin by each bank ras/cas/refresh pal." "this is the holding state which we remain in until" "both halves have completed their respective refresh" "cycle." if (/refecplt + /refocplt + /exrefcplt) then /state [7:0] = 191; if (refecplt * refocplt * exrefcplt) then /state [7:0] = 126; end; pid no. 18012 4 of 6
124 ) begin "bgrt = 0" "synchronize an at access request with the arbitration" "state machine." if (/atacreq) then /state [7:0] = 126; "set-up time was satisfied." else if (/req) then /state [7:0] = 252; "move to 252 when *req deasserts." else /state [7:0] = 124; "wait until 030 relinquishes bus." end; 252 ) begin /state [7:0] = 246; " *bgrt is deasserted here." end; 246 ) begin if (/req) then /state [7:0] = 240; else /state [7:0] = 246; end; 240 ) begin "work-around for 030 bug found 8-25-91 where 030" "asserts *req even after *bgrt is deasserted." if (req) then /state [7:0] = 246; else /state [7:0] = 220; end; 220 ) begin "atacack = 0" "at access acknowledge is now asserted indicating that" "the at can have the bus. we wait here until the at" "is ready to proceed with its access." "synchronization of its ready status is also performed" "in this and the next adjacent state." if (/atacrdy) then /state [7:0] = 220; else /state [7:0] = 212; end; pid no. 18012 5 of 6
212 ) begin "atacack = 0" if (/atacrdy) then /state [7:0] = 220; else /state [7:0] = 228; end; 228 ) begin "atacgrnt = 0" "this arbitration logic now informs the" "simple/page-mode pal to perform a simple access to" "the appropriate bank while waiting for the access to" "be completed." if (/casodd * /caseven) then /state [7:0] = 228; if (casodd + caseven) then /state [7:0] = 245; end; 245 ) begin "the at arbitration logic will inform this logic that" "its bus cycle is complete by asserting at access" "complete, but synchronization is required between it" "and this pal, i.e., different clocks." if (/ataccplt) then /state [7:0] = 245; else /state [7:0] = 253; end; 253 ) begin if (/ataccplt) then /state [7:0] = 245; else /state [7:0] = 126; end; end; end. pid no. 18012 6 of 6
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