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features low power consumption 2.5ghz input 144 frequencies, 1mhz steps (20mhz crystal) forms complete phase locked loop using external vco and loop components serially programmed via 3 wire bus contains anti-modulation circuit part of de6038 chip-set (wl600c, wl102) the wl800 is a low power single chip frequency synthesiser. the circuit is fabricated on zarlink semiconductor hg process and operates from a supply voltage of 2.7 - 3.6v. it is designed to work with the zarlink semiconductor wl600c rf and if circuit and the wl102 wlan controller chip which together make up the de6038 frequency hopping wireless local area network (wlan) transceiver. related documents wl600c, wl102 datasheets tqfp 32 figure 1 - pin connections - top view pin 1 ident absolute maximum ratings supply voltage vcc 4vdc transmit/receive and -0.5vdc to vcc +0.5vdc standby input prescaler inputs pins 30 &31 no dc. externally capacitively coupled. output current (any output) tbd ma junction temperature tj 150 c esd protection: 2kv operating temperature -20 to +85 c wl800 2.5ghz frequency synthesiser preliminary information ds4583 issue 1.6 october 1997 ordering information wl800/kg/tp1r
2 wl800 preliminary information pin reference type description 1 vcc1 vcc power for serial data bus 2 cs-data in channel data in (synth programming) 3 cs-clk in data clock (synth programming) 4 cs-loadb in data enable (synth programming) 5 stdbyb in power down control active = logic 1 standby = logic 0 6 vee1 gnd ground connection 7 iset set modulation current 8 icp set charge pump current 9 vee3 gnd ground connection 10 txd in modulation data in 11 com cap compensation capacitor for modulation data 12 rcomp out resistor for v/i converter 13 idout out modulation data out 14 txrxb in transmit/receive control transmit = logic 1 receive = logic 0 15 varicap out control v to varicap in vco 16 vcc3 vcc power for charge pump and loop amplifier and modulator 17 loopfilter out loop filter out (loop filter components) 18 cpumpref charge pump reference voltage 19 cpumpout out charge pump out (loop filter components) 20 vee2 gnd ground connection 21 sysclk out reference (system) clock out 22 xtal crystal connection (differential) 23 xtalb crystal connection (differential) 24 vcc2 vcc power for reference oscillator 25 fref out reference frequency monitor 26 lkcap lock detect capacitor 27 lckdetb out lock detect output 28 fv out vco frequency / (nm+a) monitor 29 vee5 gnd ground connection 30 vcc vcc power for prescaler, am counter ref divider, phase detector and lock detector 31 vcoipb in prescaler in- 32 vcoip in prescaler in+ device pin out
3 wl800 preliminary information pre-scaler a counter phase det & charge pump input register m counter reference osc divide by 20 ref out buffer lock detect pre amp data buffer 1,16,24,30 vcc 6,9,20,29 vee standby 5 14 txrxb data 2 clk 3 enableb 4 vcoip 32 vcoipb 31 din 10 idout 13 iset 7 21 ref out 23 xtal1 22 xtal2 lkcap 26 lkdetb 27 cpump ref 18 varicap 15 loop filter 17 cpump out 19 mod comp comp 11 icp 8 fref 25 28 fv 12 rcomp vcap charge cap buffer 1/3 sysclk stdbyb lckdetb compcap txd cs-data cs-clk cs-loadb b figure 1 - wl800 block diagram xtalb
4 wl800 preliminary information electrical characteristics these characteristics are guaranteed over the following conditions (unless otherwise stated): t amb = -20 c, to +85 c, vcc = 2.7v to 3.6v characteristic value unit condition min typ max supply current (total) transmit 37 50 ma receive 35 50 ma supply current in standby 3 5 ma programming inputs logic low voltage 0 0.4 v logic high voltage 0.8vcc vcc v input current 1 a input level high data clock frequency (1/tclock) 20 mhz see fig. 2 data/enable set up time (t set up) 10 ns see fig. 2 enable hold time (t enable) 10 ns see fig. 2 positive clock pulse width (tp) 20 ns see fig. 2 negative clock pulse width (t neg) 20 ns see fig. 2 standby input logic low input voltage 0 0.8 v circuit powered down logic high input voltage vcc -0.7 vcc v circuit powered up input current 100 150 a circuit powered up -150 a circuit powered down standby to operate time 3 s *references operational (see note 1) tx/rx input logic low input voltage 0 0.8 v receive mode logic high input voltage vcc -0.7 vcc v transmit mode input current 10 a reference output reference output frequency 20 mhz with 20mhz crystal reference clock output voltage 200 250 300 mvp-p with 15pf load reference output impedance 600 ohms mark space ratio -2% 50/50 +2% with 15pf load rise time 15 ns fall time 15 ns crystal drive levels required 200 mv pins 22,23 differential
5 wl800 preliminary information electrical characteristics (continued) these characteristics are guaranteed over the following conditions (unless otherwise stated): t amb = -20 c, to +85 c, vcc = 2.7v to 3.6v characteristic value unit condition min typ max lock detect circuit smoothing capacitor charge/ 80 110 150 a determined by application. discharge current threshold voltage vcc-0.3 v on smoothing capacitor output high voltage 1.8 vcc v i out = 10 a output low voltage vee 0.5 v i out = 0 a phase detector and charge pump comparison frequency 1 mhz divided crystal reference charge pump output current 1 ma rpin 8 = 10k up down current matching 5 % reference voltage v cc -1.05 v cc -0.7 v charge pump op-amp first stage: high output voltage 2.4 v low output voltage 0.3 v second stage: filter drive amplifier output current 1ma filter drive amp output swing 0.77 vp-p prescaler input drive voltage 40 200 mv rms maximum operating frequency 3 ghz input impedance 330 ? 0.5pf transmit data input logic low -60 -100 a rsource=20k logic high +60 +100 a tx data out logic 0 output current 25 50 100 a set by external resistor on pin 7 logic 1 output current 200 na leakage current output current in receive mode 25 a equal to 0.5 mod current
6 wl800 preliminary information electrical characteristics (continued) these characteristics are guaranteed over the following conditions (unless otherwise stated): t amb = -20 c, to +85 c, vcc = 2.7v to 3.6v characteristic value unit condition min typ max mod. current input mod current set pin current 25 a set by external resistor on pin 7. r = 47k compensation cap pin compensation current -25 a set by external resistor on pin 7. r=47k. compensation current matching 2 % compensation capacitor 8.2nf compensation capacitor voltage cpref - cpref cpref v receive mode 0.02 +0.02 compensation capacitor voltage 88 98 +110 mv 1 mhz data, 32bits ? -120 -98 -88 mv 1 mhz data, 32bits ? vcap charge settling time 100 s receive mode charging current 20 ma receive mode. vcap initially at 0 v. offset voltage 15 mv receive mode. compensation vto i (capbuffer+rcomp) compensation current into loop +52.08 na per 1us of databit 0 filter -52.08 na per 1us of databit 1 max. compensation current 1.666 ma for 32 bits(1) at 1mhz capacitor buffer offset voltage 15 mv external resistor rcomp 58000 ohms note: 1. standby to operate time refers to the time for internal current references to become operational.
7 wl800 preliminary information functional description reference frequency the reference frequency is generated using a 20mhz crystal in conjunction with an on chip oscillator maintaining circuit. a buffer circuit provides a low level voltage output signal at the crystal frequency to drive the logic in the protocol and control chip. the crystal frequency is divided by 20 to provide the reference signal to the phase comparator. counters / dividers an external oscillator is used to feed the input of the preamplifier in the synthesiser, (this isolates the counters from the oscillator and reduces the level of drive signal required by the synthesiser). the output of the preamplifier drives a dual modulus prescaler with ratios of 48/49, which in turn then drives the standard a-m counter arrangement. the a counter then provides the modulus control signal back to the prescaler. the counter system has an overall division ratio given by the formula mn+a where n is the lower divide ratio of the prescaler (48). the divide ratio of the m and a counters is programmable to allow the oscillator to be tuned over the required frequency range of 144 channels at 1mhz spacing. the m count ratio can be programmed over the range 49 to 52 and the a counter from 1 to 48 giving a total divide ratio from 2353 to 2544 which is greater than necessary to tune the required frequency range. programming the programming data for the synthesiser is entered via a three wire serial data bus consisting of enable, clock and data signals. the enable signal is taken low at the start of the program- ming sequence and remains low for the duration of the 8 serial data bits. a positive clock edge is required to strobe each data bit into the input register. when all 8 data bits are entered, the enable pin is taken high forcing the counters to zero and preloading the new count data when the counter is next clocked . the charge pump is disabled for a short period after the enable pin goes low to prevent glitch energy being trans- ferred to the vco. phase detectors a conventional digital phase frequency detector incorpo- rating dead band suppression is used in conjunction with a charge pump to steer the vco. an internal op-amp maintains the charge pump pin at the same voltage as the charge pump reference by virtual earth principles. the op-amp is split into two parts with the first section having a relatively low current drive capability but including the high gain stages of the amplifier. the second stage has a controlled voltage gain of 1/3 but high input impedance and low output impedance. this minimises loading to the high output impedance of the first stage and provides sufficient drive current via the loop filter to maintain virtual earth at the charge pump output. the output from the first stage is designed to swing close to the positive and negative rails so as to provide maximum voltage swing to the varactor controlling the vco. a compensating capacitor can be connected to this point to stabilise the amplifier. a lock detect output (active low) is provided to give an indication to the controller that the phase locked loop is locked, preventing transmission on illegal frequencies. antimodulation the wl800 contains a data buffer circuit which accepts transmit data from the cmos controller circuit and converts the cmos input to a tristate current output for driving the transmit spectrum shaping filter. the buffer gives zero current for a logic ??input, a high current (+2i) for a logic ??and a current midway between the two (+i) for use during the transmit amplifier power up/down period and during receive. this function prevents the synthesiser centring its frequency on either a logic ??or ??and removes the possibility of over- modulation at the start of a transmission. the amplitude of the output current and therefore modulation index of the radio is controlled by an external resistor connected to ground. a data compensation path is included which counteracts the tendency of the pll to drift back to centre frequency when the data is non-white. this is achieved by charging an external capacitor with a current +i when data is low, and discharging it by a current -i when data is high. the capacitor voltage, which then represents an integrated form of the data is converted to a current via a buffer and an external resistor (rcomp), and fed into the loop filter in addition to the phase detector output. during receive mode, the capacitor is charged to the charge pump reference voltage.
8 wl800 preliminary information wl800 programming frequency a counter m counter 6 bit binary a bit binary m mhz value value value d0-d5 value d6-d7 2357 5 49 101000 00 2358 6 49 011000 00 2400 48 49 000011 00 2401 1 50 100000 10 2448 48 50 000011 10 2449 1 51 100000 01 2496 48 51 000011 01 2497 1 52 100000 11 2498 2 52 010000 11 2499 3 52 110000 11 2500 4 52 001000 11 notes: 1.the binary data is in reverse order. 2.the data is programmed with bit d7 first and d0 last d0 d1 d2 d3 d4 d5 d6 d7 a counter m counter data clock data enable t set up t enable t clock tp t neg timing diagram figure 2 - timing diagram cs_loadb cs_data cs_clk
9 wl800 preliminary information control signals control line logic ? logic ? stdbyb standby active txrxb receive transmit lckdetb locked unlocked

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