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preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 1 revision 0.5 *- sn8p1700a series user?s manual preliminary sn8p1702a sn8p1703a s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improve reliability, function or desig n. sonix does not assume any liability arising out of the application or use of an y product or circuit described her ein; neither does it convey a ny license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems inten ded, for surgical implant into the body, or other applications intended to suppor t or sustain life, or for any other application in which the fai lure of the sonix product could create a situation where personal injury or death may occu r. should buyer purchase or use sonix products for any such uni ntended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subs idiaries, affiliates and distri butors harmless against all claims, cost, damages, and expenses, and re asonable attorney fees arising out of, dire ctly or indirectly, any claim of pers onal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 2 revision 0.5 amendment history version date description ver 0.1 jul. 2003 v1.0 preliminary version ver 0.2 jul. 2003 change watchdog overflow table ver 0.3 jul. 2003 aug. 2003 1. modify selection table 2. dc current chars. change 3. feature change 4. change sn8p1703 part number to sn8p1703a 5. code option table has been relocated after pin description section. 6. modify qtp approval sheet 7. change register description. 8. add lvd typical value=1.8v in elec. char. 9. add ?noise filter? code option ver 0.4 sep. 2003 1. add sn8p1702a ssop20 for mask mass production. 2. add tc1 timer in update table. 3. modify chap. 8 table/figure no. 4. modify tc0/tc1 timer description and table. 5. modify pwm description and table. 6. modify electrical characteristic table ver 0.5 sep. 2003 1. modify adc convert time table 2. modify the description of pedge register. 3. modify the description of intrq register. 3. remove approval sheet. 4. separate the pin description se ction of sn8p1702a and sn8p1703a. 5. remove pcb layout section 6. add p-dip 20 and sop 20 package information. 7. add sn8a1702b and sn8a1703a related description.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 3 revision 0.5 table of contents amendment history .............................................................................................................. 2 1 1 1 product o verview ..................................................................................................... 8 general des cription ........................................................................................................... 8 features selecti on table ................................................................................................. 8 mask/otp r elative t able .......................................................................................................... 8 adc grade table ................................................................................................................ .... 8 upgrade from sn8p1702 (o ld version otp) ....................................................................... 9 sn8p1702a/sn8p1703a features ....................................................................................... 10 system block diagra m ...................................................................................................... 11 pin assign ment ................................................................................................................. .... 12 sn8p1702a pin assignment................................................................................................... 12 sn8p1703a pin assignment................................................................................................... 14 pin descri ptions ............................................................................................................... ... 15 pin circuit diagra ms .......................................................................................................... 1 5 2 2 2 code option table ................................................................................................... 16 3 3 3 address spa ces ........................................................................................................ 17 program memory (rom)..................................................................................................... 17 overview ....................................................................................................................... ...... 17 user reset vector address ( 0000h) ......................................................................... 18 interrupt vector a ddress ( 0008h) ............................................................................ 18 checksum cal culation.................................................................................................. 20 general purpose progr am memory area ............................................................. 21 lookup table description............................................................................................ 21 jump table de scription................................................................................................. 23 data memory (ram) .............................................................................................................. 25
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 4 revision 0.5 overview ....................................................................................................................... ...... 25 working re gisters............................................................................................................. 2 6 y, z regi sters ................................................................................................................. ... 26 r regis ters .................................................................................................................... .... 27 program flag ................................................................................................................... .... 27 carry flag ..................................................................................................................... .... 27 decimal carr y flag ......................................................................................................... 27 zero flag ...................................................................................................................... ...... 27 accumula tor .................................................................................................................... .... 28 stack oper ations............................................................................................................... .29 overview ....................................................................................................................... ...... 29 stack regis ters............................................................................................................... 3 0 stack operation example ............................................................................................ 31 program co unter ............................................................................................................... 3 2 one address skipping .................................................................................................... 33 multi-address jumping .................................................................................................. 34 4 4 4 addressing mode...................................................................................................... 35 overview....................................................................................................................... .......... 35 immediate addres sing mode ........................................................................................ 35 directly addr essing mo de .......................................................................................... 35 indirectly addr essing mode....................................................................................... 35 to access data in ram ban k 0....................................................................................... 36 5 5 5 system regis ter ....................................................................................................... 37 overview....................................................................................................................... .......... 37 system register arrang ement (ban k 0) ..................................................................... 37 bytes of system registe r.............................................................................................. 37 bits of system register ................................................................................................. 38 6 6 6 power on reset ........................................................................................................ 39
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 5 revision 0.5 overview....................................................................................................................... .......... 39 external reset description........................................................................................... 40 7 7 7 oscillato rs................................................................................................................ 42 overview....................................................................................................................... .......... 42 clock block diagra m ..................................................................................................... 42 oscm register description ......................................................................................... 43 external high-speed oscilla tor............................................................................... 44 oscillator mode code op tion .................................................................................... 44 oscillator devide by 2 code op tion......................................................................... 44 oscillator safe gua rd code op tion ....................................................................... 44 system oscillato r circuit s ........................................................................................ 45 external rc oscillato r frequency meas urement .................................................................... 46 internal low-speed oscillator .................................................................................... 47 system mode d escriptio n ................................................................................................ 48 overview ....................................................................................................................... ...... 48 normal mode .................................................................................................................... .48 slow mode ...................................................................................................................... .... 48 green mode..................................................................................................................... ... 48 power down mode........................................................................................................... 48 system mode contro l ....................................................................................................... 49 system mode bloc k diagra m ....................................................................................... 49 system mode switchi ng ................................................................................................ 50 wakeup time.................................................................................................................... ....... 51 overview ....................................................................................................................... ...... 51 hardware wakeup ........................................................................................................... 51 external wakeup tr igger cont rol ......................................................................... 52 8 8 8 timers co unters ....................................................................................................... 53 watchdog time r (wdt ) ....................................................................................................... 53 t0m r egister ............................................................................................................................. 54 timer counter 0 (tc0 ) ......................................................................................................... 5 5 overview ....................................................................................................................... ...... 55 tc0m mode registe r........................................................................................................ 56
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 6 revision 0.5 tc0c counting register................................................................................................ 57 tc0 overfl ow time .............................................................................................................. ... 57 tc0r auto-loa d registe r.............................................................................................. 60 tc0 timer counter o peration se quence................................................................ 61 tc0 clock frequency output (b uzzer) ................................................................... 63 tc0out freque ncy tabl e.................................................................................................. 64 timer counter 1 (tc1 ) ......................................................................................................... 6 6 overview ....................................................................................................................... ...... 66 tc1m mode registe r........................................................................................................ 67 tc1c counting register................................................................................................ 68 tc1 overfl ow time .............................................................................................................. ... 68 tc1r auto-loa d registe r.............................................................................................. 71 tc1 timer counter o peration se quence................................................................ 72 tc1 clock frequency output (b uzzer) ................................................................... 74 pwm function de scriptio n .............................................................................................. 75 overview ....................................................................................................................... ...... 75 pwm program d escriptio n........................................................................................... 78 9 9 9 interrup t..................................................................................................................... 7 9 overview....................................................................................................................... .......... 79 inten interrupt en able regis ter ................................................................................. 80 intrq interrupt re quest regis ter.............................................................................. 80 interrupt operation descri ption ................................................................................ 81 gie global inter rupt oper ation ............................................................................... 81 int0 (p0.0) inte rrupt oper ation .................................................................................. 82 tc0 interrupt operation .............................................................................................. 83 tc1 interrupt operation .............................................................................................. 84 multi-interrupt operation.......................................................................................... 85 1 1 1 0 0 0 i/o po rt............................................................................................................... 87 overview....................................................................................................................... .......... 87 i/o port funct ion table .................................................................................................... 88 pull-up r esister s.............................................................................................................. .. 89 i/o port data registe r ...................................................................................................... 92
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 7 revision 0.5 1 1 1 1 1 1 4-channel analog to di gital conv erter............................................. 94 overview....................................................................................................................... .......... 94 adm regis ter................................................................................................................... ...... 95 adr regis ters.................................................................................................................. ..... 95 adb regis ters.................................................................................................................. ..... 96 p4con re giste rs ................................................................................................................ .. 97 adc converti ng time .......................................................................................................... 98 adc ci rcuit.................................................................................................................... ......... 99 1 1 1 2 2 2 coding i ssue .................................................................................................. 100 template code.................................................................................................................. .. 100 program check list ......................................................................................................... 104 1 1 1 3 3 3 instruction set table ............................................................................... 105 1 1 1 4 4 4 electrical char acteristi c ..................................................................... 106 absolute maximu m rating .............................................................................................. 106 standard electrical characteris tic....................................................................... 106 1 1 1 5 5 5 package info rmation ................................................................................ 107 p-dip18 pin .................................................................................................................... ......... 107 sop18 pin ...................................................................................................................... ......... 108 p-dip 20 pin ................................................................................................................... ......... 109 sop 20 pin ..................................................................................................................... ......... 110 ssop20 pin ..................................................................................................................... ........ 111
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 8 revision 0.5 1 1 1 product overview general description the sn8p1702a/sn8p1703a is a series of 8-bit micro-controller. this chip is utilized with cmos technology fabrication and featured with low po wer consumption and high performance by its unique electronic structure. this chip is designed with the excellent ic structure in cluding the large program memory otp rom, the massive data memory ram, two 8-bit timer counters (tc0, tc1), a watchd og timer, three interrupt so urces (tc0, tc1, int0), an 4-channel adc converter with 8-bit/12-bit resolution, two channels high speed pwm output (pwm0, pwm1), two channels buzzer output (bz0, bz1) and 8-level stack buffers. besides, the user can choose de sired oscillator configurations for the controller. there are four oscillator configurations to select for generating system clock, including high/low speed crystal, cera mic resonator or cost-saving rc. this series also includes an internal rc osci llator for slow mode controlled by programming. features selection table timer pwm wakeup chip rom ram stack t0 tc0 tc1 i/o avref adc buzzer pin no. package sn8p1702a 1k*16 128 - v v 12 - 4ch 2 3 dip18/sop18/ssop20 sn8p1703a 1k*16 128 8 - v v 13 v 4ch 2 3 dip20/sop20/ssop20 table 1-1. selection tabl e of sn8p1702a/sn8p1703a mask/otp relative table mask part number package form otp chip for verification assembler declaration sn8a1702a dip18/sop18 /ssop20 sn8p1702a chip sn8p1702a sn8a1702b dip18/sop18 /ssop20 sn8p1702a chip sn8p1702aotp sn8a1703a dip20/sop20 /ssop20 sn8p1703a chip sn8p1703a adc grade table chip parameter min max units resolution 12 bits no mission code 8 12 bits sn8p1702a sn8p1703a differential no linearity (dnl) 16 lsb resolution 12 bits no mission code 10 12 bits sn8p1702a-12 sn8p1703a-12 differential no linearity (dnl) 4 lsb table 1-2. adc grade table
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 9 revision 0.5 upgrade from sn8p1702 (old version otp) chip sn8p1702 sn8p1702a sn8p1702a sn8p1703a assembly declaration chip sn8p1702 chip sn8p1702a chip sn8p1702aotp chip sn8p1703a standby current (3v) 3ua < 1ua < 1ua < 1ua 4mhz operating (3v) 1. 5ma < 1ma < 1ma < 1ma 4mhz operating (5v) 7ma < 3ma < 3ma < 3ma green mode - yes yes yes p0.0 interrupt edge falling falling/rising/ both falling/rising/both falling/rising/both p1 wake up low level level change level change level change avrefh no only ssop20 only ssop20 yes adc channel 4 4 4 4 p4con register - - yes yes ram size 64 64 128 128 gpio 12 12 12 13 tc1 timer - - yes yes fast pwm - - yes yes pull-up resistor by port by port by pin by pin pull-up register @set_pur @set_pur pnur pnur sn8p1702 pin compatible yes yes yes no wdt clock source high clock high clock high clock internal rc high clock internal rc internal rc always on and wdt clock source fixed at internal rc - - yes yes power on delay at 4mhz/3v ~70ms ~200ms ~200ms ~200ms mask type sn8a1702a sn8a1702a sn8a1702b sn8a1703a package pdip18/sop18 pdip18/sop1 8/ssop20 pdip18/sop18/sso p20 pdip20/sop20/ssop20 notice: the sn8p1702 is not recommended for the new design.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 10 revision 0.5 sn8p1702a/sn8p1703a features ? memory configuration ? three interrupt sources otp rom size: 1k * 16 bits. two internal interrupts: tc0, tc1 ram size: 128 * 8 bits. one external interrupts: int0. ? i/o pin configuration ? an 4-channel 12-bit adc input only: p0 bi-directional: p1, p4, p5 ? two channel high speed pwm output. wakeup: p0, p1 ? two channel buzzer output. (bz0/bz1) pull-up resisters: p0, p1, p4, p5 external interrupt: p0 ? dual clock system offers four operating modes p4 pins shared with adc inputs. external high clock: rc type up to 10 mhz external high clock: crystal type up to 16 mhz ? two 8-bit timer counters. (tc0, tc1). internal low clock: rc type 16khz(3v), 32khz(5v) ? on chip watchdog timer. normal mode: both high and internal low clock active ? eight levels stack buffer. slow mode: internal low clock only green mode: periodical wake-up by timer sleep mode: both high and internal low clock stop ? 59 powerful instructions four clocks per instruction cycle all of instructions are one word length. ? package (chip form support) most of instructions are one cycle only . sn8p1702a -- pdip 18 / sop 18 / ssop20 all rom area lookup table function (movc) sn8p1703a-- pdip 20 / sop 20 / ssop20
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 11 revision 0.5 system block diagram figure 1-1.simplified system block diagram pc ir otp rom h-osc timing generator ram syst em regist er alu acc interrupt co nt ro l timer & counter port 0 port 1 port 4 port 5 fla gs adc ain0~ain3 internal clk pwm0 pwm0/buzzer0 l o w vo lt detector watch-dog timer pwm1 pwm1/buzzer1
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 12 revision 0.5 pin assignment format description ?g sn8p170xay y = p > pdip ?a s > sop ?a x> ssop sn8p1702a pin assignment otp type: sn8p1702as (sop 18pin) / sn8p1702ap (pdip 18pin) pin compatible to the mask ve rsion (sn8a1702as/sn8a1702ap) p0.0/int0 1 u 18 vdd rst 2 17 xin p1.1 3 16 xout p1.0 4 15 p5.0 vss 5 14 p5.1 p4.3/ain3 6 13 p5.2 p4.2/ain2 7 12 p5.3/bz1/pwm1 p4.1/ain1 8 11 p5.4/bz0/pwm0 p4.0/ain0 9 10 vdd sn8p1702ap sn8p1702as sn8p1702ax (ssop 20pin) pin compatible to the mask version (sn8a1702ax) vss 1 u 20 p1.0 vss 2 19 p1.1 p4.3/ain2 3 18 rst p4.2/ain1 4 17 p0.0/int0 p4.1/ain1 5 16 vdd p4.0/ain0 6 15 xin avrefh 7 14 xout vdd 8 13 p5.0 p5.3/bz1/pwm1 9 12 p5.1 p5.2 10 11 p5.4/bz0/pwm0 sn8p1702ax old version otp type: sn8p1702s (sop 18pin) / sn8p1702p (pdip 18pin) p0.0/int0 1 u 18 vdd/vpp rst 2 17 xin p1.1 3 16 xout p1.0 4 15 p5.0 vss 5 14 p5.1 p4.3/ain3 6 13 p5.2 p4.2/ain2 7 12 p5.3/bz1/pwm1 p4.1/ain1 8 11 p5.4/bz0/pwm0 p4.0/ain0 9 10 vdd sn8p1702p sn8p1702s notice: the sn8p1702 is not recommended for the new design.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 13 revision 0.5 mask type: sn8a1702as (sop 18pin) / sn8a1702ap (pdip 18pin) SN8A1702BS (sop 18pin) / sn8a1702bp (pdip 18pin) p0.0/int0 1 u 18 vdd rst 2 17 xin p1.1 3 16 xout p1.0 4 15 p5.0 vss 5 14 p5.1 p4.3/ain3 6 13 p5.2 p4.2/ain2 7 12 p5.3 p4.1/ain1 8 11 p5.4/bz0/pwm0 p4.0/ain0 9 10 vdd sn8a1702ap sn8a1702as sn8a1702bp SN8A1702BS sn8a1702ax (ssop 20pin) vss 1 u 20 p1.0 vss 2 19 p1.1 p4.3/ain2 3 18 rst p4.2/ain1 4 17 p0.0/int0 p4.1/ain1 5 16 vdd p4.0/ain0 6 15 xin avrefh 7 14 xout vdd 8 13 p5.0 p5.3 9 12 p5.1 p5.2 10 11 p5.4/bz0/pwm0 sn8a1702ax sn8a1702bx
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 14 revision 0.5 sn8p1703a pin assignment otp type: sn8p1703as (sop 20pin) / sn8p1703ap (pdip 20pin) / sn8p1703ax (ssop 20pin) p0.0/int0 1 u 20 vdd rst 2 19 xin p1.1 3 18 xout p1.0 4 17 p5.0 vss 5 16 p5.1 p4.3/ain3 6 15 p5.2 p4.2/ain2 7 14 p5.3/bz1/pwm1 p4.1/ain1 8 13 p5.4/bz0/pwm0 p4.0/ain0 9 12 p5.5 avrefh 10 11 vdd sn8p1703ap sn8p1703as sn8p1703ax mask type: sn8a1703as (sop 20pin) / sn8a1703ap (pdip 20pin) / sn8a1703ax (ssop 20pin) p0.0/int0 1 u 20 vdd rst 2 19 xin p1.1 3 18 xout p1.0 4 17 p5.0 vss 5 16 p5.1 p4.3/ain3 6 15 p5.2 p4.2/ain2 7 14 p5.3/bz1/pwm1 p4.1/ain1 8 13 p5.4/bz0/pwm0 p4.0/ain0 9 12 p5.5 avrefh 10 11 vdd sn8a1703ap sn8a1703as sn8a1703ax
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 15 revision 0.5 pin descriptions pin name type description vdd, vss p power supply input pins for digital circuit. rst i system reset input pin. schmitt trigger stru cture, active ?low?, normal stay to ?high?. xin, xout i, o external oscillator pins. rc mode from xin. p0.0 / int0 i port 0.0 and shared with int0 trig ger pin (schmitt trigger) / built-in pull-up resisters. p1.0 ~ p1.1 i/o port 1.0~port 1.1 bi-d irection pins / built-in pull-up resisters. p4.0 ~ p4.3 i/o port 4.0~port 4.3 bi-d irection pins / built-in pull-up resisters. p5.0~p5.2, p5.5 i/o port 5.0~port 5.2, p5.5 bi-direction pins / built-in pull-up resisters. p5.3 / bz1 / pwm1 i/o port 5.3 bi-direction pin, tc12 signal out put pin for buzzer or pwm1 output pin. built-in pull-up resisters. p5.4 / bz0 / pwm0 i/o port 5.4 bi-direction pin, tc02 signal out put pin for buzzer or pwm0 output pin. built-in pull-up resisters. avrefh i a/d converter high analog reference voltage. ain0 ~ ain3 i analog signal i nput pins for adc converter. table 1-3. pin description pin circuit diagrams figure 1-2. pin circuit diagram note: all of the latch output circuits are push-pull structures. port0 structure pur pin int. bus pur pnm pin int. bus pnm lat ch port1, 4, 5 structure pnm port0 structure pur pin int. bus pur pnm pin int. bus pnm lat ch port1, 4, 5 structure pnm
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 16 revision 0.5 2 2 2 code option table code option content function description rc low cost rc for external high clock oscillator 32k x?tal low frequency, power saving crystal (e.g. 32.768k) for external high clock oscillator 12m x?tal high speed crystal /resonator (e.g. 12m) for external high clock oscillator high_clk 4m x?tal standard crystal /resonator (e.g. 3.58m) for external high clock oscillator enable external high clock divided by two, fosc = high clock / 2 high_clk / 2 disable fosc = high clock enable enable oscillator safe guard function osg disable disable oscillator safe guard function enable enable watch dog function watch_dog disable disable watch dog function enable enable rom code security function security disable disable rom code security function 8-bit tc0 as 8-bit counter. 6-bit tc0 as 6-bit counter. 5-bit tc0 as 5-bit counter. tc0_counter 4-bit tc0 as 4-bit counter. 8-bit tc1 as 8-bit counter. 6-bit tc1 as 6-bit counter. 5-bit tc1 as 5-bit counter. tc1_counter 4-bit tc1 as 4-bit counter. enable enable noise filter function to enhance emi performance noise filter disable disable noise filter function enable enable low power function to save operating current low power disable disable low power function always on force watch dog timer clock source come from int 16k rc. also int 16k rc never stop both in power down and green mode that means watch dog timer will always enable both in power down and green mode. int_16k_rc by_cpum enable or disable internal 16k (at 3v) rc clock by cpum register table 2-1. code option ta ble of sn8p1702a/sn8p1703a notice: in high noisy environment, enable ?noise filter?, ?osg? and disable ?low power? is strongly recommended. the side effect is to increase the lowest valid working voltage level if enable ?noise filter? or ?osg? or ?low power? code option. enable ?low power? option will reduce operati ng current except in 32k x?tal or slow mode. if users select ?32k x?tal? in ?high_clk? option, assembler will force ?osg? to be enabled. if users select ?rc? in ?high_clk? option, assembler will force ?high_clk / 2? to be enabled.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 17 revision 0.5 3 3 3 address spaces program memory (rom) overview rom maps for sn8p1702a/sn8p1703a devices provide 1k x 16-bit program memory. the sn8p1702a/sn8p1703a program memory is able to fetch instructions through 12-bi t wide pc (program counter) and can look up rom data by using rom code registers (r, x, y, z). in standard configur ation, the device?s 1,024 x 16-bit program memory has four areas: 1-word reset vector addresses 1-word interrupt vector addresses 5-words reserved area 1k words (sn8p1702) all of the program memory is partitioned into three coding areas. the first area is located from 00h to 03h(the reset vector area), the second area is a reserved area 04h ~07h, t he third area is for the inte rrupt vector and the user code area from 0008h to 03feh. the address 08h is the interrupt enter address point. rom 0000h reset vector user reset vector 0001h jump to user start address 0002h jump to user start address 0003h general purpose area jump to user start address 0004h 0005h 0006h 0007h reserved 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . 03feh general purpose area end of user program 03ffh reserved figure 3-1. rom address structure
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 18 revision 0.5 user reset vector address (0000h) a 1-word vector address area is used to execute system rese t. after power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h an d all system registers will be set as default values. the following example shows the way to define the reset vector in the program memory. example: after power on reset, external reset active or reset by watchdog timer overflow. chip sn8p1702a org 0 ; 0000h jmp start ; jump to user program address. . ; 0001h ~ 0007h are reserved org 10h start: ; 0010h, the head of user program. . ; user program . . . endp ; end of program interrupt vector address (0008h) a 1-word vector address area is used to execute interrupt re quest. if any interrupt servic e is executed, the program counter (pc) value is stored in stack buffer and points to 0008h of program memory to execute the vectored interrupt. users have to define the interr upt vector. the following example shows the wa y to define the interrupt vector in the program memory. example 1: this demo program includes interrupt service routine and the user program is behind the interrupt service routine. chip sn8p1702a org 0 ; 0000h jmp start ; jump to user program address. . ; 0001h ~ 0007h are reserved org 8 ; interrupt service routine b0xch a, accbuf ; b0xch doesn?t change c, z flag b0mov a, pflag b0mov pflagbuf, a ; save pflag register in a buffer . . . b0mov a, pflagbuf b0mov pflag, a ; restore pflag register from buffer b0xch a, accbuf ; b0xch doesn?t change c, z flag reti ; end of interrupt service routine start: ; the head of user program. . ; user program . . . jmp start ; end of user program endp ; end of program
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 19 revision 0.5 example 2: the demo program includes interrupt service routine and the address of interrupt service routine is in a special address of general-purpose area. chip sn8p1702a org 0 ; 0000h jmp start ; jump to user program address. . ; 0001h ~ 0007h are reserved org 08 jmp my_irq ; 0008h, jump to interrupt service routine address org 10h start: ; 0010h, the head of user program. . ; user program . . . jmp start ; end of user program my_irq: ; the head of interrupt service routine b0xch a, accbuf ; b0xch doesn?t change c, z flag b0mov a, pflag b0mov pflagbuf, a ; save pflag register in a buffer . . . b0mov a, pflagbuf b0mov pflag, a ; restore pflag register from buffer b0xch a, accbuf ; b0xch doesn?t change c, z flag reti ; end of interrupt service routine endp ; end of program remark: it is easy to get the rules of sonix program from demo programs given above. these points are as following. 1. the address 0000h is a ?jmp? instruction to make the program go to general-purpose rom area. the 0004h~0007h are reserved. users have to skip 0004h~0007h addresses. it is very important and necessary. 2. the interrupt service starts from 0008h. users can put the whole interrupt service routine from 0008h (example1) or to put a ?jmp? instruction in 0008h then place the interrupt service routine in other general-purpose rom area (example2) to get more modularized coding style.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 20 revision 0.5 checksum calculation the rom addresses 0004h~0007h and last address are reserved area. user shoul d avoid these addresses (0004h~0007h and last address) w hen calculate the checksum value. example: the demo program shows how to avoid 0004h~0007h when calculated checksum from 00h to the end of user?s code mov a,#end_user_code$l b0mov end_addr1,a ; save low end address to end_addr1 mov a,#end_user_code$m b0mov end_addr2,a ; save middle end address to end_addr2 clr y ; set y to 00h clr z ; set z to 00h @@: call yz_check ; call function of check yz value movc ; b0bset fc ; clear c flag add data1,a ; add a to data1 mov a,r adc data2,a ; add r to data2 jmp end_check ; check if the yz address = the end of code aaa: incms z ;z=z+1 jmp @b ; if z! = 00h calculate to next address jmp y_add_1 ; if z=00h increase y end_check: mov a,end_addr1 cmprs a,z ; check if z = low end address jmp aaa ; if not jump to checksum calculate mov a,end_addr2 cmprs a,y ; if yes, check if y = middle end address jmp aaa ; if not jump to checksum calculate jmp checksum_end ; if yes checksum calculated is done. yz_check: ;check if yz=0004h mov a,#04h cmprs a,z ;check if z=04h ret ;if not return to checksum calculate mov a,#00h cmprs a,y ;if yes, check if y=00h ret ;if not return to checksum calculate incms z ;if yes, increase 4 to z incms z incms z incms z ret ;set yz=0008h then return y_add_1: incms y ;increase y nop jmp @b ;jump to checksum calculate checksum_end: ???. ???. end_user_code: ;label of program end
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 21 revision 0.5 general purpose prog ram memory area the 992-word at rom locations 0010h~0fefh are used as general-purpose memory. the area is stored instruction?s op-code and look-up table data. the sn8p 1702a/sn8p1703a includes jump table function by using program counter (pc) and look-up table function by usi ng rom code registers (r, x, y, z). the boundary of program memory is s eparated by the high-byte program counter (pch) every 100h. in jump table function and look-up table function, the program coun ter can?t leap over the boundary by program counter automatically. users need to modify the pch value to ?pch+1? as the pcl overflow (from 0ffh to 000h). lookup table description in the rom?s data lookup function, the x register is pointed to the highest 8-bit, y register to the middle 8-bit and z register to the lowest 8-bit data of ro m address. after movc instruction is ex ecuted, the low-byte data of rom then will be stored in acc and high-by te data stored in r register. example: to look up the rom data located ?table1?. b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low address. movc ; to lookup data, r = 00h, acc = 35h ; ; increment the index address for next address incms z ; z+1 jmp @f ; not overflow incms y ; z overflow (ffh 00), y=y+1 nop ; not overflow ; @@: movc ; to lookup data, r = 51h, acc = 05h. . . ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h ; ? dw 2012h ; ? causion: the y register can't increase automatical ly if z register cross boundary from 0xff to 0x00. therefore, user must take care such situation to avoid loop-up table errors. if z register overflow, y register must be added one. the following inc_yz macro shows a simple method to process y and z registers automatically. note: because the program counter (pc) is only 12-bit, the x register is useless in the application. users can omit ?b0mov x, #table1$h?. sonix ice support more larger program memory addressing capability. so make sure x register is ?0? to av oid unpredicted error in loop-up table operation. example: inc_yz macro inc_yz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 nop ; not overflow @@: endm
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 22 revision 0.5 the other coding style of loop-up table is to add y or z index register by accumulator. be careful if carry happen. refer following example for detailed information: example: increase y and z register by b0add/add instruction b0mov y, #table1$m ; to set lookup table?s middle address. b0mov z, #table1$l ; to set lookup table?s low address b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x0035 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012 . . . . ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h ; ? dw 2012h ; ?
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 23 revision 0.5 jump table description the jump table operation is one of multi-address jumpin g function. add low-byte program counter (pcl) and acc value to get one new pcl. the new program counter (pc) point s to a series jump instructions as a listing table. the way is easy to make a multi-stage program. when carry flag occurs after ex ecuting of ?add pcl, a?, it will not affect p ch register. users have to check if the jump table leaps over the rom page boundary or the listing file generated by sonix assembly software. if the jump table leaps over the rom page boundary (e.g. from xxffh to xx0 0h), move the jump table to the top of next program memory page (xx00h). here one page mean 256 words. example : if pc = 0323h (pch = 03h pcl = 23h) org 0x0100 ; the jump table is from the head of the rom boundary b0add pcl, a ; pcl = pcl + acc, the pch can?t be changed. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point in following example, the jump table starts at 0x00fd. wh en execute b0add pcl, a. if acc = 0 or 1, the jump table points to the right address. if the acc is larger then 1 will cause error because pch doesn't increase one automatically. we can see the pcl = 0 when acc = 2 but the pch still keep in 0. the program counter (pc) will point to a wrong address 0x0000 and crash system operation. it is important to check whether the jump table crosses over the boundary (xxffh to xx00h). a good coding style is to put the jump table at the start of rom boundary (e.g. 0100h). example: if ?jump table? crosses over rom boundary will cause errors. rom address . . . . . . 0x00fd b0add pcl, a ; pcl = pcl + ac c, the pch can?t be changed. 0x00fe jmp a0point ; acc = 0 0x00ff jmp a1point ; acc = 1 0x0100 jmp a2point ; acc = 2 jump table cross boundary here 0x0101 jmp a3point ; acc = 3 . . . . sonix provides a macro for safe jump table function. th is macro will check the rom boundary and move the jump table to the right position automatically . the side effect of this macro is maybe wasting some rom size. notice the maximum jump table number for this macro is limited fewer than 254. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif add pcl, a endm note: ?val? is the number of the jump table listing number.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 24 revision 0.5 example: ?@jmp_a? application in sonix macro file called ?macro3.h?. b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point jmp a4point ; acc = 4, jump to a4point if the jump table position is from 00fdh to 0101h, the ?@jmp_ a? macro will make the jump table to start from 0100h.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 25 revision 0.5 data memory (ram) overview the sn8p1702a/sn8p1703a has interna lly built-in the data memory up to 256 bytes for storing the general-purpose data. 128 * 8-bit general purpose area in bank 0 128 * 8-bit system special register area the memory is separated into bank 0 and bank 1. the user c an program ram bank selection bits of rbank register to access all data in any of the two ram banks. the ban k 0, using the first 128-byte location assigned as general-purpose area, and the remaining 128-byte in bank 0 as system register. ram location 000h 000h~07fh of bank 0 = to store general- ? purpose data (128 bytes). ? ? ? ? 07fh general purpose area 080h 080h~0ffh of bank 0 = to store system ? registers (128 bytes). ? ? ? ? system register bank 0 0ffh end of bank 0 area figure 3-2. ram location note: the undefined locations of system register area are logic ?high? after executing read instruction ?mov a, m?.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 26 revision 0.5 working registers the locations 82h to 84h of ram bank 0 in data memory stores the specially defined registers such as register r, z, y, respectively shown in the following table. these register s can use as the general purpose of working buffer and be used to access rom?s and ram?s data. for instance, all of the rom?s table can be looked-up with r, y and z registers. the data of ram memory can be i ndirectly accessed with y and z registers. 82h 83h 84h ram r z y r/w r/w r/w y, z registers the y and z registers are the 8-bit buffers. there are three ma jor functions of these registers. first, y and z registers can be used as working registers. second, these two regi sters can be used as data pointer s for @yz register. third, the registers can be address rom loca tion in order to look-up rom data. y initial value = 0000 0000 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w r/w r/w r/w r/w r/w r/w r/w z initial value = 0000 0000 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w r/w r/w r/w r/w r/w r/w r/w the @yz that is data point_1 index buffer located at addre ss e7h in ram bank 0. it employs y and z registers to addressing ram location in order to read/write data through a cc. the lower 4-bit of y register is pointed to ram bank number and z register is pointed to ram address number, respec tively. the higher 4-bit data of y register is truncated in ram indirectly access mode. example: if want to read a data from ram address 25h of bank 1, it can use indirectly addressing mode to access data as following. b0mov y, #01h ; to set ram bank 1 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc example: clear general-purpose data memory area of bank 1 using @yz register. mov a, #1 b0mov y, a ; y = 1, bank 1 mov a, #07fh b0mov z, a ; y = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; y ? 1, if y= 0, finish the routine jmp clr_yz_buf ; not zero clr @yz end_clr: ; end of clear general purpose data memory area of bank 0 note: please consult the ?look-up ta ble description? about y, z regi ster look-up table application.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 27 revision 0.5 r registers there are two major functions of the r register. first, r register can be used as working registers. second, the r registers can be store high-byte data of look-up rom data. after movc instruct ion executed, the high-byte data of a rom address will be stored in r register and the low-byte data stored in acc. r initial value = 0000 0000 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r/w r/w r/w r/w r/w r/w r/w note: please consult the ?look-up table description? about r regist er look-up table application. program flag the pflag includes carry flag (c), decimal carry flag (dc) and zero flag (z). if the result of operating is zero or there is carry, borrow occurrence, then these fl ags will be set to pflag register. pflag initial value = xxxx x000 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag - - - - - c dc z - - - - - r/w r/w r/w carry flag c = 1: if executed arithmetic addition with occurring carry si gnal or executed arithmetic subtraction without borrowing signal or executed rotation instruction with shifting out logic ?1?. c = 0: if executed arithmetic addition wit hout occurring carry signal or executed arithmetic subtract ion with borrowing signal or executed rotation instruction with shifting out logic ?0?. decimal carry flag dc = 1: if executed arithmetic addition with occurring carry signal from low ni bble or executed arit hmetic subtraction without borrow signal from high nibble. dc = 0: if executed arithmetic addition wit hout occurring carry signal from low ni bble or executed arithmetic subtraction with borrow signal from high nibble. zero flag z = 1: after operation, the content of acc is zero. z = 0: after operation, the c ontent of acc is not zero.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 28 revision 0.5 accumulator the acc is an 8-bits data register responsible for tran sferring or manipulating data between alu and data memory. if the result of operating is zero (z) or there is carry (c or dc) occurrence, then these flags will be set to pflag register. acc is not in data memory (ram), so acc can?t be acce ss by ?b0mov? instruction dur ing the instant addressing mode. example: read and write acc value. ; read acc data and store in buf data memory mov buf, a . . ; write a immediate data into acc mov a, #0fh . . ; write acc data from buf data memory mov a, buf . . the system doesn?t store acc and pf lag value as any interrupt service executed. acc must be exchanged to another data memory defined by users. t hus, once interrupt occurs, these data must be stored in the data memory based on the user?s program as follows. example: acc and working registers protection. accbuf equ 00h ; accbuf is acc data buffer in bank 0. int_service: b0xch a, accbuf ; b0xch doesn?t change c, z flag b0xch a, accbuf ; store acc value b0mov a, pflag ; store pflag value b0mov pflagbuf,a . b0mov a, pflagbuf ; re-load pflag value b0mov pflag,a b0xch a, accbuf ; re-load acc b0xch a, accbuf ; re-load acc reti ; exit interrupt service vector notice: to save and re-load acc data must be used ?b0xch? instruction, or the plage value maybe modified by acc.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 29 revision 0.5 stack operations overview the stack buffer of sn8p1702a/sn8p1703a has 8-level high ar ea and each level is 12-bits length. this buffer is designed to save and restore program counter?s (pc) data when interrupt service is executed. the stkp register is a pointer designed to point active level in order to save or restore data from stack buffer for kernel circuit. the stknh and stknl are the 12-bit stack buffers to store program counter (pc) data. figure 3-3 stack-save and stack-restore operation stack buffer stk7h stk6h stk5h stk4h stk3h stk2h stk1h stk0h stk7l stk6l stk5l stk4l stk3l stk2l stk1l stk0l stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp = 4 stkp = 5 stkp = 6 stkp = 7 stkp - 1 stkp + 1 call / interrupt ret / reti stkp pch pcl stkp stack buffer stk7h stk6h stk5h stk4h stk3h stk2h stk1h stk0h stk7l stk6l stk5l stk4l stk3l stk2l stk1l stk0l stk7h stk6h stk5h stk4h stk3h stk2h stk1h stk0h stk7l stk6l stk5l stk4l stk3l stk2l stk1l stk0l stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp = 4 stkp = 5 stkp = 6 stkp = 7 stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp = 4 stkp = 5 stkp = 6 stkp = 7 stkp - 1 stkp + 1 stkp - 1 stkp - 1 stkp + 1 call / interrupt ret / reti stkp stkp pch pcl pch pch pcl pcl stkp stkp
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 30 revision 0.5 stack registers the stack pointer (stkp) is a 4-bit regi ster to store the address used to access the stack buffer, 12-bits data memory (stknh and stknl) set aside for temp orary storage of stack addresses. the two stack operations are writing to the top of the stac k (stack-save) and reading (sta ck-restore) from the top of stack. stack-save operation decrement s the stkp and the stack-restore operat ion increments one time. that makes the stkp always points to the top address of stack buffer and writes the last progr am counter value (pc) into the stack buffer. the program counter (pc) value is stored in the stack bu ffer before a call instruction ex ecuted or during interrupt service routine. stack operation is a lifo type (last in and first out). the stack pointer (stkp) and stack buffer (stknh and stknl) are located in t he system register area bank 0. stkp (stack pointer) initial value = 0xxx 1111 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w - - - r/w r/w r/w r/w stkpbn: stack pointer. (n = 0 ~ 3) gie: global interrupt control bit. 0 = disable, 1 = enab le. more detail information is in interrupt chapter. example: stack pointer (stkp) reset routine. mov a, #00001111b b0mov stkp, a stkn (stack buffer) initial value = xxxx xxxx xxxx xxxx, stkn = stknh + stknl (n = 7 ~ 0) 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - - - - - snpc9 snpc8 - - - - - - r/w r/w 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 r/w r/w r/w r/w r/w r/w r/w r/w stknh: store pch data as interrupt or call executing. the n expressed 0 ~7. stknl: store pcl data as interrupt or call executing. the n expressed 0 ~7.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 31 revision 0.5 stack operation example the two kinds of stack-save operations to reference the st ack pointer (stkp) and write the program counter contents (pc) into the stack buffer are call inst ruction and interrupt service. under each condition, the stkp is decremented and points to the next available stack lo cation. the stack buffer stores the pr ogram counter about the op-code address. the stack-save operation is as following table. stkp register stack buffer stack level stkpb3 stkpb2 stkpb1 stkpb0 high byte low byte description 0 1 1 1 1 stk0h stk0l - 1 1 1 1 0 stk1h stk1l - 2 1 1 0 1 stk2h stk2l - 3 1 1 0 0 stk3h stk3l - 4 1 0 1 1 stk4h stk4l - 5 1 0 1 0 stk5h stk5l - 6 1 0 0 1 stk6h stk6l - 7 1 0 0 0 stk7h stk7l - >8 - - - - - - stack overflow table 3-1. stkp, stknh and stknl relative of stack-save operation the reti instruction is for interrupt service routine. t he ret instruction is for call in struction. when a stack-restore operation occurs, the stkp is incremented and points to the nex t free stack location. the stack buffer restores the last program counter (pc) to the program counter registers. the stack-restore operation is as following table. stkp register stack buffer stack level stkpb3 stkpb2 stkpb1 stkpb0 high byte low byte description 7 1 0 0 0 stk7h stk7l - 6 1 0 0 1 stk6h stk6l - 5 1 0 1 0 stk5h stk5l - 4 1 0 1 1 stk4h stk4l - 3 1 1 0 0 stk3h stk3l - 2 1 1 0 1 stk2h stk2l - 1 1 1 1 0 stk1h stk1l - 0 1 1 1 1 stk0h stk0l - table 3-2. stkp, stknh and stknl relative of stack-restore operation
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 32 revision 0.5 program counter the program counter (pc) is a 12-bit binary counter separat ed into the high-byte 4 bits and the low-byte 8 bits. this counter is responsible for pointing a location in order to fe tch an instruction for kernel circuit. normally, the program counter is automatically incremented with eac h instruction during program execution. besides, it can be replaced with specific address by execut ing call or jmp instruction. when jmp or call instruction is executed, the desti nation address will be inserted to bit 0 ~ bit 11. pc initial value = xxxx 0000 0000 0000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - - - - - 0 0 0 0 0 0 0 0 0 0 pch pcl pch initial value = xxxx 0000 0cfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pch - - - - - - pc9 pc8 - - - - - - r/w r/w pcl initial value = 0000 0000 0ceh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pcl pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w r/w r/w r/w r/w r/w r/w r/w
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 33 revision 0.5 one address skipping there are 9 instructions (cmprs, in cs, incms, decs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these instructions is matched, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is matched, the pc will add 2 steps to skip next instruction. b0bts1 fc ; skip next instruction, if carry flag = 1 jmp c0step ; else jump to c0step. . c0step: nop b0mov a, buf0 ; move buf0 value to acc. b0bts0 fz ; skip next instruction, if zero flag = 0. jmp c1step ; else jump to c1step. . c1step: nop if the acc is equal to the immediat e data or memory, the pc will add 2 steps to skip next instruction. cmprs a, #12h ; skip next instruction, if acc = 12h. jmp c0step ; else jump to c0step. . c0step: nop if the result after increasing or decreasing by 1 is 0xff or 0x00, the pc will add 2 step s to skip next instruction. incs instruction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. ? c0step: nop incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? c0step: nop decs instruction: decs buf0 jmp c0step ; jump to c0step if acc is not zero. ? c0step: nop decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? c0step: nop
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 34 revision 0.5 multi-address jumping users can jump round multi-address by either jmp instruction or add m, a instruction (m = pcl) to activate multi-address jumping function. if carry signal occurs after ex ecution of add pcl, a, the carry signal will not affect pch register. example: if pc = 0323h (pch = 03h pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h . . . . ; pc = 0328h . . mov a, #00h b0mov pcl, a ; jump to address 0300h example: if pc = 0323h (pch = 03h pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + ac c, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point . . ;
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 35 revision 0.5 4 4 4 addressing mode overview the sn8p1702a/sn8p1703a provides th ree addressing modes to access ram data, including immediate addressing mode, directly addressing mode and indirectly address mode. the main purpose of the three different modes is described in the following: immediate addressing mode the immediate addressing mode uses an immediate data to set up the location (mov a, #i, b0mov m,#i) in acc or specific ram. immediate addressing mode mov a, #12h ; to set an immediate data 12h into acc directly addressing mode the directly addressing mode uses address number to access memory location (mov a,12h, mov 12h,a). directly addressing mode b0mov a, 12h ; to get a content of location 12h of bank 0 and save in acc indirectly addressing mode the indirectly addressing mode is to set up an address in dat a pointer registers (y/z) and uses mov instruction to read/write data between acc and @yz r egister (mov a,@yz, mov @yz,a). example: indirectly addressing mode with @yz register clr y ; to clear y register to access ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 36 revision 0.5 to access data in ram bank 0 in the ram bank 0, this area memory can be read/written by these three access methods. example 1: to use ram bank0 dedicate instruction (such as b0xxx instruction). b0mov a, 12h ; to move content from location 12h of ram bank 0 to acc example 3: to use indirectly a ddressing mode with @yz register. clr y ; to clear y register for accessing ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 37 revision 0.5 5 5 5 system register overview the system special register is located at 80h~ffh. the main purpose of system registers is to control the peripheral hardware of the chip. using system r egisters can control i/o ports, sio, adc, pwm, timers and counters by programming. the memory map provides an easy and quick reference source for writing application program. to accessing these system registers is c ontrolled by the select memory bank (rbank = 0) or the bank 0 read/write instruction (b0mov, b0bset, b0bclr?). system register arrangement (bank 0) bytes of system register sn8p1702 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 - - r z y - pflag - - - - - - - - - 9 - - - - - - - - - - - - - - - - a - - - - - - - - - - - - - - p4con - b - adm adb adr - - - - - - - - - - - pedge c p1w p1m - - p4m p5m - - intrq inten oscm - - tc0r pcl pch d p0 p1 - - p4 p5 - - t0m - tc0m tc0c tc1m tc0c tc1r stkp e p0ur p1ur - - p4ur p5ur - @yz - - - - - - - - f stk7 stk7 stk6 stk6 stk5 stk5 stk4 stk4 stk3 stk3 st k2 stk2 stk1 stk1 stk0 stk0 table 5-1. system register arrangement description pflag = rom page and special flag register. r = working register and rom lookup data buffer. adb = adc?s data buffer. y, z = working, @yz and rom addressing register. pnm = port n input/output mode register . rbank = ram bank select register. intrq = interrupts? request register. adm = adc?s mode register. oscm = oscillator mode register. adr = adc?s resolution selects register. tc0/1m = timer/counter 0/1 mode register. p1w = port 1 wakeup register. tc0/1c = timer/counter 0/1 counting register. pn = port n data buffer. tc0/1r = timer/counter 0/1 auto-reload data buffer. pnur= pull-up register stkp = stack pointer buffer. inten = interrupts? enable register. @hl = ram hl indirect addressing index pointer. pch, pcl = program counter. stk0~stk7 = stack 0 ~ stack 7 buffer. @yz = ram yz indirect addressing index pointer. note: a). all of register names had been declared in sonix 8-bit mcu assembler. b). one-bit name had been declared in sonix 8-bit mcu assembler with ?f? prefix code. c). it will get logic ?h? data, when u se instruction to check empty location. d). the low nibble of adr register is read only. e). ?b0bset?, ?b0bclr?, ?bset?, ?bclr? in structions only support ?r/w? registers.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 38 revision 0.5 bits of system register address bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 r/w remarks 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 086h - - - - - c dc z r/w pflag 0aeh - - - - p4con3 p4con2 p4con1 p4con0 r/w p4con 0b1h adenb ads eoc gchs - - chs1 chs0 r/w adm mode register 0b2h adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r adb data buffer 0b3h - adcks1 adlen - adb3 adb2 adb1 adb0 r/w adr register 0bfh pedgen - - p00g1 p00g0 - - - r/w pedge 0c0h 0 0 0 0 0 0 p11w p10w w p1w wakeup register 0c1h 0 0 0 0 0 0 p11m p10m r/w p1m i/o direction 0c4h 0 0 0 0 p43m p42m p41m p40m r/w p4m i/o direction 0c5h 0 0 p55m p54m p53m p52m p51m p50m r/w p5m i/o direction 0c8h 0 tc1irq tc0irq 0 0 0 0 p00irq r/w intrq 0c9h 0 tc1ien tc0ien 0 0 0 0 p00ien r/w inten 0cah wtcks wdrst wdrate cpum1 cpum0 clkmd stphx 0 r/w oscm 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - - - - - pc9 pc8 r/w pch 0d0h - - - - - - - p00 r p0 data buffer 0d1h - - - - - - p11 p10 r/w p1 data buffer 0d4h - - - - p43 p42 p41 p40 r/w p4 data buffer 0d5h - - p55 p54 p53 p52 p51 p50 r/w p5 data buffer 0d8h - - - - tc1x8 tc0x8 tc0gn - r/w t0m 0dah tc0enb tc0rate2 tc0rat e1 tc0rate0 tc0cks aload0 tc0out pwm0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dch tc1enb tc1rate2 tc1rat e1 tc1rate0 0 aload1 tc1out pwm1out r/w tc1m 0ddh tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w tc1c 0deh tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 w tc1r 0dfh gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w stkp stack pointer 0e0h p00r r/w p0ur 0e1h p11r p10r r/w p1ur 0e4h p43r p42r p41r p40r r/w p4ur 0e5h p55r p54r p53r p52r p51r p50r r/w p5ur 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz index pointer 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h - - - - - - s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h - - - - - - s6pc9 s6pc8 r/w stk6h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - - - - - s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - - - - - s0pc9 s0pc8 r/w stk0h table 5-2. bit system register table note: a). to avoid system error, please be sure to put all the ?0? as it indicates in the above table b). all of register name had been declared in sonix 8-bit mcu assembler. c). one-bit name had been declared in sonix 8-bit mcu assembler with ?f? prefix code. d). ?b0bset?, ?b0bclr?, ?bset?, ?bclr? instructions only support ?r/w? registers.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 39 revision 0.5 6 6 6 power on reset overview this series provides two system resets. one is external re set and the other is low voltage detector (lvd). the external reset is a simple rc circuit connecting to the reset pin. t he low voltage detector (lvd) is built in internal circuit. when one of the reset devices occurs, the system will reset and the system registers become initial value. the timing diagram is as following. vdd external reset internal reset signal end of lvd reset lvd end of external reset lvd detect level external reset detect level figure 6-1 power on reset timing diagram
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 40 revision 0.5 external reset description the external reset is a low level active device. the rese t pin receives the low voltage and resets the system. when the voltage detects high level, it stops rese tting the system. users can use an exter nal reset circuit to control system operation. it is necessary that the vdd must be stable. external reset vdd internal reset signal external reset detect level end of external reset system reset figure 6-2 external reset timing diagram users must to be sure the vdd stable earlier than external rese t (figure 5-2) or the external reset will fail. the external reset circuit is a simple rc circuit as following. gnd vcc rst vdd mcu vss r 20k ohm c 0.1uf figure 6-3. external reset circuit
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 41 revision 0.5 in worse power, condition as brown out reset. the reset pin may keep high level but the vdd is low voltage. that makes the system reset fail and chip error. to connect a diode from reset pin to vdd is a good solution. the circuit can force the capacitor to release electric charge and drop the voltage, and solve the error. gnd vcc rst vdd mcu vss r 20k ohm c 0.1uf diode figure 6-4. external reset circuit with diode
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 42 revision 0.5 7 7 7 oscillators overview the sn8p1702a/sn8p1703a highly performs the dual clock micro-controller system. t he dual clocks are high-speed clock and low-speed clock. the high-spe ed clock frequency is supplied through the external oscillator circuit. the low-speed clock frequency is supplied th rough on-chip rc oscillator circuit. the external high-speed clock and the in ternal low-speed clock can be system clock (fosc). a nd the system clock is divided by 4 to be the instruction cycle (fcpu). fcpu = fosc / 4 the system clock is required by the following peripheral modules: timer counter 0 (tc0/tc1) watchdog timer ad converter pwm output (pwm0/pwm1) buzzer output (tc0out/tc1out) clock block diagram fl cpum0 lxosc. fcpu fosc/4 cpum0 fh hxosc. xin xout stphx hxrc cpum0 divided by 4 clkmd divided by 2 osg divided by 2 1 : disable 0 : enable osg : oscillator safe guard 1 : disable -- system default 0 : enable hxrc(1:0) is code option ?00= rc ?01 =32 khz oscillator ?10 = high speed oscillator (>10mhz) ?11 = standard oscillator (4mhz) fl cpum0 lxosc. fl cpum0 lxosc. fcpu fosc/4 cpum0 fcpu fosc/4 cpum0 fh hxosc. xin xout stphx hxrc cpum0 fh hxosc. xin xout stphx hxrc cpum0 divided by 4 clkmd divided by 4 divided by 4 clkmd divided by 2 divided by 2 osg osg divided by 2 1 : disable 0 : enable osg : oscillator safe guard 1 : disable -- system default 0 : enable hxrc(1:0) is code option ?00= rc ?01 =32 khz oscillator ?10 = high speed oscillator (>10mhz) ?11 = standard oscillator (4mhz) figure 7-1. clock block diagram hxosc: external high-speed clock. lxosc: internal low-speed clock. osg: oscillator safe guard.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 43 revision 0.5 oscm register description the oscm register is a oscillator control register. it can co ntrol oscillator select, system mode, watchdog timer clock source and rate. oscm initial value = 000x 000x 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst wdrate cpum1 cpum0 clkmd stphx 0 r/w r/w r/w r/ w r/w r/w r/w - bit1 stphx: external high-speed os cillator control bit. 0 = free run, 1 = stop. note: this bit only controls extern al high-speed oscillator. if stph x=1, the internal low-speed rc oscillator is still running. bit2 clkmd: system high/low speed mode select bit. 0 = normal (dual) mode, 1 = slow mode. bit[4:3] cpum[1:0] : cpu operating mode control bit. 00 = normal, 01 = sleep (power down) mode, 10 = green mode, 11 = reserved. bit5 wdrate: watchdog timer rate select bit. 0 = fcpu 2 14 1 = fcpu 2 8 (the detail information is in watchdog timer chapter.) bit6 wdrst: watchdog timer reset bit. 0 = non reset, 1 = clear the watchdog timer?s counter. (the detail information is in watchdog timer chapter.) bit7 wtcks: watchdog clock source select bit. 0 = fcpu, 1 = internal rc low clock.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 44 revision 0.5 external high-speed oscillator this series can be operated in four different oscillator modes. there are external rc oscillator modes, high crystal/resonator mode (12m code option), standard crys tal/resonator mode (4m code option) and low crystal mode (32k code option). for different applicat ion, the users can select one of sati able oscillator mode by programming code option to generate system high-s peed clock source after reset. example: stop external high-speed oscillator. b0bset fstphx ; to stop exter nal high-speed oscillator only. b0bset fcpum0 ; to stop external high- speed oscillator and in ternal low-speed ; oscillator called powe r down mode (sleep mode). oscillator mode code option this series has four oscillator modes for different app lications. these modes are 4m, 12m, 32k and rc. the main purpose is to support different oscillator types and frequen cies. high-speed crystal needs more current but the low one doesn?t. for crystals, there are three steps to select. if the o scillator is rc type, to select ?rc? and the system will divide the frequency by 2 automatically. user can select oscillator mode from code option table before compiling. the table is as follow. code option oscillator mode remark 00 rc mode output the fcpu square wave from xout pin. 01 32k 32768hz 10 12m 12mhz ~ 16mhz 11 4m 3.58mhz oscillator devide by 2 code option this series has an external clock divide by 2 function. it is a code option call ed ?high_clk / 2?. if ?high_clk / 2? is enabled, the external clock frequency is divided by 8 for the fcpu. fcpu is equal to fosc/8. if ?high_clk / 2? is disabled, the external clock frequency is divided by 4 for the fcpu. the fcpu is equal to fosc/4. note: in rc mode, ?high_clk / 2? is always enabled. oscillator safe guard code option this series builds in an oscillator safe guard (osg) to make oscillator more stable. it is a low-pass filter circuit and stops high frequency noise into system fr om external oscillator circuit. this func tion makes system to work better under ac noisy conditions.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 45 revision 0.5 system oscillator circuits mcu xin vdd xout vss crystal 20pf 20pf figure 7-2. crystal/ceramic oscillator mcu xin vdd vss xout c r figure 7-3. rc oscillator xin vdd mcu vss xout external clock input figure 7-4. external clock input note1: the vdd and vss of external oscillator circuit must be from the micro-controller. don?t connect them from the neighbor power terminal. note2: the external clock input mode can select rc type oscillator or cr ystal type oscillator of the code option and input the external clock into xin pin. note3: in rc type oscillator code option situation, the external clock?s freq uency is divided by 2. note4: the power and ground of external oscillator circ uit must be connected fr om the micro-controller?s vdd and vss. it is necessary to step up the performance of the whole system.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 46 revision 0.5 external rc oscillator frequency measurement there are two ways to get the fosc fr equency of external rc oscillator. o ne measures the xout output waveform. under external rc oscillator mode, t he xout outputs the square waveform whose frequency is fcpu. the other measures the external rc frequency by instruction cycle (fcpu). the external rc frequency is the fcpu multiplied by 4. we can get the fosc frequency of external rc from the fcpu frequency. the sub-routine to get fcpu frequency of external oscillator is as the following. example: fcpu instruction cy cle of external oscillator b0bset p1m.0 ; set p1.0 to be output mode for outputting fcpu toggle signal. @@: b0bset p1.0 ; output fcpu toggle signal in low-speed clock mode. b0bclr p1.0 ; measure the fcpu frequency by oscilloscope. jmp @b
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 47 revision 0.5 internal low-speed oscillator the internal low-speed oscillato r is built in the micro-controller. the low- speed clock?s source is a rc type oscillator circuit. the low-speed clock can supplies cl ock for system clock, timer counter, watchdog timer, sio clock source and so on. example: stop internal low-speed oscillator. b0bset fcpum0 ; to stop external high- speed oscillator and in ternal low-speed ; oscillator called powe r down mode (sleep mode). note: the internal low-speed clock can?t be turned o ff individually. it is controlled by cpum0 bit of oscm register. the low-speed oscillator uses rc type oscillator circuit. the frequency is affected by the voltage and temperature of the system. in common condition, the fr equency of the rc oscillator is about 16khz at 3v and 32khz at 5v. the relative between the rc frequency and voltage is as following. internal rc vs. vdd 7.329 8.663 11.998 15.333 18.668 22.003 25.338 28.673 32.008 35.343 38.678 0 5 10 15 20 25 30 35 40 1.80 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50 vdd (volts) fintrc (khz) figure 7-5. internal rc vs. vdd diagram example: to measure the internal rc frequency is by instruction cycle (fcpu). the internal rc frequency is the fcpu multiplied by 4. therefore, we can get the fosc frequency of internal rc from the fcpu frequency. b0bset p1m.0 ; set p1.0 to be output mode for outputting fcpu toggle signal. b0bset fclkmd ; switch the system cloc k to internal low-speed clock mode. @@: b0bset p1.0 ; output fcpu toggle signal in low-sp eed clock mode. b0bclr p1.0 ; measure the fcpu frequency by oscilloscope. jmp @b
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 48 revision 0.5 system mode description overview the chip is featured with low power consumption by switching around three different modes as following. high-speed mode low-speed mode power-down mode (sleep mode) green mode in actual application, the user can adjust the chip?s controller to work in thes e three modes by using oscm register. at the high-speed mode, the instruction cycle (fcpu) is fosc /4. at the low-speed mode and 3v, the fcpu is 16khz/4. normal mode in normal mode, the system clock source is external hi gh-speed clock. after power on, the system works under normal mode. the instruction cycle is fosc/4. when the external hi gh-speed oscillator is 3.58mhz, the instruction cycle is 3.58mhz/4 = 895khz. all software and hardware are executed and working. in normal mode, system can get into power down mode and slow mode. slow mode in slow mode, the system clock source is internal low-speed rc clock. to set clkmd = 1, the system switch to slow mode. in slow mode, the system works as normal mode but t he slower clock. the system in slow mode can get into normal mode and power down mode. to set stphx = 1 to stop the external high-speed oscillator, and then the system consumes less power. green mode the green mode is a less power consumption mode. under gr een mode, there are only tc0 still counting and the other hardware stopping. the external high-speed oscillator or internal low-speed oscillator is operating. to set cpum1 = 1 and cpum0 = 0, the system gets into green mode. to set tc0gn = 1 (bit 1 of t0m) will enable tc0 green mode wakeup function. the system can be waked up to last sy stem mode by tc0 timer timeout and p0 trigger signal. the green mode provides a time-variable wakeup function. us ers can decide wakeup time by setting tc0 timer. there are two channels into green mode. one is normal mode and the other is slow mode. in normal mode, the tc0 timer overflow time is very short. in slow mode, the overflow time is longer. users can select appropriate situation for their applications. under green mode, the power co nsumption is 5u amp in 3v condition. power down mode the power down mode is also called sleep mode. the chip stops working as sleeping status. the power consumption is very less almost to zero. the power down mode is usua lly applied to low power consum ing system as battery power productions. to set cupm0 = 1, the system gets into power down mode. the external high-speed and low-speed oscillators are turned off. the system c an be waked up by p0, p1 trigger signal.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 49 revision 0.5 system mode control system mode block diagram figure 7-6. system mode block diagram operating mode description mode normal slow green power down (sleep) remark hx osc. running by stphx by stphx stop lx osc. running running running stop cpu instruction executi ng executing stop stop tc0 timer *active *act ive *active inactive * active by program watchdog timer active active by int_16k_rc by int_16k_rc internal interrupt all active all active tc0 all inactive external interrupt all active all active all active all inactive wakeup source - - p0, p1, tc0 reset p0, p1, reset table 7-1. operating mode description normal mode green mode slow mode power down mode (sleep mode) p0, p1 wake-up function active. external reset circuit active. cpum1, cpum0 = 01 clkmd = 0 clkmd = 1 cpum1, cpum0 = 10 p0, p1 wake-up function active. tc0 time out. p0, p1 wake-up function active. tc0 time out. external reset circuit active. external reset circuit active. normal mode green mode slow mode power down mode (sleep mode) p0, p1 wake-up function active. external reset circuit active. cpum1, cpum0 = 01 clkmd = 0 clkmd = 1 cpum1, cpum0 = 10 p0, p1 wake-up function active. tc0 time out. p0, p1 wake-up function active. tc0 time out. external reset circuit active. external reset circuit active.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 50 revision 0.5 system mode switching switch normal/slow mode to power down (sleep) mode. cpum0 = 1 b0bset fcpum0 ; set cpum0 = 1. during the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode. switch normal mode to slow mode. b0bset fclkmd ;to set clkmd = 1, change the system into slow mode b0bset fstphx ;to stop external high -speed oscillator for power saving. note: to stop high-speed oscillator is not necessary and us er can omit it. switch slow mode to normal mode (the ext ernal high-speed oscillator is still running) b0bclr fclkmd ;to set clkmd = 0 switch slow mode to normal mode ( the external high-speed oscillator stops) if external high clock stop and program want to switch back normal mode. it is necessary to delay at least 10ms for external clock stable. b0bclr fstphx ; turn on the external high-speed oscillator. b0mov z, #27 ; if vdd = 5v, internal rc=32khz (typical) will delay @@: decms z ; 0.125ms x 81 = 10.125ms for external clock stable jmp @b ; b0bclr fclkmd ; change the system back to the normal mode example: go into green mode and enable tc0 wakeup function. ; set tc0 timer wakeup function. b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0enb ; to disable tc0 timer mov a,#20h ; b0mov tc0m,a ; to set tc0 clock = fcpu / 64 mov a,#74h b0mov tc0c,a ; to set tc0c initial value = 74h (to set tc0 interval = 10 ms) b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0irq ; to clear tc0 interrupt request b0bset ftc0enb ; to enable tc0 timer b0bset ftc0gn ; to enable tc0 wakeup function ; go into green mode b0bclr fcpum0 ;to set cpumx = 10 b0bset fcpum1 note: if tc0enb = 0 or tc0gn = 0, tc0 will not wake up from green mode to normal/slow mode function.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 51 revision 0.5 wakeup time overview the external high-speed oscillator needs a delay time fr om stopping to operating. the del ay is very necessary and makes the oscillator to work stably. so me conditions during system operating, the external hi gh-speed oscillator often runs and stops. under these conditions, the delay time for ex ternal high-speed oscillator restart is called wakeup time. there are two conditions need wakeup time. one is power down mode to normal mode. the other one is slow mode to normal mode. for the first case, sn8p1702a/sn8p1703a provid es 2048 oscillator clocks to be the wakeup time. but in the last case, users need to make the wakeup time by themselves. hardware wakeup when the system is in power down mode (sleep mode), the external high-speed oscillator stops. when waked up from power down mode, mcu waits for 2048 exter nal high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. after the wakeup time, the system goes into the normal mode. the value of the wakeup time is as the following. the wakeup time = 1/fosc * 2048 (sec) + x?tal settling time the x?tal settling time is depended on the x?tal type. typically, it is about 2~4ms. example: in power down mode (sleep mode), the syst em is waked up by p0 or p1 trigger signal. after the wakeup time, the system goes into normal mode. the wakeup time of p0, p1 wakeup function is as the following. the wakeup time = 1/fosc * 2048 = 0.57 ms (fosc = 3.58mhz) the total wakeup time = 0.57ms + x?tal settling time under power down mode (sleep mode), there are only i/o ports with wakeup function wake the system up to normal mode. the port 0 and port 1 have wakeup function. port 0 wa keup function always enables, but the port 1 is controlled by the p1w register. p1w initial value = xxxx xx00 0c0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w 0 0 0 0 0 0 p11w p10w - - - - - - w w bit[1:0] p11w,p10w: port 1 wakeup function control bits. 0 = disable each pin of port1 wakeup function, 1 = enable each pin of port 1 wakeup function
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 52 revision 0.5 external wakeup trigger control in the sn8p1702a/sn8p1703a, the wakeup trigger direction is control by pedge register. pedge initial value = 0xx0 0xxx 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge pedgen - - p00g1 p00g0 - - - r/w - - r/w r/w - - - bit7 pedgen: interrupt and wakeup trigger edge control bit. 0 = disable edge trigger function. port 0: low-level wakeup trigger and falling edge interrupt trigger. port 1: low-level wakeup trigger. 1 = enable edge trigger function. p0.0: wakeup and interrupt trigger is controlled by p00g1 and p00g0 bits. port 1: level change (falling or rising edge) wakeup trigger. bit[4:3] p00g[1:0]: port 0.0 edge select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 53 revision 0.5 8 8 8 timers counters watchdog timer (wdt) the watchdog timer (wdt) is a binary up counter designed for monitoring program execution. if the program gets in the unknown status by noise interferen ce, the wdt?s overflow signal will rese t this chip and restart operation. the instruction that clear the watch-dog timer (b0bset fwdrst ) should be executed at proper points in a program within a given period. if an instruct ion that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted with reset status. in order to generate different output timings, the user can control watchdog timer by modifying the wdrate cont rol bits of oscm register. the watchdog timer will be disabled at green and power down modes. oscm initial value = 0000 000x 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst wdrate cpum1 cpum0 clkmd stphx - r/w r/w r/w r/ w r/w r/w r/w - bit1 stphx: external high-speed os cillator control bit. 0 = free run, 1 = stop. note: this bit only controls extern al high-speed oscillator. if stph x=1, the internal low-speed rc oscillator is still running. bit2 clkmd: system high/low speed mode select bit. 0 = normal (dual) mode, 1 = slow mode. bit[4:3] cpum[1:0] : cpu operating mode control bit. 00 = normal, 01 = sleep (power down) mode, 10 = green mode, 11 = reserved. bit5 wdrate: watchdog timer rate select bit. 0 = fcpu 2 14 1 = fcpu 2 8 bit6 wdrst: watchdog timer reset bit. 0 = non reset, 1 = clear the watchdog timer?s counter. (the detail information is in watchdog timer chapter.) bit7 wtcks: watchdog clock source select bit. 0 = fcpu, 1 = internal rc low clock. wtcks wtrate clkmd watchdog timer overflow time 0 0 0 1 / ( fcpu 2 14 16 ) = 293 ms, fosc=3.58mhz 0 1 0 1 / ( fcpu 2 8 16 ) = 500 ms, fosc=32768hz 0 0 1 1 / ( fcpu 2 14 16 ) = 65.5s, fosc=16khz@3v 0 1 1 1 / ( fcpu 2 8 16 ) = 1s, fosc=16khz@3v 1 - - 1 / ( 16k 512 16 ) ~ 0.5s @3v table 8-1. watchdog timer overflow timetable
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 54 revision 0.5 note: the watch dog timer can be enabled or disabled by the code option. example: an operation of watchdog timer is as followi ng. to clear the watchdog timer?s counter in the top of the main routine of the program. main: b0bset fwdrst ; clear the watchdog timer?s counter. . . call sub1 call sub2 . . . . . . jmp main t0m register t0m initial value = xxxx 000x 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m - - - - tc1x8 tc0x8 tc0gn - - - - - r/w r/w r/w - bit3 tc1x8: multiple tc1 timer speed eight times. refe r tc1m register for detailed information. 0 = disable 1 = enable bit2 tc0x8: multiple tc0 timer speed eight times. refe r tc0m register for detailed information. 0 = disable 1 = enable bit0 tc0gn: enable tc0 green mode wakeup function 0 = disable 1 = enable
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 55 revision 0.5 timer counter 0 (tc0) overview the timer counter 0 (tc0) is used to generate an interrupt r equest when a specified time interval has elapsed. tc0 has a auto re-loadable counter that consists of two parts: an 8-bi t reload register (tc0r) into which you write the counter reference value, and an 8-bit counter register (tc0c) whos e value is automatically incremented by counter logic. figure 8-1. tc0 block diagram the main purposes of the tc0 timer counter is as following. 8-bit programmable timer: generates interrupts at specific time inte rvals based on the selected clock frequency. arbitrary frequency output (buzzer output): outputs selectable clock frequencies to the bz0 pin (p5.4). pwm function: pwm output can be generated by the pwm1out bit and output to pwm0out pin (p5.4). tc0r reload data buffer fcpu tc0enb tc0c 8-bit binary counter tc0 time out load aload0 auto. reload p5.4 ? 2 tc0out internal p5.4 i/o circuit cpum 0 s r compar e pw m0 o ut pw m buzzer 2 ( 8- tc0rate) int0 (schmitter trigger) tc0cks tc0r reload data buffer fcpu tc0enb tc0c 8-bit binary counter tc0 time out load aload0 auto. reload p5.4 ? 2 tc0out internal p5.4 i/o circuit cpum 0 s r compar e pw m0 o ut pw m buzzer 2 ( 8- tc0rate) int0 (schmitter trigger) tc0cks
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 56 revision 0.5 tc0m mode register the tc0m is the timer counter mode regi ster, which is an 8-bit read/write register. by loading different value into the tc0m register, users can modify the timer counter clock frequency dynamically when program executing. eight rates for tc0 timer can be selected by tc0rate0 ~ tc0rate2 and tc0x8 bits of t0m register. if tc0x8=1 the tc0 will faster 8 times than tc0x8=0 (initial value). the bit7 of tc0m named tc0enb is the control bit to start tc0 timer. tc0m initial value = 0000 0000 0dah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m tc0enb tc0rate2 tc0r ate1 tc0rate0 tc0cks aloa d0 tc0out pwm0out r/w r/w r/w r/w r/w r/w r/w r/w bit7 tc0enb: tc0 counter/bz0/pwm0out enable bit. 0 = disable, 1 = enable. bit [6:4] tc0rate[2:0]: tc0 clock source selection bits. tc0x8 is bit 2 of t0m register. tc0 clock source tc0rate [2:0] tc0x8 = 0 tc0x8 = 1 000 fcpu/256 = fosc/1024 fosc/128 001 fcpu/128 = fosc/512 fosc/64 ? ? ? 110 fcpu/4 = fosc/16 fosc/2 111 fcpu/2 = fosc/8 fosc note: fcpu = fosc / 4 bit3 tc0cks: tc0 clock source select bit. 0 = fcpu, 1 = external clock comes from int0/p0.0 pin. bit2 aload0: tc0 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. bit1 tc0out: tc0 time-out toggle signal output control bit. 0 = to disable tc0 signal output and to enable p5.4?s i/o function, 1 = to enable tc0?s signal output and to disable p5.4?s i/o function. (auto-disable the pwm0out function.) bit0 pwm0out: tc0?s pwm output control bit. 0 = to disable the pwm output, 1 = to enable the pwm output (the tc0out control bit must = 0 ) note: when tc0cks=1, tc0 became an external event c ounter. no more p0.0 interrupt request will be raised. (p0.0irq will be always 0)
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 57 revision 0.5 tc0c counting register tc0c is an 8-bit counter register for the timer counter (tc0 ). tc0c must be reset whenever the tc0enb is set ?1? to start the timer counter. tc0c is incremented by one wi th a clock pulse which the frequency is determined by tc0rate0 ~ tc0rate2. wh en tc0c has incremented to ?0ffh?, it is will be cleared to ?00h? in next clock and an overflow is generated. under tc0 interrupt service request (tc0ien) enable condition, the tc0 interrupt request flag will be set ?1? and the system executes the interrupt service routine. tc0c initial value = xxxx xxxx 0dbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w r/w r/w r/w r/w r/w r/w r/w tc0 overflow time tc0 rate is determinate by tc0rate and code option tc 0_counter, tc0rate can set tc0 clock frequency and tc0_counter set tc0 became 8-bi t, 6-bit, 5-bit or 4-bit counter. the equation of tc0c initial value is as following. tc0c initial value = n - (tc0 interrupt interval time * input clock) which n is determinate by code option: tc0_counter tc0_counter n max. tc0c value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 note: thetc0c must small or equal than max. tc0 value. example: to set 10ms interval time for tc0 interrupt at fosc = 3.58mhz tc0c value (74h) = 256 - (10ms * fcpu/64) (tc0rate=010, tc0_counter=8-bit, tc0x8=0) tc0c initial value = 256 - (tc0 inte rrupt interval time * input clock) = 256 - (10ms * 3.58 * 10 6 / 4 / 64) = 256 - (0.01 * 3.58 * 10 6 / 4 / 64) = 116 = 74h example: to set 1.25ms interval time for tc0 interrupt at fosc = 3.58mhz tc0c value (74h) = 256 - (10ms * fcpu/64) (tc0rate=010, tc0_counter=8-bit, tc0x8=1) tc0c initial value = 256 - (tc0 inte rrupt interval time * input clock) = 256 - (1.25ms * 3.58 * 10 6 / 32) = 256 - (0.00125 * 3.58 * 10 6 / 32) = 116 = 74h example: to set 1ms interval time for tc0 interrupt at fosc = 3.58mhz tc0c value (32h) = 64 - (1ms * fcpu/64) (tc0rate=010, tc0_counter=6-bit, tc0x8=0) tc0c initial value = 64 - (tc0 interrupt interval time * input clock) = 64 - (1ms * 3.58 * 10 6 / 4 / 64) = 64 - (0.001 * 3.58 * 10 6 / 4 / 64) = 64 - 14 = 32h
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 58 revision 0.5 tc0_counter=8-bit, tc0x8=0 high speed mode (fcpu = 3.58mhz / 4) low speed mode (fosc = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms tc0_counter=6-bit , tc0x8=0 high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/64 ma x overflow interval one step = max/64 000 fcpu/256 18.3 ms 286us 2000 ms 31.25 ms 001 fcpu/128 9.15 ms 143us 1000 ms 15.63 ms 010 fcpu/64 4.57 ms 71.5us 500 ms 7.8 ms 011 fcpu/32 2.28 ms 35.8us 250 ms 3.9 ms 100 fcpu/16 1.14 ms 17.9us 125 ms 1.95 ms 101 fcpu/8 0.57 ms 8.94us 62.5 ms 0.98 ms 110 fcpu/4 0.285 ms 4.47us 31.25 ms 0.49 ms 111 fcpu/2 0.143 ms 2.23us 15.63 ms 0.24 ms tc0_counter=5-bit, tc0x8=0 high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/32 ma x overflow interval one step = max/32 000 fcpu/256 9.15 ms 286us 1000 ms 31.25 ms 001 fcpu/128 4.57 ms 143us 500 ms 15.63 ms 010 fcpu/64 2.28 ms 71.5us 250 ms 7.8 ms 011 fcpu/32 1.14 ms 35.8us 125 ms 3.9 ms 100 fcpu/16 0.57 ms 17.9us 62.5 ms 1.95 ms 101 fcpu/8 0.285 ms 8.94us 31.25 ms 0.98 ms 110 fcpu/4 0.143 ms 4.47us 15.63 ms 0.49 ms 111 fcpu/2 71.25 us 2.23us 7.81 ms 0.24 ms tc0_counter=4-bit, tc0x8=0 high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/16 ma x overflow interval one step = max/16 000 fcpu/256 4.57 ms 286us 500 ms 31.25 ms 001 fcpu/128 2.28 ms 143us 250 ms 15.63 ms 010 fcpu/64 1.14 ms 71.5us 125 ms 7.8 ms 011 fcpu/32 0.57 ms 35.8us 62.5 ms 3.9 ms 100 fcpu/16 0.285 ms 17.9us 31.25 ms 1.95 ms 101 fcpu/8 0.143 ms 8.94us 15.63 ms 0.98 ms 110 fcpu/4 71.25 us 4.47us 7.81 ms 0.49 ms 111 fcpu/2 35.63 us 2.23us 3.91 ms 0.24 ms
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 59 revision 0.5 tc0_counter=8-bit, tc0x8=1 high speed mode (fosc = 3.58mhz) low speed mode (fosc = 32768hz) tc0rate tc0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fosc/128 9.153 ms 35.754us 1000 ms 3.91 ms 001 fosc/64 4.58 ms 17.877us 500 ms 1.95 ms 010 fosc/32 2.29 ms 8.939us 250 ms 0.977 ms 011 fosc/16 1.14 ms 4.470us 125 ms 0.488 ms 100 fosc/8 0.57 ms 2.235us 62.5 ms 0.244 ms 101 fosc/4 0.29 ms 1.117us 31.25 ms 0.122 ms 110 fosc/2 0.14 ms 0.587us 15.63 ms 0.061 ms 111 fosc 71.5 us 0.279us 7.81ms 0.03 ms tc0_counter=6-bit , tc0x8=1 high speed mode (fosc = 3.58mhz) low speed mode (fosc = 32768hz) tc0rate tc0clock max overflow interval one step = max/64 ma x overflow interval one step = max/64 000 fosc/128 2.29 ms 35.754us 250 ms 3.91 ms 001 fosc/64 1.14 ms 17.877us 125 ms 1.95 ms 010 fosc/32 0.57 ms 8.939us 62.5 ms 0.977 ms 011 fosc/16 0.29 ms 4.470us 31.25 ms 0.488 ms 100 fosc/8 0.14 ms 2.235us 15.63 ms 0.244 ms 101 fosc/4 71.5 us 1.117us 7.81ms 0.122 ms 110 fosc/2 35.75 us 0.587us 3.905 ms 0.061 ms 111 fosc 17.875 us 0.279us 1.953 ms 0.03 ms tc0_counter=5-bit, tc0x8=1 high speed mode (fosc = 3.58mhz) low speed mode (fosc = 32768hz) tc0rate tc0clock max overflow interval one step = max/32 ma x overflow interval one step = max/32 000 fosc/128 1.14 ms 35.754us 125 ms 3.91 ms 001 fosc/64 0.57 ms 17.877us 62.5 ms 1.95 ms 010 fosc/32 0.29 ms 8.939us 31.25 ms 0.977 ms 011 fosc/16 0.14 ms 4.470us 15.63 ms 0.488 ms 100 fosc/8 71.5 us 2.235us 7.81ms 0.244 ms 101 fosc/4 35.75 us 1.117us 3.905 ms 0.122 ms 110 fosc/2 17.875 us 0.587us 1.953 ms 0.061 ms 111 fosc 8.936 us 0.279us 0.976 ms 0.03 ms tc0_counter=4-bit, tc0x8=1 high speed mode (fosc = 3.58mhz) low speed mode (fosc = 32768hz) tc0rate tc0clock max overflow interval one step = max/16 ma x overflow interval one step = max/16 000 fosc/128 0.57 ms 35.754us 62.5 ms 3.91 ms 001 fosc/64 0.29 ms 17.877us 31.25 ms 1.95 ms 010 fosc/32 0.14 ms 8.939us 15.63 ms 0.977 ms 011 fosc/16 71.5 us 4.470us 7.81ms 0.488 ms 100 fosc/8 35.75 us 2.235us 3.905 ms 0.244 ms 101 fosc/4 17.875 us 1.117us 1.953 ms 0.122 ms 110 fosc/2 8.936 us 0.587us 0.976 ms 0.061 ms 111 fosc 4.468 us 0.279us 0.488 ms 0.03 ms table 8-2. the timing table of timer counter tc0
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 60 revision 0.5 tc0r auto-load register tc0r is an 8-bit register for the tc0 auto-reload function. tc0r?s value applies to tc0out and pwm0out functions. under tc0out application, users must enable and set the tc0r register. the main purpose of tc0r is as following. store the auto-reload value and set into tc 0c when the tc0c overflow. (aload0 = 1). store the duty value of pwm0out function. tc0r initial value = xxxx xxxx 0cdh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0r tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w w w w w w w w the equation of tc0r initial value is like tc0c as following. tc0r initial value = n - (tc0 interrupt interval time * input clock) which n is determinate by code option: tc0_counter tc0_counter n max. tc0r value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 note: thetc0r must small or equal than max. tc0r value. note: the tc0r is write-only register can?t be process by incms, decms instructions.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 61 revision 0.5 tc0 timer counter operation sequence the tc0 timer counter?s sequence of operation can be following. set the tc0c initial value to setup the interval time. set the tc0enb to be ?1? to enable tc0 timer counter. tc0c is incremented by one with each clock pulse wh ich frequency is corresponding to tc0m selection. tc0c overflow when tc 0c from ffh to 00h. when tc0c overflow occur, the tc0irq flag is set to be ?1? by hardware. execute the interrupt service routine. users reset the tc0c value and resume the tc0 timer operation. example: setup the tc0m and tc0c withou t auto-reload function. (tc0_counter=8-bit) b0bclr ftc0x8 ; b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0enb ; to disable tc0 timer mov a,#20h ; b0mov tc0m,a ; to set tc0 clock = fcpu / 64 mov a,#74h ; to set tc0c initial value = 74h b0mov tc0c,a ;(to set tc0 interval = 10 ms) b0bset ftc0ien ; to enable tc0 interrupt service b0bclr ftc0irq ; to clear tc0 interrupt request b0bset ftc0enb ; to enable tc0 timer example: setup the tc0m and tc0c with auto-reload function. (tc0_counter=8-bit) b0bclr ftc0x8 ; to select tc0=fcpu/2 as clock source b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0enb ; to disable tc0 timer mov a,#20h ; b0mov tc0m,a ; to set tc0 clock = fcpu / 64 mov a,#74h ; to set tc0c initial value = 74h b0mov tc0c,a ; (to set tc0 interval = 10 ms) b0mov tc0r,a ; to set tc0r auto-reload register b0bset ftc0ien ; to enable tc0 interrupt service b0bclr ftc0irq ; to clear tc0 interrupt request b0bset ftc0enb ; to enable tc0 timer b0bset aload0 ; to enable tc0 auto-reload function.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 62 revision 0.5 example: tc0 interrupt service routine wit hout auto-reload function. (tc0_counter=8-bit) org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a,#74h ; reload tc0c b0mov tc0c,a . . ; tc0 interrupt service routine . . jmp exit_int ; end of tc0 interrupt service routine and exit interrupt vector . . . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector example: tc0 interrupt service routine with auto-reload. (tc0_counter=8-bit) org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq . . ; tc0 interrupt service routine . . jmp exit_int ; end of tc0 interrupt service routine and exit interrupt vector . . . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 63 revision 0.5 tc0 clock frequency output (buzzer) tc0 timer counter provides a frequency output function. by setting the tc0 clock frequency, the clock signal is output to p5.4 and the p5.4 general purpose i/o function is auto-di sable. the tc0 output signal divides by 2. the tc0 clock has many combinations and easily to make difference fr equency. this function applies as buzzer output to output multi-frequency. figure 8-2. the tc0out pulse frequency example: setup tc0out output from tc0 to tc0out (p5.4). the external high-speed clock is 4mhz. the tc0out frequency is 1khz. because the tc0out signal is divided by 2, set the tc0 clock to 2khz. the tc0 clock source is from external oscillator clock. tc0 rate is fcpu/4. the tc0rate2~tc0rate1 = 110, tc0c = tc0r = 131, tc0x8 = 0, tc0_counter=8-bit b0bclr ftc0x8 ; set tc0x8 to 0 mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc0c,a b0mov tc0r,a b0bset ftc0out ; enable tc0 output to p5.4 and disable p5.4 i/o function b0bset faload0 ; enable tc0 auto-reload function b0bset ftc0enb ; enable tc0 timer
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 64 revision 0.5 tc0out frequency table fosc = 4mhz, tc0 rate = fcpu/8, tc0_counter=8-bit , tc0x8=0 tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) 0 0.2441 56 0.3125 112 0.4340 168 0.7102 224 1.9531 1 0.2451 57 0.3141 113 0.4371 169 0.7184 225 2.0161 2 0.2461 58 0.3157 114 0.4401 170 0.7267 226 2.0833 3 0.2470 59 0.3173 115 0.4433 171 0.7353 227 2.1552 4 0.2480 60 0.3189 116 0.4464 172 0.7440 228 2.2321 5 0.2490 61 0.3205 117 0.4496 173 0.7530 229 2.3148 6 0.2500 62 0.3222 118 0.4529 174 0.7622 230 2.4038 7 0.2510 63 0.3238 119 0.4562 175 0.7716 231 2.5000 8 0.2520 64 0.3255 120 0.4596 176 0.7813 232 2.6042 9 0.2530 65 0.3272 121 0.4630 177 0.7911 233 2.7174 10 0.2541 66 0.3289 122 0.4664 178 0.8013 234 2.8409 11 0.2551 67 0.3307 123 0.4699 179 0.8117 235 2.9762 12 0.2561 68 0.3324 124 0.4735 180 0.8224 236 3.1250 13 0.2572 69 0.3342 125 0.4771 181 0.8333 237 3.2895 14 0.2583 70 0.3360 126 0.4808 182 0.8446 238 3.4722 15 0.2593 71 0.3378 127 0.4845 183 0.8562 239 3.6765 16 0.2604 72 0.3397 128 0.4883 184 0.8681 240 3.9063 17 0.2615 73 0.3415 129 0.4921 185 0.8803 241 4.1667 18 0.2626 74 0.3434 130 0.4960 186 0.8929 242 4.4643 19 0.2637 75 0.3453 131 0.5000 187 0.9058 243 4.8077 20 0.2648 76 0.3472 132 0.5040 188 0.9191 244 5.2083 21 0.2660 77 0.3492 133 0.5081 189 0.9328 245 5.6818 22 0.2671 78 0.3511 134 0.5123 190 0.9470 246 6.2500 23 0.2682 79 0.3531 135 0.5165 191 0.9615 247 6.9444 24 0.2694 80 0.3551 136 0.5208 192 0.9766 248 7.8125 25 0.2706 81 0.3571 137 0.5252 193 0.9921 249 8.9286 26 0.2717 82 0.3592 138 0.5297 194 1.0081 250 10.4167 27 0.2729 83 0.3613 139 0.5342 195 1.0246 251 12.5000 28 0.2741 84 0.3634 140 0.5388 196 1.0417 252 15.6250 29 0.2753 85 0.3655 141 0.5435 197 1.0593 253 20.8333 30 0.2765 86 0.3676 142 0.5482 198 1.0776 254 31.2500 31 0.2778 87 0.3698 143 0.5531 199 1.0965 255 62.5000 32 0.2790 88 0.3720 144 0.5580 200 1.1161 33 0.2803 89 0.3743 145 0.5631 201 1.1364 34 0.2815 90 0.3765 146 0.5682 202 1.1574 35 0.2828 91 0.3788 147 0.5734 203 1.1792 36 0.2841 92 0.3811 148 0.5787 204 1.2019 37 0.2854 93 0.3834 149 0.5841 205 1.2255 38 0.2867 94 0.3858 150 0.5896 206 1.2500 39 0.2880 95 0.3882 151 0.5952 207 1.2755 40 0.2894 96 0.3906 152 0.6010 208 1.3021 41 0.2907 97 0.3931 153 0.6068 209 1.3298 42 0.2921 98 0.3956 154 0.6127 210 1.3587 43 0.2934 99 0.3981 155 0.6188 211 1.3889 44 0.2948 100 0.4006 156 0.6250 212 1.4205 45 0.2962 101 0.4032 157 0.6313 213 1.4535 46 0.2976 102 0.4058 158 0.6378 214 1.4881 47 0.2990 103 0.4085 159 0.6443 215 1.5244 48 0.3005 104 0.4112 160 0.6510 216 1.5625 49 0.3019 105 0.4139 161 0.6579 217 1.6026 50 0.3034 106 0.4167 162 0.6649 218 1.6447 51 0.3049 107 0.4195 163 0.6720 219 1.6892 52 0.3064 108 0.4223 164 0.6793 220 1.7361 53 0.3079 109 0.4252 165 0.6868 221 1.7857 54 0.3094 110 0.4281 166 0.6944 222 1.8382 55 0.3109 111 0.4310 167 0.7022 223 1.8939 table 8-3. tc0out frequency table for fosc = 4mhz, tc0 rate = fcpu/8
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 65 revision 0.5 fosc = 16mhz, tc0 rate = fcpu/8, tc0_counter=8-bit tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) 0 0.9766 56 1.2500 112 1.7361 168 2.8409 224 7.8125 1 0.9804 57 1.2563 113 1.7483 169 2.8736 225 8.0645 2 0.9843 58 1.2626 114 1.7606 170 2.9070 226 8.3333 3 0.9881 59 1.2690 115 1.7730 171 2.9412 227 8.6207 4 0.9921 60 1.2755 116 1.7857 172 2.9762 228 8.9286 5 0.9960 61 1.2821 117 1.7986 173 3.0120 229 9.2593 6 1.0000 62 1.2887 118 1.8116 174 3.0488 230 9.6154 7 1.0040 63 1.2953 119 1.8248 175 3.0864 231 10.0000 8 1.0081 64 1.3021 120 1.8382 176 3.1250 232 10.4167 9 1.0121 65 1.3089 121 1.8519 177 3.1646 233 10.8696 10 1.0163 66 1.3158 122 1.8657 178 3.2051 234 11.3636 11 1.0204 67 1.3228 123 1.8797 179 3.2468 235 11.9048 12 1.0246 68 1.3298 124 1.8939 180 3.2895 236 12.5000 13 1.0288 69 1.3369 125 1.9084 181 3.3333 237 13.1579 14 1.0331 70 1.3441 126 1.9231 182 3.3784 238 13.8889 15 1.0373 71 1.3514 127 1.9380 183 3.4247 239 14.7059 16 1.0417 72 1.3587 128 1.9531 184 3.4722 240 15.6250 17 1.0460 73 1.3661 129 1.9685 185 3.5211 241 16.6667 18 1.0504 74 1.3736 130 1.9841 186 3.5714 242 17.8571 19 1.0549 75 1.3812 131 2.0000 187 3.6232 243 19.2308 20 1.0593 76 1.3889 132 2.0161 188 3.6765 244 20.8333 21 1.0638 77 1.3966 133 2.0325 189 3.7313 245 22.7273 22 1.0684 78 1.4045 134 2.0492 190 3.7879 246 25.0000 23 1.0730 79 1.4124 135 2.0661 191 3.8462 247 27.7778 24 1.0776 80 1.4205 136 2.0833 192 3.9063 248 31.2500 25 1.0823 81 1.4286 137 2.1008 193 3.9683 249 35.7143 26 1.0870 82 1.4368 138 2.1186 194 4.0323 250 41.6667 27 1.0917 83 1.4451 139 2.1368 195 4.0984 251 50.0000 28 1.0965 84 1.4535 140 2.1552 196 4.1667 252 62.5000 29 1.1013 85 1.4620 141 2.1739 197 4.2373 253 83.3333 30 1.1062 86 1.4706 142 2.1930 198 4.3103 254 125.0000 31 1.1111 87 1.4793 143 2.2124 199 4.3860 255 250.0000 32 1.1161 88 1.4881 144 2.2321 200 4.4643 33 1.1211 89 1.4970 145 2.2523 201 4.5455 34 1.1261 90 1.5060 146 2.2727 202 4.6296 35 1.1312 91 1.5152 147 2.2936 203 4.7170 36 1.1364 92 1.5244 148 2.3148 204 4.8077 37 1.1416 93 1.5337 149 2.3364 205 4.9020 38 1.1468 94 1.5432 150 2.3585 206 5.0000 39 1.1521 95 1.5528 151 2.3810 207 5.1020 40 1.1574 96 1.5625 152 2.4038 208 5.2083 41 1.1628 97 1.5723 153 2.4272 209 5.3191 42 1.1682 98 1.5823 154 2.4510 210 5.4348 43 1.1737 99 1.5924 155 2.4752 211 5.5556 44 1.1792 100 1.6026 156 2.5000 212 5.6818 45 1.1848 101 1.6129 157 2.5253 213 5.8140 46 1.1905 102 1.6234 158 2.5510 214 5.9524 47 1.1962 103 1.6340 159 2.5773 215 6.0976 48 1.2019 104 1.6447 160 2.6042 216 6.2500 49 1.2077 105 1.6556 161 2.6316 217 6.4103 50 1.2136 106 1.6667 162 2.6596 218 6.5789 51 1.2195 107 1.6779 163 2.6882 219 6.7568 52 1.2255 108 1.6892 164 2.7174 220 6.9444 53 1.2315 109 1.7007 165 2.7473 221 7.1429 54 1.2376 110 1.7123 166 2.7778 222 7.3529 55 1.2438 111 1.7241 167 2.8090 223 7.5758 table 8-4tc0out frequency table for fosc = 16mhz, tc0 rate = fcpu/8
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 66 revision 0.5 timer counter 1 (tc1) overview the timer counter 1 (tc1) is used to generate an interrupt r equest when a specified time interval has elapsed. tc1 has a auto re-loadable counter that consists of two parts: an 8-bi t reload register (tc1r) into which you write the counter reference value, and an 8-bit counter register (tc1c) whos e value is automatically incremented by counter logic. figure 8-3. timer counter tc1 block diagram the main purposes of the tc1 timer is as following. 8-bit programmable timer: generates interrupts at specific time inte rvals based on the selected clock frequency. arbitrary frequency output (buzzer output): outputs selectable clock frequencies to the bz1 pin (p5.3). pwm function: pwm output can be generated by the pwm1out bit and output to pwm1out pin (p5.3). cpum0 tc1r reload data buffer tc1enb tc1c 8-bit binary counter tc1 time out load aload1 auto. reload p5.3 ? 2 tc1out internal p5.3 i/o circuit s r compare pwm1out pwm buzzer 2 (8-tc1rate) f cpu cpum0 tc1r reload data buffer tc1enb tc1c 8-bit binary counter tc1 time out load aload1 auto. reload p5.3 ? 2 tc1out internal p5.3 i/o circuit s r compare pwm1out pwm buzzer 2 (8-tc1rate) f cpu
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 67 revision 0.5 tc1m mode register the tc1m is the timer mode register, which is an 8-bit read/ write register. by loading different value into the tc1m register, users can modify the timer counter cloc k frequency dynamically when program executing. eight rates for tc1 timer can be selected by tc1rate0 ~ tc1rate2 and tc1x8 bits of t0m register. if tc1x8=1 the tc1 will faster 8 times than tc1x8=0 (initial value). the bit7 of tc1m named tc1enb is the control bit to start tc1 timer. tc1m initial value = 0000 0000 0dch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1m tc1enb tc1rate2 tc 1rate1 tc1rate0 0 aloa d1 tc1out pwm1out r/w r/w r/w r/ w - r/w r/w r/w bit7 tc1enb: tc1 counter/bz1/pwm1out enable bit. 0 = disable, 1 = enable. bit[6:4] tc1rate[2:0]: tc1 clock source selection bits. tc1x8 is bit 3 of t0m register. tc1 clock source tc1rate [2:0] tc1x8 = 0 tc1x8 = 1 000 fcpu/256 = fosc/1024 fosc/128 001 fcpu/128 = fosc/512 fosc/64 ? ? ? 110 fcpu/4 = fosc/16 fosc/2 111 fcpu/2 = fosc/8 fosc note: fcpu = fosc / 4 bit2 aload1: tc1 auto-reload function control bit. 0 = none auto-reload 1 = auto-reload. bit1 tc01ut: tc1 time-out toggle signal output control bit. 0 = to disable tc1 signal output and to enable p5.3?s i/o function, 1 = to enable tc1?s signal output and to disable p5.3?s i/o function. (auto-disable the pwm0out function.) bit0 pwm1out: tc1?s pwm output control bit. 0 = to disable the pwm output, 1 = to enable the pwm output (the tc1out control bit must = 0) note: tc1 doesn?t support event counter mode because sn8p1702a and sn8p1703a hasn?t p0.1 for tc1 event counter clock input. note: bit3 must set to ?0?.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 68 revision 0.5 tc1c counting register tc1c is an 8-bit counter register for the timer counter (tc1 ). tc1c must be reset whenever the tc1enb is set ?1? to start the timer. tc0c is incremented by one with a clo ck pulse which the frequency is determined by tc0rate0 ~ tc0rate2. when tc0c has incr emented to ?0ffh?, it is will be cleared to ?00h? in next clock a nd an overflow is generated. under tc1 interrupt service request (tc1ien) enable condition, the tc1 interrupt request flag will be set ?1? and the system executes t he interrupt service routine. tc1c initial value = xxxx xxxx 0ddh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1c tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w r/w r/w r/w r/w r/w r/w r/w tc1 overflow time tc1 rate is determinate by tc1rate and code option tc 1_counter, tc1rate can set tc1 clock frequency from fcpu and tc1_counter set tc1 became 8-bit, 6-bit, 5-bit or 4-bit counter. the equation of tc1c initial value is as following. tc1c initial value = n - (tc1 interrupt interval time * input clock) which n is determinate by code option: tc1_counter tc1_counter n max. tc1c value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 note: thetc1c must small or equal than max. tc1 value. example: to set 10ms interval time for tc1 interrupt at fosc = 3.58mhz tc1c value (74h) = 256 - (10ms * fcpu/64) (tc1rate=010, tc1_counter=8-bit, tc1x8=0) tc1c initial value = 256 - (tc0 inte rrupt interval time * input clock) = 256 - (10ms * 3.58 * 10 6 / 4 / 64) = 256 - (0.01 * 3.58 * 10 6 / 4 / 64) = 116 = 74h example: to set 1.25ms interval time for tc1 interrupt at fosc = 3.58mhz tc1c value (74h) = 256 - (10ms * fcpu/64) (tc1rate=010, tc1_counter=8-bit, tc1x8=1) tc1c initial value = 256 - (tc0 inte rrupt interval time * input clock) = 256 - (1.25ms * 3.58 * 10 6 / 32) = 256 - (0.00125 * 3.58 * 10 6 / 32) = 116 = 74h example: to set 1ms interval time for tc1 interrupt at fosc = 3.58mhz tc1c value (32h) = 64 - (1ms * fcpu/64) (tc1rate=010, tc1_counter=6-bit, tc1x8=0) tc1c initial value = 64 - (tc0 interrupt interval time * input clock) = 64 - (1ms * 3.58 * 10 6 / 4 / 64) = 64 - (0.001 * 3.58 * 10 6 / 4 / 64) = 64 - 14 = 32h
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 69 revision 0.5 tc1_counter=8-bit, tc1x8=0 high speed mode (fcpu = 3.58mhz / 4) low speed mode (fosc = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms tc1_counter=6-bit , tc1x8=0 high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/64 ma x overflow interval one step = max/64 000 fcpu/256 18.3 ms 286us 2000 ms 31.25 ms 001 fcpu/128 9.15 ms 143us 1000 ms 15.63 ms 010 fcpu/64 4.57 ms 71.5us 500 ms 7.8 ms 011 fcpu/32 2.28 ms 35.8us 250 ms 3.9 ms 100 fcpu/16 1.14 ms 17.9us 125 ms 1.95 ms 101 fcpu/8 0.57 ms 8.94us 62.5 ms 0.98 ms 110 fcpu/4 0.285 ms 4.47us 31.25 ms 0.49 ms 111 fcpu/2 0.143 ms 2.23us 15.63 ms 0.24 ms tc1_counter=5-bit, tc1x8=0 high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/32 ma x overflow interval one step = max/32 000 fcpu/256 9.15 ms 286us 1000 ms 31.25 ms 001 fcpu/128 4.57 ms 143us 500 ms 15.63 ms 010 fcpu/64 2.28 ms 71.5us 250 ms 7.8 ms 011 fcpu/32 1.14 ms 35.8us 125 ms 3.9 ms 100 fcpu/16 0.57 ms 17.9us 62.5 ms 1.95 ms 101 fcpu/8 0.285 ms 8.94us 31.25 ms 0.98 ms 110 fcpu/4 0.143 ms 4.47us 15.63 ms 0.49 ms 111 fcpu/2 71.25 us 2.23us 7.81 ms 0.24 ms tc1_counter=4-bit, tc1x8=0 high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/16 ma x overflow interval one step = max/16 000 fcpu/256 4.57 ms 286us 500 ms 31.25 ms 001 fcpu/128 2.28 ms 143us 250 ms 15.63 ms 010 fcpu/64 1.14 ms 71.5us 125 ms 7.8 ms 011 fcpu/32 0.57 ms 35.8us 62.5 ms 3.9 ms 100 fcpu/16 0.285 ms 17.9us 31.25 ms 1.95 ms 101 fcpu/8 0.143 ms 8.94us 15.63 ms 0.98 ms 110 fcpu/4 71.25 us 4.47us 7.81 ms 0.49 ms 111 fcpu/2 35.63 us 2.23us 3.91 ms 0.24 ms
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 70 revision 0.5 tc1_counter=8-bit, tc1x8=1 high speed mode (fosc = 3.58mhz) low speed mode (fosc = 32768hz) tc1rate tc1clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fosc/128 9.153 ms 35.754us 1000 ms 3.91 ms 001 fosc/64 4.58 ms 17.877us 500 ms 1.95 ms 010 fosc/32 2.29 ms 8.939us 250 ms 0.977 ms 011 fosc/16 1.14 ms 4.470us 125 ms 0.488 ms 100 fosc/8 0.57 ms 2.235us 62.5 ms 0.244 ms 101 fosc/4 0.29 ms 1.117us 31.25 ms 0.122 ms 110 fosc/2 0.14 ms 0.587us 15.63 ms 0.061 ms 111 fosc 71.5 us 0.279us 7.81ms 0.03 ms tc1_counter=6-bit , tc1x8=1 high speed mode (fosc = 3.58mhz) low speed mode (fosc = 32768hz) tc1rate tc1clock max overflow interval one step = max/64 ma x overflow interval one step = max/64 000 fosc/128 2.29 ms 35.754us 250 ms 3.91 ms 001 fosc/64 1.14 ms 17.877us 125 ms 1.95 ms 010 fosc/32 0.57 ms 8.939us 62.5 ms 0.977 ms 011 fosc/16 0.29 ms 4.470us 31.25 ms 0.488 ms 100 fosc/8 0.14 ms 2.235us 15.63 ms 0.244 ms 101 fosc/4 71.5 us 1.117us 7.81ms 0.122 ms 110 fosc/2 35.75 us 0.587us 3.905 ms 0.061 ms 111 fosc 17.875 us 0.279us 1.953 ms 0.03 ms tc1_counter=5-bit, tc1x8=1 high speed mode (fosc = 3.58mhz) low speed mode (fosc = 32768hz) tc1rate tc1clock max overflow interval one step = max/32 ma x overflow interval one step = max/32 000 fosc/128 1.14 ms 35.754us 125 ms 3.91 ms 001 fosc/64 0.57 ms 17.877us 62.5 ms 1.95 ms 010 fosc/32 0.29 ms 8.939us 31.25 ms 0.977 ms 011 fosc/16 0.14 ms 4.470us 15.63 ms 0.488 ms 100 fosc/8 71.5 us 2.235us 7.81ms 0.244 ms 101 fosc/4 35.75 us 1.117us 3.905 ms 0.122 ms 110 fosc/2 17.875 us 0.587us 1.953 ms 0.061 ms 111 fosc 8.936 us 0.279us 0.976 ms 0.03 ms tc1_counter=4-bit, tc1x8=1 high speed mode (fosc = 3.58mhz) low speed mode (fosc = 32768hz) tc1rate tc1clock max overflow interval one step = max/16 ma x overflow interval one step = max/16 000 fosc/128 0.57 ms 35.754us 62.5 ms 3.91 ms 001 fosc/64 0.29 ms 17.877us 31.25 ms 1.95 ms 010 fosc/32 0.14 ms 8.939us 15.63 ms 0.977 ms 011 fosc/16 71.5 us 4.470us 7.81ms 0.488 ms 100 fosc/8 35.75 us 2.235us 3.905 ms 0.244 ms 101 fosc/4 17.875 us 1.117us 1.953 ms 0.122 ms 110 fosc/2 8.936 us 0.587us 0.976 ms 0.061 ms 111 fosc 4.468 us 0.279us 0.488 ms 0.03 ms table 8-5. the timing table of timer counter tc1
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 71 revision 0.5 tc1r auto-load register tc1r is an 8-bit register for the tc1 auto-reload function. tc1r?s value applies to tc1out and pwm1out functions. under tc1out application, users must enable and set the tc1r register. the main purpose of tc1r is as following. store the auto-reload value and set into tc 1c when the tc1c overflow. (aload1 = 1). store the duty value of pwm1out function. tc1r initial value = xxxx xxxx 0deh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1r tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 w w w w w w w w the equation of tc1r initial value is like tc1c as following. tc1r initial value = n - (tc1 interrupt interval time * input clock) which n is determinate by code option: tc1_counter tc1_counter n max. tc1r value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 note: thetc1r must small or equal than max. tc1r value. note: the tc1r is write-only register can?t be process by incms, decms instructions.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 72 revision 0.5 tc1 timer counter operation sequence the tc1 timer?s sequence of operation can be following. set the tc1c initial value to setup the interval time. set the tc1enb to be ?1? to enable tc1 timer counter. tc1c is incremented by one with each clock pulse wh ich frequency is corresponding to tc1m selection. tc1c overflow if tc1c from ffh to 00h. when tc1c overflow occur, the tc1irq flag is set to be ?1? by hardware. execute the interrupt service routine. users reset the tc1c value and resume the tc1 timer operation. example: setup the tc1m and tc1c without auto -reload function.(tc1_counter=8-bit, tc1x8=0) b0bclr ftc1x8 ; b0bclr ftc1ien ; to disable tc1 interrupt service b0bclr ftc1enb ; to disable tc1 timer mov a,#20h ; b0mov tc1m,a ; to set tc1 clock = fcpu / 64 mov a,#74h ; to set tc1c initial value = 74h b0mov tc1c,a ;(to set tc1 interval = 10 ms) b0bset ftc1ien ; to enable tc1 interrupt service b0bclr ftc1irq ; to clear tc1 interrupt request b0bset ftc1enb ; to enable tc1 timer example: setup the tc1m and tc1c with auto-r eload function. (tc1_counter=8-bit, tc1x8=0) b0bclr ftc1x8 ; to select tc1=fcpu/2 as clock source b0bclr ftc1ien ; to disable tc1 interrupt service b0bclr ftc1enb ; to disable tc1 timer mov a,#20h ; b0mov tc1m,a ; to set tc1 clock = fcpu / 64 mov a,#74h ; to set tc1c initial value = 74h b0mov tc1c,a ; (to set tc1 interval = 10 ms) b0mov tc1r,a ; to set tc1r auto-reload register b0bset ftc1ien ; to enable tc1 interrupt service b0bclr ftc1irq ; to clear tc1 interrupt request b0bset ftc1enb ; to enable tc1 timer b0bset aload1 ; to enable tc1 auto-reload function.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 73 revision 0.5 example: tc1 interrupt service routine without au to-reload function. (tc1_counter=8-bit, tc1x8=0) org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a,#74h ; reload tc1c b0mov tc1c,a . . ; tc1 interrupt service routine . . jmp exit_int ; end of tc1 interrupt service routine and exit interrupt vector . . . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector example: tc1 interrupt service routine with auto-reload. (tc1_counter=8-bit, tc1x8=0) org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq . . ; tc1 interrupt service routine . . jmp exit_int ; end of tc1 interrupt service routine and exit interrupt vector . . . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 74 revision 0.5 tc1 clock frequency output (buzzer) tc1 timer counter provides a frequency output function. by setting the tc1 clock frequency, the clock signal is output to p5.3 and the p5.3 general purpose i/o function is auto-di sable. the tc1 output signal divides by 2. the tc1 clock has many combinations and easily to make difference fr equency. this function applies as buzzer output to output multi-frequency. figure 8-4the tc1out pulse frequency example: setup tc1out output from tc1 to tc1out (p5.3). the external high-speed clock is 4mhz. the tc1out frequency is 1khz. because the tc1out signal is divided by 2, set the tc1 clock to 2khz. the tc1 clock source is from external oscillator clock. tc1 rate is fcpu/4. the tc1rate2~tc1rate1 = 110, tc1c = tc1r = 131, tc1_counter=8-bit, tc1x8=0 b0bclr ftc1x8 ; set tc1x8 to 0 mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc1c,a b0mov tc1r,a b0bset ftc1out ; enable tc1 output to p5.3 and disable p5.3 i/o function b0bset faload1 ; enable tc1 auto-reload function b0bset ftc1enb ; enable tc1 timer
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 75 revision 0.5 pwm function description overview pwm function is generated by tc0/tc1 timer counter and output the pwm signal to pwm0out pin (p5.4)/ pwm1out pin (p5.3). when code option tc0/tc1_counter= 8- bit, the counter counts modulus 256, from 0-255, inclusive. the value of the 8-bit counter is compared to t he contents of the reference r egister (tc0r/tc1r). when the reference register value (tc0r/tc1r) is equal to the counter value (tc0c/tc1c), the pwm output goes low. when the counter reaches zero, the pwm output is forced high. following table listed the low-to-high ratio (duty) of the pwm0/pwm1 output. for example, tc0_counter=8-bit, all pwm outputs remain inac tive during the first 256 input clock signals. then, when the counter value (tc0c/tc1c) changes from ffh back to 00h , the pwm output is forced to high level. the pulse width ratio (duty cycle) is defined by the contents of the reference regist er (tc0r/tc1r) and is programmed in increments of 1:256. the 8-bit pwm data register tc0r /tc1r is write-only register. different code option of tc0_counter/tc1_counter will cause different pwm duty, so user can generate different pwm output by selection different tc0_counter/tc1_counter. pwm output can be held at low level by continuously loading the reference register with 00h. under pwm operating, to change the pwm?s duty cycle is to modify the tc0r/tc1r. tc0x8/tc1x8 pwm0 frequency pwm1 frequency 0 fosc/(2 10-tc0rate )/n fosc/(2 10-tc1rate )/n 1 fosc/(2 7-tc0rate ) /n fosc/(2 7-tc1rate ) /n the value of n depend on code option tc0_counter/tc1_counter tc0_counter/tc1_counter n pwm duty cycle 8-bit 256 0/256 ~ 255/256 6-bit 64 0/64 ~ 63/64 5-bit 32 0/32 ~ 31/32 4-bit 16 0/16 ~ 15/16 table 8-6. the pwm frequency calculation formula tc0x8 tc1x8 tc0_counter tc1_counter tc0 overflow boundary tc1 overflow boundary pwm duty cycle max pwm frequency (fosc = 4mhz) note 0 8-bit ffh to 00h 0/256 ~ 255/256 1.953125k overflow per 256 count 0 6-bit 3fh to 40h 0/64 ~ 63/64 7.8125k overflow per 64 count 0 5-bit 1fh to 20h 0/32 ~ 31/32 15.625k overflow per 32 count 0 4-bit 0fh to 10h 0/16 ~ 15/16 31.25k overflow per 16 count 1 8-bit ffh to 00h 0/256 ~ 255/256 15.625 overflow per 256 count 1 6-bit 3fh to 40h 0/64 ~ 63/64 62.5k overflow per 64 count 1 5-bit 1fh to 20h 0/32 ~ 31/32 125k overflow per 32 count 1 4-bit 0fh to 10h 0/16 ~ 15/16 250k overflow per 16 count table 8-7. the maximum pwm frequenc y example (tc0rate/tc1rate = 111)
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 76 revision 0.5 reference register value (tc0r/tc1r) tc0/1_counter=8-bit duty cycle tc0/1_counter=6-bit duty cycle tc0/1_counter=5-bit duty cycle tc0/1_counter=4-bit duty cycle 0000 0000 0/256 0/64 0/32 0/16 0000 0001 1/256 1/64 1/32 1/16 0000 0010 2/256 2/64 2/32 2/16 ? ? ? ? ? 0000 1110 14/256 14/64 14/32 14/16 0000 1111 15/256 15/64 15/32 15/16 0001 0000 16/256. 16/64 16/32 n/a ? ? ? ? n/a 0001 1110 30/256 30/64 30/32 n/a 0001 1111 31/256 31/64 31/32 n/a 0010 0000 32/256. 32/64 n/a n/a ? ? ? n/a n/a 0011 1110 62/256 62/64 n/a n/a 0011 1111 63/256 63/64 n/a n/a 0100 0000 64/256. n/a n/a n/a ? ? n/a n/a n/a 1111 1110 254/256 n/a n/a n/a 1111 1111 255/256 n/a n/a n/a table 8-8. the pwm duty cycle table note: functionality is not guaranteed in shaded area.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 77 revision 0.5 figure 8-5 the output of pwm with different tc0r/tc1r. (tc0/tc1_counter=8-bit) figure 8-6 the output of pwm with different tc0_counter tc0/tc1 clock tc0r/tc1r = 00h low high low low high tc0r/tc1r = 01h tc0r/tc1r = 80h tc0r/tc1r = ffh low high 01 128 ..... 254 255 ..... 01 128 ..... 254 255 ..... tc0/tc1 clock tc0r/tc1r = 00h low high low low high tc0r/tc1r = 01h tc0r/tc1r = 80h tc0r/tc1r = ffh low high low high 01 128 ..... 254 255 ..... 01 128 ..... 254 255 ..... 01 128 ..... 254 255 ..... ..... 01 128 ..... 254 255 ..... ..... 0 tc0 clock tc0r = 01h tc0_count:4-bit high low tc0r = 01h tc0_count:5-bit high low tc0r = 01h tc0_count:6-bit high low tc0r = 01h tc0_count:8-bit high low ... 1 2 16 ... 17 18 32 ... 33 34 64 ... 65 66 255 ... 01 0 tc0 clock tc0r = 01h tc0_count:4-bit high low tc0r = 01h tc0_count:5-bit high low tc0r = 01h tc0_count:6-bit high low tc0r = 01h tc0_count:8-bit high low ... 1 2 16 ... 17 18 32 ... 33 34 64 ... 65 66 255 ... 01
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 78 revision 0.5 pwm program description example: setup pwm0 output from tc0 to pwm0out (p5.4). the extern al high-speed oscillator clock is 4mhz. the duty of pwm is 30/256. the pwm freque ncy is about 1khz. the pwm clock source is from external oscillator clock. tc0 rate is fc pu/4. the tc0rate2~tc0ra te1 = 110, tc0c = tc0r = 30, tc0x8 =0, tc0_counter=8-bit b0bclr ftc0x8 mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#0x00 ;first time initial tc0 b0mov tc0c,a mov a,#30 ; set the pwm duty to 30/256 b0mov tc0r,a b0bclr ftc0out ; dis able tc0out function. b0bset fpwm0out ; enable pwm0 output to p5.4 and disable p5.4 i/o function b0bset ftc0enb ; enable tc0 timer note1: the tc0r and tc1r are write-only registers. don?t process them using incms, decms instructions. note2: set tc0c at initial is to make first duty-cycle correct. after tc0 is enabled, don?t modify tc0r value to avoid duty cycle error of pwm output. example: modify tc0r/tc1r registers? value. mov a, #30h ; input a number using b0mov instruction. b0mov tc0r, a incms buf0 ; get the new tc0r value from the buf0 buffer defined by b0mov a, buf0 ; programming. b0mov tc0r, a note2: that is better to set the tc0c and tc0r value together when pwm0 duty modified. it protects the pwm0 signal no glitch as pwm0 duty changing. that is better to set the tc1c and tc1r value together when pwm1 duty modified. it protects the pwm1 signal no glitch as pwm1 duty changing. note3: the tc0out function must be set ?0? when pwm0 output enable. the tc1out function must be set ?0? when pwm1 output enable. note4: the pwm can work with interrupt request.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 79 revision 0.5 9 9 9 interrupt overview the sn8p1702a/sn8p1703a provides 3 in terrupt sources, including two internal interrupts (tc0, tc1) and one external interrupts (int0 ). the external interrupt can wa keup the chip from power down mode to high-speed normal mode. the external clock input pins of int0 are shared with p0.0 pins. once interrupt service is executed, the gie bit in stkp register will clear to ?0? for stopping other interrupt request. when interrupt service ex its, the gie bit will set to ?1? to accept the next interrupts? request. all of the interr upt request signals are stored in intrq register. the user can program the chip to check intrq?s c ontent for setting executive priority. figure 9-1. the 7 interrupts note: the gie bit must enable a nd all interrupt operations work. int rq 3-bit lat ch s tc0irq tc1irq p00irq interrupt enable gating global interrupt request signal interrupt vector address (0008h) tc0 time out tc1 time out int en interrupt enable reg ister int 0 trigger int rq 3-bit lat ch s tc0irq tc1irq p00irq interrupt enable gating global interrupt request signal interrupt vector address (0008h) tc0 time out tc1 time out int en interrupt enable reg ister int 0 trigger
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 80 revision 0.5 inten interrupt enable register inten is the interrupt request control register including tw o internal interrupts, one exte rnal interrupts enable control bits. one of the register to be set ?1? is to enable the in terrupt request function. once of the interrupt occur, the program jump to org 8 to execute interrupt service routin es. the program exits the inte rrupt service routine when the returning interrupt service routine instruction (reti) is executed. inten initial value = x000 0000 0c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten 0 tc1ien tc0ien 0 0 0 0 p00ien - r/w r/w - - - - r/w bit0 p00ien: external p0.0 interrupt control bit. 0 = disable, 1 = enable. bit5 tc0ien: timer interrupt control bit. 0 = disable, 1 = enable. bit6 tc1ien: timer interrupt control bit. 0 = disable, 1 = enable. intrq interrupt request register intrq is the interrupt request flag regist er. the register includes all interrupt request indication flags. each one of these interrupt request occurs, the bit of the intrq register would be set ?1?. the intrq value needs to be clear by programming after detecting the flag. in the interrupt vect or of program, users know the any interrupt requests occurring by the register and do the routi ne corresponding of the interrupt request. intrq initial value = x000 0000 0c8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq 0 tc1irq tc0irq 0 0 0 0 p00irq - r/w r/w - - - - r/w bit0 p00irq: external p0.0 interrupt request bit. 0 = non-request 1 = request. bit5 tc0irq: tc0 timer interrupt request controls bit. 0 = non request 1 = request. bit6 tc1irq: tc1 timer interrupt request controls bit. 0 = non request 1 = request. when interrupt occurs, the related request bit of intrq r egister will be set to ?1? no matter the related enable bit of inten register is enabled or disabled. if the related bit of in ten = 1 and the related bit of intrq is also set to be ?1?. as the result, the system will execute the interrupt vector (org 8). if the re lated bit of inten = 0, moreover, the system won?t execute interrupt vector even when the related bit of intrq is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 81 revision 0.5 interrupt operation description sn8p1702a/sn8p1703a provides 3 interrupts. the operation of the 3 interrupts is as following. gie global interrupt operation gie is the global interrupt control bit. all interrupts start work after the gie = 1. it is necessary for interrupt service request. one of the interrupt requests occurs, and the program co unter (pc) points to the interrupt vector (org 8) and the stack add 1 level. stkp initial value = 0xxx 1111 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w - - - r/w r/w r/w r/w bit7 gie: global interrupt control bit. 0 = disable 1 = enable. example: set global interrupt control bit (gie). b0bset fgie ; enable gie note: the gie bit must enable a nd all interrupt operations work.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 82 revision 0.5 int0 (p0.0) interrupt operation the p0.0 interrupt trigger direction is control by pedge register. pedge initial value = 0xx0 0xxx 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge pedgen - - p00g1 p00g0 - - - r/w - - r/w r/w - - - bit7 pedgen: interrupt and wakeup trigger edge control bit. 0 = disable edge trigger function. port 0: low-level wakeup trigger and falling edge interrupt trigger. port 1: low-level wakeup trigger. 1 = enable edge trigger function. p0.0: wakeup and interrupt trigger is controlled by p00g1 and p00g0 bits. port 1: level change (falling or rising edge) wakeup trigger. bit[4:3] p00g[1:0]: port 0.0 edge select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction. example: int0 interrupt request setup. b0bset fp00ien ; enable int0 interrupt service b0bclr fp00irq ; clear int0 interrupt request flag b0bset fgie ; enable gie example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq . . ; int0 interrupt service routine . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector when the int0 trigger occurs, the p00irq will be set to ?1 ? no matter the p00ien is enable or disable. if the p00ien = 1 and the trigger event p00irq is also set to be ?1?. as t he result, the system will execute the interrupt vector (org 8). if the p00ien = 0 and the trigger event p00irq is still se t to be ?1?. moreover, the sy stem won?t execute interrupt vector even when the p00irq is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 83 revision 0.5 tc0 interrupt operation when the tc0c counter occurs overflow, the tc0irq will be se t to ?1? however the tc0ien is enable or disable. if the tc0ien = 1, the trigger event will make the tc0irq to be ?1? and the system enter interrupt vector. if the tc0ien = 0, the trigger event will make the tc0irq to be ?1? but the sy stem will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: tc0 interrupt request setup. b0bclr ftc0ien ; disable tc0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = fcpu / 64 mov a, #74h ; set tc0c initial value = 74h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc0ien ; enable tc0 interrupt service b0bclr ftc0irq ; clear tc0 interrupt request flag b0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, #74h b0mov tc0c, a ; reset tc0c. . . ; tc0 interrupt service routine . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 84 revision 0.5 tc1 interrupt operation when the tc1c counter occurs overflow, the tc1irq will be se t to ?1? however the tc1ien is enable or disable. if the tc1ien = 1, the trigger event will make the tc1irq to be ?1? and the system enter interrupt vector. if the tc1ien = 0, the trigger event will make the tc1irq to be ?1? but the sy stem will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: tc1 interrupt request setup. b0bclr ftc1ien ; disable tc1 interrupt service b0bclr ft c1enb ; disable tc1 timer mov a, #20h ; b0mov tc1m, a ; set tc1 clock = fcpu / 64 mov a, #74h ; set tc1c initial value = 74h b0mov tc1c, a ; set tc1 interval = 10 ms b0bset ftc1ien ; enable tc1 interrupt service b0bclr ftc1irq ; clear tc1 interrupt request flag b0bset ftc1enb ; enable tc1 timer b0bset fgie ; enable gie example: tc1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a ; b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a, #74h b0mov tc1c, a ; reset tc1c. . . ; tc1 interrupt service routine . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 85 revision 0.5 multi-interrupt operation in most conditions, the software designer uses more t han one interrupt request. processing multi-interrupt request needs to set the priority of these interrupt requests. the irq flags of the 7 interrupt are co ntrolled by the interrupt event occurring. but the irq flag set doesn?t mean the system to execute the interrupt vector. the irq flags can be triggered by the events without interrupt enable. just only any the event occurs and t he irq will be logic ?1?. the irq and its trigger event relationship is as the below table. interrupt name trigger event description p00irq p0.0 trigger. falling/rising/both. tc0irq tc0c overflow. tc1irq tc1c overflow. there are two things need to do for multi-interrupt. one is to make a good priority for these interrupt requests. two is using ien and irq flags to decide executing interrupt servic e routine or not. users have to check interrupt control bit and interrupt request flag in interrupt vector. there is a simple routine as following.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 86 revision 0.5 example: how does users check the interrupt request in multi-interrupt situation? org 8 ; interrupt vector b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a ; intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp inttc0chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 ; jump to int0 interrupt service routine inttc0chk: ; check tc0 interrupt request b0bts1 ftc0ien ; check tc0ien jmp inttc1chk ; jump check to next interrupt b0bts0 ftc0irq ; check tc0irq jmp inttc0 ; jump to tc0 interrupt service routine inttc1hk: ; check tc1 interrupt request b0bts1 ftc1ien ; check tc1ien jmp int_exit ; jump check to next interrupt b0bts0 ftc1irq ; check tc1irq jmp inttc1 ; jump to tc1 interrupt service routine int_exit: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 87 revision 0.5 1 1 1 0 0 0 i/o port overview the sn8p1702a/sn8p1703a provides up to 4 ports for users? application, consis ting of one input only port (p0), four i/o ports (p1, p4, p5). the direction of i/o port is selected by pnm register and pnur register (n=0,1,4,5) is defined for user setting pull-up register. after the system resets, all ports work as input function without pull-up resistors. figure 10-1. the i/o port block diagram note : all of the latch output circuits are push-pull structures. port0 structure pur pin int. bus pur pnm pin int. bus pnm lat ch port1, 4, 5 structure pnm port0 structure pur pin int. bus pur pnm pin int. bus pnm lat ch port1, 4, 5 structure pnm
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 88 revision 0.5 i/o port function table port/pin i/o function description remark general-purpose input function external interrupt (int0) p0.0 i wakeup for power down mode general-purpose input/output function p1.0~p1.1 i/o wakeup for power down mode general-purpose input/output function p4.0~p4.3 i/o adc analog signal input p5.0~p5.5 i/o general-purpose input/output function table 10-1. i/o function table
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 89 revision 0.5 pull-up resisters sn8p1702a/sn8p1703a series chips built-in pull-up resisters in port 0, port 1, port4 and port 5. user can set pull-up register by pin register name p0ur address e0h bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit?s name - - - - - - - p00r read/write - - - - - - - r/w after reset 0 0 0 0 0 0 0 0 register name p1ur address e1h bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit?s name - - - - - - p11r p10r read/write - - - - - - r/w r/w after reset 0 0 0 0 0 0 0 0 register name p4ur address e4h bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit?s name - - - - p43r p42r p41r p40r read/write - - - - r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 register name p5ur address 0e0h bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit?s name - - p55r p54r p53r p52r p51r p50r read/write - - r/w r/w r/ w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 chip sn8p1703a org 0x10 main: mov a, #01h b0mov p0ur,a ; enable port 0.0 pull-up resisters example 2: enable all pull-up resisters chip sn8p1703a org 0x10 main: mov a, #01h b0mov p0ur,a ; enable port 0 pull-up resisters mov a, #03h b0mov p1ur,a ; enable port 1 pull-up resisters mov a, #0fh b0mov p4ur,a ; enable port 4 pull-up resisters mov a, #01fh b0mov p5ur,a ; enable port 5 pull-up resisters note: enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup in sleep mode.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 90 revision 0.5 i/o port mode the port direction is programmed by pnm register. port 0 is always input mode. port 1,2,4 and 5 can select input or output direction. p1m initial value = xxxx xx00 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m 0 0 0 0 0 0 p11m p10m - - - - - - r/w r/w bit[1:0] p1[1:0]m: p1.0~p1.1 i/o direction control bit. 0 = input mode 1 = output mode. p4m initial value = xxxx 0000 0c4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4m 0 0 0 0 p43m p42m p41m p40m - - - - r/w r/w r/w r/w bit[3:0] p4[3:0]m: p4.0~p4.3 i/o direction control bit. 0 = input mode 1 = output mode. p5m initial value = xx00 0000 0c5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5m 0 0 p55m p54m p53m p52m p51m p50m - - r/w r/w r/ w r/w r/w r/w bit[5:0] p5[5:0]m: p5.0~p5.5 i/o direction control bit. 0 = input mode 1 = output mode. the each bit of pnm is set to ?0?, the i/o pin is input mode. the each bit of pnm is set to ?1?, the i/o pin is output mode. input mode is with pull-up resistor controlled by setti ng @set_up macro. the output mode disables the pull-up resistors no matter pull-up resistors is set or not. the pnm registers are read/write bi-direction regi sters. users can program them by bit control instructions (b0bset, b0bclr).
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 91 revision 0.5 example: i/o mode selecting. clr p1m ; set all ports to be input mode. clr p4m clr p5m mov a, #0ffh ; set all ports to be output mode. b0mov p1m, a b0mov p4m, a b0mov p5m, a b0bclr p1m.0 ; set p1.0 to be input mode. b0bset p1m.0 ; set p1.0 to be output mode.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 92 revision 0.5 i/o port data register p0 initial value = xxxx x000 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - - - - - - - p00 - - - - - - - r p1 initial value = xx00 0000 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 - - - - - - p11 p10 - - - - - - r/w r/w p4 initial value = 0000 0000 0d4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4 - - - - p43 p42 p41 p40 - - - - r/w r/w r/w r/w p5 initial value = 0000 0000 0d5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5 - - p55 p54 p53 p52 p51 p50 - - r/w r/w r/ w r/w r/w r/w example: read data from input port. b0mov a, p0 ; read data from port 0 b0mov a, p1 ; read data from port 1 b0mov a, p4 ; read data from port 4 b0mov a, p5 ; read data from port 5 example: write data to output port. mov a, #55h ; write data 55h to port 1, port 4, port 5 b0mov p1, a b0mov p4, a b0mov p5, a
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 93 revision 0.5 example: write one bit data to output port. b0bset p1.1 ; set p1.1 and p4.0 to be ?1?. b0bset p4.0 b0bclr p1.0 ; set p1.0 and p5.5 to be ?0?. b0bclr p5.5 example: port bit test. b0bts1 p0.0 ; bit test 1 for p0.0 . b0bts0 p1.1 ; bit test 0 for p1.1
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 94 revision 0.5 1 1 1 1 1 1 4-channel analog to digital converter overview this analog to digital converter of sn8p1702a/sn8p1703a has 4-input sources with up to 4096-step resolution to transfer analog signal into 12-bits digital data. the sequence of adc operation is to select input source (ain0 ~ ain3) at first, then set gchs and ads bit to ?1? to start conversi on. when the conversion is comp lete, the adc circuit will set eoc bit to ?1? and final value output in adb register. this adc circuit can select between 8-bit and 12-bit resolution operation by programming adlen bit in adr register. figure 11-1. ad converter function diagram note: for 8-bit resolution, the conversion time is 12 steps. for 12-bit resolution, the conversion time is 16 steps. note: the analog input level must be between the avrefh and vss. note: the avrefh level must be between the vdd and vss+1.2v. a/d converter (adc) data bus 8/12 ain0/p4.0 ain2/p4.2 ain3/p4.3 ain1/p4.1 a/d converter (adc) data bus 8/12 data bus 8/12 ain0/p4.0 ain0/p4.0 ain2/p4.2 ain2/p4.2 ain3/p4.3 ain3/p4.3 ain1/p4.1 ain1/p4.1
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 95 revision 0.5 adm register adm initial value = 0000 x000 0b1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adm adenb ads eoc gchs - - chs1 chs0 r/w r/w r/w r/ w - - r/w r/w bit[1:0] chs[1:0]: adc input channels select bit. 00 = ain0 01 = ain1 10 = ain2 11 = ain3 bit4 gchs: global channel select bit. 0 = to disable ain channel 1 = to enable ain channel. bit5 eoc: adc status bit. 0 = progressing 1 = end of converting and reset adenb bit. bit6 ads: adc start bit. 0 = stop 1 = starting. bit7 adenb: adc control bit. 0 = disable 1 = enable. adr registers adr initial value = x00x 0000 0b3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adr - adcks1 adlen adcks0 adb3 adb2 adb1 adb0 - r/w r/w r/w r r r r bit[3:0] adbn: adc data buffer. adb11~adb4 data for 8-bit adc. adb11~adb0 data for 12-bit adc. bit5 adlen: adc?s resolution select bits. 0 = 8-bit 1 = 12-bit. bit6,bit4 adcks1, adcks0: adc?s clock source select bit. adcks1 adcks0 adc clock source note 0 0 fcpu/4 both validate in normal mode and slow mode 0 1 fcpu/2 both validate in normal mode and slow mode 1 0 fhosc only validate in normal mode 1 1 fhosc/2 only validate in normal mode
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 96 revision 0.5 adb registers adb initial value = xxxx xxxx 0b2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adb adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r r r r r r r r adb is adc data buffer to store ad converter result. the ad b is only 8-bit register including bit4~bit11 adc data. to combine adb register and the low-nibble of adr will get full 12-bit adc data buffer. the adc buffer is a read-only register. in 8-bit adc mode, the adc data is stored in adb register. in 12-bit adc mode, the adc data is stored in adb and adr registers. note: adb[0:11] value is unknown when power on.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 97 revision 0.5 p4con registers adb initial value = xxxx 0000 0aeh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4con 0 0 0 0 p4con3 p4con2 p4con1 p4con0 - - - - r/w r/w r/w r/w p4con is port4 configuration register . this register can avoid current le akage in unselected adc channel, which connected to an analog input source. p4con [3:0] sets to high will isolate related port4 digital input path outside chip. for example, both ain0 (port4.0) and ain1 (port4.1) are co nnected to analog input signal, and ain0 be selected as conversion channel (chs [1:0] = 00), this mean the unselect ed channel p4.1 maybe in digital input mode (if p41m = 0) in this condition will possible leak current from analog input source. set p4con1 = ?1? can block p4.1 digital input path to avoid the current leakage from ain1. for the same reason, p4con0 must set to ?1? when c onversion channel is ain1. so any port4 pin be connected to analog input source should be set related bit of p4con as high to avoid unpredictable current leakage. especially before entering sleep mode, remember to set related bit of p4con as ?1?. bit [3:0] p4con: port4 configuration register. 0 pass p4.3 digital path into chip. p4con3 1 isolate p4.3 digital path into chip 0 pass p4.2 digital path into chip. p4con2 1 isolate p4.2 digital path into chip 0 pass p4.1 digital path into chip. p4con1 1 isolate p4.1 digital path into chip 0 pass p4.0 digital path into chip. p4con0 1 isolate p4.0 digital path into chip note 1: when port4 is general i/o port, set related p4con [3:0] = ?0? note 2: when port4 is adc input channel, set related p4con [3:0] = ?1? the ain?s input voltage vs. adb?s output data ain n adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 0/4096*avrefh 0 0 0 0 0 0 0 0 0 0 0 0 1/4096*avrefh 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4094/4096*avrefh 1 1 1 1 1 1 1 1 1 1 1 0 4095/4096*avrefh 1 1 1 1 1 1 1 1 1 1 1 1 for different applications, users maybe need more than 8-bit resolution but less than 12-bit adc converter. to process the adb and adr data can make the job well. first, the ad resolution must be set 12-bit mode and then to execute adc converter routine. then delete the lsb of adc data and get the new resolution result. the table is as following. adb adr adc resolution adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 8-bit o o o o o o o o x x x x 9-bit o o o o o o o o o x x x 10-bit o o o o o o o o o o x x 11-bit o o o o o o o o o o o x 12-bit o o o o o o o o o o o o o = selected, x = delete
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 98 revision 0.5 adc converting time 12-bit adc conversion time = 1/(adc clock /4)*16 sec 8-bit adc conversion time = 1/(adc clock /4)*12 sec high clock (fosc) is @3.58mhz adlen adcks1 adcks0 adc clock adc conversion time 0 0 fcpu/4 1/((3.58mhz/4)/4/4)*12 = 214.5 us 0 1 fcpu/2 1/((3.58mhz/4)/2/4)*12 = 107.3 us 1 0 fhosc 1/(3.58mhz/4)*12 = 13.4 us 0 (8-bit) 1 1 fhosc/2 1/(3.58mhz/2/4)*12 = 26.8 us 0 0 fcpu/4 1/((3.58mhz/4)/4/4)*16 = 286 us 0 1 fcpu/2 1/((3.58mhz/4)/2/4)*16 = 143 us 1 0 fhosc 1/(3.58mhz/4)*16 = 17.9 us 1 (12-bit) 1 1 fhosc/2 1/(3.58mhz/2/4)*16 = 35.8 us example: to set ain0 ~ ain1 for adc input and executing 12-bit adc adc0: mov a, #60h b0mov adr, a ; to set 12-bit adc and adc clock = fosc. b0set fp4con1 ;isolate ain1 signal to avoid current leakage b0clr fp4con0 ;pass ain0 signal into adc mov a,#90h b0mov adm,a ; to enable adc and set ain0 input b0set p4con1 ; to enable adc and set ain0 input b0bset fads ; to start conversion wadc0: b0bts1 feoc ; to skip, if end of converting =1 jmp wadc0 ; else, jump to wadc0 b0mov a,adb ; to get ain0 input data adc1: b0set fp4con0 ;isolate ain0 signal to avoid current leakage b0clr fp4con1 ;pass ain1 signal into adc mov a,#91h ; b0mov adm,a ; to enable adc and set ain1 input b0bset fads ; to start conversion . . . qexadc: b0bclr fgchs ; to release ainx input channel
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 99 revision 0.5 adc circuit avrefh is connected to vdd. avrefh is connected to external ad reference voltage. figure 11-2. the ainx and avrefh circuit of ad converter note: the capacitor between ain and gnd is a bypass capacitor. it is helpful to stable the analog signal. users can omit it. vdd avref ain0/p40 analog signal input 0.1uf mcu vdd avref ain0/p40 analog signal input 0.1uf mcu vdd avref ain0/p40 analog signal input 0.1uf mcu reference voltage input 47uf vdd avref ain0/p40 analog signal input 0.1uf mcu reference voltage input 47uf
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 100 revision 0.5 1 1 1 2 2 2 coding issue template code ;******************************************************************************* ; filename : template.asm ; author : sonix ; purpose : template code for sn8x17xx ; revision : 09/01/2002 v1.0 first issue ;******************************************************************************* ;* (c) copyright 2002, sonix technology co., ltd. ;******************************************************************************* chip sn8p1703a ; select the chip ;------------------------------------------------------------------------------- ; include files ;------------------------------------------------------------------------------- .nolist ; do not list the macro file includestd macro1.h includestd macro2.h includestd macro3.h .list ; enable the listing function ;------------------------------------------------------------------------------- ; constants definition ;------------------------------------------------------------------------------- ; one equ 1 ;------------------------------------------------------------------------------- ; variables definition ;------------------------------------------------------------------------------- .data org 0h ;bank 0 data section start from ram address 0x000 wk00b0 ds 1 ;temporary buffer for main loop iwk00b0 ds 1 ;temporary buffer for isr accbuf ds 1 ;accumulator buffer pflagbuf ds 1 ;pflag buffer org 100h ;bank 1 data section start from ram address 0x100 bufb1 ds 20 ;temporary buffer in bank 1 ;------------------------------------------------------------------------------- ; bit flag definition ;------------------------------------------------------------------------------- wk00b0_0 equ wk00b0.0 ;bit 0 of wk00b0 iwk00b0_1 equ iwk00b0.1 ;bit 1 of iwk00
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 101 revision 0.5 ;------------------------------------------------------------------------------- ; code section ;------------------------------------------------------------------------------- .code org 0 ;code section start jmp reset ;reset vector ;address 4 to 7 are reserved org 8 jmp isr ;interrupt vector org 10h ;------------------------------------------------------------------------------- ; program reset section ;------------------------------------------------------------------------------- reset: mov a,#07fh ;initial stack pointer and b0mov stkp,a ;disable global interrupt b0mov pflag,#00h ;pflag = x,x,x,x,x,c,dc,z b0mov rbank,#00h ;set initial ram bank in bank 0 mov a,#40h ;clear watchdog timer and initial system mode b0mov oscm,a call clrram ;clear ram call sysinit ;system initial b0bset fgie ;enable global interrupt ;------------------------------------------------------------------------------- ; main routine ;------------------------------------------------------------------------------- main: b0bset fwdrst ;clear watchdog timer call mnapp jmp main ;------------------------------------------------------------------------------- ; main application ;------------------------------------------------------------------------------- mnapp: ; put your main program here ret ;----------------------------------- ; jump table routine ;----------------------------------- org 0x0100 ;the jump table should start from the head ;of boundary. b0mov a,wk00 and a,#3 add pcl,a jmp jmpsub0 jmp jmpsub1 jmp jmpsub2 ;-----------------------------------
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 102 revision 0.5 jmpsub0: ; subroutine 1 jmp jmpexit jmpsub1: ; subroutine 2 jmp jmpexit jmpsub2: ; subroutine 3 jmp jmpexit jmpexit: ret ;return main ;------------------------------------------------------------------------------- ; isr (interrupt service routine) ; arguments : ; returns : ; reg change: ;------------------------------------------------------------------------------- isr: ;----------------------------------- ; save acc and system registers ;----------------------------------- b0xch a,accbuf ;b0xch instruction do not change c,z flag b0mov a,pflag b0mov pflagbuf,a ;----------------------------------- ; check which interrupt happen ;----------------------------------- intp00chk: b0bts1 fp00ien jmp inttc0chk ;modify this line for another interrupt b0bts0 fp00irq jmp p00isr ;if necessary, insert another interrupt checking here inttc0chk: b0bts1 ftc0ien jmp isrexit ;suppose tc0 is the last interrupt which you b0bts0 ftc0irq ;want to check jmp tc0isr ;----------------------------------- ; exit interrupt service routine ;----------------------------------- isrexit: ; following two lines for sn8x1702 only b0mov a,pflag b0mov pflagbuf,a b0xch a,accbuf ;b0xch instruction do not change c,z flag reti ;exit the interrupt routine
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 103 revision 0.5 ;------------------------------------------------------------------------------- ; int0 interrupt service routine ;------------------------------------------------------------------------------- p00isr: b0bclr fp00irq ;process p0.0 external interrupt here jmp isrexit ;------------------------------------------------------------------------------- ; tc0 interrupt service routine ;------------------------------------------------------------------------------- tc0isr: b0bclr ftc0irq ;process tc0 timer interrupt here jmp isrexit ;------------------------------------------------------------------------------- ; sysinit ; initialize i/o, timer, interrupt, etc. ;------------------------------------------------------------------------------- sysinit: ret ;------------------------------------------------------------------------------- ; clrram ; use index @yz to clear ram (00h~7fh) ;------------------------------------------------------------------------------- clrram: ; ram bank 0 clr y ;select bank 0 b0mov z,#0x7f ;set @yz address from 7fh clrram10: clr @yz ;clear @yz content decms z ;z = z ? 1 , skip next if z=0 jmp clrram10 clr @yz ;clear address 0x00 ; ram bank 1 mov a,#1 b0mov y,a ;select bank 1 b0mov z,#0x7f ;set @yz address from 17fh clrram20: clr @yz ;clear @yz content decms z ;z = z ? 1 , skip next if z=0 jmp clrram20 clr @yz ;clear address 0x100 ret ;------------------------------------------------------------------------------- endp
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 104 revision 0.5 program check list item description pull-up resister use pnur register to enable or disable on-chip pull-up resisters. refer i/o port chapter for detailed information. undefined bits a ll bits those are marked as ?0? (undefined bits) in system registers should be set ?0? to avoid unpredicted system errors. adc set adc input pin i/o direction as input mode a nd disable pull-up resister of adc input pin pwm0 set pwm0 (p5.4) pin as output mode. pwm1 set pwm1 (p5.3) pin as output mode. interrupt do not enable interrupt before initializing ram. non-used i/o non-used i/o ports should be pull-up or pull-down in input mode, or be set as low in output mode to save current consumption. sleep mode enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup. stack buffer be careful of function call and interrupt serv ice routine operation. don?t let stack buffer overflow or underflow. system initial 1. write 0x7f into stkp register to initial stack pointer and disable global interrupt 2. clear all ram. 3. initialize all system regist er even unused registers. noisy immunity 1. enable osg and high_clk / 2 code option together 2. enable the watchdog option and internal rc for the watchdog clock to protect system crash. 3. non-used i/o ports should be set as output low mode or input with pull-up resistors. 4. constantly refresh importan t system registers and variabl es in ram to avoid system crash by a high electrical fast transient noise.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 105 revision 0.5 1 1 1 3 3 3 instruction set table field mnemonic description c dc z cycle mov a,m a m - - 1 m mov m,a m a - - - 1 o b0mov a,m a m (bank 0) - - 1 v b0mov m,a m (bank 0) a - - - 1 e mov a,i a i - - - 1 b0mov m,i m i, (m = only for working re gisters r, y, z , rbank & pflag) - - - 1 xch a,m a m - - - 1 b0xch a,m a m (bank 0) - - - 1 movc r, a rom [y,z] - - - 2 adc a,m a a + m + c, if occur carry, then c=1, else c=0 1 a adc m,a m a + m + c, if occur carry, then c=1, else c=0 1 r add a,m a a + m, if occur carry, then c=1, else c=0 1 i add m,a m a + m, if occur carry, then c=1, else c=0 1 t b0add m,a m (bank 0) m (bank 0) + a, if occur carry, then c=1, else c=0 1 h add a,i a a + i, if occur carry, then c=1, else c=0 1 m sbc a,m a a - m - /c, if occur borrow, then c=0, else c=1 1 e sbc m,a m a - m - /c, if occur borrow, then c=0, else c=1 1 t sub a,m a a - m, if occur borrow, then c=0, else c=1 1 i sub m,a m a - m, if occur borrow, then c=0, else c=1 1 c sub a,i a a - i, if occur borrow, then c=0, else c=1 1 daa to adjust acc?s data format from hex to dec. - - 1 and a,m a a and m - - 1 l and m,a m a and m - - 1 o and a,i a a and i - - 1 g or a,m a a or m - - 1 i or m,a m a or m - - 1 c or a,i a a or i - - 1 xor a,m a a xor m - - 1 xor m,a m a xor m - - 1 xor a,i a a xor i - - 1 swap m a (b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 r rrc m a rrc m - - 1 o rrcm m m rrc m - - 1 c rlc m a rlc m - - 1 e rlcm m m rlc m - - 1 s clr m m 0 - - - 1 s bclr m.b m.b 0 - - - 1 bset m.b m.b 1 - - - 1 b0bclr m.b m(bank 0).b 0 - - - 1 b0bset m.b m(bank 0).b 1 - - - 1 cmprs a,i zf,c a - i, if a = i, then skip next instruction - 1 + s b cmprs a,m zf,c a ? m, if a = m, then skip next instruction - 1 + s r incs m a m + 1, if a = 0, then skip next instruction - - - 1 + s a incms m m m + 1, if m = 0, then skip next instruction - - - 1 + s n decs m a m - 1, if a = 0, then skip next instruction - - - 1 + s c decms m m m - 1, if m = 0, then skip next instruction - - - 1 + s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m(bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m(bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 rompages1/0, pc13~pc0 d - - - 2 call d stack pc15~pc0, pc15/14 rompages1/0, pc13~pc0 d - - - 2 m ret pc stack - - - 2 i reti pc stack, and to enable global interrupt - - - 2 s nop no operation - - - 1 c @set_pur val enable or disable pull-up resisters. bit n of val: ?0? disable port n pull-up, ?1? enable port n pull-up - - - table 13-1. instruction set table note 1: any instruction that read/write from 0scm, will add an extra cycle.
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 106 revision 0.5 1 1 1 4 4 4 electrical characteristic absolute maximum rating (all of the voltages referenced to vss) supply voltage (vdd)????????????????????????????????????? - 0.3v ~ 6.0v input in voltage (vin)?????????????????? ??????????????..vss - 0.2v ~ vdd + 0.2v operating ambient temperature (topr)????????????????????????????..-20 c ~ + 70 c storage ambient temperature (tstore)????????????????????????????-30 c ~ + 125 c power consumption (pc)?????????????????????????????????????..500 mw standard electrical characteristic (all of voltages referenced to vss, vdd = 5.0v, fosc = 3.579545 mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit normal mode, vpp = vdd 2.2 5.0 5.5 operating voltage vdd programming mode, vpp = 12.5v 4.5 5.0 5.5 v ram data retention voltage vdr - 1.5 - v internal por vpor vdd rise rate to ensure internal power-on reset - 0.05 - v/ms vil1 all input pins except those specified below vss - 0.3vdd v vil2 input with schmitt trigger buffer - port0 vss - 0.2vdd v vil3 reset pin ; xin ( in rc mode ) vss - 0.2vdd v input low voltage vil4 xin ( in x?tal mode ) vss - 0.3vdd v vih1 all input pins except thos e specified below 0.7vdd - vdd v vih2 input with schmitt trigger buffer ?port0 0.8vdd - vdd v vih3 reset pin ; xin ( in rc mode ) 0.9vdd - vdd v input high voltage vih4 xin ( in x?tal mode ) 0.7vdd - vdd v reset pin leakage current ilekg vin = vdd - - 2 ua i/o port pull-up resistor rup vin = vss , vdd = 5v - 100 - k ? i/o port input leakage current ilekg pull-up resistor disable, vin = vdd - - 2 ua port1 output source current ioh vop = vdd - 0.5v - 15 - ma sink current iol vop = vss + 0.5v - 15 - port4 output source current ioh vop = vdd - 0.5v - 15 - ma sink current iol vop = vss + 0.5v - 15 - port5 output source current ioh vop = vdd - 0.5v - 15 - ma sink current iol vop = vss + 0.5v - 15 - intn trigger pulse width tint0 int0 inte rrupt request pulse width 2/fcpu - - cycle avrefh input voltage avref vdd = 5.0v 1.2v - vdd v ain0 ~ ain3 input voltage vani vss+0.2 - avref v crystal type or ceramic resonator 32768 4m 16m vdd = 3v, rc type for external mode - 6m - oscillator frequency fhosc vdd = 5v, rc type for external mode - 10m - hz vdd= 5v 4mhz - 2.5 6 ma vdd= 3v 4mhz - 1 2 ma idd1 run mode (low power disable) vdd= 3v 32768hz - 40 80 ua vdd= 5v 4mhz - 1.6 3 ma idd2 run mode (low power enable) vdd= 3v 4mhz - 0.7 1.5 ma vdd= 5v 32khz int. rc - 30 60 ua idd3 slow mode (stop high clock) vdd= 3v 16khz int. rc - 7 20 ua vdd= 5v - 1 2 ua idd4 sleep mode vdd= 3v - 0.6 ua vdd= 5v 32khz int. rc - 16 40 supply current (disable adc) idd5 green mode (stop high clock) vdd= 3v 16khz int. rc 3 10 ua vdd=5.0v - 0.6 1 ma adc current consumption iadc vdd=3.0v - 0.4 0.8 ma lvd detect voltage vdet low voltage detect level - 1.8 - v
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 107 revision 0.5 1 1 1 5 5 5 package information p-dip18 pin symbols min. nor. max. a - - 0.210 a1 0.015 - - a2 0.125 0.130 0.135 d 0.880 0.900 0.920 e 0.300bsc. e1 0.245 0.250 0.255 l 0.115 0.130 0.150 b 0.335 0.355 0.375 ? 0 7 15 unit : inch
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 108 revision 0.5 sop18 pin symbols min. max. a 0.093 0.104 a1 0.004 0.012 d 0.447 0.463 e 0.291 0.299 h 0.394 0.419 l 0.016 0.050 ? 0 8 unit : inch
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 109 revision 0.5 p-dip 20 pin
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 110 revision 0.5 sop 20 pin
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 111 revision 0.5 ssop20 pin dimension (mm) dimension (mil) symbols min, nom. max. min. nom. max. a 1.35 1.60 1.75 53 63 69 a1 0.10 0.15 0.25 4 6 10 a2 - - 1.50 - - 59 b 0.20 0.254 0.30 8 10 12 b1 0.20 0.254 0.28 8 11 11 c 0.18 0.203 0.25 7 8 10 c1 0.18 0.203 0.23 7 8 9 d 8.56 8.66 8.74 337 341 344 e 5.80 6.00 6.20 228 236 244 e1 3.80 3.90 4.00 150 154 157 e 0.635 bsc 25 bsc h 0.25 0.42 0.50 10 17 20 l 0.40 0.635 1.27 16 25 50 l1 1.00 1.05 1.10 39 41 43 zd 1.50 ref 58 ref y - - 0.10 - - 4 ? 0 - 8 0 - 8
preliminary sn8p1702a/sn8p1703a 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 112 revision 0.5 sonix reserves the right to make change without further notic e to any products herein to im prove reliability, function or design. sonix does not assume any liability arising out of th e application or use of any product or circuit described herein; neither does it convey any license under its patent rights no r the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other applicati on in which the failure of the sonix product could create a situation where personal injury or death may occur. s hould buyer purchase or use sonix products for any such unintended or unauthorized application. buye r shall indemnify and hold sonix and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cos t, damages, and expenses, and reasonabl e attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 9f, no. 8, hsien cheng 5th s t, chupei city, hsinchu, taiwan r.o.c. tel: 886-3-551 0520 fax: 886-3-551 0523 taipei office: address: 15f-2, no. 171, song ted road, taipei, taiwan r.o.c. tel: 886-2-2759 1980 fax: 886-2-2759 8180 hong kong office: address: flat 3 9/f energy plaza 92 gr anville road, tsimshatsui east kowloon. tel: 852-2723 8086 fax: 852-2723 9179 technical support: email: sn8fae@sonix.com.tw msn: sonix8bit@hotmail.com

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