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NJU6818 -1 - 2002/08/26 80-common x 104rgb-segment in 4096-color stn lcd driver general description the NJU6818 is a stn lcd driver with 80-common x 104rgb-segment in 4096-color. it consists of 312- segment drivers (104xrgb), 80-common drivers, serial and parallel mpu interface circuits, internal power supply circuits, gradation palettes and 99,840-bit for graphic display data ram. each segment driver outputs 16-gradation level out of 32- gradation level of the gradation palette. since the NJU6818 provides low operating voltage of 1.7v and low operating current, it is ideally suited for battery- powered handheld applications. features 4096-color stn lcd driver lcd drivers 80-commons, 104rgb-segments display data ram (ddram) 99,840-bit for graphic display color display mode 16-gradation level out of 32-gradation level of the gradation palette black & white display mode 80x312 pixels in 16-gradation level or 80x312 pixels in b&w 256-color driving mode 8/16bit parallel interface directly-connective to 68/80 series mpu programmable 8- or 16-bit data bus length for display data 3-/4-line serial interface programmable duty and bias ratios programmable internal voltage booster (maximum 6-times) programmable contrast control using 128-step evr chip identification (id) various instructions display data read/write, display on/off, reverse display on/off, all pixels on/off, column address, row address, n-line inversion, initial display line, initial com line, read-modify-write, gradation mode control, increment control, data bus length, discharge on/off, duty cycle ratio, lcd bias ratio, boost level, evr control, power save on/off, etc low operating current low logic supply voltage 1.7v to 3.3v lcd driving supply voltage 5.0v to 18.0v c-mos technology rectangle out look for cog package bumped chip / tcp preliminary package outline NJU6818cj
NJU6818 - 2 - pad location note 1) the same name pads are shorted mutually in the lsi. note 2) the dmy pads are electrically open. chip center : x= 0 m, y= 0 m chip size : 19.25mm x 2.50mm chip thickness : 625 m 25 m bump size : 26 m x 120 m bump pitch : 45 m(min) bump high : 17.5 m(typ.) bump material : au 744: dmy 112 1 740: com 79 741: dmy 109 698: dmy 106 699: dmy 107 697: segc 103 696: segb 103 695: sega 103 40: v ssa 38: p/s 50: csb 39: dmy 20 694: segc 102 693: segb 102 692: sega 102 747: dmy 113 742: dmy 110 743: dmy 111 745: dmy 113 746: dmy 113 3: dmy 2 1: dmy 0 5: v dda 6: dmy 3 7: id 0 23: id 3 24: id 3 9: dmy 4 11: dmy 6 13: id 1 15: dmy 8 17: id 2 19: dmy 10 21: dmy 12 4: v dda 2: dmy 1 8: id 0 10: dmy 5 12: dmy 7 14: id 1 16: dmy 9 18: id 2 20: dmy 11 22: dmy 13 25: dmy 14 31: dmy 16 27: v ssa 29: sel 68 26: v ssa 35: dmy 18 28: dmy 15 30: sel 68 37: p/s 33: v dda 36: dmy 19 32: dmy 17 34: v dda 43: resb 44: resb 41: v ssa 42: dmy 21 45: dmy 22 47: dmy 24 49: csb 46: dmy 23 48: dmy 25 53: rs 54: rs 51: dmy 26 52: dmy 27 55: dmy 28 57: dmy 30 59: wrb 56: dmy 29 58: dmy 31 60: wrb 63: rdb 64: rdb 61: dmy 32 62: dmy 33 65: dmy 34 67: v dda 69: dmy 36 66: dmy 35 68: v dda 70: dmy 37 73: dmy 40 74: d 0 71: dmy 38 72: dmy 39 75: d 0 77: d 1 79: dmy 42 76: d 1 78: dmy 41 80: d 2 700: dmy 108 701: com 40 702: com 41 739: com 78 748: dmy 114
NJU6818 -3 - alignment mark 1 a a : 25 m b : 50 m b a alignment mark coordinates ( -9445, 1070 ) ( 9445, -1070 ) b alignment mark 2 a : 50 m c alignment mark coordinates ( 9257, -1068 ) x y 114: d 13 112: d 12 110: dmy 51 120: d 15 116: dmy 53 132: dmy 56 135: flm 140: fr 138: dmy 58 144: dmy 60 146: osc 1 150: osc 2 92: d 6 93: d 6 94: d 7 95: d 7 98: v ssa 99: dmy 48 96: dmy 47 97: v ssa 102: d 9 103: d 9 104: dmy 49 105: dmy 50 100: d 8 101: d 8 106: d 10 107: d 10 139: fr 143: dmy 59 141: clk 147: dmy 61 145: osc 1 149: osc 2 151: v ss 142: clk 148: dmy 62 161: v lcd 160: dmy 63 159: v ss 85: dmy 44 86: d 4 87: d 4 88: d 5 89: d 5 90: dmy 45 91: dmy 46 131: v dd 133: cl 136: flm 134: cl 137: dmy 57 118: d 14 122: dmy 55 121: d 15 115: d 13 119: d 14 123: v dd 117: dmy 54 113: d 12 111: dmy 52 109: d 11 108: d 11 170: v 1 169: dmy 64 168: v lcd 81: d 2 84: dmy 43 82: d 3 83: d 3 178: v 2 177: v 1 186: dmy 65 185: v 2 alignment mark coordinates a lignment mark coordinates
NJU6818 - 4 - alignment mark 3 d : 50 m e : 20 m e d alignment mark coordinates ( -9257, -1068 ) 248: v out 258: dmy 70 240: v out 239: v ssh 262: dmy 74 211: v reg 213: v ref 257: v ee 221: dmy 68 268: dmy 75 259: dmy 71 274: c 1 - 260: dmy 72 281: c 2+ 261: dmy 73 289: dmy 81 295: c 3 + 382: com 0 386: sega 0 387: segb 0 388: segc 0 230: dmy 69 212: dmy 67 220: v ref 222: v ba 229: v ba 231: v ssh 249: v ee 263: c 1 + 270: c 1 - 275: dmy 77 277: c 2 + 282: dmy 79 284: c 2 - 290: dmy 82 296: dmy 83 291: c 3 + 267: c 1 + 276: dmy 78 283: dmy 80 288: c 2 - 297: dmy 84 383: dmy 103 389: sega 1 390: segb 1 391: segc 1 203: dmy 66 194: v 3 187: v 3 195: v 4 204: v reg 202: v 4 381: com 1 385: dmy 105 384: dmy 104 a lignment mark coordinates 269: dmy 76
NJU6818 -5 - 334: dmy 96 332: dmy 94 311: dmy 88 312: c 4 - 318: dmy 90 319: c 5 + 316: c 4 - 317: dmy 89 323: c 5 + 324: dmy 91 325: dmy 92 326: c 5- 303: dmy 85 304: dmy 86 305: c 4 + 309: c 4 + 310: dmy 87 333: dmy 95 331: dmy 93 330: c 5 - 298: c 3 - 302: c 3 - 335: dmy 97 339: dmy 99 338: dmy 98 336: dmy 98 337: dmy 98 343: com 39 340: dmy 100 342: dmy 102 341: dmy 101 344: com 38
NJU6818 - 6 - pad coordinates 1 chip size 19250 m x 2500 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 1 dmy 0 -9067.5 -1055 52 dmy 27 -6772.5 -1055 103 d 9 -3487.5 -1055 2 dmy 1 -9022.5 -1055 53 rs -6727.5 -1055 104 dmy 49 -3442.5 -1055 3 dmy 2 -8977.5 -1055 54 rs -6682.5 -1055 105 dmy 50 -3307.5 -1055 4 v dda -8932.5 -1055 55 dmy 28 -6637.5 -1055 106 d 10 -3262.5 -1055 5 v dda -8887.5 -1055 56 dmy 29 -6592.5 -1055 107 d 10 -3217.5 -1055 6 dmy 3 -8842.5 -1055 57 dmy 30 -6547.5 -1055 108 d 11 -3082.5 -1055 7 id 0 -8797.5 -1055 58 dmy 31 -6502.5 -1055 109 d 11 -3037.5 -1055 8 id 0 -8752.5 -1055 59 wrb -6457.5 -1055 110 dmy 51 -2992.5 -1055 9 dmy 4 -8707.5 -1055 60 wrb -6412.5 -1055 111 dmy 52 -2857.5 -1055 10 dmy 5 -8662.5 -1055 61 dmy 32 -6367.5 -1055 112 d 12 -2812.5 -1055 11 dmy 6 -8617.5 -1055 62 dmy 33 -6322.5 -1055 113 d 12 -2767.5 -1055 12 dmy 7 -8572.5 -1055 63 rdb -6277.5 -1055 114 d 13 -2632.5 -1055 13 id 1 -8527.5 -1055 64 rdb -6232.5 -1055 115 d 13 -2587.5 -1055 14 id 1 -8482.5 -1055 65 dmy 34 -6187.5 -1055 116 dmy 53 -2542.5 -1055 15 dmy 8 -8437.5 -1055 66 dmy 35 -6142.5 -1055 117 dmy 54 -2407.5 -1055 16 dmy 9 -8392.5 -1055 67 v dda -6097.5 -1055 118 d 14 -2362.5 -1055 17 id 2 -8347.5 -1055 68 v dda -6052.5 -1055 119 d 14 -2317.5 -1055 18 id 2 -8302.5 -1055 69 dmy 36 -6007.5 -1055 120 d 15 -2182.5 -1055 19 dmy 10 -8257.5 -1055 70 dmy 37 -5962.5 -1055 121 d 15 -2137.5 -1055 20 dmy 11 -8212.5 -1055 71 dmy 38 -5917.5 -1055 122 dmy 55 -2092.5 -1055 21 dmy 12 -8167.5 -1055 72 dmy 39 -5872.5 -1055 123 v dd -1957.5 -1055 22 dmy 13 -8122.5 -1055 73 dmy 40 -5737.5 -1055 124 v dd -1912.5 -1055 23 id 3 -8077.5 -1055 74 d 0 /scl -5692.5 -1055 125 v dd -1867.5 -1055 24 id 3 -8032.5 -1055 75 d 0 /scl -5647.5 -1055 126 v dd -1822.5 -1055 25 dmy 14 -7987.5 -1055 76 d 1 /sda -5512.5 -1055 127 v dd -1777.5 -1055 26 v ssa -7942.5 -1055 77 d 1 /sda -5467.5 -1055 128 v dd -1732.5 -1055 27 v ssa -7897.5 -1055 78 dmy 41 -5422.5 -1055 129 v dd -1687.5 -1055 28 dmy 15 -7852.5 -1055 79 dmy 42 -5287.5 -1055 130 v dd -1642.5 -1055 29 sel 68 -7807.5 -1055 80 d 2 -5242.5 -1055 131 v dd -1597.5 -1055 30 sel 68 -7762.5 -1055 81 d 2 -5197.5 -1055 132 dmy 56 -1372.5 -1055 31 dmy 16 -7717.5 -1055 82 d 3 /smode -5062.5 -1055 133 cl -1327.5 -1055 32 dmy 17 -7672.5 -1055 83 d 3 /smode -5017.5 -1055 134 cl -1282.5 -1055 33 v dda -7627.5 -1055 84 dmy 43 -4972.5 -1055 135 flm -1147.5 -1055 34 v dda -7582.5 -1055 85 dmy 44 -4837.5 -1055 136 flm -1102.5 -1055 35 dmy 18 -7537.5 -1055 86 d 4 /spol -4792.5 -1055 137 dmy 57 -1057.5 -1055 36 dmy 19 -7492.5 -1055 87 d 4 /spol -4747.5 -1055 138 dmy 58 -922.5 -1055 37 p/s -7447.5 -1055 88 d 5 -4612.5 -1055 139 fr -877.5 -1055 38 p/s -7402.5 -1055 89 d 5 -4567.5 -1055 140 fr -832.5 -1055 39 dmy 20 -7357.5 -1055 90 dmy 45 -4522.5 -1055 141 clk -697.5 -1055 40 v ssa -7312.5 -1055 91 dmy 46 -4387.5 -1055 142 clk -652.5 -1055 41 v ssa -7267.5 -1055 92 d 6 -4342.5 -1055 143 dmy 59 -607.5 -1055 42 dmy 21 -7222.5 -1055 93 d 6 -4297.5 -1055 144 dmy 60 -472.5 -1055 43 resb -7177.5 -1055 94 d 7 -4162.5 -1055 145 osc 1 -427.5 -1055 44 resb -7132.5 -1055 95 d 7 -4117.5 -1055 146 osc 1 -382.5 -1055 45 dmy 22 -7087.5 -1055 96 dmy 47 -4072.5 -1055 147 dmy 61 -337.5 -1055 46 dmy 23 -7042.5 -1055 97 v ssa -3937.5 -1055 148 dmy 62 -292.5 -1055 47 dmy 24 -6997.5 -1055 98 v ssa -3892.5 -1055 149 osc 2 -157.5 -1055 48 dmy 25 -6952.5 -1055 99 dmy 48 -3757.5 -1055 150 osc 2 -112.5 -1055 49 csb -6907.5 -1055 100 d 8 -3712.5 -1055 151 v ss 22.5 -1055 50 csb -6862.5 -1055 101 d 8 -3667.5 -1055 152 v ss 67.5 -1055 51 dmy 26 -6817.5 -1055 102 d 9 -3532.5 -1055 153 v ss 112.5 -1055
NJU6818 -7 - pad coordinates 2 chip size 19250 m x 2500 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 154 v ss 157.5 -1055 205 v reg 2812.5 -1055 256 v ee 5467.5 -1055 155 v ss 202.5 -1055 206 v reg 2857.5 -1055 257 v ee 5512.5 -1055 156 v ss 247.5 -1055 207 v reg 2902.5 -1055 258 dmy 70 5647.5 -1055 157 v ss 292.5 -1055 208 v reg 2947.5 -1055 259 dmy 71 5692.5 -1055 158 v ss 337.5 -1055 209 v reg 2992.5 -1055 260 dmy 72 5737.5 -1055 159 v ss 382.5 -1055 210 v reg 3037.5 -1055 261 dmy 73 5782.5 -1055 160 dmy 63 517.5 -1055 211 v reg 3082.5 -1055 262 dmy 74 5827.5 -1055 161 v lcd 652.5 -1055 212 dmy 67 3127.5 -1055 263 c1+ 5872.5 -1055 162 v lcd 697.5 -1055 213 v ref 3172.5 -1055 264 c1+ 5917.5 -1055 163 v lcd 742.5 -1055 214 v ref 3217.5 -1055 265 c1+ 5962.5 -1055 164 v lcd 787.5 -1055 215 v ref 3262.5 -1055 266 c1+ 6007.5 -1055 165 v lcd 832.5 -1055 216 v ref 3307.5 -1055 267 c1+ 6052.5 -1055 166 v lcd 877.5 -1055 217 v ref 3352.5 -1055 268 dmy 75 6097.5 -1055 167 v lcd 922.5 -1055 218 v ref 3397.5 -1055 269 dmy 76 6142.5 -1055 168 v lcd 967.5 -1055 219 v ref 3442.5 -1055 270 c1- 6187.5 -1055 169 dmy 64 1012.5 -1055 220 v ref 3487.5 -1055 271 c1- 6232.5 -1055 170 v 1 1057.5 -1055 221 dmy 68 3532.5 -1055 272 c1- 6277.5 -1055 171 v 1 1102.5 -1055 222 v ba 3577.5 -1055 273 c1- 6322.5 -1055 172 v 1 1147.5 -1055 223 v ba 3622.5 -1055 274 c1- 6367.5 -1055 173 v 1 1192.5 -1055 224 v ba 3667.5 -1055 275 dmy 77 6412.5 -1055 174 v 1 1237.5 -1055 225 v ba 3712.5 -1055 276 dmy 78 6457.5 -1055 175 v 1 1282.5 -1055 226 v ba 3757.5 -1055 277 c2+ 6502.5 -1055 176 v 1 1327.5 -1055 227 v ba 3802.5 -1055 278 c2+ 6547.5 -1055 177 v 1 1372.5 -1055 228 v ba 3847.5 -1055 279 c2+ 6592.5 -1055 178 v 2 1507.5 -1055 229 v ba 3892.5 -1055 280 c2+ 6637.5 -1055 179 v 2 1552.5 -1055 230 dmy 69 3937.5 -1055 281 c2+ 6682.5 -1055 180 v 2 1597.5 -1055 231 v ssh 3982.5 -1055 282 dmy 79 6727.5 -1055 181 v 2 1642.5 -1055 232 v ssh 4027.5 -1055 283 dmy 80 6772.5 -1055 182 v 2 1687.5 -1055 233 v ssh 4072.5 -1055 284 c2- 6817.5 -1055 183 v 2 1732.5 -1055 234 v ssh 4117.5 -1055 285 c2- 6862.5 -1055 184 v 2 1777.5 -1055 235 v ssh 4162.5 -1055 286 c2- 6907.5 -1055 185 v 2 1822.5 -1055 236 v ssh 4207.5 -1055 287 c2- 6952.5 -1055 186 dmy 65 1867.5 -1055 237 v ssh 4252.5 -1055 288 c2- 6997.5 -1055 187 v 3 1912.5 -1055 238 v ssh 4297.5 -1055 289 dmy 81 7042.5 -1055 188 v 3 1957.5 -1055 239 v ssh 4342.5 -1055 290 dmy 82 7087.5 -1055 189 v 3 2002.5 -1055 240 v out 4567.5 -1055 291 c3+ 7132.5 -1055 190 v 3 2047.5 -1055 241 v out 4612.5 -1055 292 c3+ 7177.5 -1055 191 v 3 2092.5 -1055 242 v out 4657.5 -1055 293 c3+ 7222.5 -1055 192 v 3 2137.5 -1055 243 v out 4702.5 -1055 294 c3+ 7267.5 -1055 193 v 3 2182.5 -1055 244 v out 4747.5 -1055 295 c3+ 7312.5 -1055 194 v 3 2227.5 -1055 245 v out 4792.5 -1055 296 dmy 83 7357.5 -1055 195 v 4 2362.5 -1055 246 v out 4837.5 -1055 297 dmy 84 7402.5 -1055 196 v 4 2407.5 -1055 247 v out 4882.5 -1055 298 c3- 7447.5 -1055 197 v 4 2452.5 -1055 248 v out 4927.5 -1055 299 c3- 7492.5 -1055 198 v 4 2497.5 -1055 249 v ee 5152.5 -1055 300 c3- 7537.5 -1055 199 v 4 2542.5 -1055 250 v ee 5197.5 -1055 301 c3- 7582.5 -1055 200 v 4 2587.5 -1055 251 v ee 5242.5 -1055 302 c3- 7627.5 -1055 201 v 4 2632.5 -1055 252 v ee 5287.5 -1055 303 dmy 85 7672.5 -1055 202 v 4 2677.5 -1055 253 v ee 5332.5 -1055 304 dmy 86 7717.5 -1055 203 dmy 66 2722.5 -1055 254 v ee 5377.5 -1055 305 c4+ 7762.5 -1055 204 v reg 2767.5 -1055 255 v ee 5422.5 -1055 306 c4+ 7807.5 -1055
NJU6818 - 8 - pad coordinates 3 chip size 19250 m x 2500 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 307 c 4 + 7852.5 -1055 358 com 24 8257.5 1055 409 segc 7 5962.5 1055 308 c 4 + 7897.5 -1055 359 com 23 8212.5 1055 410 sega 8 5917.5 1055 309 c 4 + 7942.5 -1055 360 com 22 8167.5 1055 411 segb 8 5872.5 1055 310 dmy 87 7987.5 -1055 361 com 21 8122.5 1055 412 segc 8 5827.5 1055 311 dmy 88 8032.5 -1055 362 com 20 8077.5 1055 413 sega 9 5782.5 1055 312 c 4 - 8077.5 -1055 363 com 19 8032.5 1055 414 segb 9 5737.5 1055 313 c 4 - 8122.5 -1055 364 com 18 7987.5 1055 415 segc 9 5692.5 1055 314 c 4 - 8167.5 -1055 365 com 17 7942.5 1055 416 sega 10 5647.5 1055 315 c 4 - 8212.5 -1055 366 com 16 7897.5 1055 417 segb 10 5602.5 1055 316 c 4 - 8257.5 -1055 367 com 15 7852.5 1055 418 segc 10 5557.5 1055 317 dmy 89 8302.5 -1055 368 com 14 7807.5 1055 419 sega 11 5512.5 1055 318 dmy 90 8347.5 -1055 369 com 13 7762.5 1055 420 segb 11 5467.5 1055 319 c 5 + 8392.5 -1055 370 com 12 7717.5 1055 421 segc 11 5422.5 1055 320 c 5 + 8437.5 -1055 371 com 11 7672.5 1055 422 sega 12 5377.5 1055 321 c 5 + 8482.5 -1055 372 com 10 7627.5 1055 423 segb 12 5332.5 1055 322 c 5 + 8527.5 -1055 373 com 9 7582.5 1055 424 segc 12 5287.5 1055 323 c 5 + 8572.5 -1055 374 com 8 7537.5 1055 425 sega 13 5242.5 1055 324 dmy 91 8617.5 -1055 375 com 7 7492.5 1055 426 segb 13 5197.5 1055 325 dmy 92 8662.5 -1055 376 com 6 7447.5 1055 427 segc 13 5152.5 1055 326 c 5 - 8707.5 -1055 377 com 5 7402.5 1055 428 sega 14 5107.5 1055 327 c 5 - 8752.5 -1055 378 com 4 7357.5 1055 429 segb 14 5062.5 1055 328 c 5 - 8797.5 -1055 379 com 3 7312.5 1055 430 segc 14 5017.5 1055 329 c 5 - 8842.5 -1055 380 com 2 7267.5 1055 431 sega 15 4972.5 1055 330 c 5 - 8887.5 -1055 381 com 1 7222.5 1055 432 segb 15 4927.5 1055 331 dmy 93 8932.5 -1055 382 com 0 7177.5 1055 433 segc 15 4882.5 1055 332 dmy 94 8977.5 -1055 383 dmy 103 7132.5 1055 434 sega 16 4837.5 1055 333 dmy 95 9022.5 -1055 384 dmy 104 7087.5 1055 435 segb 16 4792.5 1055 334 dmy 96 9067.5 -1055 385 dmy 105 7042.5 1055 436 segc 16 4747.5 1055 335 dmy 97 9430 -964 386 sega 0 6997.5 1055 437 sega 17 4702.5 1055 336 dmy 98 9430 -919 387 segb 0 6952.5 1055 438 segb 17 4657.5 1055 337 dmy 98 9430 -874 388 segc 0 6907.5 1055 439 segc 17 4612.5 1055 338 dmy 98 9430 -829 389 sega 1 6862.5 1055 440 sega 18 4567.5 1055 339 dmy 99 9430 -784 390 segb 1 6817.5 1055 441 segb 18 4522.5 1055 340 dmy 100 9067.5 1055 391 segc 1 6772.5 1055 442 segc 18 4477.5 1055 341 dmy 101 9022.5 1055 392 sega 2 6727.5 1055 443 sega 19 4432.5 1055 342 dmy 102 8977.5 1055 393 segb 2 6682.5 1055 444 segb 19 4387.5 1055 343 com 39 8932.5 1055 394 segc 2 6637.5 1055 445 segc 19 4342.5 1055 344 com 38 8887.5 1055 395 sega 3 6592.5 1055 446 sega 20 4297.5 1055 345 com 37 8842.5 1055 396 segb 3 6547.5 1055 447 segb 20 4252.5 1055 346 com 36 8797.5 1055 397 segc 3 6502.5 1055 448 segc 20 4207.5 1055 347 com 35 8752.5 1055 398 sega 4 6457.5 1055 449 sega 21 4162.5 1055 348 com 34 8707.5 1055 399 segb 4 6412.5 1055 450 segb 21 4117.5 1055 349 com 33 8662.5 1055 400 segc 4 6367.5 1055 451 segc 21 4072.5 1055 350 com 32 8617.5 1055 401 sega 5 6322.5 1055 452 sega 22 4027.5 1055 351 com 31 8572.5 1055 402 segb 5 6277.5 1055 453 segb 22 3982.5 1055 352 com 30 8527.5 1055 403 segc 5 6232.5 1055 454 segc 22 3937.5 1055 353 com 29 8482.5 1055 404 sega 6 6187.5 1055 455 sega 23 3892.5 1055 354 com 28 8437.5 1055 405 segb 6 6142.5 1055 456 segb 23 3847.5 1055 355 com 27 8392.5 1055 406 segc 6 6097.5 1055 457 segc 23 3802.5 1055 356 com 26 8347.5 1055 407 sega 7 6052.5 1055 458 sega 24 3757.5 1055 357 com 25 8302.5 1055 408 segb 7 6007.5 1055 459 segb 24 3712.5 1055
NJU6818 -9 - ? ? ? ? pad coordinates 4 chip size 19250 m x 2500 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 460 segc 24 3667.5 1055 511 segc 41 1372.5 1055 562 segc 58 -922.5 1055 461 sega 25 3622.5 1055 512 sega 42 1327.5 1055 563 sega 59 -967.5 1055 462 segb 25 3577.5 1055 513 segb 42 1282.5 1055 564 segb 59 -1012.5 1055 463 segc 25 3532.5 1055 514 segc 42 1237.5 1055 565 segc 59 -1057.5 1055 464 sega 26 3487.5 1055 515 sega 43 1192.5 1055 566 sega 60 -1102.5 1055 465 segb 26 3442.5 1055 516 segb 43 1147.5 1055 567 segb 60 -1147.5 1055 466 segc 26 3397.5 1055 517 segc 43 1102.5 1055 568 segc 60 -1192.5 1055 467 sega 27 3352.5 1055 518 sega 44 1057.5 1055 569 sega 61 -1237.5 1055 468 segb 27 3307.5 1055 519 segb 44 1012.5 1055 570 segb 61 -1282.5 1055 469 segc 27 3262.5 1055 520 segc 44 967.5 1055 571 segc 61 -1327.5 1055 470 sega 28 3217.5 1055 521 sega 45 922.5 1055 572 sega 62 -1372.5 1055 471 segb 28 3172.5 1055 522 segb 45 877.5 1055 573 segb 62 -1417.5 1055 472 segc 28 3127.5 1055 523 segc 45 832.5 1055 574 segc 62 -1462.5 1055 473 sega 29 3082.5 1055 524 sega 46 787.5 1055 575 sega 63 -1507.5 1055 474 segb 29 3037.5 1055 525 segb 46 742.5 1055 576 segb 63 -1552.5 1055 475 segc 29 2992.5 1055 526 segc 46 697.5 1055 577 segc 63 -1597.5 1055 476 sega 30 2947.5 1055 527 sega 47 652.5 1055 578 sega 64 -1642.5 1055 477 segb 30 2902.5 1055 528 segb 47 607.5 1055 579 segb 64 -1687.5 1055 478 segc 30 2857.5 1055 529 segc 47 562.5 1055 580 segc 64 -1732.5 1055 479 sega 31 2812.5 1055 530 sega 48 517.5 1055 581 sega 65 -1777.5 1055 480 segb 31 2767.5 1055 531 segb 48 472.5 1055 582 segb 65 -1822.5 1055 481 segc 31 2722.5 1055 532 segc 48 427.5 1055 583 segc 65 -1867.5 1055 482 sega 32 2677.5 1055 533 sega 49 382.5 1055 584 sega 66 -1912.5 1055 483 segb 32 2632.5 1055 534 segb 49 337.5 1055 585 segb 66 -1957.5 1055 484 segc 32 2587.5 1055 535 segc 49 292.5 1055 586 segc 66 -2002.5 1055 485 sega 33 2542.5 1055 536 sega 50 247.5 1055 587 sega 67 -2047.5 1055 486 segb 33 2497.5 1055 537 segb 50 202.5 1055 588 segb 67 -2092.5 1055 487 segc 33 2452.5 1055 538 segc 50 157.5 1055 589 segc 67 -2137.5 1055 488 sega 34 2407.5 1055 539 sega 51 112.5 1055 590 sega 68 -2182.5 1055 489 segb 34 2362.5 1055 540 segb 51 67.5 1055 591 segb 68 -2227.5 1055 490 segc 34 2317.5 1055 541 segc 51 22.5 1055 592 segc 68 -2272.5 1055 491 sega 35 2272.5 1055 542 sega 52 -22.5 1055 593 sega 69 -2317.5 1055 492 segb 35 2227.5 1055 543 segb 52 -67.5 1055 594 segb 69 -2362.5 1055 493 segc 35 2182.5 1055 544 segc 52 -112.5 1055 595 segc 69 -2407.5 1055 494 sega 36 2137.5 1055 545 sega 53 -157.5 1055 596 sega 70 -2452.5 1055 495 segb 36 2092.5 1055 546 segb 53 -202.5 1055 597 segb 70 -2497.5 1055 496 segc 36 2047.5 1055 547 segc 53 -247.5 1055 598 segc 70 -2542.5 1055 497 sega 37 2002.5 1055 548 sega 54 -292.5 1055 599 sega 71 -2587.5 1055 498 segb 37 1957.5 1055 549 segb 54 -337.5 1055 600 segb 71 -2632.5 1055 499 segc 37 1912.5 1055 550 segc 54 -382.5 1055 601 segc 71 -2677.5 1055 500 sega 38 1867.5 1055 551 sega 55 -427.5 1055 602 sega 72 -2722.5 1055 501 segb 38 1822.5 1055 552 segb 55 -472.5 1055 603 segb 72 -2767.5 1055 502 segc 38 1777.5 1055 553 segc 55 -517.5 1055 604 segc 72 -2812.5 1055 503 sega 39 1732.5 1055 554 sega 56 -562.5 1055 605 sega 73 -2857.5 1055 504 segb 39 1687.5 1055 555 segb 56 -607.5 1055 606 segb 73 -2902.5 1055 505 segc 39 1642.5 1055 556 segc 56 -652.5 1055 607 segc 73 -2947.5 1055 506 sega 40 1597.5 1055 557 sega 57 -697.5 1055 608 sega 74 -2992.5 1055 507 segb 40 1552.5 1055 558 segb 57 -742.5 1055 609 segb 74 -3037.5 1055 508 segc 40 1507.5 1055 559 segc 57 -787.5 1055 610 segc 74 -3082.5 1055 509 sega 41 1462.5 1055 560 sega 58 -832.5 1055 611 sega 75 -3127.5 1055 510 segb 41 1417.5 1055 561 segb 58 -877.5 1055 612 segb 75 -3172.5 1055
NJU6818 - 10 - ? ? ? ? pad coordinates 5 chip size 19250 m x 2500 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 613 segc 75 -3217.5 1055 664 segc 92 -5512.5 1055 715 com 54 -7807.5 1055 614 sega 76 -3262.5 1055 665 sega 93 -5557.5 1055 716 com 55 -7852.5 1055 615 segb 76 -3307.5 1055 666 segb 93 -5602.5 1055 717 com 56 -7897.5 1055 616 segc 76 -3352.5 1055 667 segc 93 -5647.5 1055 718 com 57 -7942.5 1055 617 sega 77 -3397.5 1055 668 sega 94 -5692.5 1055 719 com 58 -7987.5 1055 618 segb 77 -3442.5 1055 669 segb 94 -5737.5 1055 720 com 59 -8032.5 1055 619 segc 77 -3487.5 1055 670 segc 94 -5782.5 1055 721 com 60 -8077.5 1055 620 sega 78 -3532.5 1055 671 sega 95 -5827.5 1055 722 com 61 -8122.5 1055 621 segb 78 -3577.5 1055 672 segb 95 -5872.5 1055 723 com 62 -8167.5 1055 622 segc 78 -3622.5 1055 673 segc 95 -5917.5 1055 724 com 63 -8212.5 1055 623 sega 79 -3667.5 1055 674 sega 96 -5962.5 1055 725 com 64 -8257.5 1055 624 segb 79 -3712.5 1055 675 segb 96 -6007.5 1055 726 com 65 -8302.5 1055 625 segc 79 -3757.5 1055 676 segc 96 -6052.5 1055 727 com 66 -8347.5 1055 626 sega 80 -3802.5 1055 677 sega 97 -6097.5 1055 728 com 67 -8392.5 1055 627 segb 80 -3847.5 1055 678 segb 97 -6142.5 1055 729 com 68 -8437.5 1055 628 segc 80 -3892.5 1055 679 segc 97 -6187.5 1055 730 com 69 -8482.5 1055 629 sega 81 -3937.5 1055 680 sega 98 -6232.5 1055 731 com 70 -8527.5 1055 630 segb 81 -3982.5 1055 681 segb 98 -6277.5 1055 732 com 71 -8572.5 1055 631 segc 81 -4027.5 1055 682 segc 98 -6322.5 1055 733 com 72 -8617.5 1055 632 sega 82 -4072.5 1055 683 sega 99 -6367.5 1055 734 com 73 -8662.5 1055 633 segb 82 -4117.5 1055 684 segb 99 -6412.5 1055 735 com 74 -8707.5 1055 634 segc 82 -4162.5 1055 685 segc 99 -6457.5 1055 736 com 75 -8752.5 1055 635 sega 83 -4207.5 1055 686 sega 100 -6502.5 1055 737 com 76 -8797.5 1055 636 segb 83 -4252.5 1055 687 segb 100 -6547.5 1055 738 com 77 -8842.5 1055 637 segc 83 -4297.5 1055 688 segc 100 -6592.5 1055 739 com 78 -8887.5 1055 638 sega 84 -4342.5 1055 689 sega 101 -6637.5 1055 740 com 79 -8932.5 1055 639 segb 84 -4387.5 1055 690 segb 101 -6682.5 1055 741 dmy 109 -8977.5 1055 640 segc 84 -4432.5 1055 691 segc 101 -6727.5 1055 742 dmy 110 -9022.5 1055 641 sega 85 -4477.5 1055 692 sega 102 -6772.5 1055 743 dmy 111 -9067.5 1055 642 segb 85 -4522.5 1055 693 segb 102 -6817.5 1055 744 dmy 112 -9430 -784 643 segc 85 -4567.5 1055 694 segc 102 -6862.5 1055 745 dmy 113 -9430 -829 644 sega 86 -4612.5 1055 695 sega 103 -6907.5 1055 746 dmy 113 -9430 -874 645 segb 86 -4657.5 1055 696 segb 103 -6952.5 1055 747 dmy 113 -9430 -919 646 segc 86 -4702.5 1055 697 segc 103 -6997.5 1055 748 dmy 114 -9430 -964 647 sega 87 -4747.5 1055 698 dmy 106 -7042.5 1055 749 648 segb 87 -4792.5 1055 699 dmy 107 -7087.5 1055 750 649 segc 87 -4837.5 1055 700 dmy 108 -7132.5 1055 751 650 sega 88 -4882.5 1055 701 com 40 -7177.5 1055 752 651 segb 88 -4927.5 1055 702 com 41 -7222.5 1055 753 652 segc 88 -4972.5 1055 703 com 42 -7267.5 1055 754 653 sega 89 -5017.5 1055 704 com 43 -7312.5 1055 755 654 segb 89 -5062.5 1055 705 com 44 -7357.5 1055 756 655 segc 89 -5107.5 1055 706 com 45 -7402.5 1055 757 656 sega 90 -5152.5 1055 707 com 46 -7447.5 1055 758 657 segb 90 -5197.5 1055 708 com 47 -7492.5 1055 759 658 segc 90 -5242.5 1055 709 com 48 -7537.5 1055 760 659 sega 91 -5287.5 1055 710 com 49 -7582.5 1055 761 660 segb 91 -5332.5 1055 711 com 50 -7627.5 1055 762 661 segc 91 -5377.5 1055 712 com 51 -7672.5 1055 763 662 sega 92 -5422.5 1055 713 com 52 -7717.5 1055 764 663 segb 92 -5467.5 1055 714 com 53 -7762.5 1055 765
NJU6818 - 11 - block diagram rs p/s sel68 csb wrb rdb resb v dda v dd v lcd , v 1 -v 4 v out v ba v ee mpu interface bus holder internal bus x address decoder display timing generator display data ram (dd ram) 80x104x(4+4+4)bit segment driver clk fr flm cl common driver 5 c 1 - c 1 + c 2 + c 2 - v ref c 3 + c 3 - c 4 + c 4 - sega 0 segb 0 segc 0 sega 103 segb 103 segc 103 com 79 gradation circuit data latch circuit shift register x address counter x address register d 7 d 4 /spol d 6 d 15 d 14 d 13 d 12 d 5 d 11 d 10 d 9 d 8 d 3 /smode d 0 /scl d 2 d 1 /sda ram interface pole control instruction decoder osc 1 c 5 + c 5 - register read control oscillator v ssa osc 2 v reg voltage regulator voltage booster sega 1 segb 1 segc 1 sega 102 segb 102 segc 102 com 0 v ss v ssh line counter line address decoder y address decoder initial display line register y address register y address counter i/o buffer chip identification id0 id1 id2 id3
NJU6818 - 12 - power supply circuits block diagram v ba v ref v out v ee voltage booster c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v reg + - + - + - + - + - reference voltage generator boost level register evr register v 1 v 2 v 3 v 4 v lcd + - gain control (1x-6x) + - voltage regulator e.v.r 1/2v reg
NJU6818 - 13 - terminal description 1 no. symbol i/o function 123~131 v dd power power supply for logic circuits 151~159 v ss power gnd for logic circuits 231~239 v ssh power gnd for high voltage circuits 4,5 33,34 67,68 v dda power this terminal is internally connected to the v dd level. ? this terminal is used to fix the selection terminals to the v dd level. note) do not use this terminal for a main power supply. 26,27 40,41 97,98 v ssa power this terminal is internally connected to the v ss level. ? this terminal is used to fix the selection terminals to the v ss level. note) do not use this terminal for a main gnd. 161~168 170~177 178~185 187~194 195~202 v lcd v 1 v 2 v 3 v 4 power/o lcd driving voltages ? when the internal voltage booster is not used, the external lcd driving voltages (v 1 to v 4 and v lcd ) must be supplied on these terminals. and the external voltages must be maintained with the following relation. v ss NJU6818 can read id data, which is determined by fixing id 3 , id 2 , id 1 and id 0 pins to ?1? or ?0?.
NJU6818 - 14 - terminal description 2 no. symbol i/o function 74,75 d 0 /scl i/o 76,77 d 1 /sda i/o 82,83 d 3 /smode i/o 86,87 d 4 /spol i/o 80.81 88,89 92,93 94,95 d 2 d 5 d 6 d 7 i/o parallel interface: d 7 to d 0 : 8-bit bi-directional bus ? in the parallel interface mode (p/s=?1?), these terminals connect to 8-bit bi-directional mpu bus. serial interface: sda : serial data scl : serial clock smode : 3-/4-line serial interface mode selection spol : rs polarity selection (in the 3-line serial interface mode) ? in the 3-/4-line serial interface mode (p/s=?0?), the d0 terminal is assigned to the scl, and the d 1 terminal to the sda. ? in the 3-line serial interface mode, the d 4 terminal is assigned to the spol. ? serial data on the sda is fetched at the rising edge of the scl signal in the order of the d 7 , d 6 ?d 0 , and the fetched data is converted into 8-bit parallel data at the falling edge of the 8th scl signal. ? the scl signal must be set to ?0? after data transmissions or during non-access. 100,101 102,103 106,107 108,109 112,113 114,115 118,119 120,121 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 i/o 8-bit bi-directional bus ? in the 16-bit data bus mode, these terminals are assigned to the upper 8-bit data bus. ? in the serial interface mode or the 8-bit data bus mode of the parallel interface, these terminals must be fixed to ?1? or ?0?. 49,50 csb i chip select active ?0? resister select ? this signal distinguishes transferred data as an instruction or display data as follows. rs h l distinct. instruction display data 53,54 rs i 63,64 rdb (e) i 80 series mpu interface (p/s=?1?, sel68=?0?) rdb signal. active ?0?. 68 series mpu interface (p/s=?1?, sel68=?1?) enable signal. active ?1?. 80 series mpu interface (p/s=?1?, sel68=?0?) wrb signal. active ?0?. 68 series mpu interface (p/s=?1?, sel68=?1?) r/w signal. r/w h l status read write 59,60 wrb (r/w) i
NJU6818 - 15 - terminal description 3 no. symbol i/o function parallel / serial interface mode selection p/s chip select data/ instruction data read/ write serial clock h csb rs d 0 ~ d 7 rdb, wrb - l csb rs sda (d1) write only scl (d0) 37,38 p/s i ? since the d 15 to d 5 and d 2 terminals are in high impedance in the serial interface mode (p/s=?0?), they must be fixed to ?1? or ?0?. the rdb and wrb terminals also must be ?1? or ?0?. 133,134 cl o this terminal must be opened. 135,136 flm o this terminal must be opened. 139,140 fr o this terminal must be opened. 141,142 clk o this terminal must be opened. 145,146 149,150 osc 1 osc 2 i o osc ? when the internal oscillator clock is used, the osc 1 terminal must be fixed to ?1? or ?0?, and the osc 2 terminal must be opened. when the oscillation frequency from the internal oscillator is adjusted by an external resistor between osc 1 terminal and osc 2 . ? when an external oscillator is used, external clock is input to the osc 1 terminal, or an external resistor is connected between the osc 1 and osc 2 terminals. segment output rev mode turn-off turn-on normal 0 1 reverse 1 0 ? these terminals output lcd driving waveforms in accordance with the combination of the fr signal and display data. in the b/w mode fr signal display data normal display mode v 2 v lcd v 3 v ss reverse display mode v lcd v 2 v ss v 3 386~697 sega 0 ~sega 103 , segb 0 ~ segb 103 , segc 0 ~ segc 103 o common output ? these terminals output lcd driving waveforms in accordance with the combination of the fr signal and scanning data. data fr output level h h v ss l h v 1 h l v lcd l l v 4 343~382 701~740 com 0 ~ com 79 o (terminal no. 1~3,6, 9~12, 15, 16, 19~22, 25, 28, 31, 32, 35, 36, 39, 42, 45~48, 51, 52, 55~58, 61, 62, 65, 66, 69~73, 78, 79, 84, 85, 90, 91, 96, 99, 104, 105, 110, 111, 116, 117, 122, 132, 137, 138, 143, 144, 147, 148, 160, 169, 186, 203, 212, 221, 230, 258~262, 2 68, 269, 275, 276, 282, 283, 289, 290, 296, 297, 303, 304, 310, 311, 317, 318, 324, 325, 331~342, 383~385, 698~700, 741~748 are dummy.)
NJU6818 - 16 - functional description (1) mpu interface (1-1) selection of parallel / serial interface mode the p/s terminal is used to select the parallel or serial interface mode, as shown in the following table. in the serial interface mode, it is not possible to read out display data from the ddram or status data from the internal registers. table 1 p/s p/s mode csb rs rdb wrb sel68 sda scl data h parallel i/f csb rs rdb wrb sel68 d7-d0 (d15-d0) l serial i/f csb rs - - - sda scl - note 1) ? -? : fix to ?1? or ?0?. (1-2) selection of mpu interface type in the parallel interface mode, the sel68 terminal is used to select 68- or 80-series mpu interface type, as shown in the following table. table 2 sel68 mpu type csb rs rdb wrb data h 68 series mpu csb rs e r/w d7-d0 (d15-d0) l 80 series mpu csb rs rdb wrb d7-d0 (d15-d0) (1-3) data distinction in the parallel interface mode, the combination of the rs, rdb and wrb (r/w) signals distinguishes transferred data between the lsi and mpu as instruction or display data, as shown in the following table. table 3 68 series 80 series rs r/w rdb wrb function h h l h read out instruction data h l h l write instruction data l h l h read out display data l l h l write display data (1-4) selection of serial interface mode in the serial interface mode, the smode terminal is used to select the 3- or 4-line serial interface mode, as shown in the following table. table 4 smode serial interface mode h 3-line l 4-line
NJU6818 - 17 - (1-5) 4-line serial interface mode in the 4-line serial interface mode, when the chip select is active (csb=?0?), the sda and the scl are enabled. when the chip select is not active (csb=?1?), the sda and the scl are disabled, and the internal shift register and the counter are being initialized. 8-bit serial data on the sda is fetched at the rising edge of the scl signal (serial clock) in order of the d 7 , d 6 ?d 0 , and the fetched data is converted into 8-bit parallel data at the rising edge of the 8th scl signal. in the 4-line serial interface mode, transferred data on the sda is distinguished as display data or instruction data in accordance with the condition of the rs signal. table 5 rs data distinction h instruction data l display data since the serial interface operation is sensitive to external noises, the scl should be set to ?0? after data transmissions or during non-access. to release a mal-function caused by the external noises, the chip-selected status should be released (csb=?1?) after each of 8-bit data transmissions. the following figure illustrates the interface timing of the 4-line serial interface operation. fig 1 4-line serial interface timing (1-6) 3-line serial interface mode in the 3-line serial interface mode, when the chip select is active (csb=?0?), the sda and the scl are enabled. when the chip select is not active (csb=?1?), the sda and the scl are disabled, and the internal shift register and counter are being initialized. 9-bit serial data on the sda is fetched at the rising edge of the scl signal in order of the rs, d 7 , d 6 ?d 0 , and the fetched data is converted into 9-bit parallel data at the rising edge of the 9th scl signal. in the 3-line serial interface mode, data on the sda is distinguished as display data or instruction data in accordance with the condition of the rs bit of the sda data and the status of the spol, as follows. table 6 spol=l spol=h rs data distinction rs data distinction l display data l instruction data h instruction data h display data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 valid 1 2 3 4 5 6 7 8 csb rs sda scl
NJU6818 - 18 - since the serial interface operation is sensitive to external noises, the scl must be set to ?0? after data transmissions or during non-access. to release a mal-function caused by the external noises, the chip-selected status should be released (csb=?1?) after each of 9-bit data transmissions. the following figure illustrates the interface timing of the 3-line serial interface operation. fig 2 3-line serial interface timing rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 1 2 3 4 5 6 7 8 csb sda scl d 0 9
NJU6818 - 19 - (2) access to the ddram when the csb signal is ?0?, transferred data from mpu is written into the ddram or the instruction register in accordance with the condition of the rs signal. when the rs signal is ?1?, the transferred data is distinguished as display data. after the ?column address? and ?row address? instructions are executed, display data can be written into the ddram by the ?display data write? instruction. the display data is written at the rising edge of the wrb signal in the 80 series mpu mode, or at the falling edge of the e signal in the 68 series mpu mode. table 6 rs data distinction l display ram data h internal command register in the sequence of the ?display data read? operation, transferred data from mpu is temporarily held in the internal bus-holder, then transferred to the internal data-bus. when the ?display data read? operation is executed just after the ?column address? and ?row address? instructions or ?display data write? instruction, unexpected data on the bus-holder is read out at the 1st execution, then the data of designated ddram address is read out from the 2nd execution. for this reason, a dummy read cycle must be executed to avoid the unexpected 1st data read. display data write operation display data read operation fig 3 note) in the 16-bit data bus mode, instruction data must be 16-bit as well as the display data. n n+2 d 0 to d 15 wrb bus holder wrb n n+1 n+2 n+3 n+4 n+1 n+3 n+4 internal d 0 to d 7 (d 0 to d 15 ) rdb n n n+1 n+2 wrb address set n dummy read data read n address data read n+1 address data read n+2 address
NJU6818 - 20 - (3) access to the instruction register each instruction resisters is assigned to each address between 0 h and f h , and the content of the instruction register can be read out by the combination of the ?instruction resister address? and ?instruction resister read?. fig 4 (4) 8-/16-bit data bus length for display data (in the parallel interface mode) the 8- or 16-bit data bus length for display data is determined by the ?wls? of the ?data bus length? instruction. in the 16-bit data bus mode, instruction data must be 16-bit (d 15 to d 0 ) as well as display data. however, for the access to the instruction register, the only lower 8-bit data (d 7 to d 0 ) of 16-bit data is valid. for the access to the ddram, all of the 16-bit data (d 15 to d 0 ) is valid. table 8 wls data bus length mode l 8-bit h 16-bit (5) initial display line register the initial display line resister specifies the line address, corresponding to the initial com line, by the ?initial display line? instruction. the initial com line signifies the common driver, starting scanning the display data in the ddram, and specified by the ?initial com line? instruction. the line address, established in the initial display line resister, is preset into the line counter whenever the flm signal becomes ?1?. at the rising edge of the cl signal, the line counter is counted-up and addressed 312-bit display data, corresponding to the counted-up line address, is latched into the data latch circuit. at the falling edge of the cl signal, the latched data outputs to the segment drivers. d 0 to d 7 m n wrb instruction resister address set instruction resister contents read mn rdb instruction resister address set instruction resister contents read
NJU6818 - 21 - (6) ddram mapping the ddram is capable of 1,248-bit (12-bit x 104-segment) for the column address and 80-bit for the row address. in the gradation mode, each pixel for rgb corresponds to successive 3-segment drivers, and each segment driver has 16-gradation. therefore, the lsi can drive up to 104x80 pixels in 4096-color display (16-gradation x 16- gradation x 16-gradation). in the b&w mode, only msb data from each 4-bit display data group in the ddram is used. therefore, 312x80 pixels in the b&w and 104x80 pixels in the 8-gradiation are available. the range of the column address varies depending on data bus length. the range between 00 h and cf h is used in the 8-bit data bus length, and the range between 00 h and 67 h is in the 16-bit data bus length. in the 8-bit data bus length mode column-address 0 h 1 h ce h cf h 0 h 7bit 5bit 7bit 5bit row-address 4f h 7bit 5bit 7bit 5bit column-address abs=?1? 0 h 1 h ce h cf h 0 h 4bit 8bit 4bit 8bit row-address 4f h 4bit 8bit 4bit 8bit column-address hsw=?1? 0 h 1 h 9a h 9b h 0 h 8bit 8bit 8bit 8bit row-address 4f h 8bit 8bit 8bit 8bit column-address c256=?1? 0 h 1 h 66 h 67 h 0 h 8bit 8bit 8bit 8bit row-address 4f h 8bit 8bit 8bit 8bit fig 5
NJU6818 - 22 - in the 16-bit data bus length mode column-address 0 h 67 h 0 h 12bit 12bit row-address 4f h 12bit 12bit fig 6 the increments for the column address and row address are set to the auto-increment mode by programming the ?axi? and ?ayi? registers of the ?increment control? instruction. in this mode, the contents of the column address and row address counters automatically increment whenever the ddram is accessed. the column address and row address counters, independent of the line counter. they are used to designate the column and row addresses for the display data transferred from mpu. on the other hand, the line counter is used to generate the line address, and output display data to the segment drivers, being synchronized with the display control timing of the flm and cl signals.
NJU6818 - 23 - (7) window addressing mode in addition to the above usual ddram addressing, it is possible to access some part of ddram in using the window addressing mode, in which the start and end points are designated. the start point is determined by the ?column address? and ?row address? instructions, and the end point is determined by the ?window end column address ?and ?window end row address? instructions. the setting example of the window addressing is listed, as follows. 1. set win=1, axi=1, and ayi=1 by the ?increment control? instruction 2. set the start point by the ?column address? and ?row address? instructions 3. set the end point by the ?window end column address? and ?window end row address? instructions 4. enable to access to the ddram in the window addressing mode in the window addressing mode (win=1, axi=1, ayi=1), the read-modify-write operation is available by setting ?0? to the ?aim? register of the ?increment control? instruction. and in the window addressing mode, the following relation for the start and end points must be maintained to avoid a malfunction. ax (column address of start point) < ex (column address of the end point) < maximum of column address ay (row address of start point) < ey (row address of the end point) < maximum of row address column address (x, y) start point end point row address window display area (x, y) whole ddram area fig 7 (8) reverse display on/off the ?reverse display on/off? function is used to reverse the display data without changing the contents of the ddram. table 9 rev display ddram data display data 0 0 0 normal 1 1 0 1 1 reverse 1 0 (9) segment direction the ?segment direction? function is used to reverse the assignments for the segment drivers and the column addresses, and it is possible to reduce restrictions for the placement of the lsi on lcd modules.
NJU6818 - 24 - 1 0 1 0 0 1 1 0 a3 a2 a1 a0 b3 b2 b1 b0 c3 c2 c1 c0 segax swap segax segbx segcx palette a palette b palette c ref swap segcx segbx note1) in the 256-color mode, the vacant lsb bit is filled with "1". note2) the function of 256-color mode is different from that of fixed 8-gradation mode (fixed 256-color mode). note3) the written data in the dd ram in "c256"=0 is not compatible with the data in "c256"=1. note4) in the 256-color mode, only 8-bit length mode is available, but 16-bit is not. d3 d7 d3 d3 d7 d7 d11 d11 d15 d15 a3 d2 d6 d2 d2 d6 d6 d10 d10 d14 d14 a2 d1 d5 d1 d1 d5 d5 d9 d9 d13 d13 a1 d0 d4 d0 d0 d4 d4 d8 d8 d12 d12 a0 d7 d3 d7 d7 d2 d2 d7 d7 d10 d10 b3 d6 d2 d6 d6 d1 d1 d6 d6 d9 d9 b2 d5 d1 d5 d5 d0 d0 d5 d5 d8 d8 b1 d4 d0 d4 d4 d7 d7 d4 d4 d7 d7 b0 d3 d7 d3 d3 d4 d4 d3 d3 d4 d4 c3 d2 d6 d2 d2 d3 d3 d2 d2 d3 d3 c2 d1 d5 d1 d1 d2 d2 d1 d1 d2 d2 c1 d0 d4 d0 d0 d1 d1 d0 d0 d1 d1 c0 d7 d3 d3 d3 d7 d7 d11 d11 d15 d15 a3 d6 d2 d2 d2 d6 d6 d10 d10 d14 d14 a2 d5 d1 d1 d1 d5 d5 d9 d9 d13 d13 a1 d4 d0 d0 d0 d4 d4 d8 d8 d12 d12 a0 d3 d7 d7 d7 d2 d2 d7 d7 d10 d10 b3 d2 d6 d6 d6 d1 d1 d6 d6 d9 d9 b2 d1 d5 d5 d5 d0 d0 d5 d5 d8 d8 b1 d0 d4 d4 d4 d7 d7 d4 d4 d7 d7 b0 d7 d3 d3 d3 d4 d4 d3 d3 d4 d4 c3 d6 d2 d2 d2 d3 d3 d2 d2 d3 d3 c2 d5 d1 d1 d1 d2 d2 d1 d1 d2 d2 c1 d4 d0 d0 d0 d1 d1 d0 d0 d1 d1 c0 d3 d7 d3 d3 d7 d7 d11 d11 d15 d15 a3 d2 d6 d2 d2 d6 d6 d10 d10 d14 d14 a2 d1 d5 d1 d1 d5 d5 d9 d9 d13 d13 a1 d0 d4 d0 d0 d4 d4 d8 d8 d12 d12 a0 d7 d3 d7 d7 d2 d2 d7 d7 d10 d10 b3 d6 d2 d6 d6 d1 d1 d6 d6 d9 d9 b2 d5 d1 d5 d5 d0 d0 d5 d5 d8 d8 b1 d4 d0 d4 d4 d7 d7 d4 d4 d7 d7 b0 d3 d7 d3 d3 d4 d4 d3 d3 d4 d4 c3 d2 d6 d2 d2 d3 d3 d2 d2 d3 d3 c2 d1 d5 d1 d1 d2 d2 d1 d1 d2 d2 c1 d0 d4 d0 d0 d1 d1 d0 d0 d1 d1 c0 d7 d3 d3 d3 d7 d7 d11 d11 d15 d15 a3 d6 d2 d2 d2 d6 d6 d10 d10 d14 d14 a2 d5 d1 d1 d1 d5 d5 d9 d9 d13 d13 a1 d4 d0 d0 d0 d4 d4 d8 d8 d12 d12 a0 d3 d7 d7 d7 d2 d2 d7 d7 d10 d10 b3 d2 d6 d6 d6 d1 d1 d6 d6 d9 d9 b2 d1 d5 d5 d5 d0 d0 d5 d5 d8 d8 b1 d0 d4 d4 d4 d7 d7 d4 d4 d7 d7 b0 d7 d3 d3 d3 d4 d4 d3 d3 d4 d4 c3 d6 d2 d2 d2 d3 d3 d2 d2 d3 d3 c2 d5 d1 d1 d1 d2 d2 d1 d1 d2 d2 c1 d4 d0 d0 d0 d1 d1 d0 d0 d1 d1 c0 mode ram map 1 0 0 1 1 wls 0 8bit 0 0 0 abs 0 0 0 0 10 1 x=ceh x=00h x=67h x=00h x=cfh x=01h x=00h x=01h x=ceh x=cfh x=cch x=cdh palette c x=02h x=66h x=01h palette a x=00h x=67h palette a seg1 palette b x=03h palette c seg102 palette b x=cdh palette c x=cch x=01h x=66h seg103 palette b x=cfh palette c x=ceh x=00h x=67h 11 0 palette a palette a 256 seg0 palette b x 1 00 x x 0 ref 16bit x=01h x=66h 1 1 0 0 hsw x x=66h x=01h x=67h x=00h 01 0 0 0 1010 00 x100 0 0 1 1 x x=cch x=cdh x=02h x=03h x=02h x=03h x=00h x=ceh x=02h x=03h x=cch x=cdh x=01h x=cfh x=00h x=01h x=00h x=01h x=02h x=99h x=9ah x=9bh x=9ah(l) x=9bh x=99h x=9ah(h) x=01h(l) x=02h x=00h x=01h(h) - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 seg103 palette b x=01h x=00h palette c x=67h palette a x=66h x 1 x 0 1 x=67h x=66h hsw ref seg1 palette b palette c x=01h palette a seg102 palette b palette c palette a 1 256 x=00h palette a seg0 palette b palette c mode ram map 2 (256 color mode) 0 wls x abs 8bit 0x
NJU6818 - 25 - (10) the relation among the ddram column address, display data, and segment drivers in the color mode and 16-bit data bus mode hsw abs ref swap column address / bit / segment assign * 0 0 0 x=00 h x=67 h * 0 1 1 x=67 h x=00 h d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 103 segb 103 segc 103 hsw abs ref swap column address / bit / segment assign * 0 0 1 x=00 h x=67 h * 0 1 0 x=67 h x=00 h d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 103 segb 103 sega 103 hsw abs ref swap column address / bit / segment assign * 1 0 0 x=00 h x=67 h * 1 1 1 x=67 h x=00 h d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 103 segb 103 segc 103 hsw abs ref swap column address / bit / segment assign * 1 0 1 x=00 h x=67 h * 1 1 0 x=67 h x=00 h d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 103 segb 103 sega 103
NJU6818 - 26 - in the color mode and 8-bit data bus mode hsw abs ref swap column address / bit / segment assign 0 0 0 0 x=00 h x=01 h x=ce h x=cf h 0 0 1 1 x=ce h x=cf h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 103 segb 103 segc 103 hsw abs ref swap column address / bit / segment assign 0 0 0 1 x=00 h x=01 h x=ce h x=cf h 0 0 1 0 x=ce h x=cf h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 103 segb 103 sega 103 hsw abs ref swap column address / bit / segment assign 0 1 0 0 x=00 h x=01 h x=ce h x=cf h 0 1 1 1 x=ce h x=cf h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 103 segb 103 segc 103 hsw abs ref swap column address / bit / segment assign 0 1 0 1 x=00 h x=01 h x=ce h x=cf h 0 1 1 0 x=ce h x=cf h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 103 segb 103 sega 103
NJU6818 - 27 - 1 hsw 1 hsw 1 hsw 1 hsw * abs * abs * abs * abs 1 ref 1 ref 0 ref 0 ref 1 swa p 0 swa p 1 swa p 0 swa p d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 palette c x=01h sega 103 palette c segc 103 palette c x=01h sega 103 x=9bh segb 103 palette b x=9bh segc 103 palette c palette a x=00h segc 103 palette a palette b segb 103 palette b sega 103 palette a x=00h segc 103 segb 103 palette b segb 103 x=9ah segc 102 palette c x=9ah sega 103 palette a palette b x=02h segb 102 palette b palette c sega 102 palette c segb 102 palette b x=02h segb 102 segc 102 palette c sega 102 x=99h sega 102 palette a x=99h segb 102 palette b palette a x=01h segc 102 palette a sega 102 palette a x=01h segc 102 segc 1 palette c palette b x=02h segc 1 palette c x=9ah sega 1 palette c x=9ah sega 1 palette c palette a sega 1 palette a segb 1 palette b segb 1 palette b segb 1 palette b x=02h palette a x=99h segc 1 palette a sega 0 palette a x=00h column-address / bit / segment assign segb 0 palette b segc 0 palette c x=01h segb 1 segc 0 palette a x=00h column-address / bit / segment assign segb 0 palette b sega 0 palette c x=01h segc 1 segc 0 palette a x=9ah column-address / bit / segment assign segb 0 palette b x=9bh sega 0 palette c x=99h sega 0 palette a x=9ah column-address / bit / segment assign segb 0 palette b x=9bh segc 0 palette c sega 1
NJU6818 - 28 - in the color mode, 8-bit data bus mode, and c256 mode (c256=1) hsw abs ref swap column address / bit / segment assign * * 0 0 x=00 h x=67 h * * 1 1 x=67 h x=00 h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 103 segb 103 segc 103 hsw abs ref swap column address / bit / segment assign * * 0 1 x=00 h x=67 h * * 1 0 x=67 h x=00 h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 103 segb 103 sega 103
NJU6818 - 29 - in the b&w mode and 16-bit data bus mode hsw abs ref swap column address / bit / segment assign * 0 0 0 x=00 h x=67 h * 0 1 1 x=67 h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 103 segb 103 segc 103 hsw abs ref swap column address / bit / segment assign * 0 0 1 x=00 h x=67 h * 0 1 0 x=67 h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 103 segb 103 sega 103 hsw abs ref swap column address / bit / segment assign * 1 0 0 x=00 h x=67 h * 1 1 1 x=67 h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 103 segb 103 segc 103 hsw abs ref swap column address / bit / segment assign * 1 0 1 x=00 h x=67 h * 1 1 0 x=67 h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 103 segb 103 sega 103
NJU6818 - 30 - in the b&w mode and 8-bit data bus mode hsw abs ref swap column address / bit / segment assign 0 0 0 0 x=00 h x=01 h x=ce h x=cf h 0 0 1 1 x=ce h x=cf h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 sega 0 segb 0 segc 0 sega 103 segb 103 segc 103 hsw abs ref swap column address / bit / segment assign 0 0 0 1 x=00 h x=01 h x=ce h x=cf h 0 0 1 0 x=ce h x=cf h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 segc 0 segb 0 sega 0 segc 103 segb 103 sega 103 hsw abs ref swap column address / bit / segment assign 0 1 0 0 x=00 h x=01 h x=ce h x=cf h 0 1 1 1 x=ce h x=cf h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 103 segb 103 segc 103 hsw abs ref swap column address / bit / segment assign 0 1 0 1 x=00 h x=01 h x=ce h x=cf h 0 1 1 0 x=ce h x=cf h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 103 segb 103 sega 103
NJU6818 - 31 - 1 hsw 1 hsw 1 hsw 1 hsw * abs * abs * abs * abs 1 ref 1 ref 0 ref 0 ref 1 swa p 0 swa p 1 swa p 0 swa p d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 sega 0 x=9ah column-address / bit / segment assign segc 0 x=9ah column-address / bit / segment assign segc 0 x=00h segb 0 x=00h column-address / bit / segment assign segb 0 x=01h segb 0 x=9bh segb 0 x=9bh segc 0 sega 0 sega 0 x=01h segc 0 segb 1 segb 1 segc 1 sega 1 sega 1 x=99h segc 1 x=99h column-address / bit / segment assign sega 0 segb 1 x=02h segb 1 x=02h sega 1 segc 1 segc 1 x=9ah sega 1 x=9ah sega 102 x=01h segc 102 x=01h segc 102 x=99h sega 102 x=99h segc 102 sega 102 segb 102 segb 102 segb 102 x=02h segb 102 x=02h sega 102 x=9ah segc 102 x=9ah segc 103 sega 103 sega 103 x=00h segc 103 x=00h segb 103 segb 103 segb 103 x=9bh segb 103 x=9bh sega 103 segc 103 segc 103 x=01h sega 103 x=01h
NJU6818 - 32 - bit assignments between write and read data (in the 16-bit data bus mode) abs=0 write data d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 15 d 14 d 13 d 12 * d 10 d 9 d 8 d 7 * * d 4 d 3 d 2 d 1 * abs=1 write data d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data * * * * d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 examples of write and read data (in the 8 bit bus mode) abs=0, hsw=0, c256=0 (address; 00, 02??cc,ce h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 * d 2 d 1 d 0 abs=0, hsw=0, c256=0 (address; 01,03 h ??cd,cf h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 * * d 4 d 3 d 2 d 1 1 abs=1, hsw=0, c256=0 (address; 00, 02??cc,ce h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data * * * * d 3 d 2 d 1 d 0 abs=1, hsw=0, c256=0 (address; 01,03 h ?? cd,cf h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 abs=0, hsw=1, c256=0 (address; 00, 01??9a,9b h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 abs=0, hsw=0, c256=1 (address; 00, 01?? 66 ,67 h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 *: invalid data
NJU6818 - 33 - (11) gradation palette in the gradation mode, either variable or fixed gradation mode is selected by programming the ?pwm? register of the ?gradation control? instruction. pwm=0: variable gradation mode (select 16-gradation level out of 32-gradation level of the gradation palette) pwm=1: fixed gradation mode (fixed 8-gradation level) in these modes, each of the gradation palettes of the aj, bj and cj can select 16-gradation level out of 32- gradation level by setting 5-bit data to the ?pa? registers in the ?gradation palette j? instructions (j=0 to fh). for instance, the gradation palettes aj correspond to the segai, the bj to the segbj, and the cj to the segci (j=0 to 15, i=0 to 103).
NJU6818 - 34 - correspondence between display data and gradation palettes table 10 (palette aj, palette bj, palette cj (j=0 to 15)) (msb) display data (lsb) gradation palette default palette value 0 0 0 0 palette 0 0 0 0 0 0 0 0 0 1 palette 1 0 0 0 1 1 0 0 1 0 palette 2 0 0 1 0 1 0 0 1 1 palette 3 0 0 1 1 1 0 1 0 0 palette 4 0 1 0 0 1 0 1 0 1 palette 5 0 1 0 1 1 0 1 1 0 palette 6 0 1 1 0 1 0 1 1 1 palette 7 0 1 1 1 1 1 0 0 0 palette 8 1 0 0 0 1 1 0 0 1 palette 9 1 0 0 1 1 1 0 1 0 palette10 1 0 1 0 1 1 0 1 1 palette11 1 0 1 1 1 1 1 0 0 palette12 1 1 0 0 1 1 1 0 1 palette13 1 1 0 1 1 1 1 1 0 palette14 1 1 1 0 1 1 1 1 1 palette15 1 1 1 1 1 gradation palette table (variable gradation mode, pwm=?0?, mon=?0?) table 11 (palette aj, palette bj, palette cj (j=0 to 15)) palette value gradation level gradation palette palette value gradation level gradation palette 0 0 0 0 0 0 palette 0(default) 1 0 0 0 0 16/31 0 0 0 0 1 1/31 1 0 0 0 1 17/31 palette 8(default) 0 0 0 1 0 2/31 1 0 0 1 0 18/31 0 0 0 1 1 3/31 palette 1(default) 1 0 0 1 1 19/31 palette 9(default) 0 0 1 0 0 4/31 1 0 1 0 0 20/31 0 0 1 0 1 5/31 palette 2(default) 1 0 1 0 1 21/31 palette 10(default) 0 0 1 1 0 6/31 1 0 1 1 0 22/31 0 0 1 1 1 7/31 palette 3(default) 1 0 1 1 1 23/31 palette 11(default) 0 1 0 0 0 8/31 1 1 0 0 0 24/31 0 1 0 0 1 9/31 palette 4(default) 1 1 0 0 1 25/31 palette 12(default) 0 1 0 1 0 10/31 1 1 0 1 0 26/31 0 1 0 1 1 11/31 palette 5(default) 1 1 0 1 1 27/31 palette 13(default) 0 1 1 0 0 12/31 1 1 1 0 0 28/31 0 1 1 0 1 13/31 palette 6(default) 1 1 1 0 1 29/31 palette 14(default) 0 1 1 1 0 14/31 1 1 1 1 0 30/31 0 1 1 1 1 15/31 palette 7(default) 1 1 1 1 1 31/31 palette 15(default)
NJU6818 - 35 - gradation palette table (fixed gradation mode, pwm=?1?, mon=?0?) table 12 8-gradation segment drivers (msb) display data (lsb) gradation level (msb) display data (lsb) gradation level 0 0 0 * 0/7 0 0 * * 0 0 1 * 1/7 0 0 * * 0/7 0 1 0 * 2/7 0 1 * * 0 1 1 * 3/7 0 1 * * 3/7 1 0 0 * 4/7 1 0 * * 1 0 1 * 5/7 1 0 * * 5/7 1 1 0 * 6/7 1 1 * * 1 1 1 * 7/7 1 1 * * 7/7 correspondence between display data and gradation level (b&w mode, mon=?1?) table 13 (msb) display data (lsb) gradation level 0 * * * 0 1 * * * 1 *:don?t care
NJU6818 - 36 - (12) gradation control and display data (12-1) gradation mode in the graduation mode, each pixel for rgb corresponds to successive 3 segment-drivers, and each segment driver provides 16-gradation pwm output by controlling 4-bit display data of the ddram. accordingly, the lsi can drive up to 104x80 pixels in 4096-color (16-gradation x 16-gradation x 16-gradation = 4-bit x 4-bit x 4-bit). in addition, the lsi can transfer the display data for the rgb by 16-bit at once or 8-bit two times. the data assignment between gradation palettes and segment drivers varies in accordance with setting for the ?swap? and ?ref? registers of the "display control (2)" instruction. (ref, swap)=(0, 0) or (1, 1) note) ddram column address :2n h ,2n h +1 h (ref=?0?) :ce h -2n h , cf h -(2n h +1 h ) (ref=?1?) hsw=1; 00 h to 9b h c256=1; 00 h to 67 h (ref, swap)=(0, 1) or (1, 0) note) ddram column address : 2n h ,2n h +1 h (ref=?0?) : ce h -2n h , cf h -(2n h +1 h ) (ref=?1?) hsw=1; 00 h to 9b h c256=1; 00 h to 67 h gradation palette j =0 to 15 display data from mpu gradation control circuit display data in ddram msb lsb msb lsb msb lsb paltte aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 d 7 d 6 d 4 d 5 d 2 d 1 d 0 d 7 d 4 d 3 d 1 d 2 column address:2n h :2n+1 h ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 abs=1 ( d 7 d 6 d 4 d 5 d 3 d 2 d 1 d 0 d 7 d 6 d 4 ) d 5 hsw=1 ( d 7 d 6 * d 5 d 4 d 3 d 2 * d 1 d 0 * ) * c256=1 segai segbi segci gradation palette j =0 to 15 display data from mpu gradation control circuit display data in ddram palette aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 7 d 6 d 4 d 5 d 2 d 1 d 0 d 7 d 4 d 3 d 1 d 2 ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 abs=1 ( d 7 d 6 d 4 d 5 d 3 d 2 d 1 d 0 d 7 d 6 d 4 ) d 5 ( d 7 d 6 d 4 d 5 d 3 d 2 d 1 d 0 d 7 d 6 d 4 ) d 5 hsw=1 ( d 7 d 6 * d 5 d 4 d 3 d 2 * d 1 d 0 * ) * ( d 7 d 6 * d 5 d 4 d 3 d 2 * d 1 d 0 * ) * c256=1 segai segbi segci (i=0 to 103) gradation palette j =0 to 15 display data from mpu gradation control circuit display data in ddram segai segbi segci segai segbi segci column address:2n h :2n+1 h ( i=0 to 103) lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb palette aj palette bj palette cj palette aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 d 7 d 6 d 4 d 5 d 2 d 1 d 0 d 7 d 4 d 3 d 1 d 2 d 7 d 6 d 4 d 5 d 2 d 1 d 0 d 7 d 4 d 3 d 1 d 2 ( d 7 d 6 * d 5 d 4 d 3 d 2 * d 1 d 0 * ) * c256=1 ( d 7 d 6 * d 5 d 4 d 3 d 2 * d 1 d 0 * ) * ( d 7 d 6 * d 5 d 4 d 3 d 2 * d 1 d 0 * ) * c256=1 ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 abs=1 ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 abs=1 ( d 7 d 6 d 4 d 5 d 3 d 2 d 1 d 0 d 7 d 6 d 4 ) d 5 hsw=1 ( d 7 d 6 d 4 d 5 d 3 d 2 d 1 d 0 d 7 d 6 d 4 ) d 5 ( d 7 d 6 d 4 d 5 d 3 d 2 d 1 d 0 d 7 d 6 d 4 ) d 5 hsw=1
NJU6818 - 37 - in the 16-bit data bus mode, the data assignments between the gradation palettes and the segment drivers vary in accordance with setting for the ?swap? and ?ref? bits of the "display control (2)" instruction as well as the assignment in the 8-bit data bus mode. (ref, swap)=(0, 0) or (1, 1) note) ddram column address :n h (ref=?0?) :67 h - n h (ref=?1?) (ref, swap)=(0, 1) or (1, 0) note) ddram column address :n h (ref=?0?) :67 h -n h (ref=?1?) segai segbi segci ( i=0 to 103) msb lsb msb lsb msb gradation palette j =0 to 15 display data from mpu gradation control circuit display data in ddram lsb palette a j palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 column address ; n h gradation palette j =0 to 15 i=0 to 103 display data from mpu gradation control circuit display data in ddram lsb msb lsb msb lsb msb segai segbi segci palette a j palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 column address ; n h ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 gradation palette j =0 to 15 display data from mpu gradation control circuit display data in ddram lsb msb lsb msb lsb msb segai segbi segci palette a j palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 column address ; n h ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1
NJU6818 - 38 - (12-2) b&w mode (mon=?1?) in the b&w mode, 3 bits of the msb data are used in both of the 16-bit and 8-bit data bus modes. in the 16-bit data bus mode (similarly 8-bit data bus access) (ref, swap)=(0, 0) or (1, 1) note) ddram column address : n h (ref=?0?) : 67 h -n h (ref=?1?) (ref, swap)=(0, 1) or (1, 0) note ) ddram column address: n h (ref=?0?) : 67 h -n h (ref=?1?) segai segbi segci msb lsb msb lsb msb gradation palette j =0 to 15 ( i=0 to 103) display data in ddram gradation control circuit display data in ddram lsb palette a j palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 column address; n h d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 gradation palette j =0 to 15 ( i=0 to 103) display data in ddram gradation control circuit display data in ddram lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb segai segbi segci palette a j palette bj palette cj palette a j palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 column address; n h d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 4 d 3 d 2 d 0 ) d 1 a bs=1 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 4 d 3 d 2 d 0 ) d 1 a bs=1
NJU6818 - 39 - (13) display timing generator the display-timing generator creates the timing pulses such as the cl, the flm, the fr and the clk by dividing the oscillation frequency oscillate an external or internal resister mode. the each of timing pulses is outputted through the each output terminals by ?son?=1. (14) lcd line clock (cl) the lcd line clock (cl) is used as a count-up signal for the line counter and a latch signal for the data latch circuit. at the rising edge of the cl signal, the line counter is counted-up and 312-bit display data, corresponding to this line address, is latched into the data latch circuit. and at the falling edge of the cl signal, this latched data output on the segment drivers. read out timing of the display data, from ddram to the latch circuits, is completely independent of the access timing to mpu. for this reason, the mpu can access to the lsi regardless of an internal operation. (15) lcd alternate signal (fr) and lcd synchronous signal (flm) the fr and flm signals are created from the cl signal. the fr signal is used to alternate the crystal polarization on a lcd panel. it is programmed that the fr signal is toggle on every frame in the default setting or once every n lines in the n-line inversion mode. the flm signal is used to indicate a start line of a new display frame. it presets an initial display line address of the line counter when the flm signal becomes ?1?. (16) data latch circuit the data latch circuit is used to temporarily store the display data that will output on the segment drivers. the display data in this circuit is updated in synchronization of the cl signal. the ?all pixels on/off?, ?display on/off? and ?reverse display on/off? instructions change the display data in this circuit but do not change the display data of the ddram. (17) common and segment drivers the lsi includes 312-segment drivers and 80-common drivers. the common drivers generate lcd driving waveforms composed of the v lcd , v 1 , v 4 and v ss in accordance with the fr signal and scanning data. the segment drivers generate waveforms composed of the v lcd , v 2 , v 3 and v ss in accordance with the fr signal and display data. (18) chip identification (id) the NJU6818 can read id data, which is determined by fixing id3, id2, id1 and id0 pins to ?1? (v dd ) or ?0? (v ss ). when the parallel interface is used, the id data can be read out through the d 7 , d 6 , d 5 and d 4 pins as upper 4-bit data of the internal register. when the serial interface is used, the id data can be read out as follows. in the 4-line serial interface mode, ?id read-out instruction? must be set by idr=1 during the sda and scl pins are enabled by cs=1. first, the serial data on the sda must be input at the rising edge of the scl clock, next the sda must be in high-impedance (hi-z) at the falling edge of the 8 th scl clock. from the rising edge of the 9 th scl clock, the id data such as id3, id2, id1 and id0 is read out. the serial data after the id0 is undefined, and this reading mode is returned to the writing mode at the rising edge of the 16 th scl clock. the serial data on the sda at the 8 th and 16 th scl clocks applies specified serial interface timing. in the 3-line serial interface mode, the sda must be in high-impedance (hi-z) at the falling edge of the 9 th scl clock. from the rising edge of the 10 th scl clock, the id data is read out as well as operation in the 4-line serial interface mode. the serial data after id0 is undefined, and this reading mode is returned to the writing mode at the rising edge of the 18 th scl clock. the serial data on the sda at the 9 th and 18 th scl clocks applies specified serial interface timing. note) refer to the ?serial interface timing? for the detail
NJU6818 - 40 - id read in the 4-line serial interface mode id read in the 4-line serial interface mode rs d 7 kkk d 0 id 3 id 2 id 1 id 0 1 2 kkk 9 10 11 12 13 csb sda scl 17 18 kkk hi-z d 7 d 6 kkk d 0 id 3 id 2 id 1 id 0 valid 1 2 kkk 8 9 10 11 12 csb rs sda scl 15 16 unfixed kkk hi-z un- fixed unfixed un- fixed
NJU6818 - 41 - lcd driving waveforms (in the b&w mode, reverse display off, 1/81 duty) fig 8 com 1 com 0 seg 1 seg 0 seg 2 com 1 com 0 v 1 v 2 cl v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss seg 1 seg 0 v lcd v 3 v 4 v ss fr flm 81 1 2 4 35 81 12 4 35 81 1
NJU6818 - 42 - (19) oscillator the oscillator generates internal clocks for the display timing and the voltage booster. since the lsi has internal capacitor (c) and resistor (r) for the oscillation, external capacitor and resistor are not usually required. however, in case that an external resistor is used, the resister is connected between the osc 1 and osc 2 terminals. the external resistor becomes enabled by setting ?1? to the ?cks? register of ?data bus length? instruction. when the internal oscillator is not used, the external clocks with 50% duty cycle ratio must be input to the osc 1 terminal. in addition, the feed back resister for the oscillation is varied by programming the ?rf? register of the ?frequency control? instruction, so that it is possible to optimize the frame frequency for a lcd panel. setting examples of the mon (b&w /gradation) and the pwm (variable gradation /fixed gradation) are described, as follows. (19-1) internal oscillation mode (cks=0) symbol mon pwm display mode fr1 0 0 variable gradation mode fr2 0 1 fixed gradation mode fr3 1 * b&w mode *: don?t care (19-2) external resistor oscillation mode (cks=1) the internal clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the ?mon? and ?pwm? registers must be set as well. (19-3) external clock input mode (cks=1) the external clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the ?mon? and ?pwm? registers must be set as well. (20) power supply circuits the internal power supply circuits are composed of the voltage booster, the electrical variable resister (evr), the voltage regulator, reference voltage generator and the voltage followers. the condition of the power supply circuits is arranged by programming the ?dcon? and ?ampon? registers on the ?power control? instruction. for this arrangement, some parts of the internal power supply circuits are activated in using an external power supply, as shown in the following table. table 15 dcon ampon voltage booster voltage followers voltage regulator evr external voltage note 0 0 disable disable v out , v lcd , v 1 , v 2 , v 3 , v 4 1, 3 0 1 disable enable v out 2, 3 1 1 enable enable ? ? note1) the internal power circuits are not used. the external v out is required and the c 1 + , c 1 - , c 2 + , c 2 - , c 3 + , c 3 - , c 4 + , c 4 - , c 5 + , c 5 - , v ref , v reg and v ee terminals must be open. note2) the internal power circuits except the voltage booster are used. the external v out is required and the c 1 + , c 1 - , c 2 + , c 2 - , c 3 + , c 3 - , c 4 + , c 4 - , c 5 + , c 5 - and v ee terminals must be open. the reference voltage is required to v ref terminal. note3) the relation among the voltages should be maintained as follows. v out v lcd v 1 v 2 v 3 v 4 v ss
NJU6818 - 43 - (21) voltage booster the voltage booster generates maximum 6x voltage of the v ee level. it is programmed so that the boost level is selected out of 1x, 2x, 3x, 4x, 5x and 6x by the ?boost level select? instruction. the boosted voltage v out must not exceed beyond the value of 18.0v, otherwise the voltage stress may cause a permanent damage to the lsi. boosted voltages capacitor connections for the voltage booster 6-time boost 5-time boost 4-time boost 3-time boost 2-time boost fig 9 3-time boost 6-time boost v ss =0v v ee =3.3v v out =9.9v v out =18v v ss =0v v ee =3v c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v ss + + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v ss + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v ss + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v ss + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v ss + +
NJU6818 - 44 - (22) reference voltage generator the reference voltage generator is used to produce the reference voltage (v ba ), which is output from the v ba terminal and should be input to the v ref terminal. v ba = v ee x 0.9 (23) voltage regulator the voltage regulator, composed of a gain control circuit and an operational amplifier, and is used to gain the reference voltage (v ref ) and to create the regulated voltage (v reg ). the v reg is used as an input voltage to the evr circuits which is programmed by the ?vu? register of the ?boost level? instruction. v reg = v ref x n (n: register value for the boost level) (24) electrical variable resister (evr) the evr is variable within 128-step, and is used to fine-tune the lcd driving voltage (v lcd ) by programming the ?dv? register of the ?evr control? instruction, so that it is possible to optimize the contrast level of lcd panels. v lcd = 0.5 x v reg + m (v reg - 0.5 x v reg ) / 127 (m: register value for the evr) (25) lcd driving voltage generation circuit lcd driving voltage generation circuit generates the v lcd voltage levels as v lcd , v 1 , v 2 , v 3 and v 4 with internal e.v.r and the bleeder resistors. the bias ratio of the lcd driving voltage is selected out of 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 and 1/10. in using the internal power supply, the capacitors ca 2 must be connected to the v lcd , v 1 , v 2 , v 3 and v 4 terminals, and the ca 2 value must be determined by the evaluation with actual lcd modules. in using the external power supply, the external lcd driving voltages such as the v lcd , v 1 , v 2 , v 3 and v 4 are supplied and the internal power supply circuits must be set to ?off? by dcon = ampon = "0". in this mode, voltage booster terminals such as c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 -, v ee , v ref and v reg must be opened. in case that the voltage booster is not used but only some parts of internal power supply circuits (voltage followers, voltage regulator and evr) are used, the c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 + and c 5 - terminals must be opened. and, the external power supply is input to the v out terminal, and the reference voltage to the v ref terminal. the capacitor ca 3 must connect to the v reg terminal for voltage stabilization.
NJU6818 - 45 - connections of the capacitors for voltage booster fig 10 fig11 reference values ca 1 1.0 to 4.7uf ca 2 1.0 to 2.2uf ca 3 0.1uf note) b grade capacitors are required. using only external power supply circuits using all of the internal power supply circuits (6-time boost) v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 v dd v lcd v 1 v 2 v 3 v 4 external power circuit c 5 - c 5 + NJU6818 v 1 v 2 v 3 v 4 v dd ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 1 v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + NJU6818 ca 3 v ss
NJU6818 - 46 - fig 12 fig 13 reference value ca1 1.0 to 4.7 f ca2 1.0 to 2.2 f ca3 0.1 f note) b grade capacitors are required. using internal power supply circuits without the reference voltage generator (1) (6-time boost) using internal power supply circuits without the reference voltage generator (2) (6-time boost) v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 v dd ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + ca 1 v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 v dd ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + ca 1 NJU6818 NJU6818 thermistor
NJU6818 - 47 - fig 14 reference value ca1 1.0 to 4.7 f ca2 1.0 to 2.2 f ca3 0.1 f note) b grade capacitors are required. using internal power supply circuits without the voltage booster v dd ca 3 v ss v ss ca 2 ca 2 ca 2 external power circuit ca 3 v ss v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 ca 2 ca 2 c 5 - c 5 + NJU6818
NJU6818 - 48 - (26) partial display function the partial display function is used to partially specify some parts of display area on lcd panels. by using this function, lcd modules can work in lower duty cycle ratio, lower lcd bias ratio, lower boost level and lower lcd driving voltage. it is usually used to display a time and calendar, and is also used to optimize the lsi condition in accordance with the display size. it can be programmed to select the duty cycle ratio (1/13, 1/17, 1/27, 1/33, 1/39,1/47, 1/57,1/69,1/77,1/81 in ?dse? is ?0?), the lcd bias ratio, the boost level and the evr value by the instructions. partial display image normal display partial display partial display sequence - boost level - evr value - lcd bias ratio - duty cycle ratio - initial display line - initial com line - other instructions njrc lcd driver low power and low voltage lcd driver optional status display off (on/off=?0?) internal power supply off (dcon=?0?, ampon=?0?) wait setting for lcd driving voltage-related functions setting for display-related functions internal power supply on (dcon=?1?, ampon=?1?) wait display on (on/off =?1?) partial display status
NJU6818 - 49 - (27) discharge circuit discharge circuit is used to discharge the electric charge of the capacitors on the v 1 to v 4 and the vlcd terminals. this circuit is activated by setting ?0? to the ?dis? register of the ?discharge? instruction or by setting the ?resb? terminal to ?0? level. the ?discharge on/off? instruction is usually required just after the internal power supply is turned off by setting ?0? into the ?dcon? and ?ampon? registers, or just after the external power supply is turned off. during the discharge operation, the internal or external power supply must not be turned on. (28) reset circuit the reset circuit initializes the lsi into the following default status. it is activated by setting the resb terminal to ?0?. the resb terminal is usually required to connect to mpu reset terminal in order that the lsi can be initialized at the same timing of the mpu. default status 1. ddram display data :undefined 2. column address :(00) h 3. row address :(00) h 4. initial display line :(0) h (1st line) 5. display on/off :off 6. reverse display on/off :off (normal) 7. duty cycle ratio :1/81 duty(dse=0) 8. n-line inversion on/off :off 9. com scan direction :com 0 com 79 10. increment mode :off 11. reverse seg direction :off (normal) 12. swap mode :off (normal) 13. evr value :(0, 0, 0, 0, 0, 0, 0) 14. internal power supply :off 15. display mode :gradation display mode 16. lcd bias ratio :1/9 bias 17. gradation palette 0 :(0, 0, 0, 0, 0) 18. gradation palette 1 :(0, 0, 0, 1, 1) 19. gradation palette 2 :(0, 0, 1, 0, 1) 20. gradation palette 3 :(0, 0, 1, 1, 1) 21. gradation palette 4 :(0, 1, 0, 0, 1) 22. gradation palette 5 :(0, 1, 0, 1, 1) 23. gradation palette 6 :(0, 1, 1, 0, 1) 24. gradation palette 7 :(0, 1, 1, 1, 1) 25. gradation palette 8 :(1, 0, 0, 0, 1) 26. gradation palette 9 :(1, 0, 0, 1, 1) 27. gradation palette 10 :(1, 0, 1, 0, 1) 28. gradation palette 11 :(1, 0, 1, 1, 1) 29. gradation palette 12 :(1, 1, 0, 0, 1) 30. gradation palette 13 :(1, 1, 0, 1, 1) 31. gradation palette 14 :(1, 1, 1, 0, 1) 32. gradation palette 15 :(1, 1, 1, 1, 1) 33. gradation mode control :variable gradation mode 34. data bus length :8-bit data bus length 35. discharge circuit :(dis/dis2) : ?0?
NJU6818 - 50 - (29) power supply on/off sequences the following paragraphs describe power supply on/off sequences, which are to protect the lsi from over current. (29-1) using an external power supply power supply on sequence logic voltage (v dd ) must be always input first, and next the lcd driving voltages (v 1 to v 4 and v lcd ) are turned on. in using the external v out , the v dd must be input first, next the reset operation must be performed, and finally the v out can be input power supply off sequence either the reset operation, cutting off the v 1 to v 4 and v lcd from the lsi, by the resb terminal or the ?power control? instruction must be performed first, and next the v dd is turned off. it is recommended that a series-resister between 50 ? and 100 ? is added on the v lcd line (or v out line in using only the external v out voltage) in order to protect the lsi from the over current. (29-2) using the internal power supply circuits power supply on sequence the v dd must be input first, next the reset operation must be performed, and finally the v 1 to v 4 and the v lcd can be turned on by setting ?1? to the ?dcon? and ?ampon? registers of the ?power control? instruction. power supply off sequence either the reset operation by the resb terminal or the ?power control? instruction must be performed first, and next the input voltage for the voltage booster (v ee ) and the v dd can be turned off. if the v ee is supplied from different power sources for the v dd , the v ee is turned off first and next the v dd is turned off
NJU6818 - 51 - (30) referential instruction sequences (30-1) initialization in using the internal power supply circuits - evr value - lcd bias ratio - power control (dcon=?1?, ampon=?1?) (30-2) display data writing - initial display line - increment mode - column address - row address v dd , v ee power on wait for power-on stabilization reset input wait setting for lcd driving voltage-related functions end of initialization end of initialization setting for display-related functions display on (on/off =?1?) display data write
NJU6818 - 52 - (30-3) power off - all com/seg output v ss level. optional status power save or reset operation v ee , v dd power off wait discharge on
NJU6818 - 53 - (31) instruction table instruction table (1) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions display data write 0 0 1 0 0/1 0/1 0/1 write data write display data to ddram display data read 0 0 0 1 0/1 0/1 0/1 read data read display data from ddram column address (lower) [0 h ] 0 1 1 0 0 0 0 0 0 0 0 ax3 ax2 ax1 ax0 ddram column address column address (upper) [1 h ] 0 1 1 0 0 0 0 0 0 0 1 ax7 ax6 ax5 ax4 ddram column address row address (lower) [2 h ] 0 1 1 0 0 0 0 0 0 1 0 ay3 ay2 ay1 ay0 ddram row address row address (upper) [3 h ] 0 1 1 0 0 0 0 0 0 1 1 * ay6 ay5 ay4 ddram row address initial display line (lower) [4 h ] 0 1 1 0 0 0 0 0 1 0 0 la3 la2 la1 la0 row address for an initial com line (scan start line) initial display line (upper) [5 h ] 0 1 1 0 0 0 0 0 1 0 1 * la6 la5 la4 row address for an initial com line (scan start line) n-line inversion (lower) [6 h ] 0 1 1 0 0 0 0 0 1 1 0 n3 n2 n1 n0 the number of n-line inversion n-line inversion (upper) [7 h ] 0 1 1 0 0 0 0 0 1 1 1 * n6 n5 n4 the number of n-line inversion display control (1) [8 h ] 0 1 1 0 0 0 0 1 0 0 0 shift mon all on on/ off shift: common direction mon: gradation or b/w display mode allon: all pixels on/off on/off: display on/off display control (2) [9 h ] 0 1 1 0 0 0 0 1 0 0 1 rev nlin swap ref rev: reverse display on/off nlin: n-line inversion on/off, swap: swap mode on/off ref: segment direction increment control [a h ] 0 1 1 0 0 0 0 1 0 1 0 win aim ayi axi win: window addressing mode on/off aim: read-modify-write on/off ayi: row auto-increment mode on/off axi: column auto-increment mode on/off power control [b h ] 0 1 1 0 0 0 0 1 0 1 1 amp on halt dc on acl ampon: voltage followers on/off halt: power save on/off dcon: voltage booster on/off acl: reset duty cycle ratio [c h ] 0 1 1 0 0 0 0 1 1 0 0 ds3 ds2 ds1 ds0 set lcd duty cycle ratio boost level / id read [d h ] 0 1 1 0 0 0 0 1 1 0 1 idr vu2 vu1 vu0 set boost level sets id reading in the serial interface lcd bias ratio [e h ] 0 1 1 0 0 0 0 1 1 1 0 * b2 b1 b0 sets lcd bias ratio re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6818 - 54 - instruction table (2) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette a0/a8 (lower) [0 h ] 0 1 1 0 0 0 1 0 0 0 0 pa03/ pa83 pa02/ pa82 pa01/ pa81 pa00/ pa80 sets palette values to gradation palette a0(ps=0)/a8(ps=1) gradation palette a0/a8 (upper) [1 h ] 0 1 1 0 0 0 1 0 0 0 1 * * * pa04/ pa84 sets palette values to gradation palette a0(ps=0)/a8(ps=1) gradation palette a1/a9 (lower) [2 h ] 0 1 1 0 0 0 1 0 0 1 0 pa13/ pa93 pa12/ pa92 pa11/ pa91 pa10/ pa90 sets palette values to gradation palette a1(ps=0)/a9(ps=1) gradation palette a1/a9 (upper) [3 h ] 0 1 1 0 0 0 1 0 0 1 1 * * * pa14/ pa94 sets palette values to gradation palette a1(ps=0)/a9(ps=1) gradation palette a2/a10 (lower) [4 h ] 0 1 1 0 0 0 1 0 1 0 0 pa23/ pa103 pa22/ pa102 pa21/ pa101 pa20/ pa100 sets palette values to gradation palette a2(ps=0)/a10(ps=1) gradation palette a2/a10 (upper) [5 h ] 0 1 1 0 0 0 1 0 1 0 1 * * * pa24/ pa104 sets palette values to gradation palette a2(ps=0)/a10(ps=1) gradation palette a3/a11 (lower) [6 h ] 0 1 1 0 0 0 1 0 1 1 0 pa33/ pa113 pa32/ pa112 pa31/ pa111 pa30/ pa110 sets palette values to gradation palette a3(ps=0)/a11(ps=1) gradation palette a3/a11 (upper) [7 h ] 0 1 1 0 0 0 1 0 1 1 1 * * * pa34/ pa114 sets palette values to gradation palette a3(ps=0)/a11(ps=1) gradation palette a4/a12 (lower) [8 h ] 0 1 1 0 0 0 1 1 0 0 0 pa43/ pa123 pa42/ pa122 pa41/ pa121 pa40/ pa120 sets palette values to gradation palette a4(ps=0)/a12(ps=1) gradation palette a4/a12 (upper) [9 h ] 0 1 1 0 0 0 1 1 0 0 1 * * * pa44/ pa124 sets palette values to gradation palette a4(ps=0)/a12(ps=1) gradation palette a5/a13 (lower) [a h ] 0 1 1 0 0 0 1 1 0 1 0 pa53/ pa133 pa52/ pa132 pa51/ pa131 pa50/ pa130 sets palette values to gradation palette a5(ps=0)/a13(ps=1) gradation palette a5/a13 (upper) [b h ] 0 1 1 0 0 0 1 1 0 1 1 * * * pa54/ pa134 sets palette values to gradation palette a5(ps=0)/a13(ps=1) gradation palette a6/a14 (lower) [c h ] 0 1 1 0 0 0 1 1 1 0 0 pa63/ pa143 pa62/ pa142 pa61/ pa141 pa60/ pa140 sets palette values to gradation palette a6(ps=0)/a14(ps=1) gradation palette a6/a14 (upper) [d h ] 0 1 1 0 0 0 1 1 1 0 1 * * * pa64/ pa144 sets palette values to gradation palette a6(ps=0)/a14(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6818 - 55 - instruction table (3) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette a7/a15 (lower) [0 h ] 0 1 1 0 0 1 0 0 0 0 0 pa73/ pa153 pa72/ pa152 pa71/ pa151 pa70/ pa150 sets palette values to gradation palette a7(ps=0)/a15(ps=1) gradation palette a7/a15 (upper) [1 h ] 0 1 1 0 0 1 0 0 0 0 1 * * * pa74/ pa154 sets palette values to gradation palette a7(ps=0)/a15(ps=1) gradation palette b0/b8 (lower) [2 h ] 0 1 1 0 0 1 0 0 0 1 0 pb03/ pb83 pb02/ pb82 pb01/ pb81 pb00/ pb80 sets palette values to gradation palette b0(ps=0)/b8(ps=1) gradation palette b0/b8 (upper) [3 h ] 0 1 1 0 0 1 0 0 0 1 1 * * * pb04/ pg84 sets palette values to gradation palette b0(ps=0)/b8(ps=1) gradation palette b1/b9 (lower) [4 h ] 0 1 1 0 0 1 0 0 1 0 0 pb13/ pb93 pb12/ pb92 pb11/ pb91 pb10/ pb90 sets palette values to gradation palette b1(ps=0)/b9(ps=1) gradation palette b1/b9 (upper) [5 h ] 0 1 1 0 0 1 0 0 1 0 1 * * * pb14/ pb94 sets palette values to gradation palette b1(ps=0)/b9(ps=1) gradation palette b2/b10 (lower) [6 h ] 0 1 1 0 0 1 0 0 1 1 0 pb23/ pb103 pb22/ pb102 pb21/ pb101 pb20/ pb100 sets palette values to gradation palette b2(ps=0)/b10(ps=1) gradation palette b2/b10 (upper) [7 h ] 0 1 1 0 0 1 0 0 1 1 1 * * * pb24/ pb104 sets palette values to gradation palette b2(ps=0)/b10(ps=1) gradation palette b3/b11 (lower) [8 h ] 0 1 1 0 0 1 0 1 0 0 0 pb33/ pb113 pb32/ pb112 pb31/ pb111 pb30/ pb110 sets palette values to gradation palette b3(ps=0)/b11(ps=1) gradation palette b3/b11 (upper) [9 h ] 0 1 1 0 0 1 0 1 0 0 1 * * * pb34/ pb114 sets palette values to gradation palette b3(ps=0)/b11(ps=1) gradation palette b4/b12 (lower) [a h ] 0 1 1 0 0 1 0 1 0 1 0 pb43/ pb123 pb42/ pb122 pb41/ pb121 pb40/ pb120 sets palette values to gradation palette b4(ps=0)/b12(ps=1) gradation palette b4/b12 (upper) [b h ] 0 1 1 0 0 1 0 1 0 1 1 * * * pb44/ pb124 sets palette values to gradation palette b4(ps=0)/b12(ps=1) gradation palette b5/b13 (lower) [c h ] 0 1 1 0 0 1 0 1 1 0 0 pb53/ pb133 pb52/ pb132 pb51/ pb131 pb50/ pb130 sets palette values to gradation palette b5(ps=0)/b13(ps=1) gradation palette b5/b13 (upper) [d h ] 0 1 1 0 0 1 0 1 1 0 1 * * * pb54/ pb134 sets palette values to gradation palette b5(ps=0)/b13(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6818 - 56 - instruction table (4) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette b6/b14 (lower) [0 h ] 0 1 1 0 0 1 1 0 0 0 0 pb63/ pb143 pb62/ pb142 pb61/ pb141 pb60/ pb140 sets palette values to gradation palette b6(ps=0)/b14(ps=1) gradation palette b6/b14 (upper) [1 h ] 0 1 1 0 0 1 1 0 0 0 1 * * * pb64/ pb144 sets palette values to gradation palette b6(ps=0)/b14(ps=1) gradation palette b7/b15 (lower) [2 h ] 0 1 1 0 0 1 1 0 0 1 0 pb73/ pb153 pb72/ pb152 pb71/ pb151 pb70/ pb150 sets palette values to gradation palette b7(ps=0)/b15(ps=1) gradation palette b7/b15 (upper) [3 h ] 0 1 1 0 0 1 1 0 0 1 1 * * * pb74/ pb154 sets palette values to gradation palette b7(ps=0)/b15(ps=1) gradation palette c0/c8 (lower) [4 h ] 0 1 1 0 0 1 1 0 1 0 0 pc03/ pc83 pc02/ pc82 pc01/ pc81 pc00/ pc80 sets palette values to gradation palette c0(ps=0)/c8(ps=1) gradation palette c0/c8 (upper) [5 h ] 0 1 1 0 0 1 1 0 1 0 1 * * * pc04/ pc84 sets palette values to gradation palette c0(ps=0)/c8(ps=1) gradation palette c1/c9 (lower) [6 h ] 0 1 1 0 0 1 1 0 1 1 0 pc13/ pc93 pc12/ pc92 pc11/ pc91 pc10/ pc90 sets palette values to gradation palette c1(ps=0)/c9(ps=1) gradation palette c1/c9 (upper) [7 h ] 0 1 1 0 0 1 1 0 1 1 1 * * * pc14/ pc94 sets palette values to gradation palette c1(ps=0)/c9(ps=1) gradation palette c2/c10 (lower) [8 h ] 0 1 1 0 0 1 1 1 0 0 0 pc23/ pc103 pc22/ pc102 pc21/ pc101 pc20/ pc100 sets palette values to gradation palette c2(ps=0)/c10(ps=1) gradation palette c2/c10 (upper) [9 h ] 0 1 1 0 0 1 1 1 0 0 1 * * * pc24/ pc104 sets palette values to gradation palette c2(ps=0)/c10(ps=1) gradation palette c3/c11 (lower) [a h ] 0 1 1 0 0 1 1 1 0 1 0 pc33p c113 pc32/ pc112 pc31/ pc111 pc30/ pc110 sets palette values to gradation palette c3(ps=0)/c11(ps=1) gradation palette c3/c11 (upper) [b h ] 0 1 1 0 0 1 1 1 0 1 1 * * * pc34/ pc114 sets palette values to gradation palette c3(ps=0)/c11(ps=1) gradation palette c4/c12 (lower) [c h ] 0 1 1 0 0 1 1 1 1 0 0 pc43/ pc123 pc42/ pc122 pc41/ pc121 pc40/ pc120 sets palette values to gradation palette c4(ps=0)/c12(ps=1) gradation palette c4/c12 (upper) [d h ] 0 1 1 0 0 1 1 1 1 0 1 * * * pc44/ pc124 sets palette values to gradation palette c4(ps=0)/c12(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6818 - 57 - instruction table (5) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette c5/c13 (lower) [0 h ] 0 1 1 0 1 0 0 0 0 0 0 pc53/ pc133 pc52/ pc132 pc51/ pc131 pc50/ pc130 sets palette values to gradation palette c5(ps=0)/c13(ps=1) gradation palette c5/c13 (upper) [1 h ] 0 1 1 0 1 0 0 0 0 0 1 * * * pc54/ pc134 sets palette values to gradation palette c5(ps=0)/c13(ps=1) gradation palette c6/c14 (lower) [2 h ] 0 1 1 0 1 0 0 0 0 1 0 pc63/p c143 pc62/ pc142 pc61/ pc141 pc60/ pc140 sets palette values to gradation palette c6(ps=0)/c14(ps=1) gradation palette c6/c14 (upper) [3 h ] 0 1 1 0 1 0 0 0 0 1 1 * * * pc64/ pc144 sets palette values to gradation palette c6(ps=0)/c14(ps=1) gradation palette c7/c15 (lower) [4 h ] 0 1 1 0 1 0 0 0 1 0 0 pc73/ pc153 pc72/ pc152 pc71/ pc151 pc70/ pc150 sets palette values to gradation palette c7(ps=0)/c15(ps=1) gradation palette c7/c15 (upper) [5 h ] 0 1 1 0 1 0 0 0 1 0 1 * * * pc74/ pc154 sets palette values to gradation palette c7(ps=0)/c15(ps=1) initial com line [6 h ] 0 1 1 0 1 0 0 0 1 1 0 sc3 sc2 sc1 sc0 scan-starting common driver display clock / duty-1 [7 h ] 0 1 1 0 1 0 0 0 1 1 1 * * dse son son : display clock on/off dse : duty-1 on/off gradation mode control [8 h ] 0 1 1 0 1 0 0 1 0 0 0 pwm c256 * * pwm : variable/fixed gradation mode c256 : 256-color mode on/off data bus length [9 h ] 0 1 1 0 1 0 0 1 0 0 1 hsw abs cks wls hsw : high speed access on/off abs : abs mode on/off cks : internal/external oscillation wls : display data length evr control (lower) [a h ] 0 1 1 0 1 0 0 1 0 1 0 dv3 dv2 dv1 dv0 sets evr level (lower bit) evr control (upper) [b h ] 0 1 1 0 1 0 0 1 0 1 1 * dv6 dv5 dv4 sets evr level (upper bit) frequency control [d h ] 0 1 1 0 1 0 0 1 1 0 1 * rf2 rf1 rf0 oscillation frequency discharge on/off [e h ] 0 1 1 0 1 0 0 1 1 1 0 * * dis2 dis discharge the electric charge in capacitors on v 1 to v 4 , v lcd re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag instruction register address [c h ] 0 1 1 0 1 0 0 1 1 0 0 register address sets instruction register address instruction register read / id read 0 1 0 1 0/1 0/1 0/1 id3 id2 id1 id0 read data read out instruction register data note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. note 4) cks=0: internal oscillation mode (default) cks=1: external oscillation mode
NJU6818 - 58 - instruction table (6) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions window end column address (lower) [0 h ] 0 1 1 0 1 0 1 0 0 0 0 ex3 ex2 ex1 ex0 sets column address for end point window end column address (upper) [1 h ] 0 1 1 0 1 0 1 0 0 0 1 ex7 ex6 ex5 ex4 sets column address for end point window end row address (lower) [2 h ] 0 1 1 0 1 0 1 0 0 1 0 ey3 ey2 ey1 ey0 sets row address for end point window end row address (upper) [3 h ] 0 1 1 0 1 0 1 0 0 1 1 * ey6 ey5 ey4 sets row address for end point initial reverse line (lower) [4 h ] 0 1 1 0 1 0 1 0 1 0 0 ls3 ls2 ls1 ls0 sets address for reverse line initial reverse line (upper) [5 h ] 0 1 1 0 1 0 1 0 1 0 1 * ls6 ls5 ls4 sets address for reverse line last reverse line (lower) [6 h ] 0 1 1 0 1 0 1 0 1 1 0 le3 le2 le1 le0 sets address for reverse line last reverse line (upper) [7 h ] 0 1 1 0 1 0 1 0 1 1 1 * le6 le5 le4 sets address for reverse line reverse line display on/off [8 h ] 0 1 1 0 1 0 1 1 0 0 0 * * bt lrev bt : blink type setting lrev : reverse line display on/off gradation palette setting [9 h ] 0 1 1 0 1 0 1 1 0 0 1 * * * ps ps : gradation setting pwm control [a h ] 0 1 1 0 1 0 1 1 0 1 0 pwm s pwm a pwm b pwm c sets pwm mode re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6818 - 59 - (32) instruction descriptions this chapter provides detail descriptions and instructions and instruction registers. nonexistent instruction codes must not be set into the lsi. (32-1) display data write the ?display data write? instruction is used to write 8-bit display data into the ddram. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0/1 0/1 0/1 display data (32-2) display data read the ?display data read? instruction is used to read out 8-bit display data from the ddram, where the column address and row address must be specified beforehand by the ?column address? and ?row address? instructions. the dummy read is required just after the ?column address? and ?row address? instructions. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0/1 0/1 0/1 display data (32-3) column address the ?column address? instruction is used to specify the column address for display data?s reading and writing operations. it requires dual bytes for lower 4-bit and upper 4-bit data. the instruction for the lower 4-bit data must be executed first, next the instruction for the upper 4-bit. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 0 0 0 0 ax3 ax2 ax1 ax0 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 0 0 0 1 ax7 ax6 ax5 ax4 (32-4) row address the ?row address? instruction is used to specify the row address for display data read and write operations. it requires dual bytes for lower 4-bit and upper 3-bit data. the instruction for the lower 4-bit data must be executed first, next the instruction for the upper 3-bit. the row address is specified in between 00 h and 4f h . the setting for nonexistent row address between 50 h and ff h is prohibited. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 0 0 1 0 ay3 ay2 ay1 ay0 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 0 0 1 1 * ay6 ay5 ay4
NJU6818 - 60 - (32-5) initial display line the ?initial display line? instruction is used to specify the line address corresponding to the initial com line. the initial com line is specified by the ?initial com line? instruction and indicates the common driver that starts scanning display data. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 0 1 0 0 la3 la2 la1 la0 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 0 1 0 1 * la6 la5 la4 la6 la5 la4 la3 la2 la1 la0 line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : 1 0 0 1 1 1 1 79 (32-6) n-line inversion the ?n-line inversion? instruction is used to control the alternate rates of liquid crystal direction. it is programmed to select the n value between 2 and 80, and the fr signal toggles once every n lines by setting ?1? into the ?nlin? register of the ?display control (2)? instruction. when the n-line inversion is disabled by setting ?0? into the ?nlin? register, the fr signal toggles by the frame. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 0 1 1 0 n3 n2 n1 n0 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 0 1 1 1 * n6 n5 n4 n6 n5 n4 n3 n2 n1 n0 n value 0 0 0 0 0 0 0 inhibited 0 0 0 0 0 0 1 2 : : : : 1 0 0 1 1 1 1 80
NJU6818 - 61 - n-line inversion timing (1/81 duty cycle ratio) n-line inversion off n-line inversion on (32-7) display control (1) the ?display control (1)? instruction is used to control display conditions by setting the ?display on/off?, ?all pixels on/off?, ?display mode? and ?common direction? registers. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 1 0 0 0 shift mon all on on/ off on/off register on/off=0 : display off (all com/seg output the vss level.) on/off=1 : display on all on register the ?all pixels on/off? register is used to turn on all pixels without changing display data of the ddram. the setting for the ?all pixels on/off? register has a priority over the ?reverse display on/off? register. allon=0 : normal allon=1 : all pixels turn on. mon register mon=0 : gradation mode mon=1 : b&w mode shift register shift=0 : com 0 com 79 shift=1 : com 79 com 0 cl flm fr 2nd line 81th line 1st line 3rd line 1st line 80th line cl fr n-line control 2nd line 1st line 1st line 3rd line 2nd line n line
NJU6818 - 62 - (32-8) display control (2) the ?display control (2)? instruction is used to control display conditions by setting the ?segment direction?, ?swap mode on/off?, ?n-line inversion on/off? and ?reverse display on/off? registers. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 1 0 0 1 rev nlin swap ref ref register the ?ref? register is used to reverse the assignment between segment drivers and column address, and it is possible to reduce restrictions for placement of the lsi on the lcd module. for more information, see (10) ?the relation among the ddram column address, display data and segment drivers?. swap register the ?swap? register is used to reverse the arrangement of display data in the ddram. swap=0 : swap mode off (normal) swap=1 : swap mode on swap=?0? swap=?1? write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ram data d7 d6 d5 d4 d3 d2 d1 d0 d0 d1 d2 d3 d4 d5 d6 d7 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 nlin register the ?nlin? is used to enable or disable the n-line inversion. nlin=0 : n-line inversion off (the fr signal toggles by the flame.) nlin=1 : n-line inversion on (the fr signal toggles once every n lines.) rev register the ?rev? register is used to enable or disable the reverse display mode that reverses the polarity of display data without changing display data of the ddram. rev=0 : reverse display mode off rev=1 : reverse display mode on rev display ddram data display data 0 0 0 normal 1 1 0 1 1 reverse 1 0
NJU6818 - 63 - (32-9) increment control the ?increment control? instruction is used for the increment mode. in using the auto-increment mode, ddram address automatically increments (+1) whenever the ddram is accessed by the ?display data write? or ?display data read? instruction. therefore, once ?display data write? or ?display data read? instruction is established, it is possible to continuously access to the ddram without the ?column address? and ?row address? instructions. the settings for the ?aim?, ?axi? and ?ayi? registers are listed in the following tables. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 1 0 1 0 win aim ayi axi aim, ayi and axi registers aim increment mode note 0 auto-increment for the both of display data read and write operations 1 1 auto-increment for the display write operation (read-modify-write) 2 note 1) it is effective for usual operations accessing successive addresses. note 2) it is effective for the read-modify-write operation. ayi axi increment mode note 0 0 no auto-increment 1 0 1 auto-increment for the column address 2 1 0 auto-increment for the row address 3 1 1 auto-increment for the column address and row address 4 note 1) auto-increment is disabled regardless of the ?aim? register. note 2) auto-increment of the column address is enabled in accordance with the ?aim? register. note 3) auto-increment of the row address is enabled in accordance with the ?aim? register. note 4) auto-increments of the column address and the row address are enabled. the row address increments whenever the column address reaches to the max h . 00 h max h 4f h 00 h max h 00 h 4f h 00 h column address row address max h in the 8-bit data bus mode : cf h max h in the 16-bit data bus mode : 67 h max h in the 8-bit data bus mode : cf h max h in the 16-bit data bus mode : 67 h
NJU6818 - 64 - win register the ?win? register is used to access to the ddram for the window display area, where the start point is determined by the ?column address? and ?row address? instructions, and the end point by the ?window end column address ?and ?window end row address? instructions. the setting sequence for the window display area is listed as follows. for more detail, see (6) ?window addressing mode?. win=0 : window addressing mode off win=1 : window addressing mode on 1. set win=1, axi=1, and ayi=1 by the ?increment control? instruction 2. set the start point by the ?column address? and ?row address? instructions 3. set the end point by the ?window end column address? and ?window end row address? instructions 4. enable to access to the ddram in the window addressing mode start address column address row address end address start address end address
NJU6818 - 65 - (32-10) power control csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 1 0 1 1 ampon halt dcon acl acl register the ?acl? register is used to initialize the internal power supply circuits. acl=0 : initialization off (normal) acl=1 : initialization on when the data of the ?acl register? is read out by the ?instruction register read? instruction, the read-out data is ?1? during the initialization, and ?0? after the initialization. this initialization is performed by using the signal produced by 2 clocks on the osc 1 . for this reason, the wait time for 2 clocks of the osc 1 is necessary until next instruction. dcon register the ?dcon? register is used to enable or disable the voltage booster. dcon=0 : voltage booster off dcon=1 : voltage booster on halt register the ?halt? register is used to enable or disable the power save mode. it is possible to reduce operating current down to stand-by level. the internal status in the power save mode is listed below. halt=0 : power save off (normal) halt=1 : power save on internal status in the power save mode ? the oscillation circuits and internal power supply circuits are halted. ? all segment and common drivers output the v ss level. ? the clock input into the osc 1 is inhibited. ? the display data in the ddram is maintained. ? the operational modes before the power save mode are maintained. ? the v 1 to v 4 and the v lcd are in high impedance. as a power save on sequence, the ?display off? must be executed first, next the ?power save on? instruction, and then all common and segment drivers output the v ss level. and as power save off sequence, the ?power save off? instruction is executed first, next the ?display on? instruction. if the ?power save off? instruction is executed in the display on status, unexpected pixels may instantly turn on. ampon register the ?ampon? register is used to enable or disable the voltage followers, voltage regulator and evr. ampon=0 : the voltage followers, the voltage regulator and the evr off ampon=1 : the voltage followers, the voltage regulator and the evr on
NJU6818 - 66 - (32-11) duty cycle ratio the ?duty cycle ratio? instruction is used to select lcd duty cycle ratio for the partial display function. the partial display function specifies some parts of display area on a lcd panel in the condition of lower duty cycle ratio, lower lcd bias ratio, lower boost level and lower lcd driving voltage. therefore, it is possible to optimize the lsi?s conditions with extremely low power consumption. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 1 1 0 0 ds3 ds2 ds1 ds0 duty cycle ratio ds3 ds2 ds1 ds0 dse=0 des=1 row way displays 0 0 0 0 1/81 1/80 80 commons 0 0 0 1 1/77 1/76 76 commons 0 0 1 0 1/69 1/68 68 commons 0 0 1 1 1/57 1/56 56 commons 0 1 0 0 1/47 1/46 46 commons 0 1 0 1 1/39 1/38 38 commons 0 1 1 0 1/33 1/32 32 commons 0 1 1 1 1/27 1/26 26 commons 1 0 0 0 1/17 1/16 16 commons 1 0 0 1 1/13 1/12 12 commons 1 0 1 0 inhibited 1 0 1 1 inhibited 1 1 0 0 inhibited 1 1 0 1 inhibited 1 1 1 0 inhibited 1 1 1 1 inhibited the duty cycle ratio is controlled by the ?ds3 to ds0? registers of the ?duty cycle ratio? instruction and the ?dse? register of the ?display clock / duty-1? instruction. dse=0 : the number of commons +1 (duty cycle ratio in the default setting) dse=1 : the number of commons (duty-1) when the ?dse? is ?0?, all common drivers output non-selective levels in period of lost common. and the segment drivers output the same data for the last line as the data for previous line: for instance they output the same data for the 80 th and 81 st lines when the duty cycle ratio is set to 1/81. for the setting of the ?dse? register, see (32-17) ?display clock / duty-1?. (32-12) boost level the ?boost level? is used to select multiple of the voltage booster for the partial display function. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 1 1 0 1 idr vu2 vu1 vu0 a) id read in serial interface id data can be read out by setting idr=1. b) boost level set vu2 vu1 vu0 boost level 0 0 0 1-time (no boost) 0 0 1 2-time 0 1 0 3-time 0 1 1 4-time 1 0 0 5-time 1 0 1 6-time 1 1 0 inhibited 1 1 1 inhibited
NJU6818 - 67 - (32-13) lcd bias ratio the ?lcd bias ratio? is used to select the lcd bias ratio for the partial display function. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 1 1 1 0 * b2 b1 b0 b2 b1 b0 lcd bias ratio 0 0 0 1/9 0 0 1 1/8 0 1 0 1/7 0 1 1 1/6 1 0 0 1/5 1 0 1 1/4 1 1 0 1/10 1 1 1 inhibited (32-14) re flag the ?re flag? registers are used to determine the contents for the re registers (re 2 , re 1 and re 0 ), and it is possible to access to the instruction registers. the data of the ?tst 0 ? register must be ?0?, and it is used for maker tests only. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst0 re2 re1 re0
NJU6818 - 68 - (32-15) gradation palette a, b and c csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 0 0 0 0 pa03/ pa83 pa02/ pa82 pa01/ pa81 pa00/ pa80 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 0 0 0 1 * * * pa04/ pa84 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 0 0 1 0 pa13/ pa93 pa12/ pa92 pa11/ pa91 pa10/ pa90 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 0 0 1 1 * * * pa14/ pa94 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 0 1 0 0 pa23/ pa103 pa22/ pa102 pa21/ pa101 pa20/ pa100 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 0 1 0 1 * * * pa24/ pa104 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 0 1 1 0 pa33/ pa113 pa32/ pa112 pa31/ pa111 pa30/ pa110 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 0 1 1 1 * * * pa34/ pa114 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 1 0 0 0 pa43/ pa123 pa42/ pa122 pa41/ pa121 pa40/ pa120
NJU6818 - 69 - csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 1 0 0 1 * * * pa44/ pa124 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 1 0 1 0 pa53/ pa133 pa52/ pa132 pa51/ pa131 pa50/ pa130 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 1 0 1 1 * * * pa54/ pa134 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 1 1 0 0 pa63/ pa143 pa62/ pa142 pa61/ pa141 pa60/ pa140 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 1 1 1 0 1 * * * pa64/ pa144 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 0 0 0 0 pa73/ pa153 pa72/ pa152 pa71/ pa151 pa70/ pa150 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 0 0 0 1 * * * pa74/ pa154 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 0 0 1 0 pb03/ pb83 pb02/ pb82 pb01/ pb81 pb00/ pb80 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 0 0 1 1 * * * pb04/ pb84
NJU6818 - 70 - csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 0 1 0 0 pb13/ pb93 pb12/ pb92 pb11/ pb91 pb10/ pb90 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 0 1 0 1 * * * pb14/ pb94 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 0 1 1 0 pb23/ pb103 pb22/ pb102 pb21/ pb101 pb20/ pb100 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 0 1 1 1 * * * pb24/ pb104 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 1 0 0 0 pb33/ pb113 pb32/ pb112 pb31/ pb111 pb30/ pb110 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 1 0 0 1 * * * pb34/ pb114 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 1 0 1 0 pb43/ pb123 pb42/ pb122 pb41/ pb121 pb40/ pb120 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 1 0 1 1 * * * pb44/ pb124 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 1 1 0 0 pb53/ pb133 pb52/ pb132 pb51/ pb131 pb50/ pb130
NJU6818 - 71 - csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 0 1 1 0 1 * * * pb54/ pb134 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 0 0 0 0 pb63/ pb143 pb62/ pb142 pb61/ pb141 pb60/ pb140 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 0 0 0 1 * * * pb64/ pb144 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 0 0 1 0 pb73/ pb153 pb72/ pb152 pb71/ pb151 pb70/ pb150 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 0 0 1 1 * * * pb74/ pb154 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 0 1 0 0 pc03/ pc83 pc02/ pc82 pc01/ pc81 pc00/ pc80 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 0 1 0 1 * * * pc04/ pc84 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 0 1 1 0 pc13/ pc93 pc12/ pc92 pc11/ pc91 pc10/ pc90 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 0 1 1 1 * * * pc14/ pc94
NJU6818 - 72 - csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 1 0 0 0 pc23/ pc103 pc22/ pc102 pc21/ pc101 pc20/ pc100 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 1 0 0 1 * * * pc24/ pc104 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 1 0 1 0 pc33/ pc113 pc32/ pc112 pc31/ pc111 pc30/ pc110 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 1 0 1 1 * * * pc34/ pc114 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 1 1 0 0 pc43/ pc123 pc42/ pc122 pc41/ pc121 pc40/ pc120 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 1 1 1 1 0 1 * * * pc44/ pc124 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 0 0 0 0 pc53/ pc133 pc52/ pc132 pc51/ pc131 pc50/ pc130 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 0 0 0 1 * * * pc54/ pc134 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 0 0 1 0 pc63/ pc143 pc62/ pc142 pc61/ pb141 pc60/ pb140
NJU6818 - 73 - csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 0 0 1 1 * * * pc64/ pc144 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 0 1 0 0 pc73/ pc153 pc72/ pc152 pc71/ pc151 pc70/ pc150 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 0 1 0 1 * * * pc74/ pc154 gradation palette table (variable gradation mode, pwm=?0? and mon=?0?) (palette aj, palette bj, palette cj (j=0 to 15)) palette value gradation level gradation palette palette value gradation level gradation palette 0 0 0 0 0 0 palette 0(default) 1 0 0 0 0 16/31 0 0 0 0 1 1/31 1 0 0 0 1 17/31 palette 8(default) 0 0 0 1 0 2/31 1 0 0 1 0 18/31 0 0 0 1 1 3/31 palette 1(default) 1 0 0 1 1 19/31 palette 9(default) 0 0 1 0 0 4/31 1 0 1 0 0 20/31 0 0 1 0 1 5/31 palette 2(default) 1 0 1 0 1 21/31 palette 10(default) 0 0 1 1 0 6/31 1 0 1 1 0 22/31 0 0 1 1 1 7/31 palette 3(default) 1 0 1 1 1 23/31 palette 11(default) 0 1 0 0 0 8/31 1 1 0 0 0 24/31 0 1 0 0 1 9/31 palette 4(default) 1 1 0 0 1 25/31 palette 12(default) 0 1 0 1 0 10/31 1 1 0 1 0 26/31 0 1 0 1 1 11/31 palette 5(default) 1 1 0 1 1 27/31 palette 13(default) 0 1 1 0 0 12/31 1 1 1 0 0 28/31 0 1 1 0 1 13/31 palette 6(default) 1 1 1 0 1 29/31 palette 14(default) 0 1 1 1 0 14/31 1 1 1 1 0 30/31 0 1 1 1 1 15/31 palette 7(default) 1 1 1 1 1 31/31 palette 15(default)
NJU6818 - 74 - (32-16) initial com line the ?initial com line? instruction is used to specify the common driver that starts scanning display data. the line address, corresponding to the initial com line, is specified by the ?initial display line? instruction. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 0 1 1 0 sc3 sc2 sc1 sc0 sc3 sc2 sc1 sc0 initial com line (shift=0) initial com line (shift=1) 0 0 0 0 com0 com79 0 0 0 1 com4 com75 0 0 1 0 com8 com71 0 0 1 1 com16 com63 0 1 0 0 com24 com55 0 1 0 1 com32 com47 0 1 1 0 com40 com39 0 1 1 1 com48 com31 1 0 0 0 com56 com23 1 0 0 1 com64 com15 1 0 1 0 com72 com7 1 0 1 1 inhibited inhibited 1 1 0 0 inhibited inhibited 1 1 0 1 inhibited inhibited 1 1 1 0 inhibited inhibited 1 1 1 1 inhibited inhibited shift=0: positive scan direction (com 0 com 79 ) shift=1: negative scan direction (com 79 com 0 ) (32-17) display clock / duty-1 the ?display clock / duty-1? instruction is used to enable or disable the display clocks (cl, flm, fr, and clk), and to control on/off of the ?duty-1?. for more detail about the ?duty-1?, see (32-11) ?duty cycle ratio?. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 0 1 1 1 * * dse son son=0: cl, flm, fr, and clk are level ?0? son=1: cl, flm, fr, and clk outputs are active. dse=0: duty-1 off dse=1: duty-1 on
NJU6818 - 75 - (32-18) gradation mode control the ?gradation mode control? is used to select display mode as follows. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 1 0 0 0 pwm c256 * * pwm register pwm=0: variable gradation mode (variable 16-gradation levels out of 32-gradation level of the gradation palette) pwm=1: fixed gradation mode (fixed 8-gradation levels) c256 register c256=0 256-color mode off (4,096-color in the default setting) c256=1 256-color mode on (32-19) data bus length the ?data bus length? instruction is used to select 8- or 16- bit data bus length and determine the internal or external oscillation. in the 16-bit data bus mode, instruction data must be 16-bit (d 15 to d 0 ) as well as display data. however, for the access to the instruction registers, the lower 8-bit data (d 7 to d 0 ) of the 16-bit data is valid. for the access to the ddram, all of the 16-bit data (d 15 to d 0 ) is valid. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 1 0 0 1 hsw abs cks wls hsw register hsw =0 :high speed access mode off hsw=1 :high speed access mode on (only in the 8-bit data bus length) abs register abs=0 :abs mode off (normal) abs=1 :abs mode on wls register wls=0 :8-bit data bus length wls =1 :16-bit data bus length cks register cks =0 :internal oscillation (the osc 1 terminal must be fixed ?1? or ?0?.) cks =1 :external oscillation (by the external clock into the osc 1 or external resister between the osc 1 and osc 2 . osc 2 should be open when clock is inputted from osc 1 .)
NJU6818 - 76 - (32-20) evr control the ?evr control? instruction is used to fine-tune the lcd driving voltage (v lcd ), so that it is possible to optimize contrast level for a lcd panel. this instruction must be programmed by upper 3-bit data first, next lower 4-bit data. and it becomes enabled when the lower 4-bit data is programmed, so that it can prevent unexpected high voltage for the v lcd from being generated. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 1 0 1 0 dv3 dv2 dv1 dv0 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 1 0 1 1 * dv6 dv5 dv4 dv6 dv5 dv4 dv3 dv2 dv1 dv0 vlcd 0 0 0 0 0 0 0 low 0 0 0 0 0 0 1 : : : : : 1 1 1 1 1 1 1 high the formula of the v lcd is shown below. v lcd [v] = 0.5 x v reg + m (v reg ? 0.5 x v reg ) / 127 v ba = v ee x 0.9 v ba : output voltage of the reference voltage generator v reg = v ref x n v ref : input voltage of the voltage regulator v reg : output voltage of the voltage regulator n : register value for the voltage booster m : register value for the evr
NJU6818 - 77 - (32-21) frequency control the ?frequency control? instruction is used to control the frame frequency for a lcd panel. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 1 1 0 1 * rf2 rf1 rf0 rfx register (x=0, 1, 2) the ?rfx? register is used to determine the feed back resister value for the internal oscillator, and it is possible to adjust the frame frequency for the lcd modules. rf 2 rf 1 rf 0 feedback resistor value 0 0 0 reference value 0 0 1 0.8 x reference value 0 1 0 0.9 x reference value 0 1 1 1.1 x reference value 1 0 0 1.2 x reference value 1 0 1 0.7 x reference value 1 1 0 1.3 x reference value 1 1 1 inhibited (32-22) discharge on/off discharge circuit is used to discharge the electric charge of the capacitors on the v 1 to v 4 and the v lcd terminals. the ?discharge on/off? instruction is usually required just after the internal power supply is turned off by setting ?0? into the ?dcon? and ?ampon? registers, or just after the external power supply is turned off. during the discharge operation, the internal or external power supply must not be turned on. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 1 1 1 0 * * dis2 dis dis=0: discharge off (capacitors on the v lcd , v 1 , v 2 , v 3 and v 4 ) dis=1: discharge on (capacitors on the v lcd , v 1 , v 2 , v 3 and v 4 ) dis2=0: discharge off (resistance between v out and v ee ) dis2=1: discharge on (resistance between v out and v ee ) note ) v out and v ee are internally connected with the resistor (100k ? typical) in the power-on.
NJU6818 - 78 - (32-23) instruction register address the ?instruction register address? is used to specify the instruction register address, so that it is possible to read out the contents of the instruction registers in combination with the ?instruction register read? instruction. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 0 1 1 0 0 ra3 ra2 ra1 ra0 (32-24) instruction register read / id read the ?instruction register read? instruction is used to read out the contents of the instruction register in combination with the ?instruction register address? instruction. upper 4-bit of the read-out data is assigned to the id data. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0/1 0/1 0/1 id3 id2 id1 id0 internal register data read (32-25) window end column address the ?window end column address? is used to specify the column address for the window end point. the lower 4- bit data is required to be programmed first and then the upper 3-bit data can be programmed. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 0 0 0 0 ex3 ex2 ex1 ex0 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 0 0 0 1 ex7 ex6 ex5 ex4 (32-26) window end row address set the ?window end row address? is used to specify the row address for the window end point. the lower 4-bit data is required to be programmed first and then the upper 3-bit data can be programmed. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 0 0 1 0 ey3 ey2 ey1 ey0 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 0 0 1 1 * ey6 ey5 ey4
NJU6818 - 79 - (32-27) initial reverse line the ?initial reverse line? instruction is used to specify the initial reverse line address for the reverse line display. lower 4-bit data must be programmed first, next upper 3-bit data. it is programmed in between 00 h and 4f h and the line address beyond 4f h is inhibited. the address relation: lsi < lei (i=7 to 0) must be maintained in the reverse line display. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 0 1 0 0 ls3 ls2 ls1 ls0 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 0 1 0 1 * ls6 ls5 ls4 (32-28) last reverse line the ?last reverse line? instruction is used to specify the last reverse line address for the reverse line display. lower 4-bit data must be programmed first, next upper 3-bit. it is programmed in between 00 h and 4f h and the line address beyond the 4f h is inhibited. the address relation: lsi < lei (i=7 to 0) must be maintained in the reverse line display. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 0 1 1 0 le3 le2 le1 le0 csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 0 1 1 1 * le6 le5 le4 (32-29) reverse line display on/off the ?reverse line display on/off? is used to enable or disable the reverse line display for the blink operation and determine the reverse line display mode. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 1 0 0 0 * * bt lrev lrev register the ?lrev? register is used to enable or disable the reverse line display. lrev =0: reverse line display off (normal) lrev =1: reverse line display on
NJU6818 - 80 - bt register the ?bt? register is used to determine the reverse line display mode in the reverse line display on (lrev=1) status. bt =0: normal reverse line display bt =1: blink once every 32 frames display examples in the lrev=?1? and bt=?1? njrc lcd driver low power and low voltage njrc lcd driver low power and low voltage blink once every 32 frames initial reverse line address last reverse line address blink once every 32 frames
NJU6818 - 81 - (32-30) gradation palette setting control csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 1 0 0 1 * * * ps ps register ps=0: lower 8 gradation setting ps=1: upper 8 gradation setting (32-31) pwm control the ?pwm control? is used to determine the pwm type for segment waveforms, where the type can be specified for each of the segai, segbi and segci (i=0-103) drivers. csb rs rdb wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 1 0 1 1 0 1 0 pwms pwma pwmb pwmc pwms register pwms=0: type 1 pwms=1: type 2 pwma, b and c registers the ?pwma, pwmb and pwmc? registers are used to select the type 1-o or type 1-e. pwmz=0 (z=a, b and c): type 1-o pwmz=1 (z=a, b and c): type 1-e pwm type1 (pwms=?0?) pwm type2 (pwms=?1?) odd line even line ?h? ?l? v lcd v 2 v 2 type-o type-e cl seg v lcd ?h? ?l? cl seg v 2 v lcd
NJU6818 - 82 - (33) the relation between common drivers and row addresses row address assignment of common drivers is programmed by the ?shift? register of the ?display control (1)?, ?duty cycle ratio?, ?initial display line? and ?initial com line? instructions. when initial display line is ?0? if the ?shift? is ?0?, the scan direction is normal. when the ?la 0 to la 6 ? registers of the ?initial display line? instruction is ?0?, the ?my? corresponding to the initial com line is ?0? and is increasing during display. when initial display line is not ?0? if the ?shift? is ?1?, the scan direction is inversed. when the ?la 0 to la 6 ? registers of the ?initial display line? instruction is not ?0?, the ?my? corresponding to the initial com line is this setting value and is increasing during display. the followings are examples of setting the start-line 0 or 5 at 1/81, or 1/13 duty.
NJU6818 - 83 - (33-1) initial display line ?0?, 1/81 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 6 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 com 0 0 76 72 64 56 48 40 32 24 16 8 com 1 com 2 com 3 79 com 4 0 com 5 com 6 com 7 79 com 8 0 com 9 com 10 com 11 com 12 com 13 com 14 com 15 79 com 16 0 com 17 com 18 com 19 com 20 com 21 com 22 com 23 79 com 24 0 com 25 com 26 com 27 com 28 com 29 com 30 com 31 79 com 32 0 com 33 com 34 com 35 com 36 com 37 com 38 com 39 79 com 40 0 com 41 com 42 com 43 com 44 com 45 com 46 com 47 79 com 48 0 com 49 com 50 com 51 com 52 com 53 com 54 com 55 79 com 56 0 com 57 com 58 com 59 com 60 com 61 com 62 com 63 79 com 64 0 com 65 com 66 com 67 com 68 com 69 com 70 com 71 79 com 72 0 com 73 com 74 com 75 com 76 com 77 com 78 com 79 79 75 71 63 55 47 39 31 23 15 7 (81 th com period) *1 79 79 79 79 79 79 79 79 79 79 79 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 81 th com period is not selected.
NJU6818 - 84 - (33-2) initial display line ?0?, 1/13 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?1001?, la 6 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 com 0 0 8 com 1 com 2 com 3 11 com 4 0 com 5 com 6 com 7 com 8 0 com 9 com 10 com 11 11 com 12 com 13 com 14 com 15 11 com 16 0 com 17 com 18 com 19 11 com 20 com 21 com 22 com 23 com 24 0 com 25 com 26 com 27 11 com 28 com 29 com 30 com 31 com 32 0 com 33 com 34 com 35 11 com 36 com 37 com 38 com 39 com 40 0 com 41 com 42 com 43 11 com 44 com 45 com 46 com 47 com 48 0 com 49 com 50 com 51 11 com 52 com 53 com 54 com 55 com 56 0 com 57 com 58 com 59 11 com 60 com 61 com 62 com 63 com 64 0 com 65 com 66 com 67 11 com 68 com 69 com 70 com 71 com 72 0 com 73 com 74 com 75 11 com 76 com 77 com 78 com 79 7 (13 th com period) *1 11 11 11 11 11 11 11 11 11 11 11 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 13 th com period is not selected.
NJU6818 - 85 - (33-3) initial display line ?0?, 1/81 duty cycle (common backward scan) shift=?1?(common backward scan), ds 3 , 2 , 1 , 0 =?0000?, la 6 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 com 0 79 75 71 63 55 47 39 31 23 15 7 com 1 com 2 com 3 com 4 com 5 com 6 com 7 0 com 8 79 com 9 com 10 com 11 com 12 com 13 com 14 com 15 0 com 16 79 com 17 com 18 com 19 com 20 com 21 com 22 com 23 0 com 24 79 com 25 com 26 com 27 com 28 com 29 com 30 com 31 0 com 32 79 com 33 com 34 com 35 com 36 com 37 com 38 com 39 0 com 40 79 com 41 com 42 com 43 com 44 com 45 com 46 com 47 0 com 48 79 com 49 com 50 com 51 com 52 com 53 com 54 com 55 0 com 56 79 com 57 com 58 com 59 com 60 com 61 com 62 com 63 0 com 64 79 com 65 com 66 com 67 com 68 com 69 com 70 com 71 0 com 72 79 com 73 com 74 com 75 0 com 76 79 com 77 com 78 com 79 0 76 72 64 56 48 40 32 24 16 8 (81 th com period) *1 79 79 79 79 79 79 79 79 79 79 79 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 81 th com period is not selected.
NJU6818 - 86 - (33-4) initial display line ?5?, 1/81 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 6 ?.la 0 =?00000101?(initial display line 5) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 com 0 5 1 77 69 61 53 45 37 29 21 13 com 1 78 com 2 79 com 3 0 com 4 5 com 5 com 6 com 7 com 8 5 com 9 com 10 79 com 11 0 com 12 com 13 com 14 com 15 com 16 5 com 17 com 18 79 com 19 0 com 20 com 21 com 22 com 23 com 24 5 com 25 com 26 79 com 27 0 com 28 com 29 com 30 com 31 com 32 5 com 33 com 34 79 com 35 0 com 36 com 37 com 38 com 39 com 40 5 com 41 com 42 79 com 43 0 com 44 com 45 com 46 com 47 com 48 5 com 49 com 50 79 com 51 0 com 52 com 53 com 54 com 55 com 56 5 com 57 com 58 79 com 59 0 com 60 com 61 com 62 com 63 com 64 5 com 65 com 66 79 com 67 0 com 68 com 69 com 70 com 71 com 72 5 com 73 com 74 79 com 75 0 com 76 com 77 com 78 79 com 79 4 0 76 68 60 52 44 36 28 20 12 (81 th com period) *1 79 79 79 79 79 79 79 79 79 79 79 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 81 th com period is not selected.
NJU6818 - 87 - (33-5) initial display line ?0?, 1/80 duty cycle (common forward scan, dse=?1?) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 6 ?.la 0 =?00000000?(initial display line 0) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 com 0 0 76 72 64 56 48 40 32 24 16 8 com 1 com 2 com 3 79 com 4 0 com 5 com 6 com 7 79 com 8 0 com 9 com 10 com 11 com 12 com 13 com 14 com 15 79 com 16 0 com 17 com 18 com 19 com 20 com 21 com 22 com 23 79 com 24 0 com 25 com 26 com 27 com 28 com 29 com 30 com 31 79 com 32 0 com 33 com 34 com 35 com 36 com 37 com 38 com 39 79 com 40 0 com 41 com 42 com 43 com 44 com 45 com 46 com 47 79 com 48 0 com 49 com 50 com 51 com 52 com 53 com 54 com 55 79 com 56 0 com 57 com 58 com 59 com 60 com 61 com 62 com 63 79 com 64 0 com 65 com 66 com 67 com 68 com 69 com 70 com 71 79 com 72 0 com 73 com 74 com 75 com 76 com 77 com 78 com 79 79 75 71 63 55 47 39 31 23 15 7 ds: duty cycle ratio, sc: initial com line, la: initial display line
NJU6818 - 88 - absolute maximum ratings parameter symbol condition terminal rating unit supply voltage (1) v dd v dd -0.3 to +4.0 v supply voltage (2) v ee v ee -0.3 to +4.0 v supply voltage (3) v out v out -0.3 to +19.0 v supply voltage (4) v reg v reg -0.3 to +19.0 v supply voltage (5) v lcd v lcd -0.3 to +19.0 v supply voltage (6) v 1 , v 2 , v 3 , v 4 v 1 , v 2 , v 3 , v 4 -0.3 to v lcd + 0.3 v input voltage v i v ss =0v ta = +25 c *1 -0.3 to v dd + 0.3 v storage temperature t stg -45 to +125 c note 1) d 0 to d 15 , csb, rs, rdb, wrb, osc 1 , resb, test 1, test 2 , terminals. recommended operating conditions parameter symbol terminal min typ max unit note v dd1 1.7 3.3 v *1 v dd2 v dd 2.4 3.3 v *2 supply voltage v ee v ee 2.4 3.3 v *3 v lcd v lcd 5 18.0 v *4 v out v out 18.0 v v reg v reg v out 0.9 v operating voltage v ref v ref 2.1 3.3 v *5 operating temperature t opr -30 85 c note1) applies to the condition when the reference voltage generator is not used. note2) applies to the condition when the reference voltage generator is used. note3) applies to the condition when the voltage booster is used. note4) the following relation among the supply voltages must be maintained. v ss NJU6818 - 89 - dc characteristics 1 v ss = 0v, v dd = +1.7 to +3.3v, ta = -30 to +85 c parameter sym bol condition min typ max unit note high level input voltage v ih 0.8 v dd v dd v *1 low level input voltage v il 0 0.2v dd v *1 high level output voltage v oh1 i oh = -0.4ma v dd - 0.4 v *2 low level output voltage v ol1 i ol = 0.4ma 0.4 v *2 high level output voltage v oh2 i oh = -0.1ma v dd - 0.4 v *3 low level output voltage v ol2 i ol = 0.1ma 0.4 v *3 input leakage current i li v i = v ss or v dd -10 10 a *4 output leakage current i lo v i = v ss or v dd -10 10 a *5 v lcd = 10v 1 2 driver on-resistance r on1 | ? v on | = 0.5v v lcd = 6v 2 4 k ? *6 stand-by current i stb csb=v dd , ta=25 c v dd = 3v 15 a *7 f osc1 309 377 445 *8 f osc2 69 85 101 *9 internal oscillation frequency f osc3 v dd = 3v ta = 2 5 c 10.0 12.2 14.4 khz *10 f r1 rf=24k ? 382 f r2 rf=120k ? 84 external oscillation frequency f r3 rf=820k ? 12.8 khz *11 voltage converter output voltage v out n-time booster (n=2 to 6) rl = 500k ? (v out - v ss ) (n x v ee ) x 0.95 v *12 supply current (1) i dd1 v dd = 3v, 6-time booster whole on pattern 760 1140 supply current (2) i dd2 v dd = 3v, 6-time booster checker pattern 930 1400 supply current (3) i dd3 v dd = 3v, 5-time booster whole on pattern 520 780 supply current (4) i dd4 v dd = 3v, 5-time booster checker pattern 650 980 supply current (5) i dd5 v dd = 3v, 4-time booster whole on pattern 360 540 supply current (6) i dd6 v dd = 3v, 4-time booster checker pattern 450 680 a *13 v ba operating voltage v ba v ee = 2.4 to 3.3v (0.9 v ee ) x 0.98 0.9 v ee (0.9 v ee ) x 1.02 v *14 v reg operating voltage v reg v ee = 2.4 to 3.3v v ref = 0.9 x v ee n-time booster (n=2 to 6) (v ref x n) x 0.97 (v ref x n) (v ref x n) x 1.03 v *15 v 2 -100 0 +100 v 3 -100 0 +100 v d12 -30 0 +30 v d34 -30 0 +30 output voltage v d24 -30 0 +30 mv *16
NJU6818 - 90 - clock and frame frequency display duty cycle ratio (1/d) parameter symbol display mode 1/81 to 1/57 1/47 to 1/27 1/17, 1/13 note 16 gradation mode f osc / (62xd) f osc / (62xdx2) f osc / (62xdx4) simplified 8 gradation mode f osc / (14xd) f osc / (14xdx2) f osc / (14xdx4) internal clock f osc b&w mode f osc / (2xd) f osc / (2xdx2) f osc / (2xdx4) 16 gradation mode f ck / (62xd) f ck / (62xdx2) f ck / (62xdx4) simplified 8 gradation mode f ck / (14xd) f ck / (14xdx2) f ck / (14xdx4) external clock f ck b&w mode f ck / (2xd) f ck / (2xdx2) f ck / (2xdx4) flm
NJU6818 - 91 - applied terminals and conditions note 1) d 0 -d 15 , csb, rs, rdb, wrb, p/s, sel68, resb note 2) d 0 -d 15 note 3) cl, flm, fr, clk note 4) csb, rs, sel68, rdb, wrb, p/s, resb, osc 1 note 5) d 0 -d 15 in high impedance note 6) sega 0 -sega 103 , segb 0 -segb 103 , segc 0 -segc 103 , com 0 -com 79 - defines the resistance between the com/seg terminals and the power supply terminals (v lcd , v 1 , v 2 , v 3 and v 4 ) at the condition of 0.5v deference and 1/9 lcd bias ratio note 7) v dd - the oscillator is halted, csb=?1? (disabled), no-load on the com/seg drivers note 8) osc - defines the internal oscillation frequency at (rf2, rf1, rf0)=(0,0,0) in the variable gradation mode note 9) osc - defines the internal oscillation frequency at (rf2, rf1, rf0)=(0,0,0) in the fixed gradation mode note 10) osc - defines the internal oscillation frequency at (rf2, rf1, rf0)=(0,0,0) in the black & white mode note 11) v dd =3v, ta=25 c note 12) v out - applies to the condition when the internal voltage booster, the internal oscillator and the internal power circuits are used - v ee =2.4v to 3.3v, evr= (1,1,1,1,1,1,1), 1/4 to 1/10 lcd bias, 1/81 duty cycle, no-load on the com/seg drivers - rl=500k ? between the vout and the vss, ca1=ca2=1.0uf, ca3=0.1uf, dcon=?1?, ampon=?1? note 13) v dd - applies to the condition using the internal oscillator and the internal power circuits, no access between the lsi and mpu - evr= (1,1,1,1,1,1,1), all pixels turned-on or checkerboard display in the gradation mode, no-load on the com/seg drivers - v dd =v ee , v ref =0.9v ee , ca1=ca2=1.0uf, ca3=0.1uf, dcon=?1?, ampon=?1?, nlin=?0?, 1/81 duty cycle, ta=25 c note 14) v ba - applies to the condition that v ba =v ref and the voltage booster n= 1, dcon=?0?, v out =13.5v input. note 15) v reg - v ee =2.4v to 3.3v, v ref =0.9v ee , v out =18v, 1/4 to 1/10 lcd bias ratio, 1/81 duty cycle, evr=(1,1,1,1,1,1,1), - checkerboard display, no-load on the com/seg drivers, the voltage booster n=2 to 6, ca1=ca2=1.0uf, ca3=0.1uf, dcon=?0?, ampon=?1?, nlin=?0? note 16) v lcd , v 1 , v 2 , v 3 , v 4 - v ee =3.0v, v ref =0.9v ee , v out =15v, 1/4 to 1/10 lcd bias, evr= (1,1,1,1,1,1,1), display off, no-load on the com/seg drivers, voltage booster n=5, ca1=ca2=1.0uf, ca3=0.1uf, dcon=?0?, ampon=?1? v d12 : (1)-(2) v d34 : (3)-(4) v d24 : (2)-(4) (1) (2) (3) (4) v lcd v 1 v 2 v 3 v 4 v ss
NJU6818 - 92 - ac characteristics write operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 90 35 35 ns ns ns wrb data setup time data hold time t ds8 t dh8 30 5 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 160 70 70 ns ns ns wrb data setup time data hold time t ds8 t dh8 40 5 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 180 80 80 ns ns ns wrb data setup time data hold time t ds8 t dh8 70 10 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb wrb rs d 0 to d 15 t ah8 t wrlw8 t wrhw8 t ds8 t dh8 t cyc8
NJU6818 - 93 - read operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 180 80 80 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 60 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 180 80 80 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 60 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 300 140 140 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 130 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb rs d 0 to d 15 t rdd8 t rdh8 t cyc8 rdb t wrlr8 t wrhr8 t ah8
NJU6818 - 94 - write operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 90 35 35 ns ns ns e data setup time data hold time t ds6 t dh6 40 5 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 160 70 70 ns ns ns e data setup time data hold time t ds6 t dh6 50 5 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 180 80 80 ns ns ns e data setup time data hold time t ds6 t dh6 70 10 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/w ( wrb ) d 0 to d 15 t ehw6 t elw6 t ds6 t dh6 t cyc6 e ( rdb )
NJU6818 - 95 - read operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 180 80 80 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 70 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 180 80 80 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 70 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 300 140 140 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 130 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/w (wrb) d 0 to d 15 t ehr6 t elr6 t rdd6 t rdh6 t cyc6 e (rdb)
NJU6818 - 96 - serial interface (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?h? level pulse width 2 scl ?l? level pulse width t cycsb t shw t shw2 t slw note 2) 50 20 300 20 ns ns ns ns scl address setup time address hold time t ass t ahs 20 20 ns ns rs data setup time data hold time t dss t dhs 20 20 ns ns sda csb ? scl time csb hold time t css t csh 20 20 ns ns csb (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?h? level pulse width 2 scl ?l? level pulse width t cycs t shw t shw2 t slw note 2) 50 20 400 20 ns ns ns ns scl address setup time address hold time t ass t ahs 20 20 ns ns rs data setup time data hold time t dss t dhs 20 20 ns ns sda csb ? scl time csb hold time t css t csh 20 20 ns ns csb (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?h? level pulse width 2 scl ?l? level pulse width t cycs t shw t shw2 t slw note 2) 80 35 500 35 ns ns ns ns scl address setup time address hold time t ass t ahs 35 35 ns ns rs data setup time data hold time t dss t dhs 35 35 ns ns sda csb ? scl time csb hold time t css t csh 35 35 ns ns csb note) each timing is specified based on 20% and 80% of v dd . note 2) t shw2 applies to the condition when the id read-out. refer to the (18) ?chip identification? for the detail. t css csb rs t csh sda t slw t shw t dss t dhs t cycs scl t a hs t ass
NJU6818 - 97 - display control timing output timing (v dd =2.4 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal flm delay time t dflm cl=15pf 0 500 ns flm fr delay time t fr 0 500 ns fr cl delay time t dcl 0 200 ns cl output timing (v dd =1.7 to 2.4v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal flm delay time t dflm cl=15pf 0 1000 ns flm fr delay time t fr 0 1000 ns fr cl delay time t dcl 0 200 ns cl note) each timing is specified based on 20% and 80% of v dd . cl t dflm t fr flm t dflm fr clk t dcl
NJU6818 - 98 - input clock timing (v dd =1.7 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal osc 1 ?h? level pulse width (1) t ckhw1 1.12 1.62 s osc 1 ?l? level pulse width (1) t cklw1 1.12 1.62 s osc 1 ? 1 osc 1 ?h? level pulse width (2) t ckhw2 4.95 7.25 s osc 1 ?l? level pulse width (2) t cklw2 4.95 7.25 s osc 1 ? 2 osc 1 ?h? level pulse width (3) t ckhw3 34.7 50.0 s osc 1 ?l? level pulse width (3) t cklw3 34.7 50.0 s osc 1 ? 3 note) each timing is specified based on 20% and 80% of v dd . note 1) applied to the variable gradation mode /mon=?0?,pwm=?0? note 2) applied to the fixed gradation mode /mon=?0?,pwm=?1? note 3) applied to the b&w mode /mon=?1? reset input timing (v dd =2.4 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal reset time t r 1.0 s resb ?l? level pulse width t rw 10.0 s resb (v dd =1.7 to 2.4v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal reset time t r 1.5 s resb ?l? level pulse width t rw 10.0 s resb note) each timing is specified based on 20% and 80% of v dd . osc 1 t cklw t ckhw t rw resb internal circuit status end of reset during reset t r
NJU6818 - 99 - typical characteristic parameter symbol min typ max unit basic delay time of gate ta=+25 c, v ss =0v, v dd =3.0v 10 ns input output terminal type (a) input circuit terminals: csb, rs, rdb, wrb, sel68, p/s, resb (b) output circuit terminals: flm, cl, fr, clk (c) input/output circuit terminals: d 0 to d 15 v dd i v ss (0v) input signal o v dd v ss (0v) output control signal output signal i/o v dd v ss (0v) input signal v dd v ss (0v) output control signal output signal v ss (0v) input control signal
NJU6818 - 100 - (d) display output circuit terminals: sega 0 to sega 103 segb 0 to segb 103 segc 0 to segc 103 com 0 to com 79 o v lcd v ss (0v) output control signal 1 v 1 /v 2 v ss (0v) output control signal 3 v lcd v ss (0v) v 3 /v 4 output control signal 2 output control signal 4 v lcd
NJU6818 - 101 application circuit examples (1) mpu connections 80-type mpu interface 68-type mpu interface serial interface a 0 v cc a 1 to a 7 iorqb d 0 to d 7 rdb wr resb gnd 7 decoder rs csb d 0 to d 7 rdb wrb resb v dd v ss 8 reset 1.7v to 3.3v (80-type mpu) a 0 v cc a 1 to a 15 vm a d 0 to d 7 e r/w resb gnd 15 decoder rs csb d 0 to d 7 rdb ( e ) wrb ( r/w ) resb v dd v ss 8 reset 1.7v to 3.3v (68-type mpu) a 0 v cc a 1 to a 7 port 1 port 2 resb gnd 7 decoder rs csb sd a scl resb v dd v ss reset 1.7v to 3.3v ( mpu )
NJU6818 - 102 - [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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