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?005 fairchild semiconductor corporation 1 www.fairchildsemi.com may 2005 f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller features selectable 1-, 2-, or 3-phase operation at up to 1mhz per phase ?% worst-case differential sensing error over temperature externally adjustable 0.8v to 5v output from a 12v supply logic-level pwm outputs for interface to external high-power drivers active current balancing between all phases built-in power-good/crowbar functions programmable over current protection with adjustable latch- off delay applications a uxiliary supplies ddr memory supplies p oint-of-load supplies description the fan5182 is a highly ef?ient multi-phase synchronous buck s witching regulator controller optimized for converting a 12v main supply into a high-current low voltage supply for use in point-of-load (pol) applications. it uses a multi-loop pwm architecture to drive the logic-level outputs at a programmable s witching frequency that can be optimized for regulator size and ef?iency. the phase relationship of the output signals can be programmed to provide 1, 2, or 3-phase operation, allowing for construction of up to three complementary interleaved buck s witching stages. the fan5182 also provides accurate and reliable over-current protection and adjustable current limiting. f an5182 is speci?d over the commercial temperature range of 0? to +85? and is available in a 20-lead qsop package. block diagram vcc 800 mv reference soft start delay uvlo shutdown & bias oscillator + gnd fan5182 14 en 6 delay 7 ilimit 10 pwrgd 5 1 rt 8 rampadj 9 pwm2 19 3 fb pwm3 18 sw1 17 cssum 12 cscomp 13 sw2 16 sw3 15 csref 11 pwm1 fbrtn 2 comp 4 950mv + 1.05v + 650mv + fb fb en current limit circuit crowbar current limit + cmp + cmp + + cmp current balancing circuit 1/ 2 / 3-phase driver logic en set reset reset reset 20
2 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller pin assignment pin description pin # pin name pin description 1 vcc supply voltage for the device. 2 fbrtn feedback return. voltage error ampli?r reference for remote sensing of the output voltage. 3f bf eedback input. error ampli?r input for remote sensing of the output voltage. an external resistor divider between the output and fbrtn connected to this pin sets the output voltage. this pin is also the reference point for the power good and crowbar comparators. 4 comp error ampli?r output and compensation pin. 5 pwrgd power good output. open-drain output that signals when the output voltage is outside the proper operating range. 6e np ow er supply enable input. pulling this pin to gnd disables the pwm outputs and pulls the pwrgd output low. 7 delay soft-start delay and current limit latch-off delay setting input. an external resistor and capacitor connected between this pin and gnd set the soft-start ramp-up time and the overcurrent latch-off delay time. 8r tf requency setting resistor input. an external resistor connected between this pin and gnd sets the oscillator frequency of the device. 9 rampadj pwm ramp current input. an external resistor from the converter input voltage to this pin sets the internal pwm ramp. 10 ilimit current limit setpoint/enable output. an external resistor connected from this pin to gnd sets the current limit threshold of the converter. this pin is actively pulled low when the fan5182 en input is low, or when vcc is below its uvlo threshold, to signal to the driver ic that the driver high-side and low-side outputs should go low. 11 csref current sense reference voltage input. the voltage on this pin is used as the reference for the cur- rent sense ampli?r. this pin should be connected to the common point of the output inductors. 12 cssum current sense summing node. external resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. 13 cscomp current sense compensation point. a resistor and a capacitor from this pin to cssum determine the gain of the current sense ampli?r. 14 gnd ground. all internal biasing and the logic output signals of the device are referenced to this ground. 15?7 sw3 to sw1 current balance inputs. these are inputs for measuring the current level in each phase. the sw pins of unused phases should be left open. 18?0 pwm3 to pwm1 logic-level pwm outputs. each output is connected to the input of an external mosfet driver such as the fan5009. connecting the pwm3 output to gnd causes that phase to turn off, allowing the f an5182 to operate as a 1- or 2-phase controller. fan5182 vcc fbrtn fb comp pwrgd en delay rt rampadj ilimit pwm1 pwm2 pwm3 sw1 sw2 sw3 gnd cscomp cssum csref 1 2 3 20 19 18 4 8 10 5 6 7 13 16 15 14 9 11 12 17 qsop-20l
3 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller absolute maximum ratings (note 1) recommended operating conditions notes: 1. stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress ratin g only and functional operation of the device at these or any other conditions above those indicated in the operational section o f this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . absolute maximum ratings apply individually only, not in combination. unless otherwise specified all other voltages are referen ced to gnd. 2. junction to ambient thermal resistance, ja , is a strong function of pcb material, board thickness, thickness and number of copper planes, number of via used, diameter of via used, available copper surface, and attached heat sink characteristics. measured wi th the device mounted on a board of fr-4 material, 0.063?thickness, no copper plane and zero airflow. p arameter min. max. unit vcc -0.3 +15 v fbrtn -0.3 +0.3 v en, delay, ilimit, rt, pwm1-pwm3, comp -0.3 5.5 v sw1-sw3 -5 +25 v all other inputs and outputs -0.3 vcc + 0.3 v operating junction temperature, t j 0 +125 ? storage temperature -65 +150 ? lead soldering temperature (10 seconds) 300 ? lead infrared temperature (15 seconds) 260 ? thermal resistance junction-to-case, ( jc )3 8 ?/w thermal resistance junction-to- ambient, ( ja ) (note 2) 90 ?/w p arameter min typ max unit supply voltage range 10.8 12 13.2 v operating ambient temperature 0 +85 ?
4 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller electrical characteristics v cc = 12v, fbrtn = gnd. indicates speci?ations over operating ambient temperature range. (note 1) p arameter symbol conditions min. typ. max. units oscillator f requency range f osc 0.25 3 mhz f requency variation f phase r t = 332k ? , 3-phase t a = 25?, r t = 154k ? , 3-phase t a = 25?, r t = 100k ? , 3-phase 155 200 400 600 245 khz output voltage v rt r t = 100k ? to gnd 2.0 v rampadj output voltage v rampadj rampadj - fb - 2k ? x i rampadj (with i rampadj set to 20 a) -50 +50 mv rampadj input current range (note 2) i rampadj 0 100 a vo lta ge error amplifier output voltage low 0.3 v output voltage high 3.1 v accuracy v fb referenced to fbrtn 784 800 816 mv input bias current i fb fb = 800mv -4 ? +4 a line regulation ? v fb v cc = 10v to 14v 0.05 % fbrtn current i fbrtn 100 140 a output current i o(err) fb forced to v out - 3% 500 a dc gain (note 2) 87 db gain bandwidth product (note 2) g bw(err) comp = fb 20 mhz slew rate (note 2) c comp = 10pf 10 v/ s current sense amplifier offset voltage v os(csa) cssum-csref ( see figure 1.) -5.5 +5.5 mv input bias current i bias(cssum) -50 +50 na dc gain (note 2) 70 db gain bandwidth product (note 2) gbw (csa) 10 mhz slew rate (note 2) c cscomp = 10pf 10 v/ s input common-mode range cssum & csref 0 v cc -2.5 v output voltage low 0.1 v output voltage high v cc -2.5 v output current i cscomp 500 a current balance circuit common-mode range (note 2) v sw(x)cm -600 +200 mv input resistance r sw(x) sw(x) = 0v 20 30 40 k ? input current i sw(x) sw(x) = 0v 4710 a input current matching ? i sw(x) sw(x) = 0v -7 +7 % current limit comparator output voltage: normal mode v ilimit(nm) en > 2v, r ilimit = 250k ? 2.9 3 3.1 v output voltage: shutdown mode v ilimit(sd) en < 0.8v, i ilimit = -100 a 400 mv output current: normal mode i ilimit(nm ) en > 2v, r ilimit = 250k ? 12 a maximum output current 60 a
5 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller notes: 1. all limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control. 2. guaranteed by design, not tested in production. current limit threshold v oltage v cl v csref - v cscomp , r ilimit = 250k ? 105 125 145 mv current limit setting ratio v cl /i ilimit 10.4 mv/ a delay normal mode voltage v delay(nm) r delay = 250k ? 2.9 3 3.1 v delay overcurrent threshold v delay(oc) r delay = 250k ? 1.7 1.8 1.9 v latch-off delay time (note 2) t delay r delay = 250k ?, c delay = 12nf 1.5 ms soft-start output current, soft-start mode i delay(ss) during startup, delay < 2.4v 15 20 25 a soft-start delay time (note 2) t delay(ss) r delay = 250k ?, c delay = 12nf 500 s enable input input low voltage v il(en) 0.8 v input high voltage v ih(en) 2.0 v input hysteresis voltage 100 mv input current i in(en) -1 +1 a power good comparator undervoltage threshold v pwrgd(uv) relative to fbrtn 600 660 720 mv overvoltage threshold v pwrgd(ov) relative to fbrtn 880 940 1000 mv ouput low voltage v ol(pwrgd) i pwrgd(sink) = 4ma 225 400 mv po w er good delay time 200 ns crowbar trip point v crowbar relative to fbrtn 0.970 1.05 1.105 v crowbar reset point relative to fbrtn 550 650 750 mv crowbar delay point (note 2) t crowbar overvoltage to pwm going low 400 ns pwm outputs output low voltage v ol(pwm) i pwm(sink) = 400 a 160 500 mv output high voltage v oh(pwm) i pwm(source) = -400 a 4.0 5 v supply dc supply current 510ma uvlo threshold voltage v uvlo v cc rising 6.5 6.9 7.3 v uvlo hysteresis 0.7 0.9 1.1 v p arameter symbol conditions min. typ. max. units
6 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller t est circuit figure 1. current sense ampli?r v os + ? cssum 13 cscomp 12 vcc csref 11 gnd 14 1 39k ? 100nf 1k ? 0.8v fan5182 + ? 12v v os = cscomp ? 0.8v 40
7 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller t ypical characteristics figure 2. master clock frequency figure 3. supply current vs. osc. frequency figure 4. normalized v fb vs. temperature 3 2 1 0 master clock frequency (mhz) r t value (k w ) 050 100 150 200 250 300 0 0.5 1 1.5 2 2.5 3 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 supply current (ma) oscillator frequency (mhz) t a = 25 c 3-phase operation 0.994 0.996 0.998 0.992 1.000 1.002 02585 temperature ( c) normalized v fb
8 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller application circuit figure 5. 1.8v, 55a application circuit ( consult fairchild sales for an updated version of the application circuit ) v in 12 v v in rtn enable power good r lim 287k ? r ph1 140k ? r r 332k ? q1 fdd6296 q2 fdd8896 q3 fdd6296 q5 fdd6296 q4 fdd8896 q6 fdd8896 c dly 68nf v out 1.8 v 55a v out 1200 f / 6.3v x 5 15m ? esr (each) + l2 600nh / 1.4m ? l3 600nh / 1.4m ? l4 600nh / 1.4m ? l1 1 h r t 255k ? c8 100nf c17 + c21 u3 fan5009 1 2 3 8 7 6 4 5 boot pwm od vcc hdrv sw pgnd ldrv c7 1 f c4 100nf c3 1 f c5 4.7 f c9 4.7 f c13 4.7 f u2 fan5009 1 2 3 8 7 6 4 5 boot pwm od vcc hdrv sw pgnd ldrv c12 100nf u4 fan5009 u1 fan5182 1 2 3 8 7 6 4 5 boot pwm od vcc hdrv sw pgnd ldrv c11 1 f c15 1 f r4 10 ? r a 6.04k ? c fb 100pf c a 1.2nf c cs 5.6nf c2 2700 f 16v c1 2700 f 16v + + 4.7 fx10 6.3v mlcc c14 2.2nf c10 2.2nf c6 2.2nf r3 2.2 ? r2 2.2 ? r1 2.2 ? d1 (optional) d2 (optional) d3 (optional) r b2 1.24k ? r b1 1.00k ? r cs 100k ? r ph2 140k ? r dly 261k ? r sw1 * r sw3 * r sw2 * r ph3 140k ? vcc fbrtn fb comp pwrgd en delay rt rampadj ilimit pwm1 pwm2 pwm3 sw1 sw2 sw3 gnd cscomp cssum csref 1 2 3 20 19 18 4 8 10 5 6 7 13 16 15 14 9 11 12 17 rtn
9 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller theory of operation the fan5182 combines a multi-loop, ?ed frequency pwm con- trol with multi-phase logic outputs for use in 1-, 2-, and 3-phase synchronous buck point-of-load power supplies. multi-phase operation is important for producing the high current and low v oltage demanded by auxiliary supplies in desktop computers, wo r kstations, and servers. handling high current in a single- phase converter places high thermal stress on components such as inductors and mosfets, therefore is not preferred. the multi-loop control of the fan5182 ensures a stable, high performance topology for: balancing current and thermal between/among phases ? ast response at the lowest possible switching frequency and output decoupling reducing switching losses due to low frequency operation tight line and load regulation reducing output ripple due to multiphase cancellation better noise immunity to facilitate pcb layout start-up sequence during start-up, the number of operational phases and their phase relationship are determined by the internal circuitry that monitors the pwm outputs. normally, the fan5182 operates as a 3-phase pwm controller. grounding the pwm3 pin programs f or 1- or 2-phase operation. when the fan5182 is enabled, the controller outputs a voltage on pwm3 which is approximately 675mv. an internal compara- tor checks this pin's voltage versus a threshold of 300mv. if the pwm3 pin is grounded, it is below the threshold and the phase 3 is disabled. the output resistance of the pwm pin is approxi- mately 5k ? during this detection period. any external pull-down resistance connected to the pwm pin should not be less than 25k ? to ensure proper operation. pwm1 and pwm2 are dis- abled during the phase detection interval, which occurs during the ?st two clock cycles of the internal oscillator. after this time, if the pwm3 output is not grounded, the 5k ? resistance is dis- connected and pwm3 switches between 0v and 5v. if the pwm3 output is grounded, the controller will operate in 1 and/or 2-phase. the pwms output logic-level signals in order to interface with e xternal gate drivers such as the fan5009. since each phase is able to operate close to 100% duty cycle, more than one pwm output can be on at the same time. master clock frequency the clock frequency of the fan5182 is set by an external resis- tor connected from the rt pin to ground. the frequency setting f ollows the graph shown in figure 2. to determine the frequency per phase, divide the clock frequency by the number of phases in use. one exception is single phase operation, in which the clock frequency is set to be twice the single phase frequency. output voltage differential sensing the fan5182 uses a differential low offset voltage error ampli- ?r to maintain ?% differential sensing accuracy over tempera- ture. the output voltage is sensed between the fb and fbrtn pins. the power supply output connects to the fb pin through a resistor divider, and the fbrtn pin should be connected directly to the remote sense ground. the internal precision ref- erence is referenced to fbrtn, which has a typical current of 100? to allow accurate remote sensing. the internal error ampli?r compares the precision reference to the fb pin to reg- ulate the output voltage. output current sensing the fan5182 uses a current sense ampli?r (csa) to monitor the total output current for current limit detection. sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side mosfet. this ampli?r can be con?ured several ways depending on the objectives of the system design: output inductor dcr sensing without a thermistor for lowest cost output inductor dcr sensing with a thermistor for improved accuracy and moderate cost discrete resistor sensing for the best accuracy the positive input of the csa is connected to the csref pin, and the csref is tied to the power supply output. the inverting input of the csa, cssum, is the summing node of load current sense through sensing elements (such as the switch node side of the output inductors). the feedback resistor between cscomp and cssum sets the gain of the ampli?r, and a ?ter capacitor is placed in parallel with this resistor. the gain of the ampli?r is programmable by adjusting the feedback resistor. the current information is then given as the difference between csref and cscomp. this difference signal is then used as a differential input for the current limit comparator. to provide the best accuracy for sensing current, the csa is designed to have low input offset voltage. the csa gain is determined by external resistors, so that it can be set very accu- r ately. current control loop and thermal balance the fan5182 adopts low side mosfet r dson sensing for phase current balance. the sensed individual phase current is combined with a ?ed internal ramp, then compared with the common voltage error ampli?r output to balance phase cur- rent. this current balance information is independent of the av erage output current information used for current limit described previously. the magnitude of the internal ramp can be set to optimize tran- sient response of the system. it also tracks the supply voltage f or better line regulation and transient response. a resistor con- nected from the power supply input to the rampadj pin deter- mines the slope of the internal pwm ramp. resistors r sw1 through r sw3 (see figure 5) can be used for adjusting phase current balance. it's recommended to put placeholders for these resistors during the initial pcb layout, so that phase current bal- ance ?e adjustments can be made on bench if necessary. to increase the current in any given phase, make r sw f or that phase larger (make r sw = 0 ? f or the hottest phase as the start- ing point). increasing r sw to 500 ? could typically make a sub- stantial increase in this particular phase current. increase each r sw v alue by small amounts to optimize phase current balance, starting with the coolest phase ?st.
10 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller v oltage control loop a high gain-bandwidth voltage error ampli?r is used for the v oltage control loop. the non-inverting input of the error ampli- ?r is derived from the internal 800mv reference. the output of the error ampli?r, the comp pin sets the termination voltage f or the internal pwm ramps plus sensed phase current. the inverting input (fb) is tied to the center point of a resistor divider from the output voltage sense point. the closed loop compensation is realized through the compensator networks connecting to the fb and comp pins. soft start the soft-start rise time of the output voltage is set by a parallel capacitor and resistor between the delay pin and ground. the resistor capacitor (rc) time constant also determines the cur- rent limit latch off delay time as explained in the following sec- tion. in uvlo or when en is logic low, the delay pin is held to g round. after the uvlo threshold is reached and en is in logic high state, the delay capacitor is charged with an internal 20? current source. the output voltage follows the ramping v oltage on the delay pin to limit the inrush current. the soft- start time depends on the value of c dly , with a secondary effect from r dly . if either en is logic low or v cc drops below uvlo, the delay capacitor resets to ground, and is ready for another soft-start cycle. figure 6. typical startup waveforms shows a typical soft-start sequence for the fan5182. figure 6. typical startup waveforms current limit and latch-off protection the fan5182 compares a programmable current limit set point to the voltage from the output of the current sense ampli?r. the level of current limit is set with the resistor from the ilimit pin to g round. during normal operation, the voltage on ilimit is 3v. the current through the external resistor is internally scaled to give a current limit threshold of 10.4mv/?. if the difference in v oltage between csref and cscomp rises above the current limit threshold, the internal current limit ampli?r controls the comp voltage to maintain the power supply output current at the over current level. after the limit is reached, the 3v pull-up voltage source on the delay pin is disconnected, and the external delay capacitor discharges through the external resistor. a comparator monitors the delay pin voltage and shuts off the controller when the v oltage drops below 1.8v. the current limit latch-off delay time is therefore set by the rc time constant discharging the delay v oltage from 3v to 1.8v. typical over-current latch-off wave- fo r ms are shown in figure 7. figure 7. over-current latch-off waveforms the controller continues to switch all phases during the latch-off delay time. if the over-current condition is removed before the 1.8v delay threshold being reached, the controller will resume its normal operation. the over current recovery characteristic also depends on the state of pwrgd. if the output voltage is within the pwrgd window during over current, the controller resumes normal operation once over current condition being removed. however, if over current causes the output voltage to drop below the pwrgd threshold, a soft-start cycle will be initi- ated. the latch-off function can be reset by either removing and reap- plying v cc to the fan5182 or by pulling the en pin low for short time. to disable the over current latch-off function, the external resistor connecting between the delay pin and ground should be removed, and a high value resistor (>1m ? ) should be con- nected from the delay pin to vcc. this prevents the delay capacitor from discharging, so the 1.8v threshold can never be reached. this pull-up resistor has some impact to the soft-start time, because the current through this pull-up resistor adds additional current to the internal 20? soft-start current. during start-up when the output voltage is below 200mv, a sec- ondary current limit is activated. this is necessary because the v oltage swing of cscomp cannot go below ground. this sec- ondary current limit clamps the comp voltage to 2v. an inherent per phase current limit protects individual phase if one or more phases cease to function because of a faulty com- ponent. this limit is based on the maximum normal mode comp voltage.
11 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller po wer good monitoring the power good comparator monitors the output voltage via the fb pin. the pwrgd pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits speci?d in the electri- cal characteristic table. pwrgd goes low if the output voltage is outside of this speci?d range or whenever the en pin is pulled low. figure 8. shows the pwrgd response when the input power supply is switched off. figure 8. shutdown waveforms as part of the protection for the load and output components of the supply, the pwm outputs are driven low (turning on the low- side mosfets) when the output voltage exceeds the crowbar trip point. this crowbar action stops once the output voltage falls below the reset threshold of approximately 650mv. tu r ning on the low-side mosfets pulls down the output as the reverse current builds up in the inductors. if the output over volt- age is due to a short in the high-side mosfet, this crowbar action can trip the input supply over current protection or blow the input fuse, protecting the load from being damaged. enable and uvlo f or the fan5182 to begin switching, the input supply (v cc ) to the controller must be higher than the uvlo threshold, and the en pin must be higher than its logic threshold. if uvlo is less than the threshold or the en pin is logic low, the fan5182 is dis- abled. this holds the pwm outputs at ground, shorts the delay capacitor to ground, and holds the i limit pin at ground. in the application circuit, the i limit pin should be connected to the od pins of the fan5009 drivers. grounding the i limit pin will disable the drivers such that both hdrv and ldrv are hold- ing low. this feature is important in preventing fast discharge of the output capacitors when the controller shuts off. if the driver outputs are not being disabled, a negative output voltage can be generated due to high current being discharged from the output capacitors through the inductors.
12 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller application information design parameters for a typical high current point-of-load dc/dc bu ck converter shown in figure 5 are as follows: input voltage (v in ) = 12v output voltage (v out ) = 1.8v duty cycle (d) = 0.15 output current i o = 55a maximum output current (i lim ) = 110a number of phases (n) = 3 switching frequency per phase ( f sw ) = 250khz setting the clock frequency the fan5182 uses a ?ed-frequency control architecture. the frequency is set by an external timing resistor (r t ). the clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and the input and output capaci- tors. with n = 3 for three phases, a clock frequency of 750khz sets the switching frequency ( f sw ) of each phase to 250khz, which represents a practical trade-off between the switching losses and the sizes of the output ?ter components. equation 1 shows that to achieve a 750khz oscillator frequency, the correct value for r t is 255k ? . alternatively, the value for r t can be calculated using (1) where 4.7pf and 27k ? are internal ic component values. for good initial accuracy and frequency stability, a 1% resistor is recommended. the closest standard 1% value for this design is 255k ? . soft-start and current limit latch-off delay time because the soft start and current limit latch-off delay functions share the delay pin, these two parameters must be considered together. the ?st step is to set c dly for the soft-start ramp. this r amp is generated with a 20? internal current source. the v alue of r dly has a second-order impact on the soft-start time because it sinks part of the current source to ground. however, as long as r dly is kept greater than 200k ? , this effect is minor. the value for c dly can be approximated using: (2) where t ss is the desired soft-start time. assuming an r dly of 390k ? and a desired soft-start time of 3ms, c dly is 71nf. the closest standard value for c dly is 68nf. once c dly is chosen, r dly can be calculated for the current limit latch-off time using: (3) if the result for r dly is less than 200k ? , a smaller soft-start time should be considered by recalculating the equation for c dly , or a longer latch-off time should be used. r dly should never be less than 200k ? . in this example, a delay time of 9ms results in r dly = 259k ? . the closest standard 1% value is 261k ? . inductor selection the inductance determines the ripple current in the inductor. small inductance leads to high ripple current, which increases the output ripple voltage and conduction losses in the mos- fets, and vise versa. in any multiphase converters, it's recom- mended to design the peak-peak inductor ripple current to be less than 50% of the maximum inductor dc current. equation 4 shows the relationship among the inductance, oscil- lator frequency, and peak-peak ripple current. (4) equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. (5) where r x is the esr of output bulk capacitors. solving equation 5 for a 20mv peak-to-peak output ripple volt- age and 3m ? r x yields if the resulting ripple voltage is too low, the inductance can be reduced until the desired ripple voltage is achieved. in this e xample, a 600nh inductor is a good starting point that pro- duces a calculated ripple current of 6.6a. the inductor should not saturate at the peak current of 21.6a, and should be able to handle the total power dissipation created by the copper and core loss. another important factor in the inductor design is the dcr, which is used for measuring the phase current. a large dcr can cause excessive power losses, whereas too small dcr can increases measurement error. for this design, a dcr of 1.4m ? w as chosen. designing an inductor once the inductance and dcr are known, the next step is to either design an inductor or ?d a suitable standard inductor if one exists. inductor design starts with choosing appropriate core material. some candidate materials that have low core loss at high frequencies are powder cores (e.g. kool-m from mag- netics, inc., or from micrometals) and gapped soft ferrite cores (e.g. 3f3 or 3f4 from philips). powdered iron cores have higher core loss, and are used for low cost applications. the best choice for a core geometry is a closed-loop type, such as a potentiometer core, a pq/u/e core, or a toroid core. some useful references for magnetics design are magnetic designer software intusoft (www.intusoft.com) designing magnetic components for high-frequency dc-dc converters, by william t. mclyman, kg magnetics, inc., isbn 1883107008 r t 1 nf sw 4. 7pf -------------------------------------- 27k ? = r t 1 3 25 0khz 4.7pf ------------------------------------------------- - 27k ? 256k ? == c dly 20 a v ref 2 r dly ---------------------- ?? ?? t ss v ref ------------ - = r dly 1.96 t delay c dly --------------------------------- - = i r v out 1d () f sw l ------------------------------------- - = l v out r x 1nd () () f sw v ripple ---------------------------------------------------------------- l 1.8v 3m ? 13 0.15 () () 25 0khz 20mv --------------------------------------------------------------------------- - 59 4nh =
13 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller selecting a standard inductor the following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request. coilcraft (847) 639-6400 www.coilcraft.com coiltronics (561) 752-5000 www.coiltronics.com sumida electric company (510) 668-0660 www.sumida.com vishay intertechnology (402) 563-6866 www.vishay.com output current sense the output current can be measured by summing the voltage across each inductor and passing the signal through a low-pass ?ter. the cs ampli?r is con?ured with resistors r ph(x) (for summing the voltage), and r cs and c cs (for the low-pass ?ter). the output current i o is set by the following equations: (6) (7) where: r l is the dcr of the output inductors. v drp is the voltage drop from cscomp to csref. when load current reaches its limit, v drp is at its maximum (v drpmax ). v drpmax can be in the range of 100mv to 200mv. in this example, it is 110mv. one has the ?xibility of choosing either r cs or r ph(x) . it is rec- ommended to select r cs equal to 100k ? , and then solve for r ph(x) by rearranging equation 6. next, use equation 7 to solve for c cs . choose the closest standard value that is greater than the result given by equation 7. this example uses a c cs value of 5.6nf. output voltage f an5182 has an internal fbrtn referred 800mv voltage refer- ence (v ref ). the output voltage can be set by using a voltage divider consists of resistors r b1 and r b2 : (8) rearranging equation 8 to solve r b2 and assuming a 1%, 1k ? resistor for r b1 yields the closest standard 1% resistor value for r b2 is 1.24k ? . po wer mosfets f or this example, one high-side and one low-side n-channel power mosfets per phase have been selected. the main selection parameters for power mosfets are v gs(th) , q g , c iss , c rss , and r ds(on) . the minimum gate drive voltage (the supply voltage to the fan5009) dictates whether standard threshold or logic-level threshold mosfets can be used. with v gate ~10v, logic-level threshold mosfets (v gs(th) < 2.5v) are recommended. the maximum output current (i o ) determines the r ds(on) requirement for the low-side (synchronous) mosfets. with good current balance among phases, the current in each low- side mosfet is the output current divided by the total number of low-side mosfets (n sf ). since conduction loss is dominant in low-side mosfet, the following expression can represent total power dissipation in each synchronous mosfet in terms of the ripple current per phase (i r ) and the total output current (i o ): (9) knowing the maximum output current and the maximum allowed power dissipation, one can determine the required r ds(on) f or the mosfet. for example, d-pak mosfets oper- ating up to ambient temperature of 50?, a safe limit for p sf is around 1w to 1.5w at 120? junction temperature. therefore, in this example, r ds(sf) (per mosfet) < 7.5m ? . this r ds(sf) is typically measured at junction temperature of about 120? in this example, we select a lower-side mosfet with 4.8m ? at 120?. another important consideration for choosing the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of feedback to input capacitance must be small (less than 10% is recommended) in order to preventing accidentally turning on the synchronous mosfets when the switch node goes high. also, the time to switch the synchronous mosfets off should not exceed the non-overlap dead time of the mosfet driver (40ns typical for the fan5009). the output impedance of the driver is approximately 2 ? , and the typical mosfet input gate resistances are about 1 ? to 2 ? . therefore, the total gate capac- itance should be less than 6000pf. in the event there are two mosfets in parallel, the input capacitance for each synchro- nous mosfet should be limited to 3000pf. the high-side (main) mosfet power dissipation consists of two elements: conduction and switching losses. the switching loss is related to the main mosfets turn on and off time, and the current and voltage being switched. based on the main i o r ph x () r cs ---------------- v drp r l ------------- = c cs l r l r cs ---------------------- r ph x () r l r cs i lim v drpmax ----------------------- - = r ph x () 1.4m ? 100k ? 110a 110mv ------------------ 140k ? == c cs 60 0nh 1.4m ? 100k ? ---------------------------------------- - 4.29nf v out r b1 r b2 + () r b1 ------------------------------ v ref = r b2 v out v ref v ref -------------------------------- - r b1 = r b2 1.8v 0.8v 0.8v ----------------------------- - 1k ? 1.25k ? == p sf 1 d () i o n sf -------- ?? ?? 2 1 12 ----- - ni r n sf ------------- - ?? ?? 2 + r ds sf () =
14 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller mosfets switching speed (rise and fall time that the gate driver can offer) and mosfet input capacitance, the following e xpression provides approximate switching loss for each main mosfet: (10) where: n mf is the total number of main mosfets. r g is the total gate resistance (2 ? f or the fan5009 and about 1 ? for typical logic level n-channel mosfets, total r g = 3 ? ). c iss is the input capacitance of the main mosfet. note that adding more main mosfets (n mf ) does not help to lower the switching loss for each main mosfet, it can only reduces conduction loss. the most ef?ient way to reduce s witching loss is to use low gate charge / capacitance devices. the conduction loss of the main mosfet is given by the follow- ing equation: (11) where r ds(mf) is the on resistance of the main mosfet. t ypically, for main mosfets, a low gate charge (c iss ) device is preferred, but low gate charge mosfets usually have higher on resistance. select a device that meets total power dissipation around 1.5w for a single d-pak mosfet. in this example, a fdd6296 is selected as the main mosfet (three total; n mf = 3), with a c iss = 1440pf, and r ds(mf) = 9m ? (at t j = 120?), and a fdd8896 is selected as the synchronous mosfet (three total; n sf = 3), with c iss = 2525pf and r ds(sf) = 5.4m ? (at t j = 120?). the synchronous mosfet c iss is less than 6000pf. solving for the power dissipation per mos- fet at i o = 55a and i r = 6.6a yields 1.56w for each synchro- nous mosfet and 1.29w for each main mosfet. these n umbers comply with the power dissipation limit of around 1.5w per mosfet. one more item that needs to be considered is the power dissi- pation in the driver for each phase. the gate drive loss is described in terms of the q g f or the mosfets, and is given by the following equation (12) where: q gmf is the total gate charge for each main mosfet. q gsf is the total gate charge for each synchronous mosfet. i cc v cc in equation (12) represents the driver's standby power dissipation. for the fan5009, the maximum dissipation should be less than 400mw. in this example, with i cc = 5ma, q gmf = 25nc, and q gsf = 50nc, there is 285mw in each driver, which is below the 400mw dissipation limit. see the ?hermal information table in the fan5009 datasheet for more details. ramp resistor selection the ramp resistor (r r ) is used for setting the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of phase current balance, stability, and tran- sient response. the following expression is used to determine the optimum value: (13) where: a r is the internal ramp ampli?r gain. a d is the current balancing ampli?r gain. r ds(on)(sf) is the equivalent low-side mosfet on resistance. c r is the internal ramp capacitor value. the closest standard 1% resistor value is 332k ? .. the internal r amp voltage magnitude can be calculated by using (14) the size of the internal ramp can be made larger or smaller. if it is made larger, stability and transient response improve, but thermal balance degrades. likewise, if the ramp is made smaller, thermal balance improves but transient response and stability degrade. the factor of three in the denominator of equation 13 sets a ramp size with optimal balance for good sta- bility, transient response, and thermal balance. current limit setpoint the current limit threshold of the fan5182 is set with a 3v source (v lim ) across r lim with a gain of 10.4 mv/? (a lim ). r lim can be found using (15) if r lim is greater than 500k ? , the actual current limit threshold may be lower than the intended value. hence some adjustment f or r lim may be neeeed. here, i lim is the average current limit f or the output of the supply. in this example, using the v drpmax v alue of 110mv from equations 6 and 7 and choosing a peak current limit of 110a for i lim results in r lim = 284k ? , for which 287k ? is chosen as the nearest 1% value. the per phase current limit described earlier is determined by (16) p smf () 2 f sw v cc i o n mf --------------------- - r g n mf n --------- - c iss = p cmf () d i o n mf --------- - ?? ?? 2 1 12 ----- - ni r n mf ------------- - ?? ?? 2 + r ds mf () = p drv f sw n ------- - n mf q gmf n sf q gsf + () i cc + v cc = r r a r l 3 a d r ds on () sf () c r ------------------------------------------------------------------ = r r 0.2 600nh 35 4.8m ? 5pf --------------------------------------------------- - 333k ? == v r v in v ref () a r d r r 2 k ? + () c r f sw ---------------------------------------------------------- = v r 12 0.8 () 0.2 0.15 332k ? 2k ? + () 5pf 250khz ---------------------------------------------------------------------------------- 80 5mv == r lim a lim v lim v drpmax ------------------------------- = i phlim v comp max () v r v bias a d r ds max () ----------------------------------------------------------------- - i r 2 ---- - + ?
15 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller close loop compensation design optimum compensation of the fan5182 assures the best possi- b le load regulation and transient response of the regulator. the target of the compensation design is to achieve reasonably high control bandwidth with suf?ient phase and gain margin. the power stage of the synchronous buck converter consists of two poles and one zero. a two-pole, one-zero compensator of the voltage error ampli?r is adequate for proper compensation, if the output bulk capacitors are electrolytic types (low esr z ero). equations 17 to 19 are able to yield an approximate start- ing point for the design. to further optimize the design, some bench adjustments may be necessary (17) (18) (19) if c x is 6000? (?e 1200? capacitors in parallel) with an equivalent esr of 3m ? , the equations above give the following compensation values: c a = 1.33nf r a = 6.05k ? c fb = 110pf selecting the nearest standard value for each of these compo- nent yields c a = 1.2nf, r a = 6.04k ? , and c fb = 100pf. as mentioned above, this compensation design scheme is typi- cally good for applications using electrolytic type capacitors, where the capacitor esr zero can roughly cancel one of the power stage poles. however, for all ceramic capacitor types of applications, since the capacitor esr zero can be very high, a three-pole, two-zero compensator has to be used. a complete mathcad control design program is available from f airchild upon request. input capacitor selection and input current di/dt reduction in continuous inductor current mode, the source current of the high-side mosfet is approximately a square wave with a duty r atio equal to n v out /v in and an amplitude of one-nth the maximum output current. to prevent large voltage variation, a low esr input capacitor, sized for the maximum rms current, m ust be used. the maximum rms capacitor current is given by (20) note that manufacturers often specify capacitor ripple current r ating based on only 2,000 hours of life. therefore, it is advis- able to further derate the capacitor or to choose a capacitor r ated at a higher temperature than required. several capacitors may be placed in parallel to meet size or height requirements in the design. in this example, the input capacitor bank is formed by two 2,700?, 16v aluminum electrolytic capacitors and three 4.7? ceramic capacitors. to reduce the input current di/dt to a level below the system requirement, in this example 0.1a/?, an additional small induc- tor (l > 370nh @ 10a) can be inserted between the converter and the supply bus. this inductor serves as a ?ter between the converter and the primary power source. inductor dcr temperature correction with the inductor's dcr being used as the sense element, one needs to compensate for temperature changes in the inductor's winding if a highly accurate current limit setpoint is desired. for- tunately, copper has a well-known temperature coef?ient (tc) of 0.39%/?. if r cs is designed to have an opposite and equal percentage of change in resistance to that of the inductor wire, it cancels the temperature variation of the inductor's dcr. due to the nonlin- ear nature of ntc thermistors, resistors r cs1 and r cs2 are needed. see figure 9. for instructions on how to linearize the ntc and produce the desired temperature coef?ient. figure 9. temperature compensation circuit values f ollow the procedures and expressions shown below for calcu- lation of r cs1 , r cs2 , and r th (the thermistor value at 25?) based on a given r cs value. 1. select an ntc according to type and value. because we do not have a value yet, start with a thermistor with a value close to r cs . the ntc should also have an initial tolerance of bet- ter than 5%. 2. based on the ntc type, ?d its relative resistance value at two temperatures. the temperatures that work well are 50? and 90?. these resistance values are called a (r th(50?) / r th(25?) ) and b (r th(90?) /r th(25?) ). note that the ntc's relative value is always 1 at 25?. 3. find the relative value of r cs required for each of these tem- peratures. this is based on the percentage of change needed, which in this example is initially 0.39%/?. these are called r1 (1/(1 + tc (t 1 - 25))) and r2 (1/(1 + tc (t 2 - 25))), where tc = 0.0039 for copper. t 1 = 50? and t 2 = 90? are chosen. from this, one can calculate that r1 = 0.9112 and r2 = 0.7978. c a c x r x 4 r b2 ------------------- - nr x v r v out ------------- r l ?? ?? a d r ds () + ------------------------------------------------------------------- ?? ?? ?? ?? ?? = r a 4 r b2 nc x r x --------------------------- lv r r x v out ------------------------- - a d r ds 2 f sw r x ----------------------------- - ?? ?? = c fb 1 2 nf sw r a --------------------------------------- - = i crms di o 1 nd ------------- 1 = i crms 0.15 55a 1 30 .15 ------------------- 1 9.1a == 12 fan5182 cscomp cssum csref r th r cs1 r cs2 c cs1 c cs2 r ph1 r ph2 r ph3 to switch nodes to v out sense place as close as possible to nearest inductor or low-side mosfet keep this path as short as possible and well away from switch node lines 13 11
16 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller 4. compute the relative values for r cs1 , r cs2 , and r th using (21) (22) (23) 5. calculate r th = r th r cs , then select the closest value of thermistor available. also, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: (24) 6. calculate values for r cs1 and r cs2 using (25) (26) pcb layout guidelines general recommendations to achieve the best possible performance, a pcb with at least f our layers is recommended. when doing the layout, please k eep in mind that each square unit of 1 ounce copper has resis- tance of ~0.53m ? at room temperature. whenever high currents must be routed to a different pcb lay- ers, vias should be used properly to create several parallel cur- rent paths so that the resistance and inductance introduced by these current paths are minimized, and the via current-rating is not exceeded. if critical signal traces must be routed close to power circuitry, a signal ground plane must be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. an analog ground island should be used around and under the f an5182 as a reference for the components associated with the controller. this analog ground should be connected to the power ground at a single point. the components around the fan5182 should be close to the controller with short traces. the output capacitors should be placed as close as possible to the load. if the load is distributed, the capacitors should also be distributed in proportion to the respective load. po wer circuitry recommendations the pcb layout starts with high frequency power component placement. try to minimize stray inductance of the mosfet half bridge which is composed of the input capacitors, and top and bottom mosfets. a good practice is to use short and wide traces or copper pours to minimize the inductance in the mos- fet half bridge. failure to do so can lead to severe phase node r inging. a snubber circuit is always recommended to partly kill the phase node switching noise. whenever using a power dissipating component, for example, a power mosfet that is soldered to the pcb, the proper use of vias, both directly on the mounting pad and immediately sur- rounding the mounting pad is recommended. make a mirror image of the power pad being used on the component side to heatsink the mosfets on the opposite side of the pcb. use large copper pour for high current traces to lower the electrical impedance and help dissipate heat. do not make the switching node copper pour unnecessarily large, since it could radiate noise. an undisturbed solid power ground plane should be used as one of the inner layers. signal circuitry recommendations the output voltage is sensed from the fb and the fbrtn pins. to av oid differential mode noise pickup in these differential sensed traces, the loop area between the fb and fbrtn traces should be minimized. in other words, the fb and fbrtn traces should be routed adjacent to each other with minimum spacing on top of the analog / power ground plane back to the controller. the signal traces connecting to the switch nodes should be tied as close as possible to the inductor pins. the csref sense trace should be connected to the second nearest inductor pin to the controller. detailed step-by-step pcb layout instructions are available from f airchild upon request. r cs2 ab () r 1 r 2 a 1 b () r 2 b 1 a () r 1 + a 1 b () r 1 b 1 a () r 2 ab () ---------------------------------------------------------------------------------------------------------------------- = r cs1 1a () 1 1r cs2 ------------------- ?? ?? a r 1 r cs2 --------------------- ?? ?? ---------------------------------------------------------- - = r th 1 1 1 r cs2 ------------------- - ?? ?? 1 r cs1 ---------- - ?? ?? ------------------------------------------------ = k r th actual ) () r th calculated () ---------------------------------------------- = r cs1 r cs kr cs1 = r cs2 r cs 1 k () kr cs2 () + () =
17 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller mechanical diagram 20 pin - qsop ordering information note: fan5182qscx_nl is a pb-free part. pa rt number t emperature range package type packing method quantity per reel f an5182qscx_nl 0? to +85? qsop-20l tape and reel 2500 a 0.069 1.75 symbol inches min. max. min. max. millimeters notes a1 0.004 0.10 0.061 1.54 0.053 1.35 0.010 0.25 a2 - - b 0.008 0.012 0.20 0.30 d 0.386 0.394 9.81 10.00 h 0.150 0.157 3.81 3.98 0.016 0.050 0.41 1.27 e 0.025 bsc 0.635 bsc e h l 0.228 0.244 0.0099 0.0196 5.80 6.19 0.26 0.49 0 8 0 8 6 5 7 9 3 4 n20 20 c 0.007 0.010 0.18 0.25 notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. symbols are defined in the "mo series symbol list" in section 2.2 of publication number 95. dimensioning and tolerancing per ansi y14.5m-1982. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusions shall not exceed 0.25mm (0.010 inch) per side. dimension "e" does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. the chamber on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. "l" is the length of terminal for soldering to a substrate. "n" is the maximum number of terminals. terminal numbers are shown for reference only. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "b" dimension at maximum material condition. controlling dimension: inches. converted millimeter dimensions are not necessarily exact. h e a a2 d e b a1 c ccc c lead coplanarity seating plane l c
18 www.fairchildsemi.com f an5182 rev. 1.0.1 f an5182 adjustable output 1, 2, or 3-phase synchronous buck controller disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy f airchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production intellimax? isoplanar? littlefet? microcoupler? microfet? micropak? microwire? msx? msxpro? ocx? ocxpro? optologic ? optoplanar? p acman? f ast ? f astr? fps? frfet? globaloptoisolator? gto? hisec? i 2 c? i-lo ? implieddisconnect? rev. i15 acex? activearray? bottomless? coolfet? crossvolt ? dome? ecospark? e 2 cmos? ensigna? f act? f act quiet series? pop? power247? poweredge? powersaver? powertrench ? qfet ? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? serdes? silent switcher ? smart start? spm? s tealth? superfet? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic ? tinyopto? trutranslation? uhc? ultrafet ? unifet? vcx? across the board. around the world.? the power franchise ? programmable active droop?

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