1 white electronic designs corporation ? phoenix, az ? (602) 437-1520 hi-reliability product edi816256ca-rp 256kx16 plastic monolithic sram features n 256kx16 bit cmos static n random access memory ? access times of 15, 17, 20, 25ns ? data retention function (lpa version) ? ttl compatible inputs and outputs ? fully static, no clocks n center power/ground pins (revolutionary) n 44 lead jedec approved revolutionary pinout ? plastic soj package n single +5v ( 10%) supply operation pin configuration top view may 1999 rev. 3 pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a0 a1 a2 a3 a4 cs i/o1 i/o2 i/o3 i/o4 v cc v ss i/o5 i/o6 i/o7 i/o8 we a5 a6 a7 a8 a9 a17 a16 a15 oe ub lb i/o16 i/o15 i/o14 i/o13 v ss v cc i/o12 i/o11 i/o10 i/o9 nc a14 a13 a12 a11 a10 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a 0-17 address inputs lb lower-byte control (i/o 1-8 ) ub upper-byte control (i/o 9-16 ) i/o 1-16 data input/output cs chip select oe output enable we write enable v cc +5.0v power v ss ground nc no connection the edi816256ca is a ruggedized plastic 256kx16 sram that allows the user to capitalize on the cost advantage of using a plastic component while not sacrificing all of the reliability available in a full military device. the edi816256ca uses 16 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. the device allows upper and lower byte access by use of the data byte control pins (lb, ub). extended temperature testing is performed with the test patterns developed for use on wedcs fully compliant 256kx16 srams. wedc fully characterizes devices to determine the proper test patterns for testing at temperature extremes. this is critical because the operating characteristics of device change when it is operated beyond the commercial guarantee a device that oper- ates reliably in the field at temperature extremes. users of wedcs ruggedized plastic benefit from wedcs extensive expe- rience in characterizing srams for use in military systems. wedc ensures low power devices will retain data in data reten- tion mode by characterizing the devices to determine the appro- priate test conditions. this is crucial for systems operating at - 40 c or below and using dense memories such as 256kx16s.wedcs ruggedized plastic soj is footprint compatible with wedcs full military ceramic 44 pin soj.
2 white electronic designs corporation ? phoenix, az ? (602) 437-1520 edi816256ca-rp truth table cs we oe lb ub mode data i/o power i/o 1-8 i/o 9-16 h x x x x not select high z high z standby lhhx x output disable high z high z active lxxh h l h data out high z l h l h l read high z data out active l l data out data out l h data in high z l l x h l write high z data in active l l data in data in parameter symbol condition max unit input capacitance c in v in = 0v, f = 1.0mhz 6pf output capicitance c out v out = 0v, f = 1.0mhz 8pf this parameter is guaranteed by design but not tested. capacitance (t a = +25 c) dc characteristics (v cc = 5.0v, v ss = 0v, t a = -55 c to +125 c) absolute maximum ratings parameter symbol min max unit operating temperature (mil.) t a -55 +125 c operating temperature (ind.) t a -40 +85 c storage temperature t stg -65 +150 c signal voltage relative to v ss v g -0.5 vcc + 0.5 v supply voltage v cc -0.5 7.0 v recommended operating conditions parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.2 v cc + 0.5 v input low voltage v il -0.3 +0.8 v operating temperature (mil.) t a -55 +125 c operating temperature (ind.) t a -40 +85 c parameter sym conditions min max units operating power supply current i cc1 we, cs = v il , i i/o = 0ma, min cycle 300 ma standby (ttl) power supply current i cc2 cs 3 v ih , v in v il , v in 3 v ih 60ma full standby power i cc3 cs 3 v cc -0.2v ca 25 ma supply current v in 3 v cc -0.2v or v in 0.2v lpa 15 ma input leakage current i li v in = 0v to v cc -10 10 m a output leakage current i lo v i/o = 0v to v cc -10 10 m a output high voltage v oh i oh =-4ma 2.4 v output low voltage v ol i ol = 8ma 0.4 v
3 white electronic designs corporation ? phoenix, az ? (602) 437-1520 edi816256ca-rp ac characteristics (v cc = 5.0v, v ss = 0v, t a = -55 c to +125 c) parameter symbol -15 -17 -20 -25 units read cycle min max min max min max min max read cycle time t rc 15 17 20 25 ns address access time t aa 15 17 20 25 ns output hold from address change t oh 000 0 ns chip select access time t acs 15 17 20 25 ns output enable to output valid t oe 10 10 10 12 ns chip select to output in low z t clz 1 555 5 ns output enable to output in low z t olz 1 000 0 ns chip disable to output in high z t chz 1 77 7 8ns output disable to output in high z t ohz 1 77 7 8ns lb, ub access time t ba 10 10 10 12 ns lb, ub enable to low z output t blz 1 000 0 ns lb, ub disable to high z output t bhz 1 77 7 8ns 1. this parameter is guaranteed by design but not tested. i current source d.u.t. c = 50 pf eff i ol v 1.5v (bipolar supply) z current source oh notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z 0 = 75 w . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. ac test circuit ac test conditions parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v ac characteristics (v cc = 5.0v, v ss = 0v, t a = -55 c to +125 c) parameter symbol -15 -17 -20 -25 units write cycle min max min max min max min max write cycle time t wc 15 17 20 25 ns chip select to end of write t cw 12 15 15 17 ns address valid to end of write t aw 12 15 15 17 ns data valid to end of write t dw 10 10 10 12 ns write pulse width t wp 12 15 15 17 ns address setup time t as 00 00 ns address hold time t ah 00 00 ns output active from end of write t ow 1 00 00 ns write enable to output in high z t whz 1 888 8ns data hold time t dh 00 00 ns lb, ub valid to end of write t bw 12 15 16 18 ns 1. this parameter is guaranteed by design but not tested.
4 white electronic designs corporation ? phoenix, az ? (602) 437-1520 edi816256ca-rp ws32k32-xhx timing waveform - read cycle write cycle - cs controlled write cycle - we controlled address data i/o read cycle 1 (cs = oe = v il , ub or lb = v il , we = v ih ) t aa t oh t rc data valid previous data valid address data i/o read cycle 2 (we = v ih ) t aa t acs t oe t clz t olz t ohz t rc data valid high impedance cs oe t chz lb, ub t bhz t ba t blz address data i/o write cycle 1, we controlled t aw t cw t ah t wp t dw t whz t as t ow t dh t wc data valid cs we t bw lb, ub address data i/o write cycle 2, cs controlled t aw t as t cw t ah t wp t dh t dw t wc cs we data valid t bw lb, ub write cycle - lb, ub controlled address data i/o write cycle 3, lb, ub controlled t aw t as t cw t ah t wp t dh t dw t wc cs we data valid t bw lb, ub
5 white electronic designs corporation ? phoenix, az ? (602) 437-1520 edi816256ca-rp ordering information 44 lead, plastic soj (400 mil) 0.69 (0.027) min 1.27 (0.05) typ 28.7 (1.130) 28.4 (1.120) 0.38 (0.015) 0.53 (0.021) 10.16 (0.400) typ 0.66 (0.026) 0.81 (0.032) 3.76 (0.148) max 0.004" max 0.95 (0.0375) typ 11.05 (0.435) 11.30 (0.445) 9.14 (0.360) 9.65 (0.380) #1 #22 #44 #23 dimensions in millimeters and (inches) white electronic designs sram organization, 256kx16 technology: ca = cmos standard power lpa = low power access time (ns) package type: m44 = 44 lead plastic soj device grade: b = mil-std-883 compliant m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c edi 8 16 256 ca x x x
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