900ps max. d to output extended 100e v ee range of ?.2v to ?.5v 800ps max. len to output differential outputs asynchronous master reset dual latch enables fully compatible with industry standard 10kh, 100k ecl levels internal 75k ? input pulldown resistors fully compatible with motorola mc10e/100e156 available in 28-pin plcc package features 3-bit 4:1 mux-latch the sy10/100e156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ecl systems. the two external latch enable signals (len 1 and len 2 ) are gated through a logical or operation before use as control for the three latches. when both len 1 and len 2 are at a logic low, the latches are transparent, thus presenting the data from the multiplexers at the output pins. if either len 1 or len 2 (or both) are at a logic high, the outputs are latched. the multiplexer operation is controlled by the select (sel 0 , sel 1 ) signals which select one of the four bits of input data at each mux to be passed through. the mr (master reset) signal operates asynchronously to take all outputs to a logic low. description rev.: c amendment: /1 issue date: february, 1998 sy10e156 sy100e156 final block diagram pin configuration v ee sel 0 sel 1 len 2 len 1 d 2a 26 27 28 1 2 3 4 18 17 16 15 14 13 12 25 24 23 22 21 20 19 567891011 d 1c mr q 0 v cco q 2 d 2b plcc top view j28-1 d 1b d 2c d 2d q 2 v cc q 1 q 1 v cco q 0 d 0d d 0c d 0b d 0a d 1d d 1a v cco pin function d 0x ? 2x input data sel 0 , sel 1 select inputs len 1 , len 2 latch enables mr master reset q 0 ? 2 true outputs q 0 ? 2 inverted outputs v cco v cc to output pin names d r e n 4:1 mux d r e n 4:1 mux d r e n 4:1 mux q 0 q 0 q 1 q 1 q 2 q 2 mr d 0a len 1 len 2 sel 1 d 0b d 0c d 0d d 1a d 1b d 1c d 1d d 2a d 2b d 2c d 2d sel 0 1
2 sy10e156 sy100e156 micrel truth tables len 1 len 2 latch l l transparent h x latched x h latched sel 0 sel 1 data ll a hl b lh c hh d dc electrical characteristics v ee = v ee (min.) to v ee (max.); v cc = v cco = gnd t a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition i ih input high current 150 150 150 a i ee power supply current ma 10e 75 90 75 90 75 90 100e 75 90 75 90 86 103 ac electrical characteristics v ee = v ee (min.) to v ee (max.); v cc = v cco = gnd t a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition t plh propagation delay to output ps t phl d 400 600 900 400 600 900 400 600 900 sel 0 550 775 1050 550 775 1050 550 775 1050 sel 1 450 650 900 450 650 900 450 650 900 len 350 500 800 350 500 800 350 500 800 mr 350 600 825 350 600 825 350 600 825 t s set-up time ps d 400 275 400 275 400 275 sel 0 700 300 700 300 700 300 sel 1 600 400 600 400 600 400 t h hold time ps d300 275 300 275 300 275 sel 0 100 300 100 300 100 300 sel 1 200 400 200 400 200 400 t rr reset recovery time 800 600 800 600 800 600 ps t pw minimum pulse width, mr 400 400 400 ps t skew within-device skew 50 50 50 ps 1 t r rise/fall time 275 475 700 275 475 700 275 475 700 ps t f 20% to 80% product ordering code ordering package operating code type range sy10e156jc j28-1 commercial sy10e156jctr j28-1 commercial sy100e156jc j28-1 commercial sy100e156jctr j28-1 commercial note: 1. within-device skew is defined as identical transitions on similar paths through a device.
3 sy10e156 sy100e156 micrel 28 lead plcc (j28-1) rev. 03
4 sy10e156 sy100e156 micrel micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated
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