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www.siliconstandard.com 1 of 14 ss8000g gsm power-management system handles all gsm baseband power management input range 2.8v to 5.5v charger input up to 15v seven ldos optimized for specific gsm subsystems high operating efficiency and low stand-by current li-ion and nimh battery charge function sim card interface three open-drain output switches to control the led, alerter and vibrator thermal overload protection under-voltage lock-out protection over-voltage protection power-on reset and start-up timer qfn-48 package the ss8000 is a power-management system chip op t i mized for g s m handsets. it contains seven ldos, one to power each of the critical gsm sub-blocks. sophisticated controls are available for power-up during battery charging, keypad interface, and rtc alarm. the ss80 00 is optimized for maximum battery life featuring a ground current of only 107 a in standby and 187 a when the phone is in operation. the ss8000 battery charger can be used with lithium ion (li-ion) and nickel metal hydride ( nimh) batteries. the ss8000 contains three open-drain output switches for led, alerter and vibrator control. the sim interface provides the level shift betwe en sim card and micr o processor. the ss8000 is available in a 48-pin qfn package. the operating temperature range is from - 25 c to +85c . features description applications gsm/gprs mobile handsets basic and high-end phones 12/06/2004 rev.2.10 this device is supplied with a pb-free lead finish (second-level interconnect).
www.siliconstandard.com 2 of 14 ss8000g ordering information packing: tr: tape and reel ty: tray package type gq: qfn-48l, pb-free lead finish ss8000gqxx leden alerteren vibratoren pwrbb pwrkey srclken vref nc agnd va avbat vtcxo dgnd dgnd simsel sio srst sclk vm vbat vio vrtc rstcap reset chrin gatedrv nc isense chrcntl chrdet batsns vsim simio simrst simclk simvcc vcore vbat dgnd vmsel vasel batdet batuse led pgnd alerter pgnd 1 2 3 4 5 6 7 8 9 10 11 12 25 26 27 28 29 30 31 32 33 34 35 36 13 14 15 16 17 18 19 20 21 22 23 24 48 43 42 41 40 39 38 37 44 45 47 46 vibrator leden alerteren vibratoren pwrbb pwrkey srclken vref nc agnd va avbat vtcxo dgnd dgnd simsel sio srst sclk vm vbat vio vrtc rstcap reset chrin gatedrv nc isense chrcntl chrdet batsns vsim simio simrst simclk simvcc vcore vbat dgnd vmsel vasel batdet batuse led pgnd alerter pgnd 1 2 3 4 5 6 7 8 9 10 11 12 25 26 27 28 29 30 31 32 33 34 35 36 13 14 15 16 17 18 19 20 21 22 23 24 48 43 42 41 40 39 38 37 44 45 47 46 ss8000 vibrator pin configuration absolute maximum ratings chrin and gatedrv relative to gnd ??????????????????. - 0.3v to 15 v all other pins relative to gnd??? ????????????????. ? . ?? - 0. 3 v to 7 v operating temperature ranges? ?????????.. ????.?? .. ???... - 25c to +85c maximum junction temper a ture?? ??????????????? ????.+165c storage temperature range?? ???????????????????. ?? - 65 c to +165 c thermal impedance, q ja ????????? ??????????????????????????????. 23c/w lead temperature (soldering, 10sec).?? ? ??????????????.. ....+ 26 0c 12/06/2004 rev.2.10
www.siliconstandard.com 3 of 14 ss8000g electrical characteristics (vbat = 3 v - 5.5v, cva=10 f, c vcore =c v m=4.7 m f, c v rtc=0.22 f, cvref=cvtcxo=c v sim=c v io=1 f, minimum loads applied on all outputs, unless ot h erwise noted. typical values are at t a =+25c.) parameter conditions min typ max units main controller battery input voltage range 3 5.5 v charger input volt age range 15 v shutdown supply current vbat<2.5v 2.5v www.siliconstandard.com 4 of 14 ss8000g electrical characteristics (cont.) parameter conditions min typ max units rtc voltage ldo (vrtc) output voltage 1.3 1.5 1.65 v output short current limit 1.35 ma off reverse input current 0.02 1 a memory voltage ldo (vm) 1.8v output vo ltage 1.7 1.8 1.9 v 2.8v output voltage 2.7 2.8 2.9 v output short current limit 315 ma load regulation(1.8v) load regulation(2.8v) 0.05ma4v 3.75 % chr_det off threshold ( chrin - vbat )/vbat , chrin>4v 2. 5 % pre - charging current i_charge@vbat=3v(uvlo active), r1=0.2 w 50 mv gsm interface vih(simclk,simrst) vio - 0.6 v vil (simclk,simrst) 0.6 v vol ? 0.4v, iol=1ma 0.23 v vilsimio vol ? 0.4v, iol=0ma 0.335 v vihsimio , vohsimio iih,ioh= 20 a vio - 0.6 v iilsimio vil=0v - 0.9 ma volsimio vil=0.4v 0.42 v simio pull - up resistance to vio 16 20 24 k w 12/06/2004 rev.2.10
www.siliconstandard.com 5 of 14 ss8000g electrical characteristics (cont.) parameter conditions min typ max units interface to 3v sim card volrst i=20 a 0.4 v voh rst i= - 200 a 0.9vsim v volclk i=20 a 0.4 v vohclk i= - 200 a 0.9vsim v vil 0.4 v vihsio , vohsio i= 20 a vsim - 0.4 v iil vil=0v - 1 ma vol iol=1ma , simio ? 0.23v 0.4 v interface to 1.8v sim card volrst i=20 a 0.2vsim v vohrst i= - 200 a 0.9vsim v volclk i=20 a 0.2vsim v vohclk i= - 200 a 0.9vsim v vil 0.4 v vihsio , vohsio i= 20 a vsim - 0.4 v iil vil=0v - 1 ma vol iol=1ma , simio ? 0.23v 0.4 v sim card interface timing sio pull - up resistance to vsim 8 10 12 k w srst , sio rise/fall time vsim=3/1.8v, load with 30pf 1 s vsim=3v, clk load with 30pf 18 ns sclk rise/fall time vsim=1.8v, clk load with 30pf 50 ns sclk frequency clk load with 30pf 5 mhz sclk duty cycle simclk duty=50%, fsimclk=5mhz 47 53 % sclk prop. delay 30 50 ns 12/06/2004 rev.2.10
www.siliconstandard.com 6 of 14 ss8000g pin descriptions pin name function 1 chrin charger input voltage 2 gatedrv gate drive output 3,29 nc 4 isense charger current sense input 5 chrcntl microprocessor control input signal for gate drive 6 chrdet charger detect o utput 7 batsns battery input voltage sense 8 vsim sim supply 9 simio non - level - shifted bidirectional d ata i/o 10 simrst non - level - shifted sim reset input 11 simclk non - level - shifted sim clock input 12 simvcc sim enable 13 simsel high for vsim=3.0v, low for vsim=1.8v 14 sio level - shifted sim bidirectional d ata input/output 15 srst level - shifted sim reset output 16 sclk level - shifted sim clock output 17,21,46 dgnd digital ground 18 vm memory supply 19 vbat battery input voltage 20 vio digital io supply 22 v rtc real time clock supply 23 rstcap reset delay time capacitance 24 /reset system reset , low active 25 vtcxo tcxo supply 26 avbat battery input voltage for analog block circuits 27 va analog supply 28 agnd analog ground 30 vref refer ence voltage output 31 srclken vtcxo and va enable 32 pwrkey power on/off key 33 pwrbb power on/off signal from microprocessor 34 vibratoren vibrator driver enable 35 alerteren alerter driver enable 36 leden led driver enable 37,40 pgnd power ground 38 vibrator vibrator driver input 39 alerter alerter driver input 41 led led driver input 42 batuse battery type selection, high for nimh, low for li - ion 43 batdet battery detect output 44 vasel high for va enabled with vtcxo, low for va enabled wit h vd 45 vmsel high for vm= 2.8 v, low for vm=1.8v 47 vbat battery input voltage 48 v core digital core supply 12/06/2004 rev.2.10
www.siliconstandard.com 7 of 14 ss8000g application information the ss8000 is a power management chip optimized for use with gsm baseband chipsets in handset applications. fi g ure 1 shows the block diagram of the ss8000. seven low-dropout regulators (core, digital i/o, analog, crystal oscillator, real-time clock, memory, sim) sim card interface vibrator, alerter, and led d rivers power sequence and protection l ogic reset generator under-voltage lockout deep discharge lockout battery charger figure 1. functional block diagram vcore vio vbat vref en dgnd out digital io ldo 20 vbat vref en dgnd out digital core ldo 48 vsim vbat vref en dgnd out sim ldo 8 vbat vref en dgnd out momory ldo 18 vm va vbat vref en agnd out analog ldo 27 vbat vref en dgnd out rtc ldo 22 vrtc vref vbat en agnd out reference 30 vbat vref en agnd out tcxo ldo 25 vtcxo vsel vsel avbat 26 agnd 28 dgnd 17,21,46 ddlo uvlo vbat 19,47 over temp battery charger sim logic level shifter charger detect 45 vmsen pwrkey 32 pwrbb 33 simvcc 12 chrdet 6 43 batdet 31 srclken 1 chrin gatedrv 2 4 isense 5 chrcntl 7 batsns 42 batuse 44 vasel 13 simsel 14 15 16 sio srst sclk reset generator 11 10 9 24 23 34 35 36 37,40 41 39 38 simclk simrst simio reset rstcap vibratoren alerteren leden pgnd led vibrator alerter vcore vio vbat vref en dgnd out digital io ldo 20 vbat vref en dgnd out digital core ldo 48 vsim vbat vref en dgnd out sim ldo 8 vbat vref en dgnd out momory ldo 18 vm va vbat vref en agnd out analog ldo 27 vbat vref en dgnd out rtc ldo 22 vrtc vref vbat en agnd out reference 30 vbat vref en agnd out tcxo ldo 25 vtcxo vsel vsel avbat 26 agnd 28 dgnd 17,21,46 ddlo uvlo vbat 19,47 over temp battery charger sim logic level shifter charger detect 45 vmsen pwrkey 32 pwrbb 33 simvcc 12 chrdet 6 43 batdet 31 srclken 1 chrin gatedrv 2 4 isense 5 chrcntl 7 batsns 42 batuse 44 vasel 13 simsel 14 15 16 sio srst sclk reset generator 11 10 9 24 23 34 35 36 37,40 41 39 38 simclk simrst simio reset rstcap vibratoren alerteren leden pgnd led vibrator alerter 12/06/2004 rev.2.10
www.siliconstandard.com 8 of 14 ss8000g application information (cont.) low dropout regulator ( ldos ) and reference the ss8000 integrates seven ldos that are optimized for their gi ven functions by balancing quiescent current, dropout voltage, line/load regulation, ripple rejection, and output noise. digital core ldo (v core ) the digital co re ldo is a regulator that can source 2 00ma (max) with 1.8v output voltage. it supplies the base band circuitry in the handset. the ldo is opt i mized for very low quies c ent current. digital io ldo (vio) the digital i /o ldo is a regulator that can source 1 00ma (max) with 2.8v output voltage. it supplies the baseband circuitry in the handset. the ldo is opt i mized for very low quies c ent current and will power up at the same time as the digital core ldo. analog ldo (va) the anal og ldo is a regulator that can source 150ma (max) with 2.8v output voltage. it supplies the analog sections of the baseband chips ets. the ldo is opt i- mized for low frequency ripple rejection in order to reject the ripple coming from the rf power amplifier burst fr e- quency at 217khz. tcxo ldo (vtcxo) the tcxo ldo is a regulator that can source 20ma (max) with 2.8v output voltage. it su pplies the temperature co m- pensated crystal oscillator, which needs its own ultra low noise supply and very good ripple rejection r a tio . rtc ldo (vrtc) the r tc ldo is a regulator that can source 200 a (max) with 1.5v output voltage. it charges up a capac i- to r- type backup coin cell to run the real - time clock mo d- ule. the ldo features the reverse current protection and is opt i mized for ultra low quiescent current since it is always on except when the battery voltage is be low 2.5v. memory ldo (vm) the memo ry ldo is a regulator that can source 150ma (max) with 1.8v or 2.8v output voltage , select ed a c- cording to the supply specs of the memory chips. it su p- plies the memory circuitry in the handset. the ldo is opt i mized for very low quiescent current and will power up at the same time as the digital core ldo. sim ldo (vsim) the sim ldo is a regulator that c an source 20ma (max) with 1.8v or 3.0v output voltage , selected according to the supply specs of the subscriber identity mo d ules (sim) card. it supplies the sims i n the handset. the ldo is co n trolled independently of the others ldo. reference voltage output (vref) the reference voltage output is a low noise, high psrr and high precision reference with a guaranteed acc u racy of 1.5% over temperature. it is used as an internal system reference within the ss80 00. however, to maintain ac- curate specs o n every ldo output voltage, it is important to avoid loading the reference voltage and it should be bypassed to gnd with 100 nf min i mum. sim card interface the sim ca rd int erface circuitry of the ss8000 meets all etsi and imt - 2000 sim interface requirements. it provides level shifting needs for the low - voltage gsm contro l ler to communicate with either 1.8v or 3v sim cards. all sim cards contain a clock input, a reset i n put, and a bi - directional data input/output. the clock and reset inputs to sim cards are level shifted from the su p- ply of the digital io (vio) of the baseband chipset to the sim supply (vsim). the bi - directional data bus is in te r- nally pull ed high with a 20kohm resistor on the controller side and with a 10kohm resistor on the sim side. all pins that connect to the sim card (vsim, srst, sclk, sio) withstand over 5 kv of human - body - mode esd. in o r der to ensure proper esd protection, careful board layout is required . vibrator, alerter, led switches three built - in open - drain output switches drive the v i- brator motor, alerter beeper and leds in the handset. each switch is controlled by the baseband chipset with en able pins. the led switch can sink 150ma to drive up to 1 0 leds simultaneously for backlight. the vibr a tor switch can sink 250ma for a vibrator motor. the aler t er switch can sink 300ma to drive the beeper. a ll the open - drain output switches are high impedance when di s able d . 12/06/2004 rev.2.10
www.siliconstandard.com 9 of 14 ss8000g application information (cont.) power sequence and protection logic t he ss8000 handles the power -on and -off of the handset. it is possible to start the power - on sequence in three different ways: n pull ing pwrkey low n pull ing pwrbb high n chrin exceeds chr_det threshold pulling pwrkey low is the normal way of turning on the ha ndset. this will turn on vcore, vio, vm ldos as long as the pwrkey is he ld low. the vtcxo and va ldos are turned on when srclken is high. the micropro c- essor then starts and pulls pwrbb high after which the pwrkey can be r e leased. pulling pwrbb high will al so turn on the handset. this is the case when the alarm in the rtc expires. applying an external supply on chrin will also turn the handset on. if the ss8000 is in the uvlo state, ap- plying the adapter will not start up the ldos. table 1 shows states of th e handset and the ldos table 1. states of mobile handset and ldo phone state chr_on - uv p wr bb ( ? p wrkey) src lken vrtc vd,v io ,v m v a, vtcxo no battery or vbat < 2.5v x l x x off off off 2.5v < vbat < 3.2v l l x x on off off pre - charging h l x x on off of f charger - on h h x x on on on s witched off l h l x on off off stand - by l h h l on off on active l h h h on on on undervoltage lockout (uvlo) the uvlo function in the ss8000 prevents startup when initial voltage of the main battery is below the 3.2 v thres h old. when the battery voltage is greater than 3.2v, the uvlo comparator trips and the thres h old is reduced to 3.0v. this allows the handset to start no r mally u n til the battery decays to below 3.0v. once the ss8000 enters a uvlo state, it draws very low quiescen t current, typically 30 a. the rtc ldo is still ru n ning until the ddlo disables it. in this mode the ss8000 draws 5a of quiescent current. deep discharge lockout (ddlo) the ddlo in the ss8000 has two functions: l to turn off the vrtc ldo. l to shut down the handset when the software fails to turn off the phone when the battery drops below 3.0v. the ddlo will shut down the handset when the ba t- tery falls below 2.5 v to prevent further di s charge and damage to the cells. reset the ss8000 contains a reset circuit that is active at both power - up and power - down. the reset pin is held low at initial power - up, and the reset delay timer is started. the delay is set by an external capacitor on rstcap: rstcap reset c nf ms 2 t = (1) at p ower - off, reset will be kept low. over - temperature protection if the die temperature of the ss8000 exceeds 165c, the ss8000 will disable all the ldos except the rtc ldo. once the over - temperature state is resolved, a new power - on sequence is required t o enable the ldos. battery charger the ss8000 battery charger can be used with li-ion and nimh batteries. the batuse pin can set ss8000 to fit the battery type. batuse is set low when a li - ion bat tery is used, and set high when a nimh ba t tery is used. t he ss8000 charges the battery in three phases: pre - charging, constant current mode charging, and co n- stant voltage mode charging. fig ure 2 shows the flow chart of charger behavior. the circuitry of the ss8000 com bines a pmos transistor, diode, current - sen se r e- sistor exte r nally to form a simple and low cost linear charger shown in fi gure 3 . the ss8000 provides a puls ed top - off charging algorithm through the chrcntl pin from the baseband chipset. 12/06/2004 rev.2.10
www.siliconstandard.com 10 of 14 ss8000g application information (cont.) figure 2. batter charger flow chart charger detector chrin > batsns vbat > uvlo pre - charging yes yes batuse=high battery type batuse=low constant current mode pulse charge mode vbat > 4.2v li+ vbat > 5.1v charger off gatedrv=high vbat < 5.1v yes yes no no no vbat < 4.3v charger off vbat < 4.3v yes constant voltage mode nimh yes yes no no no no no -charging charger detector chrin > batsns vbat > uvlo pre - charging yes yes batuse=high battery type batuse=low constant current mode pulse charge mode vbat > 4.2v li+ vbat > 5.1v charger off gatedrv=high vbat < 5.1v yes yes no no no no no vbat < 4.3v charger off vbat < 4.3v yes constant voltage mode nimh yes yes no no no no no no 12/06/2004 rev.2.10
www.siliconstandard.com 11 of 14 ss8000g application information (cont.) figure 3. ty pical application circuit sim pin of gsm processor battery used battery detect va selection vm selection vcore dgnd c17 4.7 f charger in q1 d1 charge control charger detect r1 0.2 w li or nimh battery dgnd dgnd agnd vsim vsim enable vsim slectioin i/o to sim card rst to sim card clk to sim card c2 1 f pgnd 1 2 3 4 5 6 7 8 9 10 11 12 chrin gatedrv nc isense chrcntl chrdet batsns vsim simio simrst simclk simvcc vibrator vcore vbat dgnd vmsel vasel batdet batuse led pgnd alerter pgnd leden alerteren vibratoren pwrbb pwrkey srclken vref nc agnd va avbat vtcxo 36 35 34 33 32 31 30 29 28 27 26 25 48 14 15 16 17 18 19 20 21 22 23 24 13 dgnd dgnd simsel sio srst sclk vm vbat vio vrtc rstcap reset 47 46 45 44 43 42 41 40 39 38 37 pgnd r4 100 k led sw alerter sw vibrator sw led sw enable alerter sw enable power on clk on swi sw- pb dgnd c16 1 f c15 10 f c13 1 f c12 0.1 f c11 0.22 f dgnd c4 1 f c3 4.7 f dgnd 1 f agnd 10 f agnd sim pin of gsm processor battery used battery detect va selection vm selection vcore dgnd c17 4.7 f charger in q1 d1 charge control charger detect r1 0.2 w li or nimh battery dgnd dgnd agnd vsim vsim enable vsim slectioin i/o to sim card rst to sim card clk to sim card c2 1 f pgnd 1 2 3 4 5 6 7 8 9 10 11 12 chrin gatedrv nc isense chrcntl chrdet batsns vsim simio simrst simclk simvcc chrin gatedrv nc isense chrcntl chrdet batsns vsim simio simrst simclk simvcc vibrator vcore vbat dgnd vmsel vasel batdet batuse led pgnd alerter pgnd leden alerteren vibratoren pwrbb pwrkey srclken vref nc agnd va avbat vtcxo 36 35 34 33 32 31 30 29 28 27 26 25 48 14 15 16 17 18 19 20 21 22 23 24 13 dgnd dgnd simsel sio srst sclk vm vbat vio vrtc rstcap reset dgnd dgnd simsel sio srst sclk vm vbat vio vrtc rstcap reset 47 46 45 44 43 42 41 40 39 38 37 pgnd r4 100 k led sw alerter sw vibrator sw led sw enable alerter sw enable power on clk on swi sw- pb dgnd c16 1 f c15 10 f c13 1 f c12 0.1 f c11 0.22 f dgnd c4 1 f c3 4.7 f dgnd 1 f agnd 10 f agnd 12/06/2004 rev.2.10
www.siliconstandard.com 12 of 14 ss8000g application information (cont.) charge detection the ss8000 charger block has a detection circuit that determin es via the chrin pin if an adapter has been connected . if the adapter voltage exceeds the ba t tery voltage by 3.75% , the chrdet output will go high. if the adapter is then removed and the voltage at the chrin pin drops to only 2.5% above the vbat pin, chrdet goes low. pre - c harging mode when the battery voltage is below the uvlo threshold, the charge current is i n the pre - charging mode. there are two st eps in this mode. while the battery voltage is deeply discharged below 2v, a 10ma trickl e current from the ss8000 charges the battery. when the battery vol t age e x ceeds 2v, the pre - charge current is enabled, which a l lows 10mv (typically) across the exte rnal cu r- rent sense r e sistor. this pre - charge current can be ca l- c u lated: 1 r mv 10 1 r v i sense charging _ pre == (2) constant current charging mode once the battery voltage has exceeded the uvlo threshold , the charger will switch to the constant cu r rent chargi ng mode. the ss8000 allows 160mv (typically) across the external current sense resistor. this co n stant current can be calculated. 1 r mv 160 1 r v i sense constant == (3) if the battery voltage is below 4. 2 v when charging a li - ion ba t tery (5.1v for a nimh batte ry ), the constant current charging mode is used . constant voltage charging mode this mode only applie s to li - ion battery charging. if the battery has reached the final charge voltage, a co n stant voltage is applied to the batter y and keeps it at 4.2v. th is termination of charg ing is determined by the bas e- band chip i n te r nally, which will pull the chrcntl low to stop the charger. once the battery voltage exceeds 4.3v for a li - ion ba t- tery (5.1v for a nimh battery), a hardware over - voltage pr o te c t ion (ov) should be activated to turn off the charger block of the ss8000. pulsed charging algorithm the ss8000 provide a pulsed top-off charging algo- rithm via the chr cntl pin. the control signal from the bas e band chipset limit s the charging duty cycle. this charging algorithm combines the efficiency of switch - mode chargers with the simplicity and low cost of linear char g ers. battery voltage monitor as t able 2 show s , the relationship between battery vol t ag e and charger control with the corresponding si g- nals is lis ted. when vbat <3.2v, an uvb signal is a c tive low. when vbat > / = 4.3 v , an ov si g nal is active and charging is halted. table 2. charger and voltage detection vbat charge r _on chr_cntl chr_det output - uv batuse charger condition any vbat l x l x x no - chargi ng vbat > 3.2v x l x x x no - charging vbat < uv h x h l x pre - charging 3.2v www.siliconstandard.com 13 of 14 application information (cont.) ss8000g external components selection input capacitor selection for each of the input pins (v bat ) of the ss8000, a 10 f, low esr c a pacitor is reco m mended for l o cal b y- pass . mlcc capacitors provide the best co m b i na tion of low esr and small s ize. using a 10 f t an t a lum c a pac i- tor with a small (1 f or 2.2 f) ceramic in pa r allel is an a l ternative low cost solution. for the charger input pin ( chrin ), a 1 f c e ramic c a- pac i tor is recommended for bypass . ldo capacitor selection the digital core, analog, and memor y ldos require a 4.7 f capacitor, the digital io and sim tcxo ldos r e quire a 1 f capacitor and the rtc ldo require s a 0.22 f c a pacitor. large r value capacitor s may be used for improved noise or psrr performance, b ut do not forget to co n si d er the se t tling time that is a c ce p t able for the applic a tion. for the se , mlcc is re c o m mended. reset capacitor selection res et is held low during power - up for a delay until the l d os are up. the delay is set by an e x ternal capacitor on the rescap pin. it can be determined by eq.(1). a 100nf capacitor will produce a 200ms delay. setting the charge current the ss8000 is capable of charging the battery with a char g ing current programmed by an external sense r e- si s t or, rsen. it is calculated using eq.(3). if the charge cu r rent is defin ed, rsen can be found. appropriate sense resistors are available from the fo l- lowing vendors: vishay dale, irc, panasonic. charger fet selection in selecti ng the p - ch annel mos fet for the charger, c on si de r the minimum drain - source brea k down vol t age (bvds), the m inimum turn - on threshold voltage (vgs), and cu r rent - handling and power - dissipation capabilities . charger diode selection the diode shown in fig ure 3 is used to prevent the ba t- tery from discharging through the p - channel mos fet s body - d i ode into the charger?s internal circuits. choose a d i ode with a current rating high enough to handle the battery char g ing current and a voltage rating greater than vbat. layout guideline s use the follow ing general gui de line s when designing the printed circuit boards: 1. split the battery connection to the vbat, avbat pins of the ss8000. locate the input capacitor as close to the pins as possible. 2. va and vtcxo capacitors should be returned to agnd. 3. split the ground connec tion. use separate traces or planes for the analog, digital, and power grounds (i.e. agnd, dgnd, pgnd pins of the ss8000, respec- tively) and tie them together at a single point, pre f era- bly close to the battery return. 4. run a separate trace from the batsns pin to the battery to prevent any voltage drop error in the mea s- ur e ment. 5. kelvin - connect the charge - current sense - resistor by running separate traces to the batsns and isense pins. make sure that the traces are term i nated as close to the resistor?s body as possible. 6. careful use of copper area, weight, and multi - la yer construct ion will help to improve thermal pe r for m ance. 12/06/2004 rev.2.10
www.siliconstandard.com 14 of 14 physical dimensions note: coplanarity applies to leads, corner leads and die attach pad. dimension in mm dimension in inch symbol min. no m. max. min. nom. max. a 0.80 ----- 1.00 0.031 ----- 0.039 a1 0 ----- 0.05 0 ----- 0.002 a2 0.75 ----- 1.00 0.030 ----- 0.039 b 0.20 0.25 0.30 0.008 0.010 0.012 d 7 bsc 0.276 bsc e 7 bsc 0.276 bsc e 0.5 bsc 0.020 bsc j 4.50 4.60 4.70 0.177 0.181 0. 185 k 4.50 4.60 4.70 0.177 0.181 0.185 l 0.35 0.40 0.45 0.014 0.016 0.018 p 45 ref 45 ref taping specificati on 13 12 1 48 37 24 25 36 p 48 x l 48 x b 0.1 m c a b j pin 1 corner exposed die attach pad 0.1 c a b k 0.1 c a b e e/2 view m - m 0.1 c pin 1 corner d a e b m m a1a2 a 0.1 c 0.08 c c 13 12 1 48 37 24 25 36 p 48 x l 48 x b 0.1 m c a b 0.1 m c a b j pin 1 corner exposed die attach pad 0.1 c a b 0.1 c a b k 0.1 c a b e e/2 view m - m 0.1 c 0.1 c pin 1 corner d a e b m m a1a2 a 0.1 c 0.08 c 0.08 c c feed direction typical qfn package orientation feed direction typical qfn package orientation i n formation furnished by silicon standard corporation is believ e d to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infr i ngement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limita t ion enhancement in reliability, functionality or design. no license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intelle ctual property rights of silicon standard corporation or any third parties. ss8000g 12/06/2004 rev.2.10

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