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vishay TFBS5617 document number 82557 rev. 1.1, 17-oct-03 vishay semiconductors www.vishay.com 1 18088 integrated low profile transceiver module for telecom applications 9.6 kbit/s to 1.152 mbit/s data transmission rate description the miniaturized TFBS5617 is an ideal transceiver for applications in telecommunications like mobile phones, pagers, and pdas of all kinds. the device is designed for optimum performance and minimum package size. the transceiver covers the latest irda ? physical layer specification for low power sir and mir 1.152 mbit/ s irda ? mode. the transceiver is in a very low profile package, allow- ing to replace and upgrade a variety of common sir devices to mir functionality with the additional feature of variable logic voltage swing. the TFBS5617 is using the vishay, ibm ? and infineon ? order of the pin- ning. new features the device is a modification of the tfdu5107 device. an additional new feature as in tfdu5107 is the adjustable logic voltage v ddlogic swing. it can be set externally between 1.5 v and 5.5 v. the device covers the supply voltage range from 2.7 v to 5.5 v and with its low current consump- tion it is optimum suited for battery powered appli- cations. double eye safety protection by pulse duration and current limitation is integrated. the device is defined to operate over the full irda range exceeding 1 m. a custom modification of the current control for mir low power standard is also available on request (tfbs5616). features package: TFBS5617 vishay legacy pinning order 2.7 mm height compatible to irda standard (mir and sir with lowest current consumption) wide supply voltage range (2.7 v to 5.5 v) logic input and output voltage 1.5 v to 5.5 v tri-state-receiver output with weak pull-up effi- cient in shut down mode lowest power consumption, typically 500 a (900 a max.) in receive mode, <1 a in shutdown mode fewest external components vishay?s well known high emi immunity eye safety protection integrated applications mobile phones, pagers, hand-held battery oper- ated equipment computers (wince, palmpc, pdas) digital still and video cameras extended ir adapters medical and industrial data collection parts table part description qty / reel TFBS5617-tr3 oriented in carrier tape for side view surface mounting 1000 pcs
www.vishay.com 2 document number 82557 rev. 1.1, 17-oct-03 vishay TFBS5617 vishay semiconductors functional bloc k diagram mode input is for internal current selection of customized version for low power (tfbs5616) or full irda range (TFBS5617) pin description pinout TFBS5617 weight 80 mg comparator amplifier agc logic driver current controlled driver v dd1 txd gnd rxd ired anode ired cathode mode v logic sd 18305 pin number function description i/o active 1 ired anode ired anode to be externally connected to vcc through a current control resistor. this pin is allowed to be supplied from an uncontrolled power supply separated from the controlled v cc - supply. 2 ired cathode ired cathode, internally connected to driver transistor. 3 txd transmit data input. i high 4 rxd received data output, push-pull cmos driver output capable of driving a standard cmos or ttl load. no external pull-up or pull-down resistor is required. pin is connected to v logic with a weak pull-up (500 k ? ) when device is in shutdown mode. rxd output is quiet during transmission. o low 5 sd shutdown, will switch the device into shutdown after a delay of 1 ms . i high 6 v dd supply voltage 7 v logic defines the input and output logic swing voltage. i 8 gnd ground
vishay TFBS5617 document number 82557 rev. 1.1, 17-oct-03 vishay semiconductors www.vishay.com 3 1234567 18304
www.vishay.com 4 document number 82557 rev. 1.1, 17-oct-03 vishay TFBS5617 vishay semiconductors absolute maximum ratings reference point ground, pin 8, unless otherwise noted 1) the jan. 2001 edition of the iec825-1 or en60825-1 gives no limitation below the irda standard maximum. irda max. limit is 500 mw/sr. the device is protected against txd short by an internal shut-o ff when the pulse duration is exceeding maximum irda specificati on value of pulse duration. in addition the max. current is limited. parameter test conditions symbol min ty p. max unit supply voltage range 0 v < v dd2 < 6 v v dd1 - 0.5 6 v 0 v < v dd1 < 6 v v dd2 - 0.5 6 v 0 v < v dd2 < 6 v, 0 v < v dd1 < 6 v v logic - 0.5 6 v input current all pins (pin 1 excluded) 10 ma output sinking current, rxd pin 4 25 ma rep. pulsed ired current pin 1, t on < 20 %, < 20 s i ired(rp) 500 ma average ired current i ired(dc) 125 ma power dissipation p tot 450 mw junction temperature t j 125 c ambient temperature range (operating) t amb - 25 + 85 c storage temperature range t stg - 25 + 85 c soldering temperature t = 20 s @ 215 c 215 240 c transmitter data and shutdown input voltage 2.4 v < v dd1 < 5.5 v v txd , v sd - 0.5 6 v receiver data output voltage v rxd - 0.5 v logic + 0.5 v virtual source size method: (1 - 1/e) encircled energy d 2.5 2.8 mm maximum intensity for class 1 operation of iec825 or en60825 en60825-1, edition jan. 2001 worst case irda pulse pattern, lab. conditions 500 1) save in all modes mw/sr
vishay TFBS5617 document number 82557 rev. 1.1, 17-oct-03 vishay semiconductors www.vishay.com 5 electrical characteristics transceiver v dd1 = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. 1) maximum data is for 20 % (25 %) duty cycle for sir (mir 1.152 mbit/s) low power mode. the typical value is given for the case of normal operation with statistical and equal "0" and "1" - distribution. parameter test conditions symbol min ty p. max unit supported data rates, rxd pulse duration 400 ns base band, sir mode 9.6 115.2 kbit/s base band, 1.152 mbit/s 9.6 1152 kbit/s supply voltage range specified operation v dd1 2.7 5.5 v supply voltage v dd2 = 2.7 v to 5.5 v v dd1 2.7 5.5 v supply current receive mode v dd1 = 2.7 v to 5.5 v i s 500 900 a supply current shutdown mode v dd1 = 2.7 v to 5.5 v i ssd 0.1 1 a average supply current 1) , standard mir transmit mode i e > 100 mw/sr v dd1 = 2.7 v to 5.5 v, above v dd1 = 3.3 v a serial resistor for reducing the internal power dissipation should be implemented, e.g. r l = 2.7 ? i s 60 110 ma logic voltage range v dd2 = 2.7 v to 5.5 v v logic 1.5 3.6 v shutdown/ mode clock pulse duration for t prog 0.2 20 s shutdown delay "receive off" t prog 1 1.5 ms shutdown delay "receive on" t prog 40 100 s transceiver "power on" settling time time from switching on v dd1 to established specified operation 50 s
www.vishay.com 6 document number 82557 rev. 1.1, 17-oct-03 vishay TFBS5617 vishay semiconductors optoelectronic characteristics receiver v dd1 = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. 1) rxd output pulse duration 400 ns parameter test conditions symbol min ty p. max unit minimum detection threshold irradiance sir 9.6 kbit/s to 115.2 kbit/s 1) | | 15 , v dd1 = 2.4 v to 5.5 v e e, min 4 22 35 mw/m 2 minimum detection threshold irradiance mir 9.6 kbit/s to 115.2 kbit/s 1) | | 15 , v dd1 = 2.7 v to 5.5 v e e, min 4 40 85 mw/m 2 maximum detection threshold irradiance | | 90 , v dd1 = 5 v e e, max 5000 w/m 2 | | 90 , v dd1 = 3 v e e, max 8000 15000 w/m 2 logic low receiver input irradiance e e, max,low 4 mw/m 2 output voltage rxd active, c = 15 pf, r = 2.2 k ? v ol 0.5 0.8 v non active, c = 15 pf, r = 2.2 k ? v oh v dd1 - 0.5 v output current rxd v ol < 0.8 v 4 ma rise time @ load c = 15 pf, r = 2.2 k ? , 1.5 v v logic 1.8 v t r 30 ns c = 15 pf, r = 2.2 k ? , 1.5 v v logic 5.5 v t r 25 ns fall time @ load c = 15 pf, r = 2.2 k ? , 1.5 v v logic 1.8 v t f 30 ns c = 15 pf, r = 2.2 k ? , 1.5 v v logic 5.5 v t f 25 ns rxd signal electrical output pulse width 1.5 v v logic 5.5 v t p 300 400 500 ns latency t l 50 250 s
vishay TFBS5617 document number 82557 rev. 1.1, 17-oct-03 vishay semiconductors www.vishay.com 7 transmitter v dd1 = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) the current through the ired can be reduced and defined by an external resistor; the internal current limitation is set to 450 ma peak, nominal. identification the identification of the device can be recalled by set- ting the sd active followed by activating txd for a short period. with the low going edge of txd a single pulse is generated at rxd. the sd is intended to activate the shutdown function after a delay of 1 ms. therefore the full sequence should be run with that 1 ms time limitation, see draw- ing. current derating diagram parameter test conditions symbol min ty p. max unit logic cmos high/low decision threshold v il(txd) 1/2 x v logic v logic low transmitter input voltage v il(txd) 0 0.2 x v logic v logic high transmitter input voltage 1.5 < v logic < 5.5 v v ih(txd) 0.8 v logic v logic + 0.5 v output radiant intensity, standard mir level | | 15 ,v dd2 = 3 v i e 110 175 500 mw/sr controlled ired peak drive current *) v dd1 = 2.7 v to 5.5 v i ired 450 ma maximum output pulse width (eye safety protection) p wi > 23 s p womin 23 80 s optical pulse width p wi = 1.6 s p wo 1.45 1.75 s p wi = 217 ns p wo 210 226 ns optical rise/fall time t r , t f 40 ns peak wavelength of emission p 880 900 nm spectral optical radiation bandwidth ? 45 nm output radiant intensity txd logic low level 0.04 w/sr overshoot, optical 25 % rising edge peak to peak jitter t j 0.2 s sd txd rxd sd :>5 s t for "real" shutdow n>1ms txd t : >0.5 s to 2 s ? delrxd t : 10 ns deltxd t:1s rxd t = 400 ns 18303 figure 1. current derating diagram 0 100 200 300 400 500 600 ?40 ?20 0 20 40 60 80 100 120 140 peak operating current ( ma ) temperature ( c ) 14875 current derating as a function of the maximum forward current of ired. maximum duty cycle: 25%.
www.vishay.com 8 document number 82557 rev. 1.1, 17-oct-03 vishay TFBS5617 vishay semiconductors recommended solder profile v logic setting the logic voltage swing is set by applying an external voltage to the v logic pin. table 1. truth table figure 2. recommended solder profile time(s) temperature ( c ) 14874 0 20 40 60 80 100 120 140 160 180 200 220 240 0 50 100 150 200 250 300 350 2 c-4 c/s 10 s max. @230 c 90 s max 120 s - 180 s 2 c-4 c/s inputs outputs sd txd optical input irradiance mw/ m 2 rxd led drive current resulting intensity i e in mw/sr high <1 ms pulse x low going txd triggers monostable to edit a 400 ns (nominal) low pulse 0 high <1 ms x x floating (500 k ? to v dd 0 low high x high > 40 low high > 80 s x high 0 low low < 4 high 0 low low > 40 low, edge pulse of 400 ns duration 0
vishay TFBS5617 document number 82557 rev. 1.1, 17-oct-03 vishay semiconductors www.vishay.com 9 package dimensions in mm 18074
www.vishay.com 10 document number 82557 rev. 1.1, 17-oct-03 vishay TFBS5617 vishay semiconductors appendix application hints recommended circuit diagram TFBS5617 the tfbs5615 doesn?t need any external compo- nents when operated at a "clean" power supply. in a more noisy ambient it is recommended to add a com- bination of a resistor and capacitors (r1, c1, c2) for noise suppression as shown in the figure below. a combination of an electrolytic for the low frequency range and a ceramic capacitor for suppressing the high frequency disturbance will be most effective. the capacitor c3 is only necessary when inductive wiring is used or the power supply cannot deliver the operat- ing peak pulse current. however, a low impedance layout is the better and more cost efficient solution. the inputs txd and sd are high impedance cmos inputs. therefore, the lines from the i/o to those inputs should be carefully designed not to pick up ambient noise. if long lines are used, loads at the txd input of the TFBS5617 and at the rxd input of the controller (!) are recommended. at the ired anode voltage supply line an additional capacitor might be necessary when inductive wiring is used. for adjusting the intensity depending on the applica- tion, a serial resistor in the v cc2 supply to the ired anode pin can be used. shut down to shut down the TFBS5617 into a standby mode the sd pin has to be set active. after a delay of > 1 ms it will switch to the standby mode. latency the receiver is in specified conditions after the defined latency. in a uart related application after that time (typically 50 s) the receiver buffer of the uart must be cleared. therefore, the transceiver has to wait at least the specified latency after receiv- ing the last bit before starting the transmission to be sure that the corresponding receiver is in a defined state. table 1. recommended applicatio n circuit components r1 rxd txd sd gnd c1 c2 3 5 7 4 2 c1 , (c3) :4.7 f, see text c2 : 470 nf rxd vcc1 gnd tx d sd ired anode, vdd2 1 vcc2 vdd1 vlogic 6 vlogic c3 18302 component recommended value vishay part number c1, c3 47 f, 16 v 293d 475x9 016b 2t c2 100 nf, ceramic vj 1206 y 104 j xxmt r1 47 ? , 0.125 w crcw-1206-47r0-f-rt1
vishay TFBS5617 document number 82557 rev. 1.1, 17-oct-03 vishay semiconductors www.vishay.com 11 reel dimensions 14017 w 1 w 2 reel hub tape width a max. n w 1 min. w 2 max. w 3 min. w 3 max. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4
www.vishay.com 12 document number 82557 rev. 1.1, 17-oct-03 vishay TFBS5617 vishay semiconductors tape dimensions in mm 18297
vishay TFBS5617 document number 82557 rev. 1.1, 17-oct-03 vishay semiconductors www.vishay.com 13 ozone depleting substa nces policy statement it is the policy of vishay semiconductor gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol (1987) and its london amendments (1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. vishay semiconductor gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. vishay semiconductor gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. we reserve the right to make changes to improve technical design and may do so without further notice. parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use vishay semiconductors products for any unintended or unauthorized application, the buyer shall indemnify vishay semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. vishay semiconductor gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2831, fax number: 49 (0)7131 67 2423

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