1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com hi-reliability product edi88128c 128kx8 monolithic sram, smd 5962-89598 features n access times of 70, 85, 100ns n available with single chip selects (edi88128) or dual chip selects (edi88130) n 2v data retention (lp versions) n cs and oe functions for bus control n ttl compatible inputs and outputs n fully static, no clocks n organized as 128kx8 n industrial, military and commercial temperature ranges n thru-hole and surface mount packages jedec pinout ? 32 pin ceramic dip, 0.6 mils wide (package 9) ? 32 lead ceramic zip (package 100) ? 32 lead ceramic soj (package 140) n single +5v ( 10%) supply operation 32 zip top view july 1999 rev. 13 pin description i/o 0-7 data inputs/outputs a 0-16 address inputs we write enable cs 1 , cs 2 chip selects oe output enable v cc power (+5v 10%) v ss ground nc not connected block diagram memory array address buffer address decoder i/o circuits a -16 i/o -7 we cs 1 cs 2 oe fig. 1 pin configuration the edi88128c is a high speed, high performance, monolithic cmos static ram organized as 128kx8. the device is also available as edi88130c with an additional chip select line (cs 2 ) which will automatically power down the device when proper logic levels are applied. the second chip select line (cs 2 ) can be used to provide system memory security during power down in non-battery backed up systems and simplifiy decoding schemes in memory banking where large multiple pages of memory are required. the edi88128c and the edi88130c have eight bi-directional in- put-output lines to provide simultaneous access to all bits in a word. an automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. low power versions, edi88128lp and edi88130lp, offer a 2v data retention function for battery back-up opperation. military prod- uct is available compliant to appendix a of mil-prf-38535. 32 dip 32 soj top view 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 v cc a15 nc/cs2* we a13 a8 a9 a11 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a i/o i/o1 i/o2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v cc a15 nc/cs2* we a13 a8 a9 a11 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a i/o i/o1 i/o2 v ss * pin 30 is nc for 88128 or cs 2 for 88130.
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128c absolute maximum ratings parameter unit voltage on any pin relative to vss -0.5 to 7.0 v operating t emperature t a (ambient) commercial 0 to +70 c industrial -40 to +85 c military -55 to +125 c storage temperature, plastic -65 to +150 c power dissipation 1 w output current 20 ma junction temperature, t j 175 c recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 000v input high voltage v ih 2.2 vcc +0.5 v input low voltage v il -0.3 +0.8 v parameter symbol condition max unit address lines c i v in = vcc or vss, f = 1.0mhz 12 pf input/output lines c o v out = vcc or vss, f = 1.0mhz 14 pf these parameters are sampled, not 100% tested. capacitance (t a = +25 c) truth table oe cs 1 cs 2 we mode output power x h x x standby high z icc 2 , icc 3 x x l x standby high z icc 2 , icc 3 x x l x output deselect high z icc 1 h l h h output deselect high z icc 1 l l h h read data out icc 1 x l h l write data in icc 1 note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol conditions units min typ max input leakage current i li v in = 0v to v cc -5 +5 m a output leakage current i lo v i/o = 0v to v cc , cs 1 3 v ih and/or cs 2 v il -10 +10 m a operating power supply current i cc1 we, cs 1 = v il , i i/o = 0ma, min cycle (70-85ns) 120 ma cs 2 = v ih (100ns) 110 ma standby (ttl) power supply current i cc2 cs 1 3 v ih and/or cs 2 v il , v in 3 v ih or v il 10ma cs 1 3 v cc -0.2v and/or cs 2 vcc +0.2v c 1 5ma full standby power supply current i cc3 v in 3 vcc -0.2v or v in 0.2v lp 1 ma output low voltage v ol i ol = 2.1ma 0.4 v output high voltage v oh i oh = -1.0ma 2.4 v note: dc test conditions: v il = 0.3v, v ih = vcc -0.3v dc characteristics (v cc = 5v, t a = +25 c)
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128c input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2) 30pf 480 w vcc q figure 1 figure 2 255 w 5pf 480 w vcc q 255 w ac test conditions ac characteristics C read cycle (v cc = 5.0v, v ss = 0v, t a = 0 c to +70 c) symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units read cycle time t avav t rc 70 85 100 ns address access time t avqv t aa 70 85 100 ns chip select access time t elqv t acs 70 85 100 ns t shqv t acs 70 85 100 ns chip select to output in low z (1) t elqx t clz 333 ns t shqx t clz 333 ns chip disable to output in high z (1) t ehqz t chz 030030030 ns t slqz t chz 030030030 ns output hold from address change t avqx t oh 333 ns output enable to output valid t glqv t oe 25 30 50 ns output enable to output in low z (1) t glqx t olz 000 ns output disable to output in high z (1) t ghqz t ohz 030030030 ns 1. this parameter is guaranteed by design but not tested.
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128c ac characteristics C write cycle (v cc = 5.0v, v ss = 0v, t a = 0 c to +70 c) symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units write cycle time t avav t wc 70 85 100 ns chip select to end of write t elwh t cw 60 75 85 ns t eleh t cw 60 75 85 ns t shwh t cw 60 75 85 ns t shsl t cw 60 75 85 ns address setup time t avwl t as 000ns t avel t as 000ns t avsh t as 000ns address valid to end of write t avwh t aw 60 75 85 ns write pulse width t wlwh t wp 35 70 80 ns t wleh t wp 35 70 80 ns t wlsl t wp 35 70 80 ns write recovery time t whax t wr 555ns t ehax t wr 555ns t slax t wr 555ns data hold time t whdx t dh 000ns t ehdx t dh 000ns t sldx t dh 000ns write to output in high z (1) t wlqz t whz 030035 040 ns data to write time t dvwh t dw 35 40 40 ns t dveh t dw 35 40 40 ns t dvsl t dw 35 40 40 ns output active from end of write (1) t whqx t wlz 555ns 1. this parameter is guaranteed by design but not tested.
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128c address data i/o read cycle 1 (we high; oe, cs low) t avqx t avqv t avav data 2 address 1 address 2 data 1 address data i/o read cycle 2 (we high) t avqv t elqv t glqv t elqx t shqv t shqx t glqx t avav t ehqz t ghqz oe cs 2 t slqz cs 1 ws32k32-xhx fig. 2 timing waveform - read cycle fig. 4 write cycle2 fig. 3 write cycle 1 address data in write cycle 2 - early write, cs 1 controlled t wleh t ehax t eleh t dveh t ehdx t avav data valid we cs 1 t avel cs 2 address data in write cycle 1 - late write, we controlled t avwh t elwh t whax t wlwh t dvwh t wlqz t whqx t avwl t whdx t avav data valid high z we t shwh cs 1 data out cs 2 write cycle 3 address data in write cycle 3 - early write, cs 2 controlled t wlsl t slax t shsl t dvsl t sldx t avav data valid we cs 1 t avsh cs 2
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128c characteristic sym conditions min typ max units low power version only data retention voltage v dd v dd = 2.0v 2 C C v data retention quiescent current i ccdr cs 1 3 v dd -0.2v C C 400 m a chip disable to data retention time (1) t cdr v in 3 v dd -0.2v 0 C C ns operation recovery time (1) t r or v in 0.2v t avav *C Cns note: 1. parameter guaranteed by design, but not tested. * read cycle time data retention characteristics (edi88128lp & edi88130lp only) (t a = -55 c to +125 c) ws32k32-xhx fig. 5 data retention - cs 1 controlled data retention, cs 1 controlled data retention mode t r vcc cs 1 t cdr cs 1 3 v dd -0.2v v dd 4.5v 4.5v ws32k32-xhx fig. 6 data retention - cs 2 controlled data retention, cs 2 controlled data retention mode t r vcc cs 2 t cdr cs 2 0.2v v dd 4.5v 4.5v
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128c package 9: 32 pin sidebrazed ceramic dip (600mils wide) all dimensions are in inches pin 1 indicator 0.020 0.016 0.175 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 1.616 1.584 0.061 0.017 0.600 nom 0.060 0.040 0.620 0.600 package 100: 32 lead ceramic zip all dimensions are in inches 0.050 0.155 0.125 0.040 min 31 x 0.050 = 1.550 0.040 0.020 0.500 max 1.65 max 0.125 max 0.100 nom package 140: 32 lead ceramic soj all dimensions are in inches 0.108 0.088 0.050 typ 0.440 0.430 0.840 0.820 0.155 0.120 0.040 0.030 0.379 ref
8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128c ordering information white electronic designs sram organization, 128kx8 8 130 = dual chip select technology: c = cmos standard power lp = low power access time (ns) package type: c = 32 lead sidebrazed dip, 600 mil (package 9) n = 32 lead ceramic soj (package 140) z = 32 lead ceramic zip (package 100) device grade: b = mil-std-883 compliant m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c edi 8 8 128 c x x x
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