1/4 rev. b structure silicon monolit hic integrated circuit product series lens control lsi type bu24025mwv applications digit al still cameras functions ?driver (1-5 channels) : voltage control type h-brid ge(adaptable to stm 2 systems) ?driver (6,7 channels) : current control type h-bridge absolute maximum ratings (ta ? 25) parameter symbol limits unit remark power supply voltage dvdd -0.34.5 v mvcc -0.37.0 v input voltage vin -0.3dvdd+0.3 v input/output current iin 500 ma driver block (by mvcc pin) 50 ma by piout pin storage temperature range tstg -55125 ? c operating temperature range tope -1085 ? c permissible dissipation ? 1 pd 3000 mw this product is not designed for anti-radiation applications. *1 to use this product at a temperature higher than ta=25, re duce 30mw per 1 (at mounting rohms standard board : 74.2mmx74.2mmx1.6 t mm/4 layer board ) operating conditions (ta=25) parameter symbol limits unit remark digital power supply voltage dvdd 2.73.6 v dvddQmvcc driver power supply voltage mvcc 2.75.5 v clock operating frequency fclk 127.5 mhz reference clock electrical characteristics (unless otherwise specified, ta ? 25, dvdd ?3.0v, mvcc ? 5.0v, dvss ? mgnd ? 0.0v) parameter symbol limits unit condition min. typ. max. quiescence dvdd issd - 0.45 1.5 ma cmd_rs=0 mvcc issvm - 50 100 a cmd_rs=0 operation dvdd iddd - 6 10 ma low-level input voltage vil dvss 0.3dvdd v high-level input voltage vih 0.7dvdd dvdd v low-level input current iil 0 10 a vil = dvss high-level input current iih 0 10 a vih = dvdd low-level output voltage vol dvss 0.2dvdd v iol = 1.0ma high-level output voltage voh 0.8dvdd dvdd v ioh = 1.0ma output voltage pivo - 0.16 0.50 v iih = 30ma on-resistance ron - 1.5 2.0 io =100 ma(the sum of high and lo w sides) off-leak current ioz -10 0 10 a output hiz setting average voltage accuracy between differential output pins vdiff -5 - +5 vdiff setting: 010_1011 on-resistance ron - 1.1 1.5 io =100 ma(the sum of high and lo w sides) off-leak current ioz -10 0 10 a output hiz setting output current io 190 200 210 ma dac setting: 1000_0000 rrnf= 1 [ ? ]
2/4 rev. b 3-wire serial interface control commands are framed b y 16-bit serial input (msb firs t) and input through the csb, sclk, and sdata pins. 4 higher-order bits specify addresses, while the remaining 12 b its specify data. data of every bit is input through the sdata pin, retrieved on the rising edges of sclk. data becomes valid in the csb low area. the loading timing is d ifferent in the resistor. (as shown in note4,5) register map address[3:0] data[11:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 modea[1:0] sela[1:0] 0 ach different output voltage[6:0 ] 0 0 0 1 0 0 0 0 ach cycle[7:0] 0 0 1 0 ach cycle[15:8] 0 1 1 0 a_bexc 0 0 a_bsl a_aexc 0 0 a_asl 1 1 1 0 0 0 apos[1:0] 0 0 0 astop 0 0 1 0 ena rta ach pulse[9:0] 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 modeb[1:0] selb[1:0] 0 bch different output voltage [6: 0] 1 0 0 1 0 0 0 0 bch cycle[7:0] 0 0 1 0 bch cycle[15:8] 0 1 1 0 b_bexc 0 0 b_bsl b_aexc 0 0 b_asl 1 0 0 0 0 0 3_chop[1:0] 0 0 4_chop[1:0] 1 0 1 3_pwm_ct[1:0] 3ch pwm_duty[6:0] 1 1 0 4_pwm_ct[1:0] 4ch pwm_duty[6:0] 1 1 1 0 0 0 bpos[1:0] 0 0 0 bstop 1 0 1 0 enb rtb bch pulse[9:0] 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 chopping[1:0] cachem 0 0 isel p_ctrl clk_div[2:0] 1 1 0 1 0 0 0 0 0 0 0 0 0 0 pi_ctrl1 pi_ctrl2 0 0 1 0 0 0 0 0 5_sel[1:0] 5_chop[1:0] 0 1 0 5_pwm_ct[1:0] 5ch pwm_duty[6:0] 1 1 1 0 0 0 0 0 current driver reference voltage adjustment6 (dac6 output value) [7:0] 0 1 0 0 7ch_s 0 7_pwm_ct[1:0] 6ch_s 0 6_pwm_ct[1:0] 1 0 0 0 current driver reference voltage adjustment7 (dac7 output value) [7:0] 1 1 0 0 0 0 0 0 0 0 0 cmd_rs addresses other than those above setting prohibited (note 1) the notations a, b, in the register map correspond to ach, bch respectively. (note 2) the ach is defined as 1ch and 2ch driver output, the b ch as 3ch and 4ch driver output, (note 3) after resetting (power o n reset, and cmd_rs), initial setting is saved in all registers. (note 4) for mode, different output voltage, cycle, en, and rt registers, data that are written before the access to the pulse register becomes valid, and determined at the rising edge of csb after the a ccess to the pulse register. (the mode, different output voltag e, cycle, en , rt, and pulse registers contain ca che registers, but any registers other than those do not contai n with such registers.) (note 5) for pos, stop, chop, pwm_ct, and pwm_duty registers, d ata are determined at the rising edge of csb, and for any regis ters other than those, data are determined at the rising edge of 16th sc lk . csb d13 d14 d9 d8 d10 d11 d5 d4 d6 d7 d1 d0 d2 d3 x d15 x d12 address data sclk sdata
3/4 rev. b block diagram pin functions no. pin name power supply function no. pin name power supply function 1 csb dvdd csb logic input 23 sense6 vddamp67 negative input fo r 6ch current driver 2 sclk dvdd sclk logic input 24 vddamp67 - power supply of 6-7channel current driver control 3 sdata dvdd sdata logic input 25 out6a rnf6 6-channel driver a output 4 piout1 dvdd pi driving output1 26 rnf6 rnf6 6-channel driver power supply 5 out5a mvcc5 5-channel driver a output 27 out6b rnf6 6-channel driver b output 6 mvcc5 - 5-channel driver power supply 28 mgnd67 - 6-7channel driver ground 7 mgnd5 - 5-channel driver ground 29 out7a rnf7 7-channel drive r a output 8 out5b mvcc5 5-channel driver b output 30 rnf7 rnf7 7-channel driver power supply 9 dvss - digital ground 31 out7b rnf7 7-channel driver b output 10 fclk dvdd fclk logic input 32 sense7 vddamp67 negative input for 7ch current driver 11 dvdd - digital power supply 33 in7a dvdd in7a logic input 12 out1a mvcc12 1-channel drive a output 34 in7b dvdd in7b logi c input 13 mvcc12 - 1-2channel driver power supply 35 state11 dvdd stat e11 logic output 14 out1b mvcc12 1-channel drive b output 36 state12 dvdd state1 2 logic output 15 out2a mvcc12 2-channel drive a output 37 state21 dvdd state2 1 logic output 16 mgnd12 - 1-2channel driver ground 38 state22 dvdd state22 lo gic output 17 out2b mvcc12 2-channel drive b output 39 out3a mvcc34 3-channel driver a output 18 piout2 dvdd pi driving output2 40 mvcc34 - 3-4channel driver power supply 19 in5a dvdd in5a logic input 41 out3b mvcc34 3-channel driver b output 20 in5b dvdd in5b logic input 42 out4a mvcc34 4-channel driver a output 21 in6a dvdd in6a logic input 43 mgnd34 - 3-4channel driver gro und 22 in6b dvdd in6b logic input 44 out4b mvcc34 4-channel driver b output
4/4 rev. b outline dimensions/marking figure pin assignment diagram out1a mvcc12 out1b out2a mgnd12 8 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 10 11 9 34 35 36 37 38 39 40 41 42 43 44 out4b out2b piout2 in5a in5b in6a in6b in7b state11 state12 state21 state22 out3a mvcc34 out3b out4a mgnd34 cautions on use (1) absolute maximum ratings if applied voltage, operating tem perature range, or other absol ute maximum ratings are exceeded, the lsi may be damaged. do no t apply voltages or temperatures that exceed the absolute maximum ratin gs. if you expect that any voltage or temperature could be exc eeding the absolute maximum ratings, take physical safety measures suc h as fuses to prevent any conditions exceeding the absolute max imum ratings from being applied to the lsi. (2) gnd potential maintain the gnd pin at the minimum voltage even under any oper ating conditions. actually check to be sure that none of the pins have voltage lo wer than that of gnd pin, including transient phenomena. (3) thermal design with consideration given to the permissible dissipation under a ctual use conditions, perform thermal design so that adequate m argins will be provided. (4) short circuit between pins and malfunctions to mount the lsi on a board, pay utmost attention to the orient ation and displacement of the lsi. faulty mounting to apply a voltage to the lsi may cause damage to the lsi. furthermore, the lsi m ay also be damaged if any foreign matters enter between pins, between pin and power supply, or between pin and gnd of the lsi . (5) operation in strong magnetic field make a thorough evaluation on use of the lsi in a strong magnet ic field. not doing so may malfunction the lsi. 24025mwv
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