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1 ads1212, 1213 ads1212 ads1213 22-bit analog-to-digital converter features l delta-sigma a/d converter l 22 bits no missing codes l 20 bits effective resolution at 10hz and 16 bits at 1000hz l low power: 1.4mw l differential inputs l programmable gain amplifier l spi compatible ssi interface l programmable cut-off frequency up to 6.25khz l internal/external reference l on chip self-calibration l ads1213 includes 4 channel mux description the ads1212 and ads1213 are precision, wide dynamic range, delta-sigma analog-to-digital converters with 24-bit resolution operating from a single +5v supply. the differential inputs are ideal for direct connection to transducers or low level voltage sig- nals. the delta-sigma architecture is used for wide dynamic range and to guarantee 22 bits of no missing code performance. an effective resolution of 20 bits is achieved through the use of a very low-noise input amplifier at conversion rates up to 10hz. effective resolutions of 16 bits can be maintained up to a sample rate of 1khz through the use of the unique turbo modulator mode of operation. the dynamic range of the converters is further increased by provid- ing a low-noise programmable gain amplifier with a gain range of 1 to 16 in binary steps. the ads1212 and ads1213 are designed for high resolution measurement applications in smart trans- mitters, industrial process control, weigh scales, chro- matography and portable instrumentation. both con- verters include a flexible synchronous serial interface which is spi compatible and also offers a two-wire control mode for low cost isolation. the ads1212 is a single channel converter and is offered in both 18-pin dip and 18-lead soic pack- ages. the ads1213 includes a 4 channel input multi- plexer and is available in 24-pin dip, 24-lead soic, and 28-lead ssop packages. applications l industrial process control l instrumentation l blood analysis l smart transmitters l portable instruments l weigh scales l pressure transducers ads1213 only ads1212/13 pga +2.5v reference +3.3v bias generator clock generator serial interface second-order d? modulator instruction register command register data output register offset register full-scale register third-order digital filter micro controller modulator control agnd av dd ref out ref in v bias x in x out mode dsync cs drdy a in p a in n sclk dgnd dv dd sdio sdout mux a in 1p a in 1n a in 2p a in 2n a in 3p a in 3n a in 4p a in 4n ads1212 ads1213 ads1212 ads1213 ads1213 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 ? twx: 910-952-1111 internet: http://www.burr-brown.com/ ? faxline: (800) 548-6133 (us/canada only) ? cable: bbrcorp ? telex: 066-6491 ? fa x: (520) 889-1510 ? immediate product info: (800) 548-6132 patents pending ? 1996 burr-brown corporation pds-1360c printed in u.s.a. april, 1998
2 ads1212, 1213 all specifications t min to t max , av dd = dv dd = +5v, f xin = 1mhz, programmable gain amplifier setting of 1, turbo mode rate of 1, ref out disabled, v bias disabled, and external 2.5v reference, unless otherwise specified. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. specifications ads1212u, p/ads1213u, p, e parameter conditions min typ max units analog input input voltage range (1) 0+5v with v bias (2) C10 +10 v input impedance g = gain, tmr = turbo mode rate 20/(g ? tmr) (3) m w programmable gain amplifier user programmable: 1, 2, 4, 8, or 16 1 16 input capacitance 5pf input leakage current at +25 c550pa t min to t max 1na systems performance no missing codes f data = 10hz 22 bits f data = 60hz 19 bits f data = 100hz, tmr of 4 21 bits f data = 250hz, tmr of 8 20 bits f data = 500hz, tmr of 16 20 bits f data = 1000hz, tmr of 16 18 bits integral linearity f data = 60hz 0.0015 %fsr f data = 1000hz, tmr of 16 0.0015 %fsr unipolar offset error (4) see note 5 unipolar offset drift (6) 1 ppm/ c gain error (4) see note 5 gain error drift (6) 4 ppm/ c common-mode rejection (9) at dc, t min to t max 90 100 db 50hz, f data = 50hz (7) 160 db 60hz, f data = 60hz (7) 160 db normal-mode rejection 50hz, f data = 50hz (7) 100 db 60hz, f data = 60hz (7) 100 db output noise see typical performance curves power supply rejection dc, 50hz, and 60hz 60 db voltage reference internal reference (ref out ) 2.4 2.5 2.6 v drift 25 ppm/ c noise 50 m vp-p load current source or sink 1 ma output impedance 2 w external reference (ref in ) 2.0 3.0 v load current 2.5 m a v bias output using internal reference 3.15 3.3 3.45 v drift 50 ppm/ c load current source or sink 10ma digital input/output logic family ttl compatible cmos logic level: (all except x in ) v ih i ih = +5 m a 2.0 dv dd +0.3 v v il i il = +5 m a C0.3 0.8 v v oh i oh = 2 ttl loads 2.4 v v ol i ol = 2 ttl loads 0.4 v x in input levels: v ih 3.5 dv dd +0.3 v v il C0.3 0.8 v x in frequency range (f xin ) 0.5 2.5 mhz output data rate (f data ) user programmable and tmr = 1 to 16 0.96 6,250 hz f xin = 500khz 0.48 3,125 hz f xin = 2.5mhz 2.4 15,625 hz data format user programmable twos complement or offset binary system calibration offset and full-scale limits v fs = full-scale differential voltage (8) 0.7 ? (2 ? ref in )/g v fs C | v os |v os = offset differential voltage (8) 1.3 ? (2 ? ref in )/g
3 ads1212, 1213 power supply requirements power supply voltage 4.75 5.25 v power supply current: analog current 95 m a digital current 185 m a additional analog current with ref out enabled 1.8 ma v bias enabled no load 1 ma power dissipation at +25 c 1.4 mw t min to t max 1.8 mw tmr of 16 6 8.5 mw f xin = 2.5mhz 2.2 mw f xin = 2.5mhz, tmr of 16 7.5 mw sleep mode 0.45 mw temperature range specified C40 +85 c storage C60 +125 c notes: (1) in order to achieve the converters full-scale range, the input must be fully differential (a in n = 2 ? ref in C a in p). if the input is single-ended (a in n or a in p is fixed), then the full scale range is one-half that of the differential range. (2) this range is set with external resistor s and v bias (as described in the text). other ranges are possible. (3) input impedance is higher with lower f xin . (4) applies after calibration. (5) after system calibration, these errors will be of the order of the effective resolution of the converter. refer to the typical performance curves which apply to the desired mode of operat ion. (6) recalibration can remove these errors. (7) the specification also applies at f data /i, where i is 2, 3, 4, etc. (8) voltages at the analog inputs must remain within agnd to av dd . (9) the common- mode rejection test is performed with 100mv differential input. specifications (cont) ads1212u, p/ads1213u, p, e parameter conditions min typ max units all specifications t min to t max , av dd = dv dd = +5v, f xin = 1mhz, programmable gain amplifier setting of 1, turbo mode rate of 1, ref out disabled, v bias disabled, and external 2.5v reference, unless otherwise specified. analog input: current ................................................ 100ma, momentary 10ma, continuous voltage ................................... agnd C0.3v to av dd +0.3v av dd to dv dd .......................................................................... C0.3v to 6v av dd to agnd ........................................................................ C0.3v to 6v dv dd to dgnd ........................................................................ C0.3v to 6v agnd to dgnd ................................................................................ 0.3v ref in voltage to agnd ............................................ C0.3v to av dd +0.3v digital input voltage to dgnd .................................. C0.3v to dv dd +0.3v digital output voltage to dgnd ............................... C0.3v to dv dd +0.3v lead temperature (soldering, 10s) ............................................... +300 c power dissipation (any package) .................................................. 500mw absolute maximum ratings package/ordering information package drawing temperature product package number (1) range ads1212p 18-pin plastic dip 218 C40 c to +85 c ads1212u 18-lead soic 219 C40 c to +85 c ads1213p 24-pin plastic dip 243 C40 c to +85 c ads1213u 24-lead soic 239 C40 c to +85 c ads1213e 28-lead ssop 324 C40 c to +85 c note: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with ap- propriate precautions. failure to observe proper handling and installation procedures can cause damage. electrostatic discharge can cause damage ranging from performance degradation to complete device failure. burr- brown corporation recommends that all integrated circuits be handled and stored using appropriate esd protection methods.
4 ads1212, 1213 pga +2.5v reference +3.3v bias generator clock generator serial interface second-order ds modulator instruction register command register data output register offset register full-scale register third-order digital filter micro controller modulator control 11 9 10 12 13 agnd av dd ref out ref in v bias x in x out 3 1 2 16 17 18 4 7 8 65 14 15 dsync cs drdy mode a in p a in n sclk dgnd dv dd sdio sdout ads1212 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd ads1212 simplified block diagram ads1212 pin definitions pin no name description 1a in p noninverting input. 2a in n inverting input. 3 agnd analog ground. 4v bias bias voltage output, +3.3v nominal. 5 cs chip select input. 6 dsync control input to synchronize serial output data. 7x in system clock input. 8x out system clock output. 9 dgnd digital ground. 10 dv dd digital supply, +5v nominal. 11 sclk clock input/output for serial data transfer. 12 sdio serial data input (can also function as serial data output). 13 sdout serial data output. 14 drdy data ready. 15 mode sclk control input (master = 1, slave = 0). 16 av dd analog supply, +5v nominal. 17 ref out reference output, +2.5v nominal. 18 ref in reference input. top view dip/soic ads1212 pin configuration
5 ads1212, 1213 pga +2.5v reference +3.3v bias generator clock generator serial interface second-order d? modulator third-order digital filter modulator control 14 12 13 15 16 agnd av dd ref out ref in v bias x in x out 6 19 20 21 7 10 11 98 17 18 dsync cs drdy mode sclk dgnd dv dd sdio sdout 4 5 2 3 24 1 22 23 mux a in 1p a in 1n a in 2p a in 2n a in 3p a in 3n a in 4p a in 4n instruction register command register data output register offset register full-scale register micro controller ads1213 simplified block diagram ads1213p and ads1213u pin definitions top view dip/soic ads1213p and ads1213u pin configuration pin no name description 1a in 3n inverting input channel 3. 2a in 2p noninverting input channel 2. 3a in 2n inverting input channel 2. 4a in 1p noninverting input channel 1. 5a in 1n inverting input channel 1. 6 agnd analog ground. 7v bias bias voltage output, +3.3v nominal. 8 cs chip select input. 9 dsync control input to synchronize serial output data. 10 x in system clock input. 11 x out system clock output. 12 dgnd digital ground. 13 dv dd digital supply, +5v nominal. 14 sclk clock input/output for serial data transfer. 15 sdio serial data input (can also function as serial data output). 16 sdout serial data output. 17 drdy data ready. 18 mode sclk control input (master = 1, slave = 0). 19 av dd analog supply, +5v nominal. 20 ref out reference output: +2.5v nominal. 21 ref in reference input. 22 a in 4p noninverting input channel 4. 23 a in 4n inverting input channel 4. 24 a in 3p noninverting input channel 3. ads1213p ads1213u 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a in 3n a in 2p a in 2n a in 1p a in 1n agnd v bias cs dsync x in x out dgnd a in 3p a in 4n a in 4p ref in ref out av dd mode drdy sdout sdio sclk dv dd
6 ads1212, 1213 ads1213e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a in 3n a in 2p a in 2n a in 1p a in 1n agnd v bias nic nic cs dsync x in x out dgnd a in 3p a in 4n a in 4p ref in ref out av dd mode nic nic drdy sdout sdio sclk dv dd ads1213e pin definitions pin no name description 1a in 3n inverting input channel 3. 2a in 2p noninverting input channel 2. 3a in 2n inverting input channel 2. 4a in 1p noninverting input channel 1. 5a in 1n inverting input channel 1. 6 agnd analog ground. 7v bias bias voltage output, +3.3v nominal. 8 nic not internally connected. 9 nic not internally connected. 10 cs chip select input. 11 dsync control input to synchronize serial output data. 12 x in system clock input. 13 x out system clock output. 14 dgnd digital ground. 15 dv dd digital supply, +5v nominal. 16 sclk clock input/output for serial data transfer. 17 sdio serial data input (can also function as serial data output). 18 sdout serial data output. 19 drdy data ready. 20 nic not internally connected. 21 nic not internally connected. 22 mode sclk control input (master = 1, slave = 0). 23 av dd analog supply, +5v nominal. 24 ref out reference output: +2.5v nominal. 25 ref in reference input. 26 a in 4p noninverting input channel 4. 27 a in 4n inverting input channel 4. 28 a in 3p noninverting input channel 3. ads1213e pin configuration top view ssop
7 ads1212, 1213 typical performance curves at t a = +25 c, av dd = dv dd = +5v, f xin = 1mhz, programmable gain amplifier setting of 1, turbo mode rate of 1, ref out disabled, v bias disabled, and external 2.5v reference, unless otherwise noted. 24 22 20 18 16 14 12 10 8 effective resolution vs data rate (1mhz clock) data rate (hz) 1 10 100 1k effective resolution in bits (rms) pga 1 pga 4 pga 2 pga 16 pga 8 24 22 20 18 16 14 12 10 8 effective resolution vs data rate (2.5mhz clock) data rate (hz) 1 10 100 1k effective resolution in bits (rms) pga 1 pga 2 pga 4 pga 16 pga 8 linearity vs temperature (60hz data rate) analog input differential voltage (v) ? ? ? ? ? 0 1 2 3 4 5 integral nonlinearity (ppm) 8 6 4 2 0 ? ? ? ?0? +25? +85? 24 22 20 18 16 14 12 effective resolution vs data rate (1mhz clock) data rate (hz) 1 10 100 1k effective resolution in bits (rms) turbo 1 turbo 2 turbo 4 turbo 8 turbo 16 24 22 20 18 16 14 12 effective resolution vs data rate (2.5mhz clock) data rate (hz) 1 10 100 1k effective resolution in bits (rms) turbo 1 turbo 2 turbo 4 turbo 16 turbo 8 rms noise vs input voltage level (60hz data rate) analog input differential voltage (v) ?.0 ?.0 ?.0 ?.0 ?.0 0 1.0 2.0 3.0 4.0 5.0 rms noise (ppm) 14 12 10 8 6 4
8 ads1212, 1213 typical performance curves (cont) at t a = +25 c, av dd = dv dd = +5v, f xin = 1mhz, programmable gain amplifier setting of 1, turbo mode rate of 1, ref out disabled, v bias disabled, and external 2.5v reference, unless otherwise noted. power dissipation vs pga setting (ref out enabled) pga setting 124816 power dissipation (mw) 15 14.5 14 13.5 13 12.5 12 11.5 11 10.5 10 turbo 1 turbo 2 turbo 4 turbo 8 turbo 16 analog current vs pga setting (ref out enabled) pga setting 124816 analog i dd (?) 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 turbo 1 turbo 2 turbo 4 turbo 8 turbo 16 analog current vs pga setting (external reference; ref out disabled) pga setting 124816 analog i dd (?) 980 880 780 680 580 480 380 280 180 80 turbo 1 turbo 2 turbo 4 turbo 8 turbo 16 power dissipation vs pga setting (external reference; ref out disabled) pga setting 124816 power dissipation (mw) 6 5 4 3 2 1 0 turbo 1 turbo 2 turbo 4 turbo 8 turbo 16
9 ads1212, 1213 theory of operation the ads1212 and ads1213 are precision, high dynamic range, self-calibrating, 24-bit, delta-sigma a/d converters capable of achieving very high resolution digital results. each contains a programmable gain amplifier (pga); a second-order delta-sigma modulator; a programmable digi- tal filter; a microcontroller including the instruction, com- mand and calibration registers; a serial interface; a clock generator circuit; and an internal 2.5v reference. the ads1213 includes a 4-channel input multiplexer. in order to provide low system noise, common-mode rejec- tion of 100db and excellent power supply rejection, the design topology is based on a fully differential switched capacitor architecture. turbo mode, a unique feature of the ads1212/13, can be used to boost the sampling rate of the input capacitor, which is normally 7.8khz with a 1mhz clock. by programming the command register, the sam- pling rate can be increased to 15.6khz, 31.2khz, 62.5khz, or 125khz. each increase in sample rate results in an increase in performance when maintaining the same output data rate. the programmable gain amplifier (pga) of the ads1212/ 13 can be set to a gain of 1, 2, 4, 8 or 16substantially increasing the dynamic range of the converter and simplify- ing the interface to the more common transducers (see table i). this gain is implemented by increasing the number of samples taken by the input capacitor from 7.8khz for a gain of 1 to 125khz for a gain of 16. since the turbo mode and pga functions are both implemented by varying the sam- pling frequency of the input capacitor, the combination of pga gain and turbo mode rate is limited to 16 (see table ii). for example, when using a turbo mode rate of 8 (62.5khz at 1mhz), the maximum pga gain setting is 2. the output data rate of the ads1212/13 can be varied from less than 1hz to as much as 6.25khz, trading off lower resolution results for higher data rates. in addition, the data rate determines the first null of the digital filter and sets the C3db point of the input bandwidth (see the digital filter section). changing the data rate of the ads1212/13 does not result in a change in the sampling rate of the input capacitor. the data rate effectively sets the number of samples which are used by the digital filter to obtain each conversion result. a lower data rate results in higher resolution, lower input bandwidth, and different notch frequencies than a higher data rate. it does not result in any change in input impedance or modulator frequency, or any appreciable change in power consumption. the ads1212/13 also includes complete on-board calibra- tion that can correct for internal offset and gain errors or limited external system errors. internal calibration can be run when needed, or automatically and continuously in the background. system calibration can be run as needed and the appropriate input voltages must be provided to the ads1212/ 13. for this reason, there is no continuous system calibration mode. the calibration registers are fully readable and writ- able. this feature allows for switching between various configurationsdifferent data rates, turbo mode rates, and gain settingswithout re-calibrating. the various settings, rates, modes, and registers of the ads1212/13 are read or written via a synchronous serial interface. this interface can operate in either a self-clocked mode (master mode) or an externally clocked mode (slave mode). in the master mode, the serial clock (sclk) fre- quency is one-quarter of the ads1212/13 x in clock fre- quency. the high resolution and flexibility of the ads1212/13 allow these converters to fill a wide variety of a/d conversion tasks. in order to ensure that a particular configuration will meet the design goals, there are several important items which must be considered. these include (but are certainly not limited to) the needed resolution, required linearity, desired input bandwidth, power consumption goal, and sen- sor output voltage. the remainder of this data sheet discusses the operation of the ads1212/13 in detail. in order to allow for easier comparison of different configurations, effective resolu- tion is used as the figure of merit for most tables and graphs. for example, table iii shows a comparison between data rate (and C3db input bandwidth) versus pga setting at a turbo mode rate of 1 and a clock rate of 1mhz. see the definition of terms section for a definition of effective resolution. analog analog input input (1) utilizing v bias (1,2) full- example full- example scale voltage scale voltage gain range range (3) range range (3) setting (v) (v) (v) (v) 1 10 0 to 5 40 10 2 5 1.25 to 3.75 20 5 4 2.5 1.88 to 3.13 10 2.5 8 1.25 2.19 to 2.81 5 1.25 16 0.625 2.34 to 2.66 2.5 0.625 note: (1) with a 2.5v reference, such as the internal reference. (2) this example utilizes the circuit in figure 12. other input ranges are possible. (3) the ads1212/13 allows common-mode voltage as long as the absolute input voltage on a in p or a in n does not go below agnd or above av dd . table i. full-scale range vs pga setting. turbo mode rate available pga settings 1 1, 2, 4, 8, 16 2 1, 2, 4, 8 4 1, 2, 4 8 1, 2 16 1 table ii. available pga settings vs turbo mode rate.
10 ads1212, 1213 data -3db rate frequency (hz) (hz) g = 1 g = 2 g = 4 g = 8 g = 16 10 2.62 20 20 20 19 18 25 6.55 19 19 19 18 18 30 7.86 19 19 18 18 17 50 13.1 17 17 17 17 16 60 15.7 17 17 17 16 16 100 26.2 15 15 15 15 15 250 65.5 12 12 12 12 12 effective resolution (bits rms) for example, when the converter is configured with a 2.5v reference and placed in a gain setting of 2, the typical input voltage range is 1.25v to 3.75v (common- mode voltage = 2.5v). however, an input range of 0v to 2.5v (common-mode voltage = 1.25v) or 2.5v to 5v (common-mode voltage = 3.75v) would also cover the converters full-scale range. voltage span this is simply the magnitude of the typical analog input voltage range. for example, when the converter is configured with a 2.5v reference and placed in a gain setting of 2, the input voltage span is 2.5v. least significant bit (lsb) weight this is the theoreti- cal amount of voltage that the differential voltage at the analog input would have to change in order to observe a change in the output data of one least significant bit. it is computed as follows: where n is the number of bits in the digital output. effective resolution the effective resolution of the ads1212/13 in a particular configuration can be expressed in two different units: bits rms (referenced to output) and microvolts rms (referenced to input). computed directly from the converters output data, each is a statistical calcu- lation based on a given number of results. knowing one, the other can be computed as follows: the 10v figure in each calculation represents the full-scale range of the ads1212/13 in a gain setting of 1. this means that both units are absolute expressions of resolutionthe performance in different configurations can be directly com- pared regardless of the units. comparing the resolution of different gain settings expressed in bits rms requires ac- counting for the pga setting. main controller a generic term for the external microcontroller, microprocessor, or digital signal processor which is controlling the operation of the ads1212/13 and receiving the output data. table iii. effective resolution vs data rate and gain setting. (turbo mode rate of 1 and a 1mhz clock.) definition of terms an attempt has been made to be consistent with the termi- nology used in this data sheet. in that regard, the definition of each term is given as follows: analog input differential voltage for an analog signal that is fully differential, the voltage range can be compared to that of an instrumentation amplifier. for example, if both analog inputs of the ads1212 are at 2.5v, then the differ- ential voltage is 0v. if one is at 0v and the other at 5v, then the differential voltage magnitude is 5v. but, this is the case regardless of which input is at 0v and which is at 5v, while the digital output result is quite different. the analog input differential voltage is given by the follow- ing equation: a in p C a in n. thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced when- ever the differential is negative. for example, when the converter is configured with a 2.5v reference and placed in a gain setting of 2, the positive full- scale output is produced when the analog input differential is 2.5v. the negative full-scale output is produced when the differential is C2.5v. in each case, the actual input voltages must remain within the agnd to av dd range (see table i). actual analog input voltage the voltage at any one analog input relative to agnd. full-scale range (fsr) as with most a/d converters, the full-scale range of the ads1212/13 is defined as the input which produces the positive full-scale digital output minus the input which produces the negative full-scale digital output. for example, when the converter is configured with a 2.5v reference and is placed in a gain setting of 2, the full-scale range is: [2.5v (positive full scale) minus C2.5v (negative full scale)] = 5v. typical analog input voltage range this term de- scribes the actual voltage range of the analog inputs which will cover the converters full-scale range, assuming that each input has a common-mode voltage that is greater than ref in /pga and smaller than (av dd C ref in /pga). lsb weight = full - scale range 2 n er in bits rms = 20 log 10 v pga ? ? ? er in vrms ? ? ? ? ? ? -1 . 76 6 . 02 er in vrms = 10 10 v pga ? ? ? 6 . 02 er in bits rms +1 . 76 20 ? ? ?
11 ads1212, 1213 f data = f xin turbo mode 128 decimation ratio +1 () f mod = f xin turbo mode 128 f xin the frequency of the crystal oscillator or cmos compatible input signal at the x in input of the ads1212/13. f mod the frequency or speed at which the modulator of the ads1212/13 is running, given by the following equation: f samp the frequency or switching speed of the input sampling capacitor. the value is given by the following equation: f data , t data the frequency of the digital output data produced by the ads1212/13 or the inverse of this (the period), respectively, f data is also referred to as the data rate. conversion cycle the term conversion cycle usually refers to a discrete a/d conversion operation, such as that performed by a successive approximation converter. as used here, a conversion cycle refers to the t data time period. however, each digital output is actually based on the modu- lator results from the last three t data time periods. digital filter the digital filter of the ads1212/13 computes the output result based on the most recent results from the delta-sigma modulator. the number of modulator results that are used depend on the decimation ratio set in the command regis- ter. at the most basic level, the digital filter can be thought of as simply averaging the modulator results and presenting this average as the digital output. while the decimation ratio determines the number of modu- lator results to use, the modulator runs faster at higher turbo modes. these two items, together with the ads1212/13 clock frequency, determine the output data rate: also, since the conversion result is essentially an average, the data rate determines where the resulting notches are in the digital filter. for example, if the output data rate is 1khz, then a 1khz input frequency will average to zero during the 1ms conversion cycle. likewise, a 2khz input frequency will average to zero, etc. in this manner, the data rate can be used to set specific notch frequencies in the digital filter response (see figure 1 for the normalized response of the digital filter). for example, if the rejection of power line frequencies is desired, then the data rate can simply be set to the power line frequency. figures 2 and 3 show the digital filter response for a data rate of 50hz and 60hz, respectively. f samp = f xin turbo mode gain setting 128 filter response frequency (hz) ?0 ?0 ?0 ?00 ?20 ?40 ?60 45 46 47 48 49 50 51 52 53 54 55 filter response frequency (hz) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 0 50 100 150 200 250 300 gain (db) gain (db) normalized digital filter response frequency (hz) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 01234 56 gain (db) figure 3. digital filter response at a data rate of 60hz. figure 1. normalized digital filter response. figure 2. digital filter response at a data rate of 50hz. if the effective resolution at a 50hz or 60hz data rate is not adequate for the particular application, then power line fre- quencies could still be rejected by operating the ads1212/13 at 25/30hz, 16.7/20hz, 12.5/15hz, etc. if a higher data rate is needed, then power line frequencies must either be rejected before conversion (with an analog notch filter) or after conversion (with a digital notch filter running on the main controller). filter response frequency (hz) ?0 ?0 ?0 ?00 ?20 ?40 ?60 55 56 57 58 59 60 61 62 63 64 65 filter response frequency (hz) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 0 50 100 150 200 250 300 gain (db) gain (db) f data = f xin turbo mode 128 decimation ratio +1 () ,t data = 1 f data
12 ads1212, 1213 filter equation the digital filter is described by the following transfer function: where n is the decimation ratio. this filter has a (sin(x)/x) 3 response and is referred to a sinc 3 filter. for the ads1212/13, this type of filter allows the data rate to be changed over a very wide range (nearly four orders of magnitude). however, the C3db point of the filter is 0.262 times the data rate. and, as can be seen in figures 1 and 2, the rejection in the stopband (frequencies higher than the first notch frequency) may only be C40db. these factors must be considered in the overall system design. for example, with a 50hz data rate, a significant signal at 75hz may alias back into the passband at 25hz. the analog front end can be designed to provide the needed attenuation to prevent aliasing, or the system may simply provide this inherently. another possibility is increasing the data rate and then post filtering with a digital filter on the main controller. filter settling the number of modulator results used to compute each conversion result is three times the decimation ratio. this means that any step change (or any channel change for the ads1213) will require at least three conversions to fully settle. however, if the change occurs asynchronously, then at least four conversions are required to ensure complete set- tling. for example, on the ads1213, the fourth conversion result after a channel change will be valid (see figure 4). |h(f)| = sin p f n f mod ? ? ? ? n sin p f f mod ? ? ? ? 3 the effective resolution of the output data at a given data rate, but there is also an increase in power dissipation. for turbo mode rates 2 and 4, the increase is slight. for rates 8 and 16, the increase is more substantial. see the typical perfor- mance curves for more information. in a turbo mode rate of 16, the ads1212/13 can offer 16 bits of effective resolution at a 1khz data rate. a comparison of effective resolution versus turbo mode rates and output data rates is shown in table iv while table v shows the corresponding noise level in m vrms. turbo mode the ads1212/13 offers a unique turbo mode feature which can be used to increase the modulator sampling rate by 2, 4, 8, or 16 times normal. with the increase of modulator sampling frequency, there can be a substantial increase in data turbo turbo turbo turbo turbo rate mode mode mode mode mode (hz) rate 1 rate 2 rate 4 rate 8 rate 16 10 20 21 21 20 19 20 21 21 40 18 20 21 21 21 50 17 19 20 21 21 60 17 19 20 21 21 100 15 17 19 21 21 250 12 14 16 19 20 1000 12 14 16 effective resolution (bits rms) figure 4. asynchronous ads1212/13 analog input volt- age step or ads1213 channel change to fully settled output data. drdy serial i/o valid data valid data valid data valid data data not valid data not valid data not valid significant analog input change or ads1213 channel change t data table iv. effective resolution vs data rate and turbo mode rate. (gain setting of 1 and 1mhz clock.) data turbo turbo turbo turbo turbo rate mode mode mode mode mode (hz) rate 1 rate 2 rate 4 rate 8 rate 16 10 7.6 3.8 3.8 20 15 7.6 3.8 3.8 40 30 7.6 3.8 3.8 3.8 50 60 15 7.6 3.8 3.8 60 60 15 7.6 3.8 3.8 100 240 60 15 3.8 3.8 250 1900 480 120 15 7.6 1000 1900 480 120 noise level ( m vrms) table v. noise level vs data rate and turbo mode rate. (gain setting of 1 and 1mhz clock.) the turbo mode feature allows trade-offs to be made between the ads1212/13 x in clock frequency, power dissi- pation, and effective resolution. if a 0.5mhz clock is avail- able but a 1mhz clock is needed to achieve the desired performance, a turbo mode rate of 2x will result in the same effective resolution. table vi provides a comparison of effective resolution at various clock frequencies, data rates, and turbo mode rates. data x in clock turbo effective rate frequency mode resolution (hz) (mhz) rate (bits rms) 60 2 2 20 60 1 4 20 60 0.5 8 20 100 2 2 19 100 1 4 19 100 0.5 8 19 table vi. effective resolution vs data rate, clock frequency, and turbo mode rate. (gain set- ting of 1.)
13 ads1212, 1213 the turbo mode rate (tmr) is programmed via the sam- pling frequency bits of the command register. due to the increase in input capacitor sampling frequency, higher turbo mode settings result in lower analog input impedance; a in impedance ( w ) = (1mhz/f xin )?20e6/(g?tmr) where g is the gain setting. because the modulator rate also changes in direct relation to the turbo mode setting, higher values result in a lower impedance for the ref in input: ref in impedance ( w ) = (1mhz/f xin )?5e6/tmr the turbo mode rate can be set to 1, 2, 4, 8, or 16. consult the graphs shown in the typical performance curves for full details on the performance of the ads1212/13 operating in different turbo mode rates. keep in mind that higher turbo mode rates result in fewer available gain settings as shown in table ii. programmable gain amplifier the programmable gain amplifier gain setting is programmed via the pga gain bits of the command register. changes in the gain setting (g) of the programmable gain amplifier results in an increase in the input capacitor sampling fre- quency. thus, higher gain settings result in a lower analog input impedance: a in impedance ( w ) = (1mhz/f xin )?20e6/(g?tmr) where tmr is the turbo mode rate. because the modulator speed does not depend on the gain setting, the input imped- ance seen at ref in does not change. the pga can be set to gains of 1, 2, 4, 8, or 16. these gain settings with their resulting full-scale range and typical voltage range are shown in table i. keep in mind that higher turbo mode rates result in fewer available gain settings as shown in table ii. software gain the excellent performance, flexibility, and low cost of the ads1212/13 allow the converter to be considered for de- signs which would not normally need a 24-bit adc. for example, many designs utilize a 12-bit converter and a high- gain ina or pga for digitizing low amplitude signals. for some of these cases, the ads1212/13 by itself may be a solution, even though the maximum gain is limited to 16. to get around the gain limitation, the digital result can simply be shifted up by n bits in the main controller resulting in a gain of n times g, where g is the gain setting. while this type of manipulation of the output data is obvious, it is easy to miss how much the gain can be increased in this manner on a 24-bit converter. for example, shifting the result up by three bits when the ads1212/13 is set to a gain of 16 results in an effective gain of 128. at lower data rates, the converter can easily provide more than 12 bits of resolution. even higher gains are possible. the limitation is a combination of the needed data rate, desired noise performance, and desired linearity. calibration the ads1212/13 offers several different types of calibra- tion, and the particular calibration desired is programmed via the command register. in the case of background calibration, the calibration will repeat at regular intervals indefinitely. for all others, the calibration is performed once and then normal operation is resumed. each type of calibration is covered in detail in their respec- tive section. in general, calibration is recommended imme- diately after power-on and whenever there is a significant change in the operating environment. the amount of change which should cause a re-calibration is dependent on the application, effective resolution, etc. where high accuracy is important, re-calibration should be done on changes in temperature and power supply. in all cases, re-calibration should be done when the gain, turbo mode, or data rate is changed. after a calibration has been accomplished, the offset cali- bration register and the full-scale calibration register contain the results of the calibration. the data in these registers are accurate to the effective resolution of the ads1212/13s mode of operation during the calibration. thus, these values will show a variation (or noise) equiva- lent to a regular conversion result. for those cases where this error must be reduced, it is tempting to consider running the calibration at a slower data rate and then increasing the converters data rate after the calibration is complete. unfortunately, this will not work as expected. the reason is that the results calculated at the slower data rate would not be valid for the higher data rate. instead, the calibration should be done repeatedly. after each calibration, the results can be read and stored. after the desired number of calibrations, the main controller can compute an average and write this value into the calibration registers. the resulting error in the calibration values will be reduced by the square root of the number of calibrations which were averaged. the calibration registers can also be used to provide system offset and gain corrections separate from those computed by the ads1212/13. for example, these might be burned into e 2 prom during final product testing. on power-on, the main controller would load these values into the calibration registers. a further possibility is a look-up table based on the current temperature. note that the values in the calibration registers will vary from configuration to configuration and from part to part. there is no method of reliably computing what a particular calibration register should be to correct for a given amount of system error. it is possible to present the ads1212/13 with a known amount of error, perform a calibration, read the desired calibration register, change the error value, perform another calibration, read the new value and use these values to interpolate an intermediate value.
14 ads1212, 1213 valid data drdy serial i/o valid data soc (1) t data normal mode offset calibration on system offset (2) analog input conversion system offset calibration mode possibly valid data possibly valid data normal mode notes: (1) soc = system offset calibration instruction. (2) in slave mode, this function requires 4 cycles. figure 5. self-calibration timing. mode bits are reset to 000 (normal mode). a single conver- sion is done with drdy high. after this conversion, the drdy signal goes low indicating resumption of normal operation. normal operation returns within a single conversion cycle because it is assumed that the input voltage at the converters input is not removed immediately after the offset calibration is performed. in this case, the digital filter already contains a valid result. for full system calibration, offset calibration must be per- formed first and then full-scale calibration. in addition, the offset calibration error will be the rms sum of the conversion error and the noise on the system offset voltage. see the system calibration limits section for information regarding the limits on the magnitude of the system offset voltage. system full-scale calibration a system full-scale calibration is performed after the bits 011 have been written to the command register operation mode bits (md2 through md0). this initiates the following sequence (see figure 7). at the start of the next conversion cycle, the drdy signal will not go low but will remain high and will continue to remain high throughout the calibration sequence. the full-scale calibration will be per- formed on the differential input voltage (2 ? ref in /g) present at the converters input over the next three conver- sion periods (four in slave mode). when this is done, the operation mode bits are reset to 000 (normal mode). a single conversion is done with drdy high. after this conversion, the drdy signal goes low indicating resump- tion of normal operation. figure 7. system full-scale calibration timing. figure 6. system offset calibration timing. valid data drdy serial i/o valid data sc (1) t data normal mode valid data valid data normal mode offset calibration on internal offset (2) self-calibration mode full-scale calibration on internal full-scale analog input conversion notes: (1) sc = self-calibration instruction. (2) in slave mode, this function requires 4 cycles. valid data drdy serial i/o valid data sfsc (1) t data normal mode full-scale calibration on system full-scale (2) analog input conversion system full-scale calibration mode possibly valid data possibly valid data normal mode notes: (1) sfsc = system full-scale calibration instruction. (2) in slave mode, this function requires 4 cycles. self-calibration a self-calibration is performed after the bits 001 have been written to the command register operation mode bits (md2 through md0). this initiates the following sequence at the start of the next conversion cycle (see figure 5). the drdy signal will not go low but will remain high and will continue to remain high throughout the calibration sequence. the inputs to the sampling capacitor are discon- nected from the converters analog inputs and are shorted together. an offset calibration is performed over the next three conversion periods (four in slave mode). then, the input to the sampling capacitor is connected across ref in , and a full-scale calibration is performed over the next three conversions. after this, the operation mode bits are reset to 000 (normal mode) and the input capacitor is reconnected to the input. conversions proceed as usual over the next three cycles in order to fill the digital filter. drdy remains high during this time. on the start of the fourth cycle , drdy goes low indicating valid data and resumption of normal operation. system offset calibration a system offset calibration is performed after the bits 010 have been written to the command register operation mode bits (md2 through md0). this initiates the following sequence (see figure 6). at the start of the next conversion cycle, the drdy signal will not go low but will remain high and will continue to remain high throughout the calibration sequence. the offset calibration will be per- formed on the differential input voltage present at the converters input over the next three conversion periods (four in slave mode). when this is done, the operation
15 ads1212, 1213 normal operation returns within a single conversion cycle because it is assumed that the input voltage at the converters input is not removed immediately after the full-scale calibra- tion is performed. in this case, the digital filter already contains a valid result. for full system calibration, offset calibration must be per- formed first and then full-scale calibration. the calibration error will be a sum of the rms noise on the conversion result and the input signal noise. see the system calibration limits section for information regarding the limits on the magni- tude of the system full-scale voltage. pseudo system calibration the pseudo system calibration is performed after the bits 100 have been written to the command register operation mode bits (md2 through md0). this initiates the following sequence (see figure 8). at the start of the next conversion cycle, the drdy signal will not go low but will remain high and will continue to remain high throughout the calibration sequence. the offset calibration will be performed on the differential input voltage present at the converters input over the next three conversion periods (four in slave mode). then, the input to the sampling capacitor is discon- nected from the converters analog input and connected across ref in . a gain calibration is performed over the next three conversions. after this, the operation mode bits are reset to 000 (nor- mal mode) and the input capacitor is then reconnected to the input. conversions proceed as usual over the next three cycles in order to fill the digital filter. drdy remains high during this time. on the next cycle, the drdy signal goes low indicating valid data and resumption of normal operation. the system offset calibration range of the ads1212/13 is limited and is listed in the specifications table. for more information on how to use these specifications, see the system calibration limits section. to calculate v os , use 2 ? ref in /gain for v fs . background calibration the background calibration mode is entered after the bits 101 have been written to the command register operation mode bits (md2 through md0). this initiates the following continuous sequence (see figure 9). at the start of the next conversion cycle, the drdy signal will not go low but will remain high. the inputs to the sampling capacitor are disconnected from the converters analog input and shorted together. an offset calibration is performed over the next three conversion periods (in slave mode, the very first offset calibration requires four periods, and all subsequent offset calibrations require three periods). then, the input capacitor is reconnected to the input. conversions proceed as usual over the next three cycles in order to fill the digital filter. drdy remains high during this time. on the next cycle, the drdy signal goes low indicating valid data. figure 8. pseudo system calibration timing. figure 9. background calibration timing. valid data drdy serial i/o valid data psc (1) t data normal mode valid data valid data normal mode offset calibration on system offset (2) pseudo system calibration mode full-scale calibration on internal full-scale analog input conversion notes: (1) psc = pseudo system calibration instruction. (2) in slave mode, this function requires 4 cycles. normal mode background calibration mode valid data drdy serial i/o valid data bc (1) t data offset calibration on internal offset (2) analog input conversion analog input conversion cycle repeats with offset calibration full-scale calibration on internal full-scale notes: (1) bc = background calibration instruction. (2) in slave mode, the very first offset calibration will require 4 cycles. all subsequent offset calibrations will require 3 cycles.
16 ads1212, 1213 also, during this cycle, the sampling capacitor is discon- nected from the converters analog input and is connected across ref in . a gain calibration is initiated and proceeds over the next three conversions. after this, the input capaci- tor is once again connected to the analog input. conversions proceed as usual over the next three cycles in order to fill the digital filter. drdy remains high during this time. on the next cycle, the drdy signal goes low indicating valid data, the input to the sampling capacitor is shorted, and an offset calibration is initiated. at this point, the background calibration sequence repeats. in essence, the background calibration mode performs continuous self-calibration where the offset and gain cali- brations are interleaved with regular conversions. thus, the data rate is reduced by a factor of 6. the advantage is that the converter is continuously adjusting to environmental changes such as ambient or component temperature (due to airflow variations). the ads1212/13 will remain in the background calibra- tion mode indefinitely. to move to any other mode, the command register operation mode bits (md2 through md0) must be set to the appropriate values. system calibration offset and full-scale calibration limits the system offset and full-scale calibration range of the ads1212/13 is limited and is listed in the specifications table. the range is specified as: (v fs C | v os |) < 1.3 ? (2 ? ref in )/gain (v fs C | v os |) > 0.7 ? (2 ? ref in )/gain where v fs is the system full-scale voltage and | v os | is the absolute value of the system offset voltage. in the following discussion, keep in mind that these voltages are differential voltages. for example, with the internal reference (2.5v) and a gain of two, the previous equations become (after some manipulation): v fs C 3.25 < v os < v fs C 1.75 if v fs is perfect at 2.5v (positive full-scale), then v os must be greater than C0.75v and less than 0.75v. thus, when offset calibration is performed, the positive input can be no more than 0.75v below or above the negative input. if this range is exceeded, the ads1212/13 may not calibrate properly. this calculation method works for all gains other than one. for a gain of one and the internal reference (2.5v), the equation becomes: v fs C 6.5 < v os < v fs C 3.5 with a 5v positive full-scale input, v os must be greater than C1.5v and less than 1.5v. since the offset represents a common-mode voltage and the input voltage range in a gain of one is 0v to 5v, a common-mode voltage will cause the actual input voltage to possibly go below 0v or above 5v. the specifications also show that for the specifications to be valid, the input voltage must not go below agnd by more than 30mv or above av dd by more than 30mv. this will be an important consideration in many systems which use a 2.5v or greater reference, as the input range is constrained by the expected power supply variations. in addition, the expected full-scale voltage will impact the allowable offset voltage (and vice-versa) as the combination of the two must remain within the power supply and ground potentials, regardless of the results obtained via the range calculation shown previously. there are only two solutions to this constraint: either the system design must ensure that the full-scale and offset voltage variations will remain within the power supply and ground potentials, or the part must be used in a gain of 2 or greater. sleep mode the sleep mode is entered after the bits 110 have been written to the command register operation mode bits (md2 through md0). this mode is exited by entering a new mode into the md2-md0 bits. the sleep mode causes the analog section and a good deal of the digital section to power down. for full analog power down, the v bias generator and the internal reference must also be powered down by setting the bias and refo bits in the command register accordingly. the power dissipa- tion shown in the specifications table is with the internal reference and the v bias generator disabled. to establish serial communication with the converter while it is in sleep mode, one of the following procedures must be used: if cs is being used, simply taking cs low will enable serial communication to proceed normally. if cs is not being used (tied low) and the ads1212/13 is in the master mode, then a falling edge must be produced on the sdio line. if sdio is low, the sdio line must be taken high for 4 ? t xin periods (minimum) and then taken low. alternatively, sdio can be forced high after putting the ads1212/13 to sleep and then taken low when the sleep mode is to be exited. finally, if cs is not being used (tied low) and the ads1212/13 is in the slave mode, then simply sending a normal instruction register command will re-establish communication. once serial communication is resumed, the sleep mode is exited by changing the md2-md0 bits to any other mode. when a new mode (other than sleep) has been entered, the ads1212/13 will execute a very brief internal power-up sequence of the analog and digital circuitry. once this has been done, one normal conversion cycle is performed before the new mode is actually entered. at the end of this conversion cycle, the new mode takes effect and the converter will respond accordingly. the drdy signal will remain high through the first conversion cycle. it will also remain high through the second, even if the new mode is the normal mode. if the v bias generator and/or the internal reference have been disabled, then they must be manually re-enabled via the appropriate bits in the command register. in addition, the internal reference will have to charge the external bypass capacitor(s) and possibly other circuitry. there may also be
17 ads1212, 1213 considerations associated with v bias and the settling of external circuitry. all of these must be taken into account when determining the amount of time required to resume normal operation. the timing diagram shown in figure 10 does not take into account the settling of external circuitry. figure 10. sleep mode to normal mode timing. drdy serial i/o note: (1) assuming that the external circuitry has been stable for the previous three t data periods. t data one normal conversion (other modes start here) data not valid valid data (1) valid data (1) sleep mode change to normal mode occurs here analog operation analog input the input impedance of the analog input changes with ads1212/13 clock frequency (f xin ), gain (g), and turbo mode rate (tmr). the relationship is: a in impedance ( w ) = (1mhz/f xin )?20e6/(g?tmr) figure 11 shows the basic input structure of the ads1212. the ads1213 includes an input multiplexer, but this has little impact on the analysis of the input structure. the impedance is directly related to the sampling frequency of the input capacitor. the x in clock rate sets the basic sam- pling rate in a gain of 1 and turbo mode rate of 1. higher gains and higher turbo mode rates result in an increase of the sampling rate, while slower clock (x in ) frequencies result in a decrease. figure 11. analog input structure. this input impedance can become a major point of consid- eration in some designs. if the source impedance of the input signal is significant or if there is passive filtering prior to the ads1212/13, then a significant portion of the signal can be lost across this external impedance. how significant this effect is depends on the desired system performance. there are two restrictions on the analog input signal to the ads1212/13. under no conditions should the current into or out of the analog inputs exceed 10ma. in addition, while the analog signal must reside within this range, the linearity of the ads1212/13 is only guaranteed when the actual analog input voltage resides within a range defined by agnd C30mv and av dd +30mv. this is due to leakage paths which occur within the part when agnd and av dd are exceeded. for this reason, the 0v to 5v input range (gain of 1 with a 2.5v reference) must be used with caution. should av dd be 4.75v, the analog input signal would swing outside of the guaranteed specifications of the device. designs utilizing this mode of operation should consider limiting the span to a slightly smaller range. common-mode voltages are also a significant concern in this mode and must be carefully analyzed. an input voltage range of 0.75v to 4.25v is the smallest span that is allowed if a full system calibration will be performed (see the calibration section for more details). this also assumes an offset error of zero. a better choice would be 0.5v to 4.5v (a full-scale range of 9v). this span would allow some offset error, gain error, power supply drift, and common-mode voltage while still providing full system calibration over reasonable variation in each of these parameters. the actual input voltage exceeding agnd or av dd should not be a concern in higher gain settings as the input voltage range will reside well within 0v to 5v. this is true unless the common-mode voltage is large enough to place positive full- scale or negative full-scale outside of the agnd to av dd range. reference input the input impedance of the ref in input changes with clock frequency (f xin ) and turbo mode rate (tmr). the relationship is: ref in impedance ( w ) = (1mhz/f xin )?5e6/tmr unlike the analog input, the reference input impedance has a negligible dependency on the pga gain setting. the reference input voltage can vary between 2v and 3v. a nominal voltage of 2.5v appears at ref out , and this can be directly connected to ref in . higher reference voltages will cause the full-scale range to increase while the internal circuit noise of the converter remains approximately the same. this will increase the lsb weight but not the internal noise, resulting in increased signal-to-noise ratio and effec- tive resolution. likewise, lower reference voltages will de- crease the signal-to-noise ratio and effective resolution. reference output the ads1212/13 contains an internal +2.5v reference. tolerances, drift, noise, and other specifications for this reference are given in the specification table. note that it is not designed to sink or to source more than 1ma of current. in addition, loading the reference with a dynamic or variable load is not recommended. this can result in small changes in reference voltage as the load changes. finally, for designs approaching or exceeding 20 bits of effective resolution, a low-noise external reference is recommended as the internal reference may not have adequate performance. r sw (8k w typical) switching frequency = f samp high impedance > 1g w c int 5pf typical v cm a in
18 ads1212, 1213 ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd xtal c 1 6pf dv dd gnd dgnd dgnd dgnd r 1 3k w r 2 3k w r 4 1k w r 3 1k w c 2 6pf ?0v ?0v av dd agnd dv dd 1.0? figure 12. 10v input configuration using v bias . the circuitry which generates the +2.5v reference can be disabled via the command register and will result in a lower power dissipation. the reference circuitry consumes a little over 1.6ma of current with no external load. when the ads1212/13 is in its default state, the internal reference is enabled. v bias the v bias output voltage is dependent on the reference input (ref in ) voltage and is approximately 1.33 times as great. this output is used to bias input signals such that bipolar signals with spans of greater than 5v can be scaled to match the input range of the ads1212/13. figure 12 shows a connection diagram which will allow the ads1212/13 to accept a 10v input signal (40v full-scale range). this method of scaling and offsetting the 20v differential input signal will be a concern for those requiring minimum power dissipation. v bias will supply 1.68ma for every chan- nel connected as shown. for the ads1213, the current draw is within the specifications for v bias , but, at 12mw, the power dissipation is significant. if this is a concern, resistors r 1 and r 2 can be set to 9k w and r 3 and r 4 to 3k w . this will reduce power dissipation by one-third. in addition, these resistors can also be set to values which will provide any arbitrary input range. in all cases, the maximum current into or out of v bias should not exceed its specification of 10ma. note that the connection diagram shown in figure 12 causes a constant amount of current to be sourced by v bias . this will be very important in higher resolution designs as the voltage at v bias will not change with loading, as the load is constant. however, if the input signal is single-ended and one side of the input is grounded, the load will not be constant and v bias will change slightly with the input signal. also, in all cases, note that noise on v bias introduces a common-mode error signal which is rejected by the converter. the circuitry to generate v bias is disabled when the ads1212/13 is in its default state, and it must be enabled, via the command register, in order for the v bias voltage to be present. when enabled, the v bias circuitry consumes approximately 1ma with no external load. on power-up, external signals may be present before v bias is enabled. this can create a situation in which a negative voltage is applied to the analog inputs (C2.5v for the circuit shown in figure 12), reverse biasing the negative input protection diode. this situation should not be a problem as long as the resistors r 1 and r 2 limit the current being sourced by each analog input to under 10ma (a potential of 0v at the analog input pin should be used in the calculation). digital operation system configuration the micro controller (mc) consists of an alu and a register bank. the mc has two states: power-on reset and convert. in the power-on reset state, the mc resets all the registers to their default state, sets up the modulator to a stable state, and performs self-calibration at a 340hz data rate. after this, it enters the convert mode, which is the normal mode of operation for the ads1212/13. the ads1212/13 has 5 internal registers, as shown in table vii. two of these, the instruction register and the com- mand register, control the operation of the converter. the data output register (dor) contains the result from the most recent conversion. the offset and full-scale calibra- tion registers (ocr and fcr) contain data used for correct- ing the internal conversion result before it is placed into the dor. the data in these two registers may be the result of a calibration routine, or they may be values which have been written directly via the serial interface. table vii. ads1212/13 registers. insr instruction register 8 bits dor data output register 24 bits cmr command register 32 bits ocr offset calibration register 24 bits fcr full-scale calibration register 24 bits communication with the ads1212/13 is controlled via the instruction register (insr). under normal operation, the insr is written as the first part of each serial communication. the instruction that is sent determines what type of communication will occur next. it is not possible to read the insr.
19 ads1212, 1213 the command register (cmr) controls all of the ads1212/ 13s options and operating modes. these include the pga gain setting, the turbo mode rate, the output data rate (decimation ratio), etc. the cmr is the only 32-bit register within the ads1212/13. it, and all the remaining registers, may be read from or written to. instruction register (insr) the insr is an 8-bit register which commands the serial interface either to read or to write n bytes beginning at the specified register location. table viii shows the format for the insr. each serial communication starts with the 8-bits of the insr being sent to the ads1212/13. this directs the remainder of the communication cycle, which consists of n bytes being read from or written to the ads1212/13. the read/write bit, the number of bytes n, and the starting register address are defined, as shown in table viii. when the n bytes have been transferred, the insr is complete. a new communication cycle is initiated by sending a new insr (under restrictions outlined in the interfacing section). command register (cmr) the cmr controls all of the functionality of the ads1212/ 13. the new configuration takes effect on the negative transition of sclk for the last bit in each byte of data being written to the command register. the organization of the cmr is shown in table x. the internal reference circuitry consumes approximately 1.6ma of steady state current with no external load. see the reference output section for full details on the internal reference. table viii. instruction register. r/w (read/write) bit for a write operation to occur, this bit of the insr must be 0. for a read, this bit must be 1, as follows: mb1, mb0 (multiple bytes) bits these two bits are used to control the word length (number of bytes) of the read or write operation, as follows: a3-a0 (address) bits these four bits select the begin- ning register location which will be read from or written to, as shown in table ix. each subsequent byte will be read from or written to the next higher location. (if the bd bit in the command register is set, each subsequent byte will be read from the next lower location. this bit does not affect the write operation.) if the next location is not defined in table ix, then the results are unknown. reading or writing contin- ues until the number of bytes specified by mb1 and mb0 have been transferred. a3 a2 a1 a0 register byte 0000 data output register byte 2 (msb) 0001 data output register byte 1 0010 data output register byte 0 (lsb) 0100 command register byte 3 (msb) 0101 command register byte 2 0110 command register byte 1 0111 command register byte 0 (lsb) 1000 offset cal register byte 2 (msb) 1001 offset cal register byte 1 1010 offset cal register byte 0 (lsb) 1100 full-scale cal register byte 2 (msb) 1101 full-scale cal register byte 1 1110 full-scale cal register byte 0 (lsb) note: msb = most significant byte, lsb = least significant byte r/w 0 write 1 read mb1 mb0 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes table ix. a3-a0 addressing. msb lsb r/w mb1 mb0 0 a3 a2 a1 a0 the v bias circuitry consumes approximately 1ma of steady state current with no external load. see the v bias section for full details. when the internal reference (ref out ) is con- nected to the reference input (ref in ), v bias is 3.3v, nominal. refo (reference output) bit the refo bit controls the internal reference (ref out ) state, either on (2.5v) or off (disabled), as follows: refo internal reference ref out status 0 off high impedance 1 on 2.5v default bias (bias voltage) bit the bias bit controls the v bias output stateeither on (1.33 ? ref in ) or off (disabled), as follows: bias v bias generator v bias status 0 off disabled default 1 on 1.33?ref in most significant bit byte 3 dsync (1) bias refo df u/b bd msb sdl drdy 0 off 1 on 0 twos 0 biplr 0 msbyte 0 msb 0 sdio 0 defaults note: (1) dsync is write only, drdy is read only. byte 2 md2 md1 md0 g2 g1 g0 ch1 ch0 000 normal mode 000 gain 1 00 channel 1 defaults byte 1 sf2 sf1 sf0 dr12 dr11 dr10 dr9 dr8 000 turbo mode rate of 1 00000 defaults byte 0 least significant bit dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 (00000) 0001 0111 (23) data rate of 326hz defaults table x. organization of the command register and default status.
20 ads1212, 1213 df (data format) bit the df bit controls the format of the output data, either twos complement or offset binary, as follows: df format analog input digital output 0 twos +full-scale 7fffff h default complement zero 000000 h Cfull scale 800000 h 1 offset binary +full-scale ffffff h zero 800000 h Cfull-scale 000000 h these two formats are the same for all bits except the most significant, which is simply inverted in one format vs the other. this bit only applies to the data output registerit has no effect on the other registers. u/b (unipolar) bit the u/b bit controls the limits im- posed on the output data, as follows: u/b mode limits 0 bipolar none default 1 unipolar zero to +full-scale only the particular mode has no effect on the actual full-scale range of the ads1212/13, data format, or data format vs input voltage. in the bipolar mode, the ads1212/13 oper- ates normally. in the unipolar mode, the conversion result is limited to positive values only (zero included). this bit only controls what is placed in the data output register. it has no effect on internal data. when cleared, the very next conversion will produce a valid bipolar result. bd (byte order) bit the bd bit controls the order in which bytes of data are read, either most significant byte first or least significant byte, as follows: sdl (serial data line) bit the sdl bit controls which pin on the ads1212/13 will be used as the serial data output pin, either sdio or sdout, as follows: bd byte access order 0 most significant default to least significant byte 1 least significant to most significant byte note that when bd is clear and a multi-byte read is initiated, a3-a0 of the instruction register is the address of the most significant byte and subsequent bytes reside at higher ad- dresses. if bd is set, then a3-a0 is the address of the least significant byte and subsequent bytes reside at lower ad- dresses. the bd bit only affects read operations, it has no affect on write operations. msb (bit order) bit the msb bit controls the order in which bits within a byte of data are read, either most significant bit first or least significant bit, as follows: msb bit order 0 most significant bit first default 1 least significant bit first the msb bit only affects read operations, it has no affect on write operations. sdl serial data output pin 0 sdio default 1 sdout if sdl is low, then sdio will be used for both input and output of serial datasee the timing section for more details on how the sdio pin transitions between these two states. in addition, sdout will remain in a tri-state condi- tion at all times. important note: since the default condition is sdl low, sdio has the potential of becoming an output once every data output cycle if the ads1212/13 is in the master mode. this will occur until the command register can be written and the sdl bit set high. see the interfacing section for more information. drdy (data ready) bit the drdy bit is a read only bit which reflects the state of the ads1212/13s drdy output pin, as follows: drdy meaning 0 data ready 1 data not ready dsync (data synchronization) bit the dsync bit is a write only bit which occupies the same location as drdy. when a one is written to this location, the affect on the ads1212/13 is the same as if the dsync input pin had been taken low and returned high. that is, the modulator count for the current conversion cycle will be reset to zero. the dsync bit is provided in order to reduce the number of interface signals that are needed between the ads1212/13 and the main controller. consult making use of dsync in the serial interface section for more information. md2-md0 (operating mode) bits the md2-md0 bits initiate or enable the various calibration sequences, as follows: dsync meaning 0 no change in modulator count 1 modulator count reset to zero md2 md1 md0 operating mode 0 0 0 normal mode 0 0 1 self-calibration 0 1 0 system offset calibration 0 1 1 system full-scale calibration 1 0 0 pseudo system calibration 1 0 1 background calibration 1 1 0 sleep 1 1 1 reserved the normal mode, background calibration mode, and sleep mode are permanent modes and the ads1212/13 will remain in these modes indefinitely. all other modes are temporary and will revert to normal mode once the appro- priate actions are complete. see the calibration and sleep mode sections for more information.
21 ads1212, 1213 table xi. decimation ratios for various data rates (turbo mode rate of 1 and 1mhz clock). ch1 ch0 active input 0 0 channel 1 default 0 1 channel 2 1 0 channel 3 1 1 channel 4 turbo available mode pga sf2 sf1 sf0 rate settings 0 0 0 1 1, 2, 4, 8, 16 default 0 0 1 2 1, 2, 4, 8 0 1 0 4 1, 2, 4 0118 1, 2 10016 1 most significant bit byte 2 dor23 dor22 dor21 dor20 dor19 dor18 dor17 dor16 byte 1 dor15 dor14 dor13 dor12 dor11 dor10 dor9 dor8 byte 0 least significant bit dor7 dor6 dor5 dor4 dor3 dor2 dor1 dor0 table xii. data output register. g2-g0 (pga control) bits the g2-g0 bits control the gain setting of the pga, as follows: gain available turbo g2 g1 g0 setting mode rates 0 0 0 1 1, 2, 4, 8, 16 default 0 0 1 2 1, 2, 4, 8 0 1 0 4 1, 2, 4 0 1 1 8 1, 2 100 16 1 the gain is partially implemented by increasing the input capacitor sampling frequency, which is given by the follow- ing equation: f samp = g ? tmr ? f xin / 128 where g is the gain setting and tmr is the turbo mode rate. the product of g and tmr cannot exceed 16. the sampling frequency of the input capacitor directly relates to the analog input impedance. see the programmable gain amplifier and analog input sections for more details. ch1-ch0 (channel selection) bits the ch1 and ch0 bits control the input multiplexer on the ads1213, as follows: (for the ads1212, ch1 and ch0 must always be zero.) the channel change takes effect when the last bit of byte 2 has been written to the command register. output data will not be valid for the next three conversions despite the drdy signal indicating that data is ready. on the fourth time that drdy goes low after a channel change has been written to the command register, valid data will be present in the data output register (see figure 4). sf2-sf0 (turbo mode rate) bits the sf2-sf0 bits control the input capacitor sampling frequency and modula- tor rate, as follows: the input capacitor sampling frequency and modulator rate can be calculated from the following equations: f samp = g ? tmr ? f xin / 128 f mod = tmr ? f xin / 128 where g is the gain setting and tmr is the turbo mode rate. the sampling frequency of the input capacitor directly relates to the analog input impedance. the modulator rate relates to the power consumption of the ads1212/13 and the output data rate. see the turbo mode, analog input, and reference input sections for more details. dr12-dr0 (decimation ratio) bits the dr12-dr0 bits control the decimation ratio of the ads1212/13. in essence, these bits set the number of modulator results which are used in the digital filter to compute each individual conversion result. since the modulator rate depends on both the ads1212/13 clock frequency and the turbo mode rate, the actual output data rate is given by the following equation: f data = f xin ? tmr / (128 ? (decimation ratio + 1)) where tmr is the turbo mode rate. table xi shows various data rates and corresponding decimation ratios (with a 1mhz clock). valid decimation ratios are from 19 to 8000. outside of this range, the digital filter will compute results incorrectly due to inadequate or too much data. data output register (dor) the dor is a 24-bit register which contains the most recent conversion result (see table xii). this register is updated with a new result just prior to drdy going low. if the contents of the dor are not read within a period of time defined by 1/f data C24?(1/f xin ), then a new conversion result will overwrite the old. (drdy is forced high prior to the dor update, unless a read is in progress). the contents of the dor can be in twos complement or offset binary format. this is controlled by the df bit of the command register. in addition, the contents can be limited to unipolar data only with the u/b bit of the command register. data deci- rate mation (hz) ratio dr12 dr11 dr10 dr9 dr8 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 391190000000010011 250300000000011110 100770000001001101 601290000010000001 501550000010011011 203900000110000110 107800001100001100 0.96 8000 1 1 1 1 1 0 1 0 0 0 0 0 0
22 ads1212, 1213 t 4 t 5 t 6 t 8 t 7 t 9 sclk (internal) sdio (as input) sdout (or sdlo as output) offset calibration register (ocr) the ocr is a 24-bit register which contains the offset correction factor that is applied to the conversion result before it is placed in the data output register (see table xiii). in most applications, the contents of this register will be the result of either a self-calibration or a system calibration. the ocr is both readable and writeable via the serial interface. for applications requiring a more accurate offset calibration, multiple calibrations can be performed, each resulting ocr value read, the results averaged, and a more precise offset calibration value written back to the ocr. the actual ocr value will change from part-to-part and with configuration, temperature, and power supply. thus, the actual ocr value for any arbitrary situation cannot be accurately predicted. that is, a given system offset could not be corrected simply by measuring the error externally, com- puting a correction factor, and writing that value to the ocr. in addition, be aware that the contents of the ocr are not used to directly correct the conversion result. rather, the correction is a function of the ocr value. this function is linear and two known points can be used as a basis for interpolating intermediate values for the ocr. consult the calibration section for more details. most significant bit byte 2 ocr23 ocr22 ocr21 ocr20 ocr19 ocr18 ocr17 ocr16 byte 1 ocr15 ocr14 ocr13 ocr12 ocr11 ocr10 ocr9 ocr8 byte 0 least significant bit ocr7 ocr6 ocr5 ocr4 ocr3 ocr2 ocr1 ocr0 table xiii. offset calibration register. the contents of the ocr are in twos complement format. this is not affected by the df bit in the command register. full-scale calibration register (fcr) the fcr is a 24-bit register which contains the full-scale correction factor that is applied to the conversion result before it is placed in the data output register (see table xiv). in most applications, the contents of this register will be the result of either a self-calibration or a system calibration. table xiv. full-scale calibration register. most significant bit byte 2 fsr23 fsr22 fsr21 fsr20 fsr19 fsr18 fsr17 fsr16 byte 1 fsr15 fsr14 fsr13 fsr12 fsr11 fsr10 fsr9 fsr8 byte 0 least significant bit fsr7 fsr6 fsr5 fsr4 fsr3 fsr2 fsr1 fsr0 the fcr is both readable and writable via the serial inter- face. for applications requiring a more accurate full-scale calibration, multiple calibrations can be performed, each resulting fcr value read, the results averaged, and a more precise calibration value written back to the fcr. the actual fcr value will change from part-to-part and with configuration, temperature, and power supply. thus, the actual fcr value for any arbitrary situation cannot be accurately predicted. that is, a given system full-scale error cannot be corrected simply by measuring the error exter- nally, computing a correction factor, and writing that value to the fcr. in addition, be aware that the contents of the fcr are not used to directly correct the conversion result. rather, the correction is a function of the fcr value. this function is linear and two known points can be used as a basis for interpolating intermediate values for the fcr. consult the calibration section for more details. the con- tents of the fcr are in unsigned binary format. this is not affected by the df bit in the command register. timing table xv and figures 13 through 21 define the basic digital timing characteristics of the ads1212/13. figure 13 and the associated timing symbols apply to the x in input signal. figures 14 through 20 and associated timing symbols apply to the serial interface signals (sclk, sdio, sdout, and cs) and their relationship to drdy. the serial interface is discussed in detail in the serial interface section. figure 21 and the associated timing symbols apply to the maximum drdy rise and fall times. figure 13. x in clock timing. t xin t 2 x in t 3 figure 14. serial input/output timing, master mode. figure 15. serial input/output timing, slave mode. t 10 t 11 t 12 t 14 t 13 t 15 sclk (external) sdio (as input) sdout (or sdlo as output)
23 ads1212, 1213 symbol description min nom max units f xin x in clock frequency 0.5 1 2.5 mhz t xin x in clock period 400 2000 ns t 2 x in clock high 0.4 ? t xin ns t 3 x in clock low 0.4 ? t xin ns t 4 internal serial clock high 2 ? t xin ns t 5 internal serial clock low 2 ? t xin ns t 6 data in valid to internal sclk falling edge (setup) 40 ns t 7 internal sclk falling edge to data in not valid (hold) 20 ns t 8 data out valid to internal sclk falling edge (setup) 2 ? t xin C25 ns t 9 internal sclk falling edge to data out not valid (hold) 2 ? t xin ns t 10 external serial clock high 5 ? t xin ns t 11 external serial clock low 5 ? t xin ns t 12 data in valid to external sclk falling edge (setup) 40 ns t 13 external sclk falling edge to data in not valid (hold) 20 ns t 14 data out valid to external sclk falling edge (setup) t xin C40 ns t 15 external sclk falling edge to data out not valid (hold) 4 ? t xin ns t 16 falling edge of drdy to first sclk rising edge 12 ? t xin ns (mode, cs tied low) t 17 falling edge of last sclk for insr to rising edge of first 10 ? t xin ns sclk for register data (master mode) t 18 falling edge of last sclk for register data to rising edge 6 ? t xin ns of drdy (master mode) t 19 falling edge of last sclk for insr to rising edge of first 13 ? t xin ns sclk for register data (slave mode) ns t 20 falling edge of last sclk for register data to rising edge 8 ? t xin 10 ? t xin ns of drdy (slave mode) t 21 falling edge of drdy to falling edge of cs (master and 3 ? t xin ns slave mode) t 22 falling edge of cs to rising edge of sclk (master mode) 10 ? t xin 12 ? t xin ns t 23 rising edge of drdy to rising edge of cs (master and 2 ? t xin ns slave mode) t 24 falling edge of cs to rising edge of sclk (slave mode) 11 ? t xin ns t 25 falling edge of last sclk for insr to sdio tri-state 4 ? t xin ns (master mode) t 26 sdio as output to rising edge of first sclk for register 4 ? t xin ns data (master and slave modes) t 27 falling edge of last sclk for insr to sdio tri-state 6 ? t xin 8 ? t xin ns (slave mode) t 28 sdio tri-state time (master and slave modes) 2 ? t xin ns t 29 falling edge of last sclk for register data to sdio tri-state 2 ? t xin ns (master mode) t 30 falling edge of last sclk for register data to sdio 4 ? t xin 6 ? t xin ns tri-state (slave mode) t 31 drdy fall time 30 ns t 32 drdy rise time 30 ns t 33 minimum dsync low time 21 ? t xin ns t 34 dsync valid high to falling edge of x in (for exact 10 ns synchronization of multiple converters only) t 35 falling edge of x in to dsync not valid low (for exact 10 ns synchronization of multiple converters only) t 36 falling edge of last sclk for register data to rising edge 41 ? t xin ns of first sclk of next insr (slave mode, cs tied low) t 37 rising edge of cs to falling edge of cs (slave mode, 22 ? t xin ns using cs) t 38 falling edge of drdy to first sclk 11 ? t xin ns rising edge (slave mode, cs tied low) table xv. digital timing characteristics.
24 ads1212, 1213 t 16 t 17 t 18 in7 in1 in0 inm in1 in0 in7 in1 in0 outm out1 out0 write register data outm out1 out0 in7 in1 in0 read register data using sdio read register data using sdout drdy sclk sdio sdio sdio sdout figure 17. serial interface timing (cs low), slave mode. figure 16. serial interface timing (cs low), master mode. t 21 drdy cs sclk sdio t 23 in0 in1 in0 in1 in7 inm t 22 t 17 write register data t 18 sdio out0 out1 in0 in1 in7 outm read register data using sdio sdio in0 in1 in7 sdout out0 out1 outm read register data using sdout drdy cs sclk sdio out0 out1 outm continuous read of data output register using sdio continuous read of data output register using sdout t 18 t 16 sdout out0 out1 outm figure 18. serial interface timing (using cs), master mode. t 20 t 36 t 38 t 19 in7 in0 in1 inm in1 in0 in7 write register data out0 out1 outm read register data using sdout in7 in7 out0 out1 outm in1 in0 in7 in1 in0 in7 read register data using sdio drdy sclk sdio sdio sdio sdout
25 ads1212, 1213 figure 19. serial interface timing (using cs), slave mode. t 21 drdy cs sclk sdio t 37 t 23 t 24 in7 in0 in1 in0 in1 in7 inm t 24 t 19 write register data t 20 sdio in7 out0 out1 in0 in1 in7 outm read register data using sdio sdio in7 in0 in1 in7 sdout out0 out1 outm read register data using sdout drdy cs sclk sdio out0 out1 outm continuous read of data output register using sdio continuous read of data output register using sdout t 20 t 16 sdout out0 out1 outm figure 20. sdio input to output transition timing. figure 21. drdy rise and fall time. t 31 t 32 drdy out m out0 out msb out0 t 26 t 16 t 22 t 24 t 38 t 19 sdio is an input sdio is an output t 28 t 21 in7 in7 in6 t 23 t 18 t 29 t 20 t 30 t 27 t 17 t 25 t 26 in5 in2 in1 in0 in0 drdy cs (1) sdio sclk sclk sdio master mode slave mode note: (1) cs is optional.
26 ads1212, 1213 synchronizing multiple converters a negative going pulse on dsync can be used to synchro- nize multiple ads1212/13s. this assumes that each ads1212 is driven from the same master clock and is set to the same decimation ratio and turbo mode rate. the affect that this signal has on data output timing in general is discussed in the serial interface section. the concern here is what happens if the dsync input is completely asynchronous to this master clock. if the dsync input rises at a critical point in relation to the master clock input, then some ads1212/13s may start-up one x in clock cycle before the others. thus, the output data will be syn- chronized, but only to within one x in clock cycle. for many applications, this will be more than adequate. in these cases, the timing symbols which relate the dsync signal to the x in signal can be ignored. for other multiple- converter applications, this one x in clock cycle difference could be a problem. these types of applications would include using the drdy and/or the sclk output from one ads1212/13 as the master signal for all converters. to ensure exact synchronization to the same x in edge, the timing relationship between the dsync and x in signals, as shown in figure 22, must be observed. figure 23 shows a simple circuit which can be used to clock multiple ads1212/13s from one ads1212/13, as well as to ensure that an asynchronous dsync signal will exactly synchro- nize all the converters. figure 22. dsync to x in timing for synchronizing mutliple ads1212/13s. serial interface the ads1212/13 includes a flexible serial interface which can be connected to microcontrollers and digital signal processors in a variety of ways. along with this flexibility, there is also a good deal of complexity. this section de- scribes the trade-offs between the different types of interfac- ing methods in a top-down approachstarting with the overall flow and control of serial data, moving to specific interface examples, and then providing information on vari- ous issues related to the serial interface. multiple instructions the general timing diagrams which appear throughout this data sheet show serial communication to and from the ads1212/13 occurring during the drdy low period (see figures 4 through 10 and figure 36). this communication represents one instruction that is executed by the ads1212/ 13, resulting in a single read or write of register data. however, more than one instruction can be executed by the ads1212/13 during any given conversion period (see fig- ure 24). note that drdy remains high during the subse- quent instructions. there are several important restrictions on how and when multiple instructions can be issued during any one conversion period. drdy serial i/o 24 ?t xin internal update of dor figure 24. timing of data output register update. the first restriction is that the converter must be in the slave mode. there is no provision for multiple instructions when the ads1212/13 is operating in the master mode. the second is that some instructions will produce invalid results if started at the end of one conversion period and carried into the start of the next conversion period. figure 23. exactly synchronizing multiple ads1212/13s to an asynchronous dsync signal. c 2 6pf c 1 6pf xtal dsync x in x out dgnd ads1212/13 sdout sdio sclk dv dd d clk 1/2 74hc74 1/6 74hc04 q q dsync x in x out dgnd ads1212/13 sdout sdio sclk dv dd dsync x in x out dgnd ads1212/13 sdout sdio sclk dv dd asynchronous dsync strobe dgnd t 33 t 34 t 35 x in dsync
27 ads1212, 1213 start writing ads1212/13 drives drdy low cs state ads1212/13 generates 8 serial clock cycles and receives instruction register data via sdio ads1212/13 generates n serial clock cycles and receives specified register data via sdio ads1212/13 drives drdy high end ads1212/13 generates 8 serial clock cycles and receives instruction register data via sdio ads1212/13 generates n serial clock cycles and transmits specified register data via sdout end start reading ads1212/13 drives drdy low cs state continuous read m ode ? ads1212/13 drives drdy high sdout returns to tri-state condition sdout becomes active from tri-state use sdio for output? l o w no yes low high n o yes ads1212/13 generates n serial clock cycles and transmits specified register data via sdio sdio transitions to tri-state condition sdio input to output transition high cs state l o w high for example, figure 24 shows that just prior to the drdy signal going low, the internal data output register (dor) is updated. this update involves the offset calibration register (ocr) and the full-scale register (fsr). if the ocr or fsr are being written, their final value may not be correct, and the result placed into the dor will certainly not be valid. problems can also arise if certain bits of the command register are being changed. note that reading the data output register is an excep- tion. if the dor is being read when the internal update is initiated, the update is blocked. the old output data will remain in the dor and the new data will be lost. the old data will remain valid until the read operation has com- pleted. in general, multiple instructions may be issued, but the last one in any conversion period should be complete within 24 ? x in clock periods of the next drdy low time. in this usage, complete refers to the point where drdy rises in figures 17 and 19 (in the timing section). consult figures 25 and 26 for the flow of serial data during any one conversion period. figure 25. flowchart for writing and reading register data, master mode.
28 ads1212, 1213 start writing ads1212/13 drives drdy low cs state external device generates 8 serial clock cycles and transmits instruction register data via sdio external device generates n serial clock cycles and transmits specified register data via sdio ads1212/13 drives drdy high end external device generates 8 serial clock cycles and receives instruction register data via sdio external device generates n serial clock cycles and receives specified register data via sdout end start reading ads1212/13 drives drdy low cs state continuous read m ode ? ads1212/13 drives drdy high sdout returns to tri-state condition sdout becomes active use sdio for output? low high no yes low n o yes external device generates n serial clock cycles and receives specified register data via sdio sdio transitions to tri-state condition sdio input to output transition more instructions? no yes is next instruction a r ead ? to read flowchart from read flowchart cs taken high for 22 t periods minimum (see text if cs tied low). cs state low high more instructions? no is next instruction a writ e ? to write flowchart yes see text for restrictions yes to write flowchart cs taken high for 22 t periods minimum (see text if cs tied low). cs state low high no see text for restrictions yes no high xin xin figure 26. flowchart for writing and reading register data, slave mode. transmits
29 ads1212, 1213 using cs and continuous read mode the serial interface may make use of the cs signal, or this input may simply be tied low. there are several issues associated with choosing to do one or the other. the cs signal does not directly control the tri-state condition of the sdout or sdio output. these signals are normally in the tri-state condition. they only become active when serial data is being transmitted from the ads1212/13. if the ads1212/13 is in the middle of a serial transfer and sdout or sdio is an output, taking cs high will not tri-state the output signal. if there are multiple serial peripherals utilizing the same serial i/o lines and communication may occur with any peripheral at any time, then the cs signal must be used. the ads1212/13 may be in the master mode or the slave mode. in the master mode, the cs signal is used to hold-off serial communication with a ready (drdy low) ads1212/13 until the main controller can accommodate the communica- tion. in the slave mode, the cs signal is used to enable communication with the ads1212/13. the cs input has another use. if the cs state is left low after a read of the data output register has been performed, then the next time that drdy goes low, the ads1212/13 instruction register will not be entered. instead, the instruc- tion register contents will be re-used, and the new contents of the data output register, or some part thereof, will be transmitted. this will occur as long as cs is low and not toggled. this mode of operation is called the continuous read mode and is shown in the read flowcharts of figures 25 and 26. it is also shown in the timing diagrams of figures 18 and 19 in the timing section. note that once cs has been taken high, the continuous read mode will be enabled (but not entered) and can never be disabled. the mode is actually entered and exited as described above. power-on conditions for sdio even if the sdio connection will be used only for input, there is one important item to consider regarding sdio. this only applies when the ads1212/13 is in the master mode and cs will be tied low. at power-up, the serial i/o lines of most microcontrollers and digital signal processors will be in a tri-state condition, or they will be configured as inputs. when power is applied to the ads1212/13, it will begin operating as defined by the default condition of the com- mand register (see table x in the system configuration section). this condition defines sdio as the data output pin. since the ads1212/13 is in the master mode and cs is tied low, the serial clock will run whenever drdy is low and an instruction will be entered and executed. if the sdio line is high, as it might be with an active pull-up, then the instruction is a read operation and sdio will become an output every drdy low periodfor 32 serial clock cycles. when the serial port on the main controller is enabled, signal contention could result. the recommended solution to this problem is to actively pull sdio low. if sdio is low when the ads1212/13 enters the instruction byte, then the resulting instruction is a write of one byte of data to the data output register, which results in no internal operation. if the sdio signal cannot be actively pulled low, then another possibility is to time the initialization of the controllers serial port such that it becomes active between adjacent drdy low periods. the default configuration for the ads1212/13 produces a data rate of 326hza conver- sion period of 2.9ms. this time should be more than ad- equate for most microcontrollers and dsps to monitor drdy and initialize the serial port at the appropriate time. master mode the master mode is active when the mode input is high. all serial clock cycles will be produced by the ads1212/13 in this mode, and the sclk pin is configured as an output. the frequency of the serial clock will be one-quarter of the x in frequency. multiple instructions cannot be issued during a single conversion period in this modeonly one instruc- tion per conversion cycle is possible. the master mode will be difficult for some microcontrollers, particularly when the x in input frequency is greater than 2mhz, as the serial clock may exceed the microcontrollers maximum serial clock frequency. for the majority of digital signal processors, this will be much less of a concern. in addition, if sdio is being used as an input and an output, then the transition time from input to output may be a concern. this will be true for both microcontrollers and dsps. see figure 20 in the timing section. note that if cs is tied low, there are special considerations regarding sdio as outlined previously in this section. also note that if cs is being used to control the flow of data from the ads1212/13 and it remains high for one or more conversion periods, the ads1212/13 will operate properly. however, the result in the data output register will be lost when it is overwritten by each new result. just prior to this update, drdy will be forced high and will return low after the update. slave mode most systems will use the ads1212/13 in the slave mode. this mode allows multiple instructions to be issued per conversion period as well as allowing the main controller to set the serial clock frequency and pace the serial data transfer. the ads1212/13 is in the slave mode when the mode input is low. there are several important items regarding the serial clock for this mode of operation. the maximum serial clock frequency cannot exceed the ads1212/13 x in frequency divided by 10 (see figure 15 in the timing section).
30 ads1212, 1213 reset, power-on reset and brown-out the ads1212/13 contains an internal power-on reset cir- cuit. if the power supply ramp rate is greater than 50mv/ms, this circuit will be adequate to ensure the device powers up correctly. (due to oscillator settling considerations, commu- nication to and from the ads1212/13 should not occur for at least 25ms after power is stable). if this requirement cannot be met or if the circuit has brown-out considerations, the timing diagram of figure 27 can be used to reset the ads1212/13. this timing applies only when the ads1212/13 is in the slave mode and accomplishes the reset by controlling the duty cycle of the sclk input. in general, reset is required after power-up, after a brown-out has been detected, or when a watchdog timer event has occured. if the ads1212/13 is in the master mode, a reset of the device is not possible. if the power supply does not meet the minimum ramp rate requirement or brown-out is of concern, low on-resistance mosfets or equivalent should be used to control power to the ads1212/13. when pow- ered down, the device should be left unpowered for at least 300ms before power is reapplied. an alternate method would be to control the mode pin and temporarily place the ads1212/13 in the slave mode while a reset is initiated as shown in figure 27. two-wire interface for a two-wire interface, the master mode of operation may be preferable. in this mode, serial communication occurs only when data is ready, informing the main controller as to the status of the ads1212/13. the disadvantages are that the ads1212/13 must have a dedicated serial port on the main controller and only one instruction can be issued per data ready period. in the slave mode, the main controller must read and write to the ads1212/13 blindly. writes to the internal regis- ters, such as the command register or offset calibration register, might occur during an update of the data output register. this can result in invalid data in the dor. a two- wire interface can be used if the main controller can read and/or write to the converter either much slower or much faster than the data rate. for example, if much faster, the main controller can use the drdy bit to determine when data is becoming valid (polling it multiple times during one conversion cycle). thus, the controller obtains some idea of when to write to the internal registers. if much slower, then reads of the dor might always return valid data (mulitple conversions have occurred since the last read of the dor or since any write of the internal registers). as with the master mode of operation, when using sdio as edge of the last serial clock cycle of the instruction byte, the sdio pin will begin its transition from input to output. between six and eight x in cycles after this falling edge, the sdio pin will become an output. this transition may be too fast for some microcontrollers and digital signal processors. if a serial communication does not occur during any conver- sion period, the ads1212/13 will continue to operate prop- erly. however, the results in the data output register will be lost when they are overwritten by the new result at the start of the next conversion period. just prior to this update, drdy will be forced high and will return low after the update. making use of dsync the dsync input pin and the dsync write bit in the command register reset the current modulator count to zero. this causes the current conversion cycle to proceed as normal, but all modulator outputs from the last data output to the point where dsync is asserted are discarded. note that the previous two data outputs are still present in the ads1212/13 internal memory. both will be used to com- pute the next conversion result, and the most recent one will be used to compute the result two conversions later. dsync does not reset the internal data to zero. there are two main uses of dsync. in the first case, dsync allows for synchronization of multiple converters. in regards to the dsync input pin, this case was discussed under synchronizing multiple converters in the timing section. in regards to the dsync bit, it will be difficult to set all of the converters dsync bits at the same time unless all of the converters are in the slave mode and the same instruction can be sent to all of the converters at the same time. the second use of dsync is to reset the modulator count to zero in order to obtain valid data as quickly as possible. for example, if the input channel is changed on the ads1213, the current conversion cycle will be a mix of the old channel and the new channels. thus, four conversions are needed in order to ensure valid data. however, if the channel is changed and then dsync is used to reset the modulator count, the modulator data at the end of the current conver- sion cycle will be entirely from the new channel. after two additional conversion cycles, the output data will be com- pletely valid. note that the conversion cycle in which dsync is used will be slightly longer than normal. its length will depend on when dsync was set. figure 27. resetting the ads1212/13 (slave mode only). t 1 : > 512 ? t xin < 800 ? t xin t 2 : > 10 ? t xin t 3 : > 1024 ? t xin < 1800 ? t xin t 4 : 3 2048 ? t xin < 2400 ? t xin t 2 t 3 t 1 t 3 t 4 t 2 t 2 sclk reset occurs at 2048 ?t xin
31 ads1212, 1213 figure 28. three-wire interface with a 8xc32 microprocessor. figure 29. three-wire interface with a 8xc51 microprocessor. three-wire interface figure 28 shows a three-wire interface with a 8xc32 micro- processor. note that the slave mode is selected and the sdio pin is being used for input and output. figure 29 shows a different type of three-wire interface with an 8xc51 microprocessor. here, the master mode is used. the interface signals consist of sdout, sdio, and sclk. ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 reset rxd txd int0 int1 t0 t1 wr rd x2 x1 v ss 8xc32 c 2 27pf c 1 27pf r 1 10k w dv dd agnd dgnd dgnd av dd dv dd d clk q q d clk q q 1/2 74hc74 1/2 74hc74 xtal agnd 1.0? ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 v cc p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 8xc51 c 1 6pf (1) c 2 6pf (1) dv dd agnd dgnd dgnd av dd dv dd xtal agnd 1.0? r 1 10k w note: (1) acceptable capacitive load not to exceed 6pf (?0%).
32 ads1212, 1213 four-wire interface figure 30 shows a four-wire interface with a 8xc32 micro- processor. again, the slave mode is being used. multi-wire interface figures 31 and 32 show multi-wire interfaces with a 8xc51 or 68hc11 microprocessor. in these interfaces, the mode of the ads1212/13 is actually controlled dynamically. this could be extremely useful when the ads1212/13 is to be used in a wide variety of ways. for example, it might be desirable to have the ads1212/13 produce data at a steady rate and to have the converter operating in the continuous read mode. but for system calibration, the slave mode might be preferred because multiple instructions can be issued per conversion period. note that the mode input should not be changed in the middle of a serial transfer. this could result in misoperation of the device. a master/slave mode change will not affect the output data. note that the x in input can also be controlled. it is possible with some microcontrollers and digital signal processors to produce a continuous serial clock, which could be connected to the x in input. the frequency of the clock is often settable over some range. thus, the power dissipation of the ads1212/13 could be dynamically varied by changing both the turbo mode and x in input-trading off conversion speed and resolution for power consumption. i/o recovery if serial communication stops during an instruction or data transfer for longer than 4 ? t data , the ads1212/13 will reset its serial interface. this will not affect the internal registers. the main controller must not continue the transfer after this event, but must re-start the transfer from the beginning. this feature is very useful if the main controller can be reset at any point. after reset, simply wait 8 ? t data before starting serial communication. figure 31. full interface with a 8xc51 microprocessor. ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 v cc p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 8xc51 c 2 6pf c 1 6pf xtal agnd dgnd av dd dv dd dgnd agnd 1.0? r 2 10k w r 1 10k w figure 30. four-wire interface with a 8xc32 microprocessor. dgnd ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 reset rxd txd int0 int1 wr rd x2 x1 v ss 8xc32 c 2 27pf c 1 27pf dv dd agnd dgnd av dd dv dd d clk q q d clk q q 1/2 74hc74 1/2 74hc74 xtal agnd 1.0? r 1 10k w
33 ads1212, 1213 figure 32. full interface with a 68hc11 microprocessor. isolation the serial interface of the ads1212/13 provides for simple isolation methods. an example of an isolated four-wire interface is shown in figure 33. the iso150 is used to transmit the digital signals over the isolation barrier. in addition, the digital outputs of the ads1212/13 can, in some cases, drive opto-isolators directly. figures 34 and 35 show the voltage of the sdout pin versus source or sink current under worst case conditions. worst-case conditions for source current occur when the analog input differential figure 33. isolated four-wire interface. ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pe0 pe1 pe2 xirq reset pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 xtal 68hc11 c 2 6pf c 1 6pf agnd dgnd av dd dv dd xtal agnd 1.0? r 2 10k w r 1 10k w ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd xtal c 2 6pf c 1 6pf v dd1 agnd dgnd dgnd av dd v dd1 iso150 d 1a r/t 1a v sa g b r/t 1b d 1b d 2a r/t 2a g a v sb r/t 2b d 2b v dd2 v dd1 v dd1 v dd2 r 1 100 w dgnd gnd dgnd gnd sclk sd in v dd2 v dd1 v dd2 dgnd dgnd gnd sd out drdy iso150 d 1a r/t 1a v sa g b r/t 1b d 1b d 2a r/t 2a g a v sb r/t 2b d 2b agnd 1.0?
34 ads1212, 1213 ads1213u, p a in 3n a in 2p a in 2n a in 1p a in 1n agnd v bias cs dsync x in x out dgnd a in 3p a in 4n a in 4p ref in ref out av dd mode drdy sdout sdio sclk dv dd av dd +5v +5v v ol 0v v ol +5v r 1 49.9k w c 2 6pf c 1 6pf dgnd xtal dgnd ref1004 +2.5v 0v +5v p1 2k w 1.0? +5v ads1213u, p a in 3n a in 2p a in 2n a in 1p a in 1n agnd v bias cs dsync x in x out dgnd a in 3p a in 4n a in 4p ref in ref out av dd mode drdy sdout sdio sclk dv dd 1.0? av dd +5v +5v +5v 0v +5v r 1 49.9k w c 2 6pf c 1 6pf xtal dgnd dgnd ref1004 +2.5v +5v +5v v oh v oh p1 2k w drdy a drdy b drdy c dsync t data t data t data t data voltage is 5v and the output format is offset binary (ffffff h ). for sink current, the worst-case condition oc- curs when the analog input differential voltage is 0v and the output format is twos complement (000000 h ). note that sdout is tri-stated for the majority of the conversion period and the opto-isolator connection must take this into account. synchronization of multiple converters the dsync input is used to synchronize the output data of multiple ads1212/13s. synchronization involves configur- ing each ads1212/13 to the same decimation ratio and turbo mode setting, and providing a common signal to the x in inputs. then, the dsync signal is pulsed low (see figure 22 in the timing section). this results in an internal reset of the modulator count for the current conversion. thus, all the converters start counting from zero at the same time, producing a drdy low signal at approximately the same point (see figure 36). figure 36. affect of synchronization on output data timing. figure 35. sink current vs v ol for sdout under worst-case conditions. 30 25 20 15 10 5 0 sink current v ol (v) 012345 i out (ma) 25? 85? ?0? figure 34. source current vs v oh for sdout under worst-case conditions. 30 25 20 15 10 5 0 source current v oh (v) 02 1345 i out (ma) 25? 85? ?0? note that an asynchronous dsync input may cause mul- tiple converters to be different from one another by one x in clock cycle. this should not be a concern for most applica- tions. however, the timing section contains information on exactly synchronizing multiple converters to the same x in clock cycle.
35 ads1212, 1213 layout power supplies the ads1212/13 requires the digital supply (dv dd ) to be no greater than the analog supply (av dd ) +0.3v. in the majority of systems, this means that the analog supply must come up first, followed by the digital supply. failure to observe this condition could cause permanent damage to the ads1212/13. inputs to the ads1212/13, such as sdio, a in , or ref in , should not be present before the analog and digital supplies are on. violating this condition could cause latch-up. if these signals are present before the supplies are on, series resistors should be used to limit the input current (see the analog input and v bias sections of this data sheet for more details concerning these inputs). the best scheme is to power the analog section of the design and av dd of the ads1212/13 from one +5v supply and the digital section (and dv dd ) from a separate +5v supply. the analog supply should come up first. this will ensure that a in and ref in do not exceed av dd and that the digital inputs are present only after av dd has been established, and that they do not exceed dv dd . the requirements for the digital supply are not as strict. however, high frequency noise on dv dd can capacitively couple into the analog portion of the ads1212/13. this noise can originate from switching power supplies, very fast microprocessors or digital signal processors. for either supply, high frequency noise will generally be rejected by the digital filter except at interger multiplies of f mod . just below and above these frequencies, noise will alias back into the passband of the digital filter, affecting the conversion result. if one supply must be used to power the ads1212/13, the av dd supply should be used to power dv dd . this connec- tion can be made via a 10 w resistor which, along with the decoupling capacitors, will provide some filtering between dv dd and av dd . in some systems, a direct connection can be made. experimentation may be the best way to determine the approprate connection between av dd and dv dd . grounding the analog and digital sections of the design should be carefully and cleanly partitioned. each section should have its own ground plane with no overlap between them. agnd should be connected to the analog ground plane as well as all other analog grounds. dgnd should be connected to the digital ground plane and all digital signals referenced to this plane. for a single converter system, agnd and dgnd of the ads1212/13 should be connected together, underneath the converter. do not join the ground planes, but connect the two with a moderate signal trace. for multiple converters, connect the two ground planes at one location as central to all of the converters as possible. in some cases, experimen- tation may be required to find the best point to connect the two planes together. the printed circuit board can be de- signed to provide different analog/digital ground connec- tions via short jumpers. the initial prototype can be used to establish which connection works best. decoupling good decoupling practices should be used for the ads1212/ 13 and for all components in the design. all decoupling capacitors, but specifically the 0.1 m f ceramic capacitors, should be placed as close as possible to the pin being decoupled. a 1 m f to 10 m f capacitor, in series with a 0.1 m f ceramic capacitor, should be used to decouple av dd to agnd. at a minimum, a 0.1 m f ceramic capacitor should be used to decouple dv dd to dgnd, as well as for the digital supply on each digital component. system considerations the recommendations for power supplies and grounding will change depending on the requirements and specific design of the overall system. achieving 20 bits or more of effective resolution is a great deal more difficult than achiev- ing 12 bits. in general, a system can be broken up into four different stages: analog processing analog portion of the ads1212/13 digital portion of the ads1212/13 digital processing for the simplest system consisting of minimal analog signal processing (basic filtering and gain), a self-contained microcontroller, and one clock source, high-resolution could be achieved by powering all components by a common power supply. in addition, all components could share a common ground plane. thus, there would be no distinctions between analog and digital power and ground. the layout should still include a power plane, a ground plane, and careful decoupling. in a more extreme case, the design could include: multiple ads1212/13s; extensive analog signal processing; one or more microcontrollers, digital signal processors, or micro- processors; many different clock sources; and interconnec- tions to various other systems. high resolution will be very difficult to achieve for this design. the approach would be to break the system into a many different parts as possible. for example, each ads1212/13 may have its own analog processing front end, its own analog power and ground (possibly shared with the analog front end), and its own digital power and ground. the converters digital power and ground would be separate from the power and ground for the systems processors, ram, rom, and glue logic.
36 ads1212, 1213 ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd c 2 6pf c 1 6pf dv dd agnd dgnd agnd av dd dv dd dgnd 1/2 opa1013 3k w agnd xtal agnd 1.0? figure 37. bridge transducer interface with voltage excitation. figure 38. bridge transducer interface with current excitation. ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd c 2 6pf c 1 6pf xtal dv dd dgnd dgnd agnd dgnd agnd av dd dv dd ina118 10k w 1 3 5 8 2 6 r g +in ?n r 1 6k w 7 ab o c i ref200 12 34 865 100? 100? agnd 1.0? applications the ads1212/13 can be used in a broad range of data acquisition tasks. the following application diagrams show the ads1212 and/or ads1213 being used for bridge trans- ducer measurements, temperature measurement, and 4-20ma receiver applications.
37 ads1212, 1213 figure 39. pt100 interface. figure 40. complete 4-20ma receiver. figure 41. single supply, high accuracy thermocouple. ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd c 2 6pf c 1 6pf dv dd agnd dgnd dgnd dgnd agnd xtal agnd av dd dv dd ina118 1 3 7 4 8 2 6 5 r g +in ?n ab ref200 100? 100? r 3 14k w r 2 100 w r 1 100 w agnd 1.0? ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd c 2 6pf c 1 6pf dv dd agnd dgnd dgnd dgnd xtal av dd dv dd rcv420 15 +in 3 2 ?n 1 c t ?5v 14 13 5 +15v 4?0ma agnd 1.0? ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd c 2 6pf c 1 6pf dv dd agnd dgnd dgnd dgnd xtal +5v dv dd ina128 r g r 1 10k w agnd 1 3 7 8 2 6 4 5 +in ?n termination agnd 1.0?
38 ads1212, 1213 figure 42. dual supply, high accuracy thermocouple. figure 43. single supply, high accuracy thermocouple interface with cold junction compensation. ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd c 2 6pf c 1 6pf dv dd dgnd dgnd dgnd xtal +5v dv dd agnd agnd ina128 r g r 1 10k w 1 3 7 8 2 6 4 5 +in ?n ?v agnd 1.0? c 2 6pf c 1 6pf dv dd dgnd xtal +5v dv dd agnd agnd agnd dgnd dgnd ina118 r g r 1 10k w r 2 13k w agnd 1 3 7 8 2 6 4 5 +in ?n ads1213u, p a in 3n a in 2p a in 2n a in 1p a in 1n agnd v bias cs dsync x in x out dgnd a in 3p a in 4n a in 4p ref in ref out av dd mode drdy sdout sdio sclk dv dd agnd 1n4148 agnd 1.0?
39 ads1212, 1213 ads1212 a in p a in n agnd v bias cs dsync x in x out dgnd ref in ref out av dd mode drdy sdout sdio sclk dv dd c 2 6pf c 1 6pf xtal dv dd agnd a vdd dgnd dgnd agnd av dd dv dd 10k w ?n +in r 1 6k w 7 ab o c i ref200 12 34 865 100? 100? agnd 1.0? figure 44. dual supply, high accuracy thermocouple interface with cold junction compensation. figure 45. low cost bridge transducer interface with current excitation. c 2 6pf c 1 6pf dv dd dgnd xtal ?v +5v dv dd agnd agnd dgnd dgnd ina118 r g r 1 10k w r 2 13k w agnd 1 3 7 8 2 6 4 5 +in ?n ads1213u, p a in 3n a in 2p a in 2n a in 1p a in 1n agnd v bias cs dsync x in x out dgnd a in 3p a in 4n a in 4p ref in ref out av dd mode drdy sdout sdio sclk dv dd agnd 1n4148 agnd 1.0?
40 ads1212, 1213 topic index topic page topic page analog operation ................................................................ 17 analog input ....................................................................................... 17 reference input ................................................................................ 17 reference output ............................................................................ 17 v bias ............................................................................................................................... ...................... 18 digital operation .................................................................. 18 system configuration .................................................................... 18 instruction register (insr) ................................................................... 19 command register (cmr) .................................................................... 19 data output register (dor) ................................................................. 21 offset calibration register (ocr) ......................................................... 22 full-scale calibration register (fcr) ................................................... 22 timing ..................................................................................................... 22 synchronizing multiple converters ........................................................ 26 serial interface ................................................................................ 26 multiple instructions ............................................................................... 26 using cs and continuous read mode ................................................. 29 power-on conditions for sdio ............................................................. 29 master mode .......................................................................................... 29 slave mode ............................................................................................ 29 making use of dsync ......................................................................... 30 reset, power-on reset, and brown-out .............................................. 30 two-wire interface ................................................................................ 30 three-wire interface .............................................................................. 30 four-wire interface ................................................................................ 30 multi-wire interface ............................................................................... 32 i/o recovery .......................................................................................... 32 isolation ................................................................................................. 33 synchronization of multiple converters ................................................. 34 layout ........................................................................................ 35 power supplies .................................................................................. 35 grounding ............................................................................................ 35 decoupling .......................................................................................... 35 system considerations .................................................................. 35 applications ............................................................................ 36 features .................................................................................... 1 applications .............................................................................. 1 description ................................................................................ 1 specifications ........................................................................... 2 absolute maximum ratings ............................................................. 3 electrostatic discharge sensitivity ........................................ 3 package information ........................................................................ 3 ordering information ...................................................................... 3 ads1212 simplified block diagram ................................................ 4 ads1212 pin configuration .............................................................. 4 ads1212 pin definitions ..................................................................... 4 ads1213 simplified block diagram ................................................ 5 ads1213p and ads1213u pin configuration ................................. 5 ads1213p and ads1213u pin definitions ........................................ 5 ads1213e pin configuration ........................................................... 6 ads1213e pin definitions ................................................................... 6 typical performance curves ........................................... 7 theory of operation ............................................................. 9 definition of terms ......................................................................... 10 digital filter ...................................................................................... 11 filter equation ....................................................................................... 12 filter settling .......................................................................................... 12 turbo mode ......................................................................................... 12 programmable gain amplifier ..................................................... 13 software gain .................................................................................... 13 calibration .......................................................................................... 13 self-calibration ...................................................................................... 14 system offset calibration ...................................................................... 14 system full-scale calibration ............................................................... 14 pseudo system calibration ................................................................... 15 background calibration ......................................................................... 15 system calibration offset and full-scale calibration limits ................ 16 sleep mode .......................................................................................... 16
41 ads1212, 1213 figure index table index figure title page figure 1 normalized digital filter response ......................................... 11 figure 2 digital filter response at a data rate of 50hz ..................... 11 figure 3 digital filter response at a data rate of 60hz ..................... 11 figure 4 asynchronous ads1212/13 analog input voltage step or ads1213 channel change to fully settled output data .. 12 figure 5 self-calibration timing ............................................................ 14 figure 6 system offset calibration timing ............................................ 14 figure 7 system full-scale calibration ................................................. 14 figure 8 pseudo system calibration timing ......................................... 15 figure 9 background calibration ........................................................... 15 figure 10 sleep mode to normal mode timing ...................................... 17 figure 11 analog input structure ............................................................. 17 figure 12 10v input configuration using v bias .................................................... 18 figure 13 x in clock timing ...................................................................... 22 figure 14 serial input/output timing, master mode ............................... 22 figure 15 serial input/output timing, slave mode ................................. 22 figure 16 serial interface timing (cs low), master mode ................... 24 figure 17 serial interface timing (cs low), slave mode ..................... 24 figure 18 serial interface timing (using cs), master mode .................. 24 figure 19 serial interface timing (using cs), slave mode .................... 25 figure 20 sdio input to output transition timing ................................. 25 figure 21 drdy rise and fall time ....................................................... 25 figure 22 dsync to x in timing for synchronizing multiple ads1212/13s ........................................................................... 26 figure 23 exactly synchronizing multiple ads1212/13s to asynchronous dsync signal ............................................. 26 figure 24 timing of data output register update ................................. 26 figure 25 flowchart for writing and reading register data, master mode 27 figure 26 flowchart for writing and reading register data, slave mode .. 28 figure 27 resetting the ads1212/13 (slave mode only) ...................... 30 figure 28 three-wire interface with an 8xc32 microprocessor ............. 31 figure 29 three-wire interface with an 8xc51 microprocessor ............. 31 figure 30 four-wire interface with an 8xc32 microprocessor ............... 32 figure 31 full interface with an 8xc51 microprocessor ......................... 32 figure 32 full interface with a 68hc11 microprocessor ......................... 33 figure 33 isolated four-wire interface .................................................... 33 figure 34 source current vs v oh for sdout under worst-case conditions ............................................................ 34 figure 35 sink current vs v ol for sdout under worst-case conditions ............................................................ 34 figure 36 affect of synchronization on output data timing .................. 34 figure 37 bridge transducer interface with voltage excitation .............. 36 figure 38 bridge transducer interface with current excitation .............. 36 figure 39 pt100 interface ....................................................................... 37 figure 40 complete 4-20ma receiver .................................................... 37 figure 41 single supply, high accuracy thermocouple ......................... 37 figure 42 dual supply, high accuracy thermocouple ........................... 38 figure 43 single supply, high accuracy thermocouple interface with cold junction compensation ........................................... 38 figure 44 dual supply, high accuracy thermocouple interface with cold junction compensation ........................................... 39 figure 45 low cost bridge transducer interface with current excitation .... 39 table title page table i full-scale range vs pga setting ............................................. 9 table ii available pga settings vs turbo mode rate ........................... 9 table iii effective resolution vs data rate and gain setting .............. 10 table iv effective resolution vs data rate and turbo mode rate ..... 12 table v noise level vs data rate and turbo mode rate .................. 12 table vi effective resolution vs data rate, clock frequency, and turbo mode rate .................................................................... 12 table vii ads1212/13 registers ............................................................ 18 table viii instruction register .................................................................. 19 table ix a3-a0 addressing .................................................................... 19 table x organization of the command register and default status .. 19 table xi decimation ratios vs data rates ........................................... 21 table xii data output register ............................................................... 21 table xiii offset calibration register ...................................................... 22 table xiv full-scale calibration register ................................................ 22 table xv digital timing characteristics .................................................. 23

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