any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. overview the LC4104C-T2A is a segment driver ic for large-scale dot matrix lcd displays. the LC4104C-T2A latches 160- bits of display data transferred from the controller over a 4- or 8-bit parallel interface and generates the lcd drive signals. in conjunction with the lc4102c-t2a common driver, the LC4104C-T2A forms a chip set that can drive large-screen lcd panels. features high-voltage cmos (p-sub) process lcd drive voltage: 36 v logic system power-supply voltage: 2.7 to 5.5 v maximum fcp: 12 mhz (v dd = 5 v ?0%), 10 mhz (v dd = 2.7 to 4.5 v) parallel input circuit can be switched between 4 and 8 bits. output directionality switching dispoff function (holds the lcd drive voltage at a fixed level.) display duty ratios: 1/160 to 1/480 package: tcp (tape carrier package) cmos ic ordering number : enn * 6790 20702tn (ot) no. 6790-1/8 preliminary sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan lcd dot matrix segment driver for stn displays LC4104C-T2A
block diagram specifications the following electrical characteristics apply when sealed in a sanyo standard pga-208 package. absolute maximum ratings at v ss = 0 v note: v0, v2, v3, and v5 must obey the following relationships: v ddh 3 v0 3 v2 3 v ddh ?7 v, and 7 v 3 v3 3 v5 3 v ss . no. 6790- 2 /8 LC4104C-T2A parameter symbol conditions ratings unit maximum supply voltage v dd max ?.3 to +7 v maximum supply voltage v ddh max ?.3 to +40 v maximum supply voltage v ss max ?.3 to +0.3 v input voltage v in d0 to d7, load, cp, r/l, test, disp, m, eio1, eio2, bs ?.3 to v dd + 0.3 v input voltage v0, v2 v0, v2 v ddh ?7 to v ddh + 0.3 v input voltage v3 v3 ?.3 to v ss + 7 v input voltage v5 v5 ?.3 to +0.3 v operating temperature topr ?0 to +75 c storage temperature tstg ?5 to +125 c v0 v2 v3 v dd h load bs disp m v5 v0 v2 v3 v dd h v dd v ss eio2 v5 o1 test d0 d7 eio1 cp r/l o2 o3 o4 o158 o159 o160 output control 4 level lcd drive circuit (160bits) level shifter 2nd latch (160bits) 1st latch (8bits 20) address decoder address counter a1367 bits control chip disable & latch control
allowable operating ranges at ta = ?0 to +75 c, v ss = 0 v note: v0, v2, v3, and v5 must obey the following relationships: v ddh 3 v0 3 v2 3 v ddh ?7 v, and 7 v 3 v3 3 v5 3 v ss . at power on: first turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively, turn both on at the same time. at power off: first turn off the high-voltage system power supply and then turn off the logic system power supply; alternativel y, turn both off at the same time. allowable operating ranges at ta = ?0 to +75 c, v ss = 0 v, v dd = 5 v 10% note: * the clock rise time (tr) and fall time (tf) must obey inequalities and - below. : tr, tf < - : tr, tf 50 ns allowable operating ranges at ta = ?0 to +75 c, v ss = 0 v, v dd = 2.7 to 4.5 v note: * the clock rise time (tr) and fall time (tf) must obey inequalities and - below. : tr, tf < - : tr, tf 50 ns 1 ?tw (cph) ?tw (cpl) fcp 2 1 ?tw (cph) ?tw (cpl) fcp 2 no. 6790- 3 /8 LC4104C-T2A parameter symbol conditions ratings unit min typ max supply voltage v dd 2.7 5.5 v supply voltage v ddh 14 36 v supply voltage v ss 0 v input high-level voltage v ih d0 to d7, load, cp, r/l, m, test, disp, bs, 0.8 v dd v dd v eio1, eio2 input low-level voltage v il d0 to d7, load, cp, r/l, m, test, disp, bs, 0 0.2 v dd v eio1, eio2 input voltage v0, v2 v0, v2 v ddh ?7 v ddh v input voltage v3 v3 0 v ssh + 7 v input voltage v5 v5 0 v parameter symbol conditions ratings unit min typ max cp clock frequency fcp cp 12 mhz high-level load pulse width tw (ldh) load 50 ns high-level clock pulse width tw (cph) cp 20 ns low-level clock pulse width tw (cpl) cp 20 ns load/cp setup time tsu (ld) load, cp 100 ns load/cp hold time tho (ld) load, cp 200 ns data/cp setup time tsu (cp) cp, d0 to d7 10 ns data/cp hold time tho (cp) cp, d0 to d7 10 ns eio input setup time tsu (ei) cp, eio1, eio2 24 ns clock rise time tr load, cp * 50 ns clock fall time tf load, cp * 50 ns parameter symbol conditions ratings unit min typ max cp clock frequency fcp cp 10 mhz high-level load pulse width tw (ldh) load 50 ns high-level clock pulse width tw (cph) cp 37 ns low-level clock pulse width tw (cpl) cp 37 ns load/cp setup time tsu (ld) load, cp 100 ns load/cp hold time tho (ld) load, cp 200 ns data/cp setup time tsu (cp) cp, d0 to d7 35 ns data/cp hold time tho (cp) cp, d0 to d7 35 ns eio input setup time tsu (ei) cp, eio1, eio2 30 ns clock rise time tr load, cp * 50 ns clock fall time tf load, cp * 50 ns
electrical characteristics at ta = ?0 to +75 c, v dd = 2.7 to 5.5 v, v ss = 0 v note: 1. v o is the voltage applied for an on output, v0 = v ddh , v2 = 18/20 (v ddh ?v ss ), v3 = 2/20 (v ddh ?v ss ), v5 = v ss 2. load = 28 khz, cp = 10 mhz, m = 75 hz alternatively: no output load and with the inputs v ih = v dd and v il = v ss . 3. the current drain in standby mode. note that the eion pins must be held at v dd . switching characteristics at ta = ?0 to +75 c, v ss = 0 v, v dd = 5 v 10% switching characteristics at ta = ?0 to +75 c, v ss = 0 v, v dd = 2.7 to 4.5 v timing chart no. 6790- 4 /8 LC4104C-T2A parameter symbol conditions ratings unit min typ max input high-level current i ih v in = v dd : d0 to d7, load, cp, r/l, m, disp, 5 a eio1, eio2, bs, test i il 1 v in = v ss : d0 to d7, load, cp, r/l, m, disp, ? input low-level current eio1, eio2, bs a i il 2 v in = v ss : test ?00 output high-level voltage v oh i o = ?.4 ma: eio1, eio2 v dd ?0.4 v dd v output low-level voltage v ol i o = 0.4 ma: eio1, eio2 v ss 0.4 v output on resistance r out v ddh = 36 v * 1 , v0 ?v o = 0.5 v, v2 ?v o = 0.5 v, 1 3 k v o ?v3 = 0.5 v, v o ?v5 = 0.5 v: o1 to o160 i dd v dd = 2.7 to 5.5 v 5.0 ma current drain i ddh v dd = 2.7 to 5.5 v, v ddh = 32 v * 2 , 2.0 ma v dd = 5 v 10%, v ddh = 36 v 2.0 ma i st * 3 500 a parameter symbol conditions ratings unit min typ max eio output delay time td (eo) 30 pf capacitive load: cp, eio1, eio2 40 ns ld/eio output delay time td (leo) 30 pf capacitive load: load, eio1, eio2 70 ns load/on delay time td (ldo) 100 pf capacitive load: load, o1 to o160 3 s m/on delay time td (mo) 100 pf capacitive load: m, o1 to o160 3 s parameter symbol conditions ratings unit min typ max eio output delay time td (eo) 30 pf capacitive load: cp, eio1, eio2 80 ns ld/eio output delay time td (leo) 30 pf capacitive load: load, eio1, eio2 130 ns load/on delay time td (ldo) 100 pf capacitive load: load, o1 to o160 3 s m/on delay time td (mo) 100 pf capacitive load: m, o1 to o160 3 s tsu(ld) tw(ldh) tr(ld) tf(ld) tw(cph) tr(cp) tf(cp) tsu(cp) td(mo) td(ldo) td(leo) td(eo) tsu(ei) tho(cp) tw(cpl) tho(ld) load cp d0 to d7 m on eion (output) (input to the next stage) a13677 0.2v dd 0.8v dd
pin functions no. 6790- 5 /8 LC4104C-T2A symbol i/o function o1 to o160 v0 v2 v3 v5 v ddh v dd v ss disp m eio1 eio2 cp load test r/l d0 to d7 bs o i i i i i i i/o i/o i i i i i i lcd drive outputs v0 level drive voltage supply (selected level) v2 level drive voltage supply (unselected level) v3 level drive voltage supply (unselected level) v5 level drive voltage supply (selected level) high-voltage system power supply. logic system power supply. gnd lcd off function. all outputs go to the v5 level when this pin is low. alternation signal input enable i/o enable input: the enable input at the first stage is fixed at v ss . for succeeding stages, the enable input is connected to the enable output from the preceding stage. enable output: connected to the enable input of the next stage when cascode connection is used. data acquisition clock (falling edge) data load clock (falling edge) test input. must be tied high in normal use. * data shift direction setting parallel data inputs input bus setting. set high for 8-bit input, low for 4-bit input. for 4-bit input, d0 to d3 are used for data input and d4 to d 7 must be tied to ground. * : don? care. m data disp on h h h v0 h l h v2 l l h v3 l h h v5 * * l v5 r/l eio1 eio2 l in out h out in r/l bs o1 to o160 outputs o1 o2 o3 o4 ? . . . o157 o158 o159 o160 l - - - - - - - - h d7 d6 d5 d4 d3 d2 d1 d0 o1 o2 o3 o4 . . . ? o157 o158 o159 o160 h - - - - - - - - d0 d1 d2 d3 d4 d5 d6 d7 o1 o2 o3 o4 ? . . . o157 o158 o159 o160 l - - - - - - - - l d3 d2 d1 d0 d3 d2 d1 d0 o1 o2 o3 o4 . . . ? o157 o158 o159 o160 h - - - - - - - - d0 d1 d2 d3 d0 d1 d2 d3
pin assignment no. 6790- 6 /8 LC4104C-T2A d u m m y l c 4 1 0 4 c - t 2 a ( c h i p t o p v i e w ) v 3 v 5 v 2 v 3 v 5 a 1 3 6 7 8 d i s p d 6 v d d c p l o a d m d 7 e i o 2 e i o 1 d 1 r / l d 2 d 3 d 4 d 5 v d d h v 0 v 2 v d d h v 0 v s s d 0 b s o u t 1 6 0 o u t 1 5 9 o u t 1 5 8 d u m m y o u t 3 o u t 2 o u t 1 note: this figure shows the chip pattern surface as seen from abobe. this figure dose not stipulate the tcp package.
no. 6790- 7 /8 LC4104C-T2A package dimensions unit: mm LC4104C-T2A (cu) ?.0 0.1 0.6 max lsi chip flex hole 0.3 max 0.75 max 1.35 max 0.4 0.05 ?.0 0.05 0.4 0.02 0.6 0.02 1.981 0.03 4.75(p) 4=19.0 0.05 4.75 0.03 1.2 0.05(sl) 2.0 0.05(sl) 4.48 max (sealing area) 1.98(lsi) 2.48 0.05 8.0 0.1(sl) 4.0 0.1(sl) r0.8 0.3(sr) r0.5 0.05 0.6 max 0.6 max 0.3 0.05 10.3 0.05 3.7( cut line ) 8.5 0.3(sr) 1.7 0.3(sr) 1.2 0.05(sl) 6.7 0.05(sl) 1.2 0.05(sl) 4.9 0.05(sl) 15.0 19.8 0.1 19.8 0.1 1.7 0.1(sl) 1.7 0.1(sl) 12.55 0.1(sl) 12.55 0.1(sl) 23.6 0.05(sl) 24.0 0.055 0.14(p) (162- -1)=22.54 0.055 (w=0.09) 25.5 (cut line) 24.3 0.3(sr) 23.0 0.05(sl) 22.0 0.05(sl) 13.05(lsi) 13.55 0.05(device hole) 15.55 max(sealing area) 0.8(p) (28- -1)=21.6 0.055 (w=0.34) 32.0 0.1 48.175 0.2 42.177 0.07 v5 v5 v3 vddh v2 v0 d0 d1 d2 d3 d4 d5 d6 d7 vdd eio2 ei01 cp load m disp r/l bs vss vddh v0 v2 v3 device hole sealing area
ps no. 6790- 8 /8 LC4104C-T2A this catalog provides information as of february, 2002. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
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