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dac712 v out v ref out +10v reference circuit 16-bit d/a converter d/a latch 16 gain adjust input latch 16 a 1 a 0 wr clr db 0 db 15 bipolar offset adjust features l high-speed 16-bit parallel double- buffered interface l voltage output: 10v l 13-, 14-, and 15-bit linearity grades l 16-bit monotonic over temperature (l grade) l power dissipation: 600mw max l gain and offset adjust: convenient for auto-cal d/a converters l 28-lead dip and soic packages description dac712 is a complete 16-bit resolution d/a converter with 16 bits of monotonicity over temperature. dac712 has a precision +10v temperature compen- sated voltage reference, 10v output amplifier and 16-bit port bus interface. the digital interface is fast, 60ns minimum write pulse width, is double-buffered and has a clear function that resets the analog output to bipolar zero. gain and offset adjustment inputs are arranged so that they can be easily trimmed by external d/a converters as well as by potentiometers. dac712 is available in two linearity error perfor- mance grades: 4lsb and 2lsb and three differen- tial linearity grades: 4lsb, 2lsb, and 1lsb. the dac712 is specified at power supply voltages of 12v and 15v. dac712 is packaged in a 28-pin 0.3" wide plastic dip and in a 28-lead wide-body plastic soic. the dac712p, u, pb, ub, are specified over the C40 c to +85 c temperature range and the dac712pk, uk, pl, ul are specified over the 0 c to +70 c range. 16-bit digital-to-analog converter with 16-bit bus interface international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 ? twx: 910-952-1111 internet: http://www.burr-brown.com/ ? faxline: (800) 548-6133 (us/canada only) ? cable: bbrcorp ? telex: 066-6491 ? fa x: (520) 889-1510 ? immediate product info: (800) 548-6132 dac712 dac712 ? 1994 burr-brown corporation pds-1164g printed in u.s.a. may, 1998 sbas023
2 dac712 specifications electrical at t a = 25 c, +v cc = +12v and +15v, Cv cc = C12v and C15v, unless otherwise noted. dac712p, u dac712pb, ub parameter min typ max min typ max units input resolution 16 [ bits digital inputs input code binary twos complement [ logic levels (1) v ih +2.0 +v cc C 1.4 [[ v v il 0 +0.8 [[ v i ih (v i = +2.7v) 10 [ m a i il (v i = +0.4v) 10 [ m a transfer characteristics accuracy linearity error 4 2 lsb t min to t max 8 4 lsb differential linearity error 4 2 lsb t min to t max 8 4 lsb monotonicity over temp 13 14 bits gain error (3) 0.1 0.1 % t min to t max 0.2 0.15 % bipolar zero error (3) 0.1 [ % fsr (2) 20 [ mv t min to t max 0.2 0.15 % fsr 40 30 mv power supply sensitivity of full scale: 0.003 [ % fsr/% v cc 30 [ ppm fsr/% v cc dynamic performance settling time (to 0.003%fsr, 5k w || 500pf load) (4) 20v output step 6 [ 10 m s 1 lsb output step (5) 4 [ m s output slew rate 10 [ v/ m s total harmonic distortion + noise 0db, 1001hz, f s = 100khz 0.005 [ % C20db, 1001hz, f s = 100khz 0.03 [ % C60db, 1001hz, f s = 100khz 3.0 [ % sinad 1001hz, f s = 100khz 87 [ db digital feedthrough (5) 2 [ nv-s digital-to-analog glitch impulse (5) 15 [ nv-s output noise voltage (includes reference) 120 [ nv/ ? hz analog output output voltage range +v cc , Cv cc = 11.4v 10 [ v output current 5 [ ma output impedance 0.1 [ w short circuit to acom, duration indefinite [ reference voltage voltage +9.975 +10.000 +10.025 [[ [ v t min to t max +9.960 +10.040 [[ v output resistance 1 [ w source current 2 [ ma short circuit to acom, duration indefinite [ power supply requirements voltage: +v cc +11.4 +15 +16.5 [[ [ v Cv cc C11.4 C15 C16.5 [[ [ v current (no load, 15v supplies) +v cc 13 15 [[ ma Cv cc 22 25 [[ ma power dissipation (6) 525 600 [[ mw temperature ranges specification all grades C40 +85 [[ c storage C60 +150 [[ c thermal coefficient q ja dip package 75 [ c/w soic package 75 [ c/w [ specifications are the same as grade to the left. notes: (1) digital inputs are ttl and +5v cmos compatible over the specification temperature range. (2) fsr means full scale ra nge. for example, for a 10v output, fsr = 20v. (3) errors externally adjustable to zero. (4) maximum represents the 3 s limit. not 100% tested for this parameter. (5) for the worst case code changes: ffff hex to 0000 hex and 0000 hex to ffff hex . these are binary twos complement (btc) codes. (6) typical supply voltages times maximum currents.
3 dac712 specifications electrical at t a = +25 c, +v cc = +12v and +15v, Cv cc = C12v and C15v, unless otherwise noted. dac712pk, uk dac712pl, ul parameter min typ max min typ max units input resolution 16 [ bits digital inputs input code binary twos complement [ logic levels (1) v ih +2.0 +v cc C 1.4 [[ v v il 0 +0.8 [[ v i ih (v i = +2.7v) 10 [ m a i il (v i = +0.4v) 10 [ m a transfer characteristics accuracy linearity error 2 2 lsb t min to t max 2 2 lsb differential linearity error 2 1 lsb t min to t max 2 1 lsb monotonicity over temp 15 16 bits gain error (3) 0.1 [ % t min to t max 0.15 0.02 % bipolar zero error (3) 0.1 [ % fsr (2) 20 [ mv t min to t max 0.15 0.15 % fsr 30 [ mv power supply sensitivity of full scale 0.003 [ %fsr/% v cc 30 [ ppm fsr/% v cc dynamic performance settling time (to 0.003%fsr, 5k w || 500pf load) (4) 20v output step 6 10 [ 10 m s 1lsb output step (5) 4 [ m s output slew rate 10 [ v/ m s total harmonic distortion + noise 0db, 1001hz, f s = 100khz 0.005 [ % C20db, 1001hz, f s = 100khz 0.03 [ % C60db, 1001hz, f s = 100khz 3.0 [ % sinad 1001hz, f s = 100khz 87 [ db digital feedthrough (5) 2 [ nvCs digital-to-analog glitch impulse (5) 15 [ nvCs output noise voltage (includes reference) 120 [ nv/ ? hz analog output output voltage range +v cc , Cv cc = 11.4v 10 [ v output current 5 [ ma output impedance 0.1 [ w short circuit to acom, duration indefinite [ reference voltage voltage +9.975 +10.000 +10.025 [[[ v t min to t max +9.960 +10.040 [[ v output resistance 1 [ w source current 2 [ ma short circuit to acom, duration indefinite [ power supply requirements voltage: +v cc +11.4 +15 +16.5 [[[ v Cv cc C11.4 C15 C16.5 [[[ v current (no load, 15v supplies) +v cc 13 15 [[ ma Cv cc 22 25 [[ ma power dissipation (6) 525 600 [ mw temperature ranges specification all grades 0 +70 [[ c storage C60 +150 [[ c thermal coefficient, q ja dip package 75 [ c/w soic package 75 [ c/w [ same specification as grade to the left. notes: (1) digital inputs are ttl and +5v cmos compatible over the specification temperature range. (2) fsr means full scale ra nge. for example, for a 10v output, fsr = 20v. (3) errors externally adjustable to zero. (4) maximum represents the 3 s limit. not 100% tested for this parameter. (5) for the worst case code changes: ffff hex to 0000 hex and 0000 hex to ffff hex . these are binary twos complement (btc) codes. (6) typical supply voltages times maximum currents.
4 dac712 absolute maximum ratings +v cc to common ...................................................................... 0v, +17v Cv cc to common ...................................................................... 0v, C17v +v cc to Cv cc ........................................................................................ 34v digital inputs to common .......................................... C1v to +v cc C0.7v external voltage applied to bpo and range resistors ..................... v cc v ref out ...................................................... indefinite short to common v out ............................................................ indefinite short to common power dissipation .......................................................................... 750mw storage temperature ...................................................... C60 c to +150 c lead temperature (soldering, 10s) ................................................ +300 c note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. package drawing product package number (1) dac712p plastic dip 246 dac712u plastic soic 217 dac712pb plastic dip 246 dac712ub plastic soic 217 dac712pk plastic dip 246 DAC712UK plastic soic 217 dac712pl plastic dip 246 dac712ul plastic soic 217 note: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. package information timing diagram timing specifications t a = C40 c to +85 c, +v cc = +12v or +15v, Cv cc = C12v or C15v. symbol parameter min max units t dw data valid to end of wr 50 ns t aw a 0 , a 1 valid to end of wr 50 ns t ah a 0 , a 1 hold after end of wr 10 ns t dh data hold after end of wr 10 ns t wp (1) write pulse width 50 ns t cp clear pulse width 200 ns notes: (1) for single-buffered operation, t wp is 80ns min. refer to page 10. wr a 0 , a 1 d0-d15 t dh t aw t wp t dw t ah a 0 a 1 wr clr description 011 ? 0 ? 1 1 load input latch 101 ? 0 ? 1 1 load d/a latch 111 ? 0 ? 1 1 no change 0 0 0 1 latches transparent x x 1 1 no change x x x 0 reset d/a latch truth table electrostatic discharge sensitivity electrostatic discharge can cause damage ranging from per- formance degradation to complete device failure. burr-brown corporation recommends that all integrated circuits be handled and stored using appropriate esd protection methods. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published speci- fications. ordering information linearity differential temperature error max linearity error product range at +25 c max at +25 c dac712p C40 c to +85 c 4lsb 4lsb dac712u C40 c to +85 c 4lsb 4lsb dac712pb C40 c to +85 c 2lsb 2lsb dac712ub C40 c to +85 c 2lsb 2lsb dac712pk 0 c to +70 c 2lsb 2lsb DAC712UK 0 c to +70 c 2lsb 2lsb dac712pl 0 c to +70 c 2lsb 1lsb dac712ul 0 c to +70 c 2lsb 1lsb
5 dac712 the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. pin configuration pin label description 1 dcom power supply return for digital currents. 2 acom analog supply return. 3v out 10v d/a output. 4 off adj offset adjust (bipolar). 5v ref out voltage reference output. 6 gain adj gain adjust. 7+v cc +12v to +15v supply. 8Cv cc C12v to C15v supply. 9 clr clear. sets d/a output to bipolar zero (active low). 10 wr write (active low). 11 a 1 enable for d/a latch (active low). 12 a 0 enable for input latch (active low). 13 d15 data bit 15 (most significant bit). 14 d14 data bit 14. 15 d13 data bit 13. 16 d12 data bit 12. 17 d11 data bit 11. 18 d10 data bit 10. 19 d9 data bit 9. 20 d8 data bit 8. 21 d7 data bit 7. 22 d6 data bit 6. 23 d5 data bit 5. 24 d4 data bit 4. 25 d3 data bit 3. 26 d2 data bit 2. 27 d1 data bit 1. 28 d0 data bit 0 (least significant bit). pin descriptions dcom acom v out offset adjust v ref out gain adjust +v cc ? cc clr wr a 1 a 0 d15 msb d14 lsb d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 dac712
6 dac712 time (10?/div) ?full scale output swing v (v) out typical performance curves at t a = +25 c, v cc = 15v, unless otherwise noted. 0 10 C10 frequency (hz) [change in fsr]/[change in supply voltage] 1k 10 100 1k 10k 100k 1m power supply rejection vs power supply ripple frequency (ppm of fsr/ %) 100 10 1 0.1 +v cc ? cc 2.0 ?.85 0 2.55 4.25 5.95 6.8 logic vs v level 1.0 0 ?.0 ?.0 0.85 1.7 3.4 5.1 data wr, a 0 , a 1 clr v digital input i digital input (?) wr (v) settling time, +10v to ?0v time (1?/div) 2500 2000 1500 1000 500 0 ?00 ?000 ?500 ?000 ?500 d around ?0v (?) +5v 0v wr settling time, ?0v to +10v time (1?/div) 2500 2000 1500 1000 500 0 ?00 ?000 ?500 ?000 ?500 d around +10v (?) +5v ?v 1000 100 10 1 1 10 100 1k 10k 100k 1m 10m frequency (hz) nv/ ? hz spectral noise density
7 dac712 discussion of specifications linearity error linearity error is defined as the deviation of the analog output from a straight line drawn between the end points of the transfer characteristic. differential linearity error differential linearity error (dle) is the deviation from 1lsb of an output change from one adjacent state to the next. a dle specification of 1/2lsb means that the output step size can range from 1/2lsb to 3/2lsb when the digital input code changes from one code word to the adjacent code word. if the dle is more positive than C1lsb, the d/a is said to be monotonic. monotonicity a d/a converter is monotonic if the output either increases or remains the same for increasing digital input values. monotonicity of dac712 is guaranteed over the specifica- tion temperature range to 13, 14, 15, and 16 bits for perfor- mance grades dac712p/u, dac712pb/ub, dac712pk/ uk, and dac712pl/ul respectively. settling time settling time is the total time (including slew time) for the d/a output to settle to within an error band around its final value after a change in input. settling times are specified to within 0.003% of full scale range (fsr) for an output step change of 20v and 1lsb. the 1lsb change is mea- sured at the major carry (ffff hex to 0000 hex , and 0000 hex to ffff hex : btc codes), the input transition at which worst-case settling time occurs. total harmonic distortion + noise total harmonic distortion + noise is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental fre- quency. it is expressed in % of the fundamental frequency amplitude at sampling rate f s . signal-to-noise and distortion ratio (sinad) sinad includes all the harmonic and outstanding spurious components in the definition of output noise power in addition to quantizing and internal random noise power. sinad is expressed in db at a specified input frequency and sampling rate, f s . digital-to-analog glitch impulse the amount of charge injected into the analog output from the digital inputs when the inputs change state. it is mea- sured at half scale at the input codes where as many as possible switches change statefrom 7fff hex to 8000 hex . digital feedthrough when the a/d is not selected, high frequency logic activity on the digital inputs is coupled through the device and shows up as output noise. this noise is digital feedthrough. operation dac712 is a monolithic integrated-circuit 16-bit d/a con- verter complete with 16-bit d/a switches and ladder net- work, voltage reference, output amplifier and microproces- sor bus interface. interface logic dac712 has double-buffered data latches. the input data latch holds a 16-bit data word before loading it into the second latch, the d/a latch. this double-buffered organiza- tion permits simultaneous update of several d/a converters. all digital control inputs are active low. refer to block diagram of figure 1. all latches are level-triggered. data present when the enable inputs are logic 0 will enter the latch. when the enable inputs return to logic 1, the data is latched. the clr input resets both the input latch and the d/a latch to give a bipolar zero output. logic input compatibility dac712 digital inputs are ttl compatible (1.4v switching level) with low leakage, high impedance inputs. thus the inputs are suitable for being driven by any type of 5v logic such as 5v cmos logic. an equivalent circuit of a digital input is shown in figure 2. data inputs will float to logic 0 and control inputs will float to logic 0 if left unconnected. it is recommended that any unused inputs be connected to dcom to improve noise immunity. digital inputs remain high impedance when power is off. input coding dac712 is designed to accept positive-true binary twos complement (btc) input codes which are compatible with bipolar analog output operation. for bipolar analog output configuration, a digital input of 7fff hex gives a plus full scale output, 8000 hex gives a minus full scale output, and 0000 hex gives bipolar zero output. internal reference dac712 contains a +10v reference. the reference output may be used to drive external loads, sourcing up to 2ma. the load current should be constant, otherwise the gain and bipolar offset of the converter will vary.
8 dac712 figure 1. dac712 block diagram. figure 2. equivalent circuit of digital inputs. r r = 1k: a 0 , a 1 , wr, clr 3k: d 0 ...d 15 esd protection circuit 6.8v 5pf digital input ? cc +v cc output voltage swing the output amplifier of dac712 is committed to a 10v output range. dac712 will provide a 10v output swing while operating on 11.4v or higher voltage supplies. gain and offset adjustments figure 3 illustrates the relationship of offset and gain adjust- ments for a bipolar connected d/a converter. offset should be adjusted first to avoid interaction of adjustments. see table i for calibration values and codes. these adjustments have a minimum range of 0.3%. + full scale all bits logic 0 1lsb range of offset adjust offset adj. translates the line digital input all bits logic 1 analog output full scale range gain adjust rotates the line ?full scale msb on all others off bipolar offset range of gain adjust ? ?.3% ? ?.3% figure 3. relationship of offset and gain adjustments. db15 msb 16-bit input latch 16-bit d/a latch 28 27 26 25 24 23 22 21 20 19 18 17 db0 lsb 6 5 +10v reference 2 1 7 dcom +v cc acom v ref out gain adjust 10 wr 12 a 0 11 a 1 9 clr 8 ?v cc 16 15 14 13 bipolar offset adjust 4 3 v out d/a switches ? cc +2.5v 15k w 170 w 9750 w 250 w 10k w offset adjustment apply the digital input code that produces the maximum negative output voltage and adjust the offset potentiometer or the offset adjust d/a converter for C10v.
9 dac712 dac712 calibration values 1 least significant bit = 305 m v digital input code analog binary twos output complement, btc (v) description 7fff h +9.999695 + full scale C1lsb | 4000 h +5.000000 3/4 scale | 0001 h +0.000305 bpz + 1lsb 0000 h 0.000000 bipolar zero (bpz) ffff h C0.000305 bpz C 1lsb | c000 h C5.000000 1/4 scale | 8000 h C10.00000 minus full scale table i. digital input and analog output voltage calibra- tion values. gain adjustment apply the digital input that gives the maximum positive voltage output. adjust the gain potentiometer or the gain adjust d/a converter for this positive full scale voltage. installation general considerations due to the high-accuracy of these d/a converters, system design problems such as grounding and contact resistance become very important. a 16-bit converter with a 20v full- scale range has a 1lsb value of 305 m v. with a load current of 5ma, series wiring and connector resistance of only 60m w will cause a voltage drop of 300 m v. to understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copper-clad printed circuit board is 1/2 m w per square. for a 5ma load, a 10 milli-inch wide printed circuit conductor 60 milli-inches long will result in a voltage drop of 150 m v. the analog output of dac712 has an lsb size of 305 m v (C96db). the noise floor of the d/a must remain below this level in the frequency range of interest. the dac712s noise spectral density (which includes the noise contributed by the internal reference,) is shown in the typical performance curves section. wiring to high-resolution d/a converters should be routed to provide optimum isolation from sources of rfi and emi. the key to elimination of rf radiation or pickup is small loop area. signal leads and their return conductors should be kept close together such that they present a small capture cross-section for any external field. wire-wrap construction is not recommended. power supply and reference connections power supply decoupling capacitors should be added as shown in figure 4. best performance occurs using a 1 to 10 m f tantalum capacitor at Cv cc . applications with less 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 + 0.01? dcom acom v out v ref out +v cc ? cc 0.01? + +12v to +15v ?2v to ?5v figure 4. power supply connections. critical settling time may be able to use 0.01 m f at Cv cc as well as at +v cc . the capacitors should be located close to the package. dac712 has separate analog common and digital common pins. the current through dcom is mostly switching transients and are up to 1ma peak in amplitude. the current through acom is typically 5 m a for all codes. use separate analog and digital ground planes with a single interconnection point to minimize ground loops. the analog pins are located adjacent to each other to help isolate analog from digital signals. analog signals should be routed as far as possible from digital signals and should cross them at right angles. a solid analog ground plane around the d/a package, as well as under it in the vicinity of the analog and power supply pins, will isolate the d/a from switching currents. it is recommended that dcom and acom be connected directly to the ground planes under the package. if several dac712s are used or if dac712 shares supplies with other components, connecting the acom and dcom lines to together once at the power supplies rather than at each chip may give better results. load connections since the reference point for v out and v ref out is the acom pin, it is important to connect the d/a converter load directly to the acom pin. refer to figure 5. lead and contact resistances are represented by r 1 through r 3 . as long as the load resistance r l is constant, r 1 simply introduces a gain error and can be removed by gain adjust- ment of the d/a or system-wide gain calibration. r 2 is part of r l if the output voltage is sensed at acom. in some applications it is impractical to return the load to the acom pin of the d/a converter. sensing the output voltage at the system ground point is reasonable, because
10 dac712 there is no change in dac712 acom current, provided that r 3 is a low-resistance ground plane or conductor. in this case you may wish to connect dcom to system ground as well. gain and offset adjust connections using potentiometers gain and offset adjust pins provide for trim using external potentiometers. 15-turn potentiometers provide suf- ficient resolution. range of adjustment of these trims is at least 0.3% of full scale range. refer to figure 6. using d/a converters the gain adjust and offset adjust circuits of dac712 have been arranged so that these points may be easily driven by external d/a converters. refer to figure 7. 12-bit d/a converters provide an offset adjust resolution and a gain adjust resolution of 30 m v to 50 m v per lsb step. nominal values of gain and offset occur when the d/a converters outputs are at approximately half scale, +5v. output voltage range connections the dac712 output amplifier is connected internally for the 10v bipolar (20v) output range. that is, the bipolar offset resistor is connected to an internal reference voltage and the 20v range resistor is connected internally to v out . dac712 cannot be connected by the user for unipolar operation. digital interface bus interface dac712 has 16-bit double-buffered data bus interface with control lines for easy interface to interface to a 16-bit bus. the double-buffered feature permits update of several d/as simultaneously. figure 5. system ground considerations for high-resolution d/a converters. r 1 sense output r l r 2 r 3 alternate ground sense connection system ground acom dcom bus interface dac712 analog power supply 0.01? (1) 0.01? to +v cc to ? cc note: (1) locate close to dac712 package. v out 10k w 10k w v ref
11 dac712 a 0 is the enable control for the data input latch. a 1 is the enable for the d/a latch. wr is used to strobe data into latches enabled by a 0 , and a 1 . refer to the block diagram of figure 1 and to timing diagram on page 3. clr sets the input data latch to all zero and the d/a latch to a code that gives bipolar 0v at the d/a output. single-buffered operation to operate the dac712 interface as a single-buffered latch, the data input latch is permanently enabled by connecting a 0 to dcom. if a 1 is not used to enable the d/a, it should be connected to dcom also. for this mode of operation, the width of wr will need to be at least 80ns minimum to pass data through the data input latch and into the d/a latch. transparent interface the digital interface of the dac712 can be made transpar- ent by asserting a o , a 1 , and wr low, and asserting clr high. for no external adjustments, pins 4 and 6 are not connected. external resistors r 1 - r 4 are standard 1% values. range of adjustment at least 0.3% fsr. 10k w 3 4 6 ?0v v out 9.75k w idac 0-2ma ? +2.5v 15k w r 3 27k w r 4 10k w 120 w 180 w r 1 500 w r 2 500 w 5 170 w 250 w internal +10v reference v ref out gain adjust bipolar offset adjust 2 acom figure 6. manual offset and gain adjust circuits.
12 dac712 10k w 3 4 6 ?0v v out dac712 9.75k w idac 0-2ma 15k w r 3 20k w 0 to +10v r 4 10k w 170 w 250 w internal +10v reference v ref out gain adjust bipolar offset adjust r 1 340 w r 2 500 w r fb v ref a 5 suggested op amps opa177gp, gs or opa604ap, au r fb v ref b 0 to 10v suggested op amps opa177gp, gs: single or opa2604ap, au: dual 5k w 10k w +10v 10k w ?0v suggested d/as cmos dac7800: dual: serial input, 12-bit resolution dac7801: dual: 8-bit port input, 12-bit resolution dac7802: dual: 12-bit port input, 12-bit resolution dac7528: dual: 8-bit port input, 8-bit resolution dac7545: dual: 12-bit port input, 12-bit resolution dac8043: single: serial input, 12-bit resolution bipolar (complete) dac813 (use 11-bit resolution for 0v to +10v output. no op amps required). for no external adjustments, pins 4 and 6 are not connected. external resistors r 1 - r 4 tolerance: 1%. range of adjustment at least 0.3% fsr. figure 7. gain and offset adjustment using d/a converters.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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