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nternational airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson blv d., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 opa2680 ? 1997 burr-brown corporation pds-1433c printed in u.s.a. october, 1999 dual wideband, voltage feedback operational amplifier with disable tm features l wideband +5v operation: 220mhz (g = 2) l high output current: 150ma l output voltage swing: 4.0v l high slew rate: 1800v/ m s l low supply current: 6.4ma/ch. l low disabled current: 300 m a/ch. l enable/disable time: 25ns/100ns applications l video line driving l xdsl line driver/receiver l high speed imaging channels l adc buffers l portable instruments l transimpedance amplifiers l active filters single-supply, dc-coupled, single-to-differential adc driver description the opa2680 represents a major step forward in unity gain stable, voltage feedback op amps. a new internal architecture provides slew rate and full power band- width previously found only in wideband current feed- back op amps. a new output stage architecture delivers high currents with a minimal headroom requirement. these combine to give exceptional single supply opera- tion. using a single +5v supply, the opa2680 can deliver a 1v to 4v output swing with over 100ma drive current and 150mhz bandwidth. this combination of features makes the opa2680 an ideal rgb line driver or single supply adc input driver. the opa2680s low 6.4ma/ch. supply current is pre- cisely trimmed at 25 c. this trim, along with low tem- perature drift, guarantees lower maximum supply current than competing products. system power may be reduced further using the optional disable control pin (so-14 package only). leaving this disable pin open, or holding it high, will operate the opa2680n normally. if pulled low, the opa2680n supply current drops to less than 600 m a while the output goes into a high impedance state. 1/2 opa2680 1/2 opa2680 +5v 50 w v in 0v to +1v 1.5k w 1.5k w 50 w 1.6k w 1.6k w 3.2k w 800 w 400 w 400 w 50 w 200 w 0.1 f in +3.5v 0.1 f +1.5v +5v 10pf 10pf clock in 0.1 f +2.5v +1.5v reft refb ads822 10-bit 40msps 2.5v cm 1v diff opa2680 related products singles duals triples voltage feedback opa680 opa2680 opa3680 current feedback opa681 opa2681 opa3681 fixed gain opa682 opa2682 opa3682 opa2680 opa2680 sbos086
2 opa2680 specifications: v s = 5v r f = 402 w , r l = 100 w , and g = +2 , (figure 1 for ac performance only), unless otherwise noted. opa2680u, n typ guaranteed 0 c to C40 c to min/ test parameter conditions +25 c +25 c (2) 70 c (3) +85 c (3) units max level (1) ac performance (figure 1) small-signal bandwidth g = +1, v o = 0.5vp-p, r f = 25 w 400 mhz typ c g = +2, v o = 0.5vp-p 220 210 200 190 mhz min b g = +10, v o = 0.5vp-p 30 20 20 20 mhz min b gain-bandwidth product g 3 10 300 200 200 200 mhz min b bandwidth for 0.1db gain flatness g = +2, v o < 0.5vp-p 30 mhz typ c peaking at a gain of +1 v o < 0.5vp-p 4 db typ c large signal bandwidth g = +2, v o = 5vp-p 175 mhz typ c slew rate g = +2, 4v step 1800 1400 1200 900 v/ m s min c rise/fall time g = +2, v o = 0.5v step 1.4 ns typ c g = +2, v o = 5v step 2.8 ns typ c settling time to 0.02% g = +2, v o = 2v step 12 ns typ c 0.1% g = +2, v o = 2v step 8 ns typ c harmonic distortion g = +2, f = 5mhz, v o = 2vp-p 2nd harmonic r l = 100 w C68 C63 C62 C60 dbc max , r l 3 500 w C80 C70 C68 C65 dbc max b 3rd harmonic r l = 100 w C80 C75 C73 C70 dbc max b r l 3 500 w C88 C85 C83 C80 dbc max b input voltage noise f > 1mhz 4.8 5.3 5.9 6.1 nv/ ? hz max b input current noise f > 1mhz 2.5 2.8 3.0 3.6 pa/ ? hz max b differential gain g = +2, ntsc, v o = 1.4vp, r l = 150 0.05 % typ c differential phase g = +2, ntsc, v o = 1.4vp, r l = 150 0.03 deg typ c channel-to-channel crosstalk f = 5mhz C70 dbc typ c dc performance (4) open-loop voltage gain (a ol )v o = 0v, r l = 100 w 58 54 52 50 db min a input offset voltage v cm = 0v 1.0 4.5 5.2 6.0 mv max a average offset voltage drift v cm = 0v 10 10 m v/ c max b input bias current v cm = 0v +8 +14 +19 +32 m a max a average bias current drift (magnitude) v cm = 0v C70 C150 na/ c max b input offset current v cm = 0v 0.1 0.7 1 1.2 m a max a average offset current drift v cm = 0v 1 1.5 na/ c max b input common-mode input range (cmir) (5) 3.5 3.4 3.3 3.2 v min a common-mode rejection ratio (cmrr) v cm = 1v 59 56 53 52 db min a input impedance differential-mode v cm = 0 190 || 0.6 k w || pf typ c common-mode v cm = 0 3.2 || 0.9 m w || pf typ c output voltage output swing no load 4.0 3.8 3.7 3.6 v min a 100 w load 3.9 3.7 3.6 3.3 v min a current output, sourcing v o = 0 +190 +160 +140 +80 ma min a current output, sinking v o = 0 C150 C135 C130 C80 ma min a closed-loop output impedance g = +2, f = 100khz 0.03 w typ c disable (so-14 only) disabled low power down supply current (+v s )v dis = 0, both channels C600 m a typ c disable time 100 ns typ c enable time 25 ns typ c off isolation g = +2, 5mhz 70 db typ c output capacitance in disable 4 pf typ c turn on glitch g = +2, r l = 150 w , v in = 0 50 mv typ c turn off glitch g = +2, r l = 150 w , v in = 0 20 mv typ c enable voltage 3.3 3.5 3.6 3.7 v min a disable voltage 1.8 1.7 1.6 1.5 v max a control pin input bias current (v dis )v dis = 0, each channel 100 160 160 160 m a max a power supply specified operating voltage 5 v typ c maximum operating voltage range 6 6 6 v max a max quiescent current v s = 5v 12.8 13.6 14.0 14.4 ma max a min quiescent current v s = 5v 12.8 12.0 12.0 10.6 ma min a power supply rejection (+psrr) input referred 65 60 58 56 db min a thermal characteristics specified operating range u, n package C40 to +85 c typ c thermal resistance, q ja junction-to-ambient u so-8 125 c/w typ c n so-14 100 c/w typ c notes: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (2) junction temperature = ambient for 25 c guaranteed specifications. (3) junction temperature = ambient at low temperature limit: junction temperature = ambient +23 c at high temperature limit for over temperature guaranteed specifications. (4) current is considered positive-out-of node. v cm is the input common-mode voltage. (5) tested < 3db below minimum cmrr specification at cmir limits.
opa2680 3 specifications: v s = +5v r f = 402 w , r l = 100 w to v s /2, g = +2 , (figure 2 for ac performance only), unless otherwise noted. opa2680u, n typ guaranteed 0 c to C40 c to min/ test parameter conditions +25 c +25 c (2) 70 c (3) +85 c (3) units max level (1) ac performance (figure 2) small-signal bandwidth g = +1, v o < 0.5vp-p, r f = 25 w 300 mhz typ c g = +2, v o < 0.5vp-p 220 120 160 140 mhz min b g = +10, v o < 0.5vp-p 25 20 19 18 mhz min b gain-bandwidth product g 3 10 250 200 190 180 mhz min b bandwidth for 0.1db gain flatness g = +2, v o < 0.5vp-p 20 mhz typ c peaking at a gain of +1 v o < 0.5vp-p 5 db typ c large signal bandwidth g = +2, v o = 2vp-p 200 mhz typ c slew rate g = +2, 2v step 1000 700 670 550 v/ m s min b rise/fall time g = +2, v o = 0.5v step 1.6 ns typ c g = +2, v o = 2v step 2.0 ns typ c settling time to 0.02% g = +2, v o = 2v step 12 ns typ c 0.1% g = +2, v o = 2v step 8 ns typ c harmonic distortion g = +2, f = 5mhz, v o = 2vp-p 2nd harmonic r l = 100 w to v s /2 C60 C55 C54 C51 dbc max b r l 3 500 w to v s /2 C70 C66 C63 C59 dbc max b 3rd harmonic r l = 100 w to v s /2 C72 C66 C64 C62 dbc max b r l 3 500 w to v s /2 C80 C76 C74 C71 dbc max b input voltage noise f > 1mhz 5 5.3 6.0 6.2 nv/ ? hz max b input current noise f > 1mhz 2.5 2.8 3.0 3.4 pa/ ? hz max b differential gain g = +2, ntsc, v o = 1.4vp, r l = 150 to v s /2 0.06 % typ c differential phase g = +2, ntsc, v o = 1.4vp, r l = 150 to v s /2 0.03 deg typ c dc performance (4) open-loop voltage gain v o = 2.5v, r l = 100 w to 2.5v 58 54 52 50 db min a input offset voltage v cm = 2.5v 2.0 6.0 7 8.5 mv max a average offset voltage drift v cm = 2.5v C10 C12 m v/ c max b input bias current v cm = 2.5v +8 +15 +18 +32 m a max a average bias current drift (magnitude) v cm = 2.5v C52 C52 na/ c max b input offset current v cm = 2.5v 0.1 0.6 1.0 1.2 m a max a average offset current drift v cm = 2.5v 0.5 1.0 na/ c max b input least positive input voltage (5) 1.5 1.6 1.7 1.8 v max a most positive input voltage (5) 3.5 3.4 3.3 3.2 v min a common-mode rejection ratio (cmrr) v cm = 2.5v 0.5v 59 56 53 52 db min a input impedance differential-mode v cm = 2.5v 92 || 1.4 k w || pf typ c common-mode v cm = 2.5v 2.2 || 1.5 m w || pf typ c output most positive output voltage no load 4 3.8 3.6 3.5 v min a r l = 100 w to 2.5v 3.9 3.7 3.5 3.4 v min a least positive output voltage no load 1 1.2 1.4 1.5 v max a r l = 100 w to 2.5v 1.1 1.3 1.5 1.7 v max a current output, sourcing +150 +110 +110 +60 ma min a current output, sinking C110 C75 C70 C50 ma min a closed-loop output impedance g =+2, f = 100khz 0.03 w typ c disable (so-14 only) disabled low power down supply current (+v s )v dis = 0, both channels C500 m a typ c disable time 100 ns typ c enable time 25 ns typ c off isolation g = +2, 5mhz 65 db typ c output capacitance in disable 4 pf typ c turn on glitch g = +2, r l = 150 w , v in = v s /2 50 mv typ c turn off glitch g = +2, r l = 150 w , v in = v s /2 20 mv typ c enable voltage 3.3 3.5 3.6 3.7 v min a disable voltage 1.8 1.7 1.6 1.5 v max a control pin input bias current (v dis )v dis = 0, each channel 100 m a typ c power supply specified single supply operating voltage 5 v typ c maximum single supply operating voltage 12 12 12 v max b max quiescent current v s = +5v 10.2 12.0 12.0 12.0 ma max a min quiescent current v s = +5v 10.2 8.0 8.0 7.6 ma min a power supply rejection (+psrr) input referred 55 db typ c temperature range specification: u, n C40 to +85 c typ c thermal resistance, q ja junction-to-ambient u so-8 125 c/w typ c n so-14 100 c/w typ c notes: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (2) junction temperature = ambient for 25 c guaranteed specifications. (3) junction temperature = ambient at low temperature limit: junction temperature = ambient +23 c at high temperature limit for over temperature guaranteed specifications. (4) current is considered positive-out-of node. v cm is the input common-mode voltage. (5) tested < 3db below minimum cmrr specification at cmir limits.
4 opa2680 pin configurations top view so-8 the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. price s and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. absolute maximum ratings power supply .............................................................................. 6.5vdc internal power dissipation ..................................... see thermal analysis differential input voltage .................................................................. 1.2v input voltage range ............................................................................ v s storage temperature range: u, n ................................ C40 c to +125 c lead temperature (soldering, 10s) .............................................. +300 c junction temperature (t j ) ........................................................... +175 c 1 2 3 4 8 7 6 5 +v s out b ?n b +in b out a ?n a +in a ? s a b so-14 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ?n a +in a disa ? s disb +in b ?n b out a nc nc +v s nc nc out b package specified drawing temperature package ordering transport product package number (1) range marking number (2) media opa2680u so-8 surface mount 182 C40 c to +85 c opa2680u opa2680u rails """"" opa2680u/2k5 tape and reel opa2680n so-14 surface mount 235 C40 c to +85 c opa2680n opa2680n rails """"" opa2680n/2k5 tape and reel notes: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. (2 ) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 devices per reel). ordering 2500 pieces of opa2680u/2k5 will get a single 2500-piece tape and reel. for detailed tape and reel mechanical information, refer to appendix b of burr-brown ic data book. package/ordering information electrostatic discharge sensitivity electrostatic discharge can cause damage ranging from perfor- mance degradation to complete device failure. burr-brown corpo- ration recommends that all integrated circuits be handled and stored using appropriate esd protection methods. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications.
opa2680 5 typical performance curves: v s = 5v at t a = +25 c, g = +2, r f = 402 w , and r l = 100 w , unless otherwise noted. see figure 1. 6 3 0 ? ? ? ?2 ?5 ?8 ?1 ?4 small-signal frequency response frequency (mhz) normalized gain (3db/div) 0.5 10 100 500 g = +5 v o = 0.5vp-p g = +10 g = +2 g = +1 r f = 25 w 15 12 9 6 3 0 ? ? ? ?2 ?5 large-signal frequency response frequency (mhz) 0.5 10 100 500 v o = 7vp-p v o = 1vp-p v o = 2vp-p v o = 4vp-p gain (3db/div) 400 300 200 100 0 ?00 ?00 ?00 ?00 small-signal pulse response time (5ns/div) output voltage (100mv/div) g = +2 v o = 0.5vp-p +4 +3 +2 +1 0 ? ? ? ? large-signal pulse response time (5ns/div) output voltage (1v/div) g = +2 v o = 5vp-p channel-to-channel crosstalk 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 frequency (mhz) 1 10 100 crosstalk (10db/div) 2.0 1.6 1.2 0.8 0.4 0 5.0 4.0 2.0 0 large-signal disable/enable response time (50ns/div) v o (0.4v/div) v dis (2v/div) output voltage v dis g = +2 v in = +1v each channel so-14 package only
6 opa2680 typical performance curves: v s = 5v (cont) at t a = +25 c, g = +2, r f = 402 w , and r l = 100 w , unless otherwise noted. see figure 1. ?0 ?5 ?0 ?5 ?0 ?5 ?0 5mhz 2nd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 2nd harmonic distortion (dbc) r l = 200 w r l = 500 w r l = 100 w ?0 ?5 ?0 ?5 ?0 ?5 ?0 5mhz 3rd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 3rd harmonic distortion (dbc) r l = 200 w r l = 100 w r l = 500 w ?0 ?5 ?0 ?5 ?0 ?5 ?0 10mhz 2nd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 2nd harmonic distortion (dbc) r l = 500 w r l = 100 w r l = 200 w ?0 ?5 ?0 ?5 ?0 ?5 ?0 10mhz 3rd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 3rd harmonic distortion (dbc) r l = 500 w r l = 100 w r l = 200 w ?0 ?5 ?0 ?5 ?0 ?5 ?0 20mhz 2nd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 2nd harmonic distortion (dbc) r l = 500 w r l = 100 w r l = 200 w ?0 ?5 ?0 ?5 ?0 ?5 ?0 20mhz 3rd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 3rd harmonic distortion (dbc) r l = 500 w r l = 100 w r l = 200 w
opa2680 7 typical performance curves: v s = 5v (cont) at t a = +25 c, g = +2, r f = 402 w , and r l = 100 w , unless otherwise noted. see figure 1. ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 2nd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 2nd harmonic distortion (dbc) v o = 2vp-p r l = 100 w g = +2 g = +10 g = +5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 3rd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 3rd harmonic distortion (dbc) v o = 2vp-p r l = 100 w g = +2 g = +10 g = +5 ?0 ?0 ?0 ?0 ?0 ?0 two-tone, 3rd-order spurious level single-tone load power (dbm) 86420246810 3rd-order spurious level (dbc) 50mhz 20mhz 10mhz load power at matched 50 w load 80 70 60 50 40 30 20 10 0 recommended r s vs capacitive load capacitive load (pf) 10 100 r s ( w ) 12 9 6 3 0 ? ? ? ?2 ?5 ?8 frequency response vs capacitive load frequency (20mhz/div) 0 200mhz 100mhz gain-to-capacitive load (3db/div) 1/2 opa2680 r s v in v o c l 1k w 402 w 402 w 1k w is optional c l = 22pf c l = 10pf g = +2 c l = 47pf c l = 100pf 100 10 1 input voltage and current noise density frequency (hz) 100 1k 10k 100k 1m 10m voltage noise (nv/ ? hz) current noise (pa/ ? hz) voltage noise current noise 2.5pa/ ? hz 4.8nv/ ? hz
8 opa2680 typical performance curves: v s = 5v (cont) at t a = +25 c, g = +2, r f = 402 w , and r l = 100 w , unless otherwise noted. see figure 1. 100 90 80 70 60 50 40 30 20 10 0 cmrr and psrr vs frequency frequency (hz) 10k 100m 100k 1m 10m power supply rejection ratio (db) common-mode rejection ratio (db) ?srr +psrr cmrr 70 60 50 40 30 20 10 0 ?0 ?0 0 ?0 ?0 ?0 ?20 ?50 ?80 ?10 ?40 ?70 open-loop gain and phase frequency (hz) 10k 1g 100k 10m 1m 100m open-loop gain (db) open-loop phase (degrees) open-loop gain open-loop phase 15 10 5 0 ? ?0 ?5 typical dc drift over temperature ambient temperature (?) ?0 ?0 0 20 40 60 80 100 120 140 input offset voltage (mv) input bias and offset current (?) i b v io i os 5 4 3 2 1 0 ? ? ? ? ? output voltage and current limitations i o (ma) ?00 ?00 ?00 0 100 200 300 v o (volts) 100 w load line 50 w load line 25 w load line output current limited 1w internal power limit one channel only 1w internal power limit output current limit 0.2 0.175 0.15 0.125 0.1 0.075 0.05 0.025 0 composite video dg/dp number of 150 w loads 1234 dp dg dg/dp (%/degrees) 1/2 opa2680 402 w 402 w 75 w optional 1.3k w pulldown video in +5v ?v video loads dp dg no pulldown with 1.3k w pulldown 200 150 100 50 0 20.0 15.0 10.0 5.0 0 supply and output current vs temperature ambient temperature (?) ?0 ?0 0 20 40 60 80 100 120 140 output current (50ma/div) supply current (5.0ma/div) quiescent supply current sourcing output current sinking output current
opa2680 9 typical performance curves: v s = +5v at t a = +25 c, g = +2, r f = 402 w , and r l = 100 w , unless otherwise noted. see figure 2. 6 3 0 ? ? ? ?2 ?5 ?8 ?1 ?4 small-signal frequency response frequency (mhz) normalized gain (3db/div) 0.5 10 100 500 g = +5 g = +10 g = +2 g = +1 r f = 25 w v o = 0.5vp-p 12 9 6 3 0 ? ? ? ?2 ?5 ?8 large-signal frequency response frequency (mhz) 0.5 10 100 500 v o = 2vp-p v o = 0.5vp-p v o = 1vp-p v o = 3vp-p gain (3db/div) 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 small-signal pulse response time (5ns/div) output voltage (100mv/div) g = +2 v o = 0.5vp-p 4.1 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 large-signal pulse response time (5ns/div) output voltage (400mv/div) g = +2 v o = 2vp-p 70 60 50 40 30 20 10 0 recommended r s vs capacitive load capacitive load (pf) 1 10 100 r s ( w ) noise gain = 2.6 12 9 6 3 0 ? ? ? ?2 ?5 ?8 frequency response vs capacitive load frequency (20mhz/div) 0 200mhz 100mhz gain-to-capacitive load (3db/div) c l = 22pf c l = 10pf signal gain = +2 noise gain = 2.6 c l = 47pf c l = 100pf 1/2 opa2680 402 w 402 w 58 w 714 w 714 w 714 w v i +5v 0.1? v o r s c l 0.1?
10 opa2680 typical performance curves: v s = +5v at t a = +25 c, g = +2, r f = 402 w , and r l = 100 w , unless otherwise noted. see figure 2. ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 2nd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 2nd harmonic distortion (dbc) v o = 2vp-p r l = 100 w to v s /2 g = +2 g = +10 g = +5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 3rd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 3rd harmonic distortion (dbc) v o = 2vp-p r l = 100 w to v s /2 g = +2 g = +10 g = +5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 2nd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 2nd harmonic distortion (dbc) r l = 500 w r l = 200 w r l = 100 w v o = 2vp-p ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 3rd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 3rd harmonic distortion (dbc) r l = 500 r l = 100 v o = 2vp-p r l = 200 10 1 0.1 0.01 closed-loop output impedance vs frequency frequency (hz) 10k 100m 100k 1m 10m output impedance ( w ) 1/2 opa2680 402 w +5v ?v 402 w 200 w z o ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 two-tone, 3rd-order spurious level single-tone load power (dbm) ?4 ?2 ?0 ? ? ? ? 0 2 3rd-order spurious level (dbc) 50mhz 10mhz load power at matched 50 w load 20mhz dbc = db below carrier
opa2680 11 applications information wideband voltage feedback operation the opa2680 provides an exceptional combination of high output power capability in a dual, wideband, unity gain stable voltage feedback op amp using a new high slew rate input stage. typical differential input stages used for voltage feedback op amps are designed to steer a fixed-bias current to the compensation capacitor, setting a limit to the achiev- able slew rate. the opa2680 uses a new input stage which places the transconductance element between two input buffers, using their output currents as the forward signal. as the error voltage increases across the two inputs, an increas- ing current is delivered to the compensation capacitor. this provides very high slew rate (1800v/ m s) while consuming relatively low quiescent current (6.4ma/ch.). this excep- tional full power performance comes at the price of a slightly higher input noise voltage than alternative architectures. the 4.8nv/ ? hz input voltage noise for the opa2680 is excep- tionally low for this type of input stage. figure 1 shows the dc-coupled, gain of +2, dual power supply circuit configuration used as the basis of the 5v specifications and typical performance curves. this is for one channel. the other channel is connected similarly. for test purposes, the input impedance is set to 50 w with a resistor to ground and the output impedance is set to 50 w with a series output resistor. voltage swings reported in the specifications are taken directly at the input and output pins, while output powers (dbm) are at the matched 50 w load. for the circuit of figure 1, the total effective load will be 100 w || 804 w . the disable control line (so-14 package only) is typically left open to guarantee normal amplifier operation. two optional components are included in figure 1. an additional resistor (175 w ) is included in series with the non- inverting input. combined with the 25 w dc source resis- tance looking back towards the signal generator, this gives an input bias current cancelling resistance that matches the 200 w source resistance seen at the inverting input (see the dc accuracy and offset control section). in addition to the usual power supply decoupling capacitors to ground, a 0.1 m f capacitor is included between the two power supply pins. in practical pc board layouts, this optional-added capacitor will typically improve the 2nd harmonic distortion performance by 3db to 6db. figure 2 shows the ac-coupled, gain of +2, single supply circuit configuration which is the basis of the +5v specifi- cations and typical performance curves. though not a rail- to-rail design, the opa2680 requires minimal input and output voltage headroom compared to other very wideband voltage feedback op amps. it will deliver a 3vp-p output swing on a single +5v supply with >150mhz bandwidth. the key requirement of broadband single-supply operation is to maintain input and output signal swings within the useable voltage ranges at both the input and the output. the circuit of figure 2 establishes an input midpoint bias using a simple resistive divider from the +5v supply (two 698 w resistors). separate networks would be required at each input. the input signal is then ac-coupled into the midpoint voltage bias. the input voltage can swing to within 1.5v of either supply pin, giving a 2vp-p input signal range centered between the supply pins. the input impedance matching resistor (59 w ) used for testing is adjusted to give a 50 w input load when the parallel combination of the biasing divider network is included. again, an additional resistor (50 w in this case) is included directly in series with the non-inverting input. this minimum recommended value provides part of the dc source resistance matching for the non-inverting input bias current. it is also used to form a simple parasitic pole to roll off the frequency response at very high frequen- cies (>500mhz) using the input parasitic capacitance. the gain resistor (r g ) is ac-coupled, giving the circuit a dc gain of +1, which puts the input dc bias voltage (2.5v) on the output as well. the output voltage can swing to within 1v of either supply pin while delivering >100ma output figure 1. dc-coupled, g = +2, bipolar supply, specifi- cation and test circuit. figure 2. ac-coupled, g = +2, single supply specifica- tion and test circuit. 1/2 opa2680 +5v + dis ?v 50 w load 50 w 175 w 50 w v o v d v i 50 w source r g 402 w r f 402 w + 6.8? 0.1? 6.8? 0.1? 0.1? 1/2 opa2680 +5v +v s dis v s /2 698 w 100 w v o v d v i 698 w 50 w r g 402 w r f 402 w 0.1? 0.1? 59 w + 6.8? 0.1?
12 opa2680 current. a demanding 100 w load to a midpoint bias is used in this characterization circuit. the new output stage circuit used in the opa2680 can deliver large bipolar output cur- rents into this midpoint load with minimal crossover distor- tion, as shown in the +5v supply, 3rd harmonic distortion plots. single supply a/d converter interface most modern, high performance analog-to-digital convert- ers (such as the burr-brown ads8xx and ads9xx series) operate on a single +5v (or lower) power supply. it has been a considerable challenge for single supply op amps to deliver a low distortion input signal at the adc input for signal frequencies exceeding 5mhz. the high slew rate, exceptional output swing and high linearity of the opa2680 make it an ideal single supply adc driver. the circuit on the front page shows one possible interface particularly suited to dc-coupled pulse digitization requirements. figure 3 shows the ac-coupled test circuit of figure 2 modified for a capacitive (a/d) load and with an optional output pull-down resistor (r b ). the opa2680 in the circuit of figure 3 provides >200mhz bandwidth for a 2vp-p output swing. minimal 3rd harmonic distortion or two-tone, 3rd-order intermodulation distortion will be observed due to the very low crossover distortion in the opa2680 output stage. the limit of output spurious free dynamic range (sfdr) will be set by the 2nd har- monic distortion. without r b , the circuit of figure 3 mea- sured at 10mhz shows an sfdr of 65dbc. this may be improved by pulling additional dc bias current (i b ) out of the output stage through the optional r b resistor to ground (the output midpoint is at 2.5v for figure 3). adjusting i b gives the improvement in sfdr shown in figure 4. sfdr improvement is achieved for i b values up to 6ma, with worse performance for higher values. using the dual opa2680 in an iq receiver channel will give matched ac performance through high frequencies. figure 4. sfdr vs i b . 73 72 71 70 69 68 67 66 65 output pull-down current (ma) 012345678910 sfdr (dbc) v o = 2vp-p, 10mhz high performance dac transimpedance amplifier high frequency dds dacs require a low distortion output amplifier to retain their sfdr performance into real-world loads. a differential output drive implementation is shown in figure 5. the diagram shows the signal output current(s) connected into the virtual ground summing junction(s) of the opa2680, which is set up as a transimpedance stage or i-v converter. if the dac requires its outputs terminated to a compliance voltage other than ground for operation, the appropriate voltage level may be applied to the non- inverting inputs of the opa2680. the dc gain for this circuit is equal to r f . at high frequencies, the dac output capacitance (c d in figure 5) will produce a zero in the noise gain for the opa2680 that may cause peaking in the closed-loop frequency response. c f is added across r f to compensate for this noise gain peaking. to achieve a flat figure 3. single-supply adc input driver. one of two channels. 1/2 opa2680 402 w 50 w 402 w 59 w 1vp-p 698 w 698 w v i +5v 0.1? r s 30 w i b r b 50pf 0.1? 2.5v dc ?v ac adc input power supply decoupling not shown
opa2680 13 transimpedance frequency response, the pole in each feed- back network should be set to: 1/2 p r f c f = ? gbp/4 p r f c d which will give a corner frequency f C3db of approximately: f C3db = ? gbp/(2 p r f c d ) wideband video multiplexing one common application for video speed amplifiers which include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. this simple wired-or video multiplexer can be easily implemented using the op2680n (so-14 package only) as shown in figure 6. typically, channel switching is performed either on sync or retrace time in the video signal. the two inputs are approxi- mately equal at this time. the make-before-break disable characteristic of the opa2680n ensures that there is always one amplifier controlling the line when using a wired-or circuit like that shown in figure 6. since both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (82.5 w in this case). when one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. the gain and output matching resistor have been slightly increased to get a signal gain of +1 at the matched load and provide a 75 w output impedance to the cable. the video multiplexer connection (figure 6) also insures that the maximum differential voltage across the inputs of the unselected channel does not exceed the rated 1.2v maximum for standard video signal levels. the section on disable operation shows the turn-on and turn-off switching glitches using a 0v input for a single channel is typically less than 50mv. where two outputs are switched (as shown in figure 6), the output line is always under the control of one amplifier or the other due to the make-before-break disable timing. in this case, the switch- ing glitches for two 0v inputs drop to <20mv. figure 6. two-channel video multiplexer (so-14 package only). figure 5. high speed dacdifferential transimpedance amplifier 1/2 opa2680 1/2 opa2680 high speed dac v o = i o r f v o = i o r f r f1 r f2 c f1 c f2 gbp ? gain bandwidth product (hz) for the opa2680 c d1 c d2 i o i o 50 w 50 w 50 w 2k w 82.5 w 75 w cable 75 w load rg-59 82.5 w 75 w 402 w 340 w video 1 +5v +5v ?v 1/2 opa2680 1/2 opa2680 50 w 2k w 75 w 402 w 340 w video 2 ?v +5v v dis disa disb
14 opa2680 high speed delay circuit the opa2680 makes an ideal amplifier for a variety of active filter designs. shown in figure 7 is a circuit that utilizes the two amplifiers within the dual opa2680 to design a two-stage analog group delay adjustment circuit. for simplicity, the circuit assumes a dual supply ( 5v) operation, but it can also be modified to operate on signal supply. the input to the first filter stage is driven by the wideband buffer amplifier, buf601 to isolate the signal input from the filter network. the buf601 features an open- loop design, holding its output impedance at 4 w for frequen- cies in excess of 200mhz. each of the two filter stages is a 1st-order filter with a voltage gain of +1. the delay time through one filter is given by equation 1. equation 1: t gr0 = 2rc for a more accurate analysis of the circuit consider the group delay for the amplifiers. for example, in the case of the opa2680, the group delay in the bandwidth from 1mhz to 100mhz is approximately 1.0ns. to account for this, modify the transfer function, which now comes out to be: equation 2: t gr = 2 (2rc +t d ) with t d = (1/360) ? (d f /df) = delay of the op amp itself. the values of resistors r f and r g should be equal and low to avoid parasitic effects. if the all-pass filter is designed for very low delay times, include parasitic board capacitances to calculate the correct delay time. simulating this applica- tion using the pspice model of the opa2680 will allow this design to be tuned. differential receiver/driver a very versatile application for a dual operational amplier is the differential amplifier configuration shown in figure 8. with both amplifiers of the opa2680 connected for non-inverting operation, the circuit provides a high input impedance while the gain can easily be set by just one resistor, r g . when operated in low gains, the output swing may be limited as a result of the common-mode input swing limits of the amplifier itself. an interesting modifi- cation of this circuit is to place a capacitor in series with the r g . now the dc gain for each side is reduced to +1, while the ac gain still follows the standard transfer func- tion of g = 1 + 2r f /r g . this might be advantageous for applications processing only a frequency band which ex- cludes dc or very low frequencies. an input dc voltage resulting from input bias currents will not be amplified by the ac gain and can be kept low. this circuit can be used as a differential line receiver, driver, or as an interface to a differential input a/d converter. figure 7. two stage, all-pass network. figure 8. high speed differential receiver. r r f 402 w r g 402 w r f 402 w r g 402 w v in v out r 1/2 opa2680 buf601 c c 1/2 opa2680 50 w v i v i r o r o r f 402 w r f 402 w 50 w r g 1/2 opa2680 1/2 opa2680 v diff = 1 + v i ? v i 2r f r g
opa2680 15 design-in tools demonstration boards several pc boards are available to assist in the initial evalu- ation of circuit performance using the opa2680 in its two package styles. all of these are available free as an unpopulated pc board delivered with descriptive documenta- tion. the summary information for these boards is shown below: a good rule of thumb is to target the parallel combination of r f and r g (figure 1) to be less than approximately 300 w . the combined impedance r f || r g interacts with the invert- ing input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. assuming a 2pf total parasitic on the inverting node, hold- ing r f || r g < 300 w will keep this pole above 250mhz. by itself, this constraint implies that the feedback resistor r f can increase to several k w at high gains. this is acceptable as long as the pole formed by r f and any parasitic capaci- tance appearing in parallel is kept out of the frequency range of interest. bandwidth vs gain: non-inverting operation voltage feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. in theory, this relationship is described by the gain bandwidth product (gbp) shown in the specifications. ideally, dividing gbp by the non-inverting signal gain (also called the noise gain, or ng) will predict the closed-loop bandwidth. in practice, this only holds true when the phase margin approaches 90 , as it does in high gain configurations. at low gains (increased feedback factor), most amplifiers will exhibit a more com- plex response with lower phase margin. the opa2680 is compensated to give a slightly peaked response in a non- inverting gain of 2 (figure 1). this results in a typical gain of +2 bandwidth of 220mhz, far exceeding that predicted by dividing the 300mhz gbp by 2. increasing the gain will cause the phase margin to approach 90 and the bandwidth to more closely approach the predicted value of (gbp/ng). at a gain of +10, the 30mhz bandwidth shown in the typical specifications agrees with that predicted using the simple formula and the typical gbp of 300mhz. the frequency response in a gain of +2 may be modified to achieve exceptional flatness simply by increasing the noise gain to 2.5. one way to do this, without affecting the +2 signal gain, is to add an 804 w resistor across the two inputs in the circuit of figure 1. a similar technique may be used to reduce peaking in unity gain (voltage follower) applica- tions. for example, by using a 402 w feedback resistor along with a 402 w resistor across the two op amp inputs, the voltage follower response will be similar to the gain of +2 response of figure 2. reducing the value of the resistor across the op amp inputs will further limit the frequency response due to increased noise gain. the opa2680 exhibits minimal bandwidth reduction going to single supply (+5v) operation as compared with 5v. this is because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins is changed. inverting amplifier operation since the opa2680 is a general purpose, wideband volt- age feedback op amp, all of the familiar op amp applica- tion circuits are available to the designer. inverting opera- tion is one of the more common requirements and offers board part ordering product package number number opa2680u 8-lead so-8 dem-opa26xu mkt-352 opa2680n so-14 dem-opa26xn mkt-353 contact the burr-brown applications support line to request any of these boards. macromodels and applications support computer simulation of circuit performance using spice is often useful when analyzing the performance of analog circuits and systems. this is particularly true for video and rf amplifier circuits where parasitic capacitance and induc- tance can have a major effect on circuit performance. a spice model for the opa2680 is available through either the burr-brown internet web page (http://www.burr- brown.com) or as one model on a disk from the burr-brown applications department (1-800-548-6132). the applica- tion department is also available for design assistance at this number. these models do a good job of predicting small- signal ac and transient performance under a wide variety of operating conditions. they do not do as well in predicting the harmonic distortion or dg/dp characteristics. these models do not attempt to distinguish between the package types in their small-signal ac performance. operating suggestions optimizing resistor values since the opa2680 is a unity gain stable voltage feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. the primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. for a non-inverting unity gain follower application, the feedback connection should be made with a 25 w resistor, not a direct short. this will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. usually, the feedback resistor value should be between 200 w and 1.5k w . below 200 w , the feedback network will present additional output loading which can degrade the harmonic distortion performance of the opa2680. above 1.5k w , the typical parasitic capacitance (approximately 0.2pf) across the feedback resistor may cause unintentional band-limiting in the amplifier response.
16 opa2680 several performance benefits. figure 9 shows a typical inverting configuration where the i/o impedances and signal gain from figure 1 are retained in an inverting circuit configuration. ance is added in series with r g for calculating the noise gain (ng). the resultant ng is 2.8 for figure 9, as opposed to only 2 if r m could be eliminated as discussed above. the band- width will therefore be slightly lower for the gain of C2 circuit of figure 9 than for the gain of +2 circuit of figure 1. the third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the non-inverting input (r b ). if this resistor is set equal to the total dc resistance looking out of the inverting node, the output dc error, due to the input bias currents, will be reduced to (input offset current) ? r f . if the 50 w source impedance is dc-coupled in figure 9, the total resistance to ground on the inverting input will be 228 w . combining this in parallel with the feedback resistor gives the r b = 146 w used in this example. to reduce the additional high fre- quency noise introduced by this resistor, it is sometimes bypassed with a capacitor. as long as r b <350 w , the capacitor is not required since the total noise contribution of all other terms will be less than that of the op amps input noise voltage. as a minimum, the opa2680 requires an r b value of 50 w to damp out parasitic-induced peakinga direct short to ground on the non-inverting input runs the risk of a very high frequency instability in the input stage. output current and voltage the opa2680 provides output voltage and current capabili- ties that are unsurpassed in a low cost monolithic op amp. under no-load conditions at +25 c, the output voltage typically swings closer than 1v to either supply rail; the guaranteed swing limit is within 1.2v of either rail. into a 15 w load (the minimum tested load), it is guaranteed to deliver more than 135ma. the specifications described above, though familiar in the industry, consider voltage and current limits separately. in many applications, it is the voltage ? current, or v-i product, which is more relevant to circuit operation. refer to the output voltage and current limitations plot in the typical performance curves. the x and y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. the four quadrants give a more detailed view of the opa2680s output drive capabili- ties, noting that the graph is bounded by a safe operating area of 1w maximum internal power dissipation for each channel separately. superimposing resistor load lines onto the plot shows that the opa2680 can drive 2.5v into 25 w or 3.5v into 50 w without exceeding the output capabilities or the 1w dissipation limit. a 100 w load line (the standard test circuit load) shows the full 3.9v output swing capabil- ity, as shown in the typical specifications. the minimum specified output voltage and current specifi- cations over temperature are set by worst-case simulations at the cold temperature extreme. only at cold startup will the output current and voltage decrease to the numbers shown in the guaranteed tables. as the output transistors deliver power, their junction temperatures will increase, decreasing their v be s (increasing the available output voltage swing) and increasing their current gains (increasing the available out- put current). in steady-state operation, the available output 1/2 opa2680 50 w r f 402 w r g 200 w r b 146 w r m 67 w source +5v ?v r o 50 w 0.1 f 6.8 f + 0.1 f 0.1 f 6.8 f + 50 w load v o v i = ? v o v i figure 9. gain of C2 example circuit. in the inverting configuration, three key design consider- ation must be noted. the first is that the gain resistor (r g ) becomes part of the signal channel input impedance. if input impedance matching is desired (which is beneficial when- ever the signal is coupled through a cable, twisted pair, long pc board trace or other transmission line conductor), r g may be set equal to the required termination value and r f adjusted to give the desired gain. this is the simplest approach and results in optimum bandwidth and noise per- formance. however, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. for an inverting gain of C2, setting r g to 50 w for input matching eliminates the need for r m but requires a 100 w feedback resistor. this has the interesting advantage that the noise gain becomes equal to 2 for a 50 w source impedancethe same as the non-inverting circuits considered above. however, the amplifier output will now see the 100 w feedback resistor in parallel with the external load. in general, the feedback resistor should be limited to the 200 w to 1.5k w range. in this case, it is preferable to increase both the r f and r g values as shown in figure 8, and then achieve the input matching impedance with a third resistor (r m ) to ground. the total input impedance becomes the parallel combination of r g and r m . the second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and influences the bandwidth. for the example in figure 9, the r m value combines in parallel with the external 50 w source impedance, yielding an effec- tive driving impedance of 50 w || 67 w = 28.6 w . this imped-
opa2680 17 voltage and current will always be greater than that shown in the over-temperature specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient. to maintain maximum output stage linearity, no output short-circuit protection is provided. this will not normally be a problem since most applications include a series match- ing resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. however, shorting the output pin directly to the adjacent positive power supply pin (8-pin packages) will, in most cases, destroy the amplifier. including a small series resistor (5 w ) in the power supply line will protect against this. always place the 0.1 m f decoupling capacitor directly on the supply pins. driving capacitive loads one of the most demanding and yet very common load conditions for an op amp is capacitive loading. often, the capacitive load is the input of an a/d converterincluding additional external capacitance which may be recommended to improve a/d linearity. a high speed, high open-loop gain amplifier like the opa2680 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. when the amplifiers open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. several external solutions to this problem have been suggested. when the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the sim- plest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. this does not eliminate the pole from the loop re- sponse, but rather shifts it and adds a zero at a higher frequency. the additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. the typical performance curves show the recommended r s versus capacitive load and the resulting frequency re- sponse at the load. parasitic capacitive loads greater than 2pf can begin to degrade the performance of the opa2680. long pc board traces, unmatched cables, and connections to multiple devices can easily exceed this value. always con- sider this effect carefully, and add the recommended series resistor as close as possible to the opa2680 output pin (see board layout guidelines). the criterion for setting this r s resistor is a maximum bandwidth, flat frequency response at the load. for the opa2680 operating in a gain of +2, the frequency response at the output pin is already slightly peaked without the capacitive load requiring relatively high values of r s to flatten the response at the load. increasing the noise gain will reduce the peaking as described previously. the circuit of figure 10 demonstrates this technique, allowing lower val- ues of r s to be used for a given capacitive load. 100 90 80 70 60 50 40 30 20 10 0 capacitive load (pf) 1 10 100 series resistor, r s ( w ) ng = 2 ng = 3 ng = 4 figure 11. required r s vs noise gain. this gain of +2 circuit includes a noise gain tuning resistor across the two inputs to increase the noise gain, increasing the unloaded phase margin for the op amp. although this technique will reduce the required r s resistor for a given capacitive load, it does increase the noise at the output. it also will decrease the loop gain, nominally decreasing the distortion performance. if, however, the dominant distortion mechanism arises from a high r s value, significant dynamic range improvement can be achieved using this technique. figure 11 shows the required r s versus c load parametric on noise gain using this technique. this is the circuit of figure 10 with r ng adjusted to increase the noise gain (increasing the phase margin) then sweeping c load and finding the required r s to get a flat frequency response. this plot also gives the required r s versus c load for the opa2680 oper- ated at higher signal gains. distortion performance the opa2680 provides good distortion performance into a 100 w load on 5v supplies. relative to alternative solu- tions, it provides exceptional performance into lighter loads and/or operating on a single +5v supply. generally, until the fundamental signal reaches very high frequency or power levels, the 2nd harmonic will dominate the distortion with a negligible 3rd harmonic component. focusing then on the 2nd harmonic, increasing the load impedance im- figure 10. capacitive load driving with noise gain tuning. 1/2 opa2680 402 w 175 w 402 w +5v 50 w 50 w c load r ng v o r ?v power supply decoupling not shown.
18 opa2680 proves distortion directly. remember that the total load includes the feedback network; in the non-inverting configu- ration (figure 1) this is sum of r f + r g , while in the inverting configuration, it is just r f . also, providing an additional supply decoupling capacitor (0.1 m f) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3db to 6db). in most op amps, increasing the output voltage swing in- creases harmonic distortion directly. the new output stage used in the opa2680 actually holds the difference between fundamental power and the 2nd and 3rd harmonic powers relatively constant with increasing output power until very large output swings are required (>4vp-p). this also shows up in the two-tone, 3rd-order intermodulation spurious (im3) response curves. the 3rd-order spurious levels are extremely low at low output power levels. the output stage continues to hold them low even as the fundamental power reaches very high levels. as the typical performance curves show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. as the fundamen- tal power level increases, the dynamic range does not de- crease significantly. for 2 tones centered at 20mhz, with 10dbm/tone into a matched 50 w load (i.e., 2vp-p for each tone at the load, which requires 8vp-p for the overall two- tone envelope at the output pin), the typical performance curves show 57dbc difference between the test tone powers and the 3rd-order intermodulation spurious powers. this exceptional performance improves further when operating at lower frequencies. noise performance high slew rate, unity gain stable, voltage feedback op amps usually achieve their slew rate at the expense of a higher input noise voltage. the 4.8nv/ ? hz input voltage noise for the opa2680 is, however, much lower than comparable amplifiers. the input-referred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. figure 12 shows the op amp noise analysis model with all the noise terms included. in this model, all noise terms are taken to be noise voltage or current density terms in either nv/ ? hz or pa/ ? hz. the total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. equation 3 shows the general form for the output noise voltage using the terms shown in figure 12. equation 3: dividing this expression by the noise gain (ng = (1+r f /r g )) will give the equivalent input-referred spot noise voltage at the non-inverting input, as shown in equation 4. equation 4: evaluating these two equations for the opa2680 circuit and component values shown in figure 1 will give a total output spot noise voltage of 11nv/ ? hz and a total equivalent input spot noise voltage of 5.5nv/ ? hz. this is including the noise added by the bias current cancellation resistor (175 w ) on the non-inverting input. this total input-referred spot noise voltage is only slightly higher than the 4.8nv/ ? hz specifica- tion for the op amp voltage noise alone. this will be the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 300 w . keeping both (r f || r g ) and the non-inverting input source impedance less than 300 w will satisfy both noise and frequency response flatness considerations. since the resis- tor-induced noise is relatively negligible, additional capaci- tive decoupling across the bias current cancellation resistor (r b ) for the inverting op amp configuration of figure 9 is not required. dc accuracy and offset control the balanced input stage of a wideband voltage feedback op amp allows good output dc accuracy in a wide variety of applications. the power supply current trim for the opa2680 gives even tighter control than comparable amplifiers. al- though the high speed input stage does require relatively high input bias current (typically 14 m a out of each input terminal), the close matching between them may be used to reduce the output dc error caused by this current. the total output offset voltage may be considerably reduced by match- ing the dc source resistances appearing at the two inputs. this reduces the output dc error due to the input bias currents to the offset current times the feedback resistor. evaluating the configuration of figure 1, using worst-case +25 c input offset voltage and current specifications, gives a worst-case output offset voltage equal to: (ng ? v os(max) ) (r f ? i os(max) ) = (2 ? 4.5mv) (402 w ? 0.7 m a) = 9.3mv C (ng = non-inverting signal gain) 4kt r g r g r f r s 1/2 opa2680 i bi e o i bn 4kt = 1.6e ?0j at 290? e rs e ni 4ktr s ? 4ktr f ? figure 12. op amp noise analysis model. e n = e ni 2 + i bn r s () 2 +4 ktr s + i bi r f ng ? ? ? 2 + 4 ktr f ng e o = e ni 2 + i bn r s () 2 +4 ktr s () ng 2 + i bi r f () 2 +4 ktr f ng
opa2680 19 a fine scale output offset null, or dc operating point adjustment, is often required. numerous techniques are available for introducing dc offset control into an op amp circuit. most of these techniques eventually reduce to add- ing a dc current through the feedback resistor. in selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. if the signal path is intended to be non-inverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. if the signal path is intended to be inverting, applying the offset control to the non-inverting input may be considered. however, the dc offset voltage on the summing junction will set up a dc current back into the source which must be considered. applying an offset adjust- ment to the inverting op amp input can change the noise gain and frequency response flatness. for a dc-coupled invert- ing amplifier, figure 13 shows one example of an offset adjustment technique that has minimal impact on the signal frequency response. in this case, the dc offsetting current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. this will insure that the adjustment circuit has minimal effect on the loop gain and hence the frequency response. eventually turning on those two diodes ( ? 100ua). at this point, any further current pulled out of v dis goes through those diodes holding the emitter-base voltage of q1 at approximately zero volts. this shuts off the collector current out of q1, turning the amplifier off. the supply current in the disable mode are only those required to operate the circuit of figure 14. additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). when disabled, the output and input nodes go to a high impedance state. if the opa2680 is operating in a gain of +1, this will show a very high impedance at the output and exceptional signal isolation. if operating at a gain greater than +1, the total feedback network resistance (r f + r g ) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. if configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (r f + r g ) and the isolation will be very poor as a result. one key parameter in disable operation is the output glitch when switching in and out of the disabled mode. figure 15 shows these glitches for the circuit of figure 1 with the input signal at 0v. the glitch waveform at the output pin is plotted along with the dis pin voltage. r f 1k w ?00mv output adjustment = ? = ? supply decoupling not shown 5k w 5k w 328 w 0.1? r g 500 w v i 20k w 10k w 0.1? ?v +5v 1/2 opa2680 +5v ?v v o v o v i r f r g figure 13. dc-coupled, inverting gain of C2, with offset adjustment. 25k w 110k w 15k w i s control ? s +v s v dis q1 figure 14. simplified disable control circuit. 40 20 0 ?0 ?0 time (20ns/div) output voltage (20mv/div) output voltage (0v input) v dis 0.2v 4.8v figure 15. disable/enable glitch. disable operation (so-14 package only) the opa2680n provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. if the dis control pin is left unconnected, the opa2680n will operate nor- mally. to disable, the control pin must be asserted low. figure 14 shows a simplified internal circuit for the disable control feature. in normal operation, base current to q1 is provided through the 110k w resistor, while the emitter current through the 15k w resistor sets up a voltage drop that is inadequate to turn on the two diodes in q1s emitter. as v dis is pulled low, additional current is pulled through the 15k w resistor
20 opa2680 the transition edge rate (dv/dt) of the dis control line will influence this glitch. for the plot of figure 15, the edge rate was reduced until no further reduction in glitch amplitude was observed. this approximately 1v/ns maximum slew rate may be achieved by adding a simple rc filter into the dis pin from a higher speed logic line. if extremely fast transition logic is used, a 2k w series resistor between the logic gate and the dis input pin will provide adequate bandlimiting using just the parasitic input capacitance on the dis pin while still ensuring adequate logic level swing. thermal analysis due to the high output power capability of the opa2680, heatsinking or forced airflow may be required under extreme operating conditions. maximum desired junction tempera- ture will set the maximum allowed internal power dissipa- tion as described below. in no case should the maximum junction temperature be allowed to exceed 175 c. operating junction temperature (t j ) is given by t a + p d ? q ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipated in the output stage (p dl ) to deliver load power. quiescent power is simply the specified no-load supply current times the total supply voltage across the part. p dl will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). under this condition, p dl = v s 2 /(4?r l ) where r l includes feedback network loading. note that it is the power in the output stage and not into the load that determines internal power dissipation. as a worst-case example, compute the maximum t j using an opa2680u (so-8 package) in the circuit of figure 1 operat- ing at the maximum specified ambient temperature of +85 c and with both outputs driving a grounded 20 w load to +2.5v. p d = 10v ? 14.4ma + 2 [5 2 /(4?(20 w || 804 w ))] = 785mw maximum t j = +85 c + (0.79w ? 125 c/w) = 184 c. this absolute worst-case condition exceeds the specified maximum junction temperature. actual p dl will always be less than that considered here. carefully consider maximum t j in your application. board layout guidelines achieving optimum performance with a high frequency amplifier like the opa2680 requires careful attention to board layout parasitics and external component types. rec- ommendations that will optimize performance include: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output and inverting input pins can cause instability: on the non- inverting input, it can react with the source impedance to cause unintentional bandlimiting. to reduce unwanted ca- pacitance, a window around the signal i/o pins should be opened in all of the ground and power planes around those pins. otherwise, ground and power planes should be unbro- ken elsewhere on the board. b) minimize the distance (<0.25") from the power supply pins to high frequency 0.1 m f decoupling capacitors. at the device pins, the ground and power plane layout should not be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. the power supply connections should always be decoupled with these capaci- tors. an optional supply decoupling capacitor (0.1 m f) across the two power supplies (for bipolar operation) will improve 2nd harmonic distortion performance. larger (2.2 m f to 6.8 m f) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. these may be placed somewhat farther from the device and may be shared among several devices in the same area of the pc board. c) careful selection and placement of external compo- nents will preserve the high frequency performance of the opa2680. resistors should be a very low reactance type. surface-mount resistors work best and allow a tighter overall layout. metal film or carbon composition axially- leaded resistors can also provide good high frequency per- formance. again, keep their leads and pc board traces as short as possible. never use wirewound type resistors in a high frequency application. since the output pin and invert- ing input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. other network components, such as non-inverting input termination resis- tors, should also be placed close to the package. where double-side component mounting is allowed, place the feed- back resistor directly under the package on the other side of the board between the output and inverting input pins. even with a low parasitic capacitance shunting the external resis- tors, excessively high resistor values can create significant time constants that can degrade performance. good axial metal film or surface-mount resistors have approximately 0.2pf in shunt with the resistor. for resistor values >1.5k w , this parasitic capacitance can add a pole and/or zero below 500mhz that can effect circuit operation. keep resistor values as low as possible consistent with load driving con- siderations. the 402 w feedback used in the typical perfor- mance specifications is a good starting point for design. note that a 25 w feedback resistor, rather than a direct short, is suggested for the unity gain follower application. this effectively isolates the inverting input capacitance from the output pin that would otherwise cause additional peaking in the gain of +1 frequency response. d) connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. for short connections, consider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50 to 100mils) should be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r s from the plot of recommended r s vs capacitive load. low parasitic capacitive loads (<5pf) may not need an r s since the
opa2680 21 opa2680 is nominally compensated to operate with a 2pf parasitic load. higher parasitic capacitive loads without an r s are allowed as the signal gain increases (increasing the unloaded phase margin) if a long trace is required, and the 6db signal loss intrinsic to a doubly terminated transmission line is acceptable, implement a matched impedance trans- mission line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout techniques). a 50 w environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. with a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the opa2680 is used as well as a terminating shunt resistor at the input of the destination device. remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. the high output voltage and current capa- bility of the opa2680 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. if the 6db attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of recommended r s vs capacitive load. this will not preserve signal integ- rity as well as a doubly terminated line. if the input imped- ance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) socketing a high speed part like the opa2680 is not recommended. the additional lead length and pin-to-pin capacitance introduced by the socket can create an ex- tremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. best results are obtained by soldering the opa2680 onto the board. figure 16. internal esd protection. external pin +v cc ? cc internal circuitry input and esd protection the opa2680 is built using a very high speed complemen- tary bipolar process. the internal junction breakdown volt- ages are relatively low for these very small geometry de- vices. these breakdowns are reflected in the absolute maxi- mum ratings table. all device pins are protected with internal esd protection diodes to the power supplies as shown in figure 16. these diodes provide moderate protection to input overdrive voltages above the supplies as well. the protection diodes can typically support 30ma continuous current. where higher currents are possible (e.g., in systems with 15v supply parts driving into the opa2680), current-limiting series resistors should be added into the two inputs. keep these resistor values as low as possible since high values degrade both noise performance and frequency response.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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