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isplsi 1048e in-system programmable high density pld 1048e_11 1 use isplsi 1048ea for new designs functional block diagram features high density programmable logic 8,000 pld gates 96 i/o pins, twelve dedicated inputs 288 registers high-speed global interconnects wide input gating for fast counters, state machines, address decoders, etc. small logic block size for random logic functionally and pin-out compatible to isplsi 1048c high performance e 2 cmos technology f max = 125 mhz maximum operating frequency t pd = 7.5 ns propagation delay ttl compatible inputs and outputs electrically eraseable and reprogrammable non-volatile 100% tested at time of manufacture in-system programmable in-system programmable (isp) 5v only increased manufacturing yields, reduced time-to- market and improved product quality reprogram soldered devices for faster prototyping offers the ease of use and fast system speed of plds with the density and flexibility of field programmable gate arrays complete programmable device can combine glue logic and structured designs enhanced pin locking capability four dedicated clock input pins synchronous and asynchronous clocks programmable output slew rate control to minimize switching noise flexible pin placement optimized global routing pool provides global interconnectivity output routing pool output routing pool f7 f6 f5 f4 f3 f2 f1 f0 b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 output routing pool output routing pool output routing pool clk e7 e6 e5 e4 e3 e2 e1 e0 c0 c1 c2 c3 c4 c5 c6 c7 d7 d6 d5 d4 d3 d2 d1 d0 output routing pool logic array dq dq dq dq global routing pool (grp) glb 0139g1a-isp description the isplsi 1048e is a high density programmable logic device containing 288 registers, 96 universal i/o pins, 12 dedicated input pins, four dedicated clock input pins, two dedicated global oe input pins, and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 1048e offers 5v non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. a functional superset of the isplsi 1048 archi- tecture, the isplsi 1048e device adds two new global output enable pins and two additional dedicated inputs. the basic unit of logic on the isplsi 1048e device is the generic logic block (glb). the glbs are labeled a0, a1?7 (see figure 1). there are a total of 48 glbs in the isplsi 1048e device. each glb has 18 inputs, a pro- grammable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any other glb on the device. copyright ?2002 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. january 2002 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com
specifications isplsi 1048e 2 use isplsi 1048ea for new designs functional block diagram figure 1. isplsi 1048e functional block diagram the device also has 96 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, registered in- put, latched input, output or bi-directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be programmed independently for fast or slow output slew rate to mini- mize overall output switching noise. eight glbs, 16 i/o cells, two dedicated inputs and one orp are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 16 universal i/o cells by the orp. each isplsi 1048e device contains six megablocks. the grp has, as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 1048e device are selected using the clock distribution network. four dedicated clock pins (y0, y1, y2 and y3) are brought into the distribution network, and five clock outputs (clk 0, clk 1, clk 2, ioclk 0 and ioclk 1) are provided to route clocks to the glbs and i/o cells. the clock distribution network can also be driven from a special clock glb (d0). the logic of this glb allows the user to create an internal clock from a combination of internal signals within the device. output routing pool (orp) b0 b1 b2 b3 b4 b5 b6 b7 output routing pool (orp) c0 c1 c2 c3 c4 c5 c6 c7 output routing pool (orp) f7 f6 f5 f4 f3 f2 f1 f0 input bus output routing pool (orp) e7 e6 e5 e4 e3 e2 e1 e0 input bus a0 a1 a2 a3 a4 a5 a6 a7 output routing pool (orp) generic logic blocks (glbs) megablock input bus global routing pool (grp) clk 0 clk 1 clk 2 ioclk 0 ioclk 1 clock distribution network d7 d6 d5 d4 d3 d2 d1 d0 output routing pool (orp) i/o 94 i/o 95 i/o 93 i/o 92 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 in 11 i/o 78 i/o 79 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 in 9 in 10 i/o 17 i/o 16 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 sdo/ in 3 y 0 y 1 y 2 y 3 i/o 33 i/o 32 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 sclk/ in 5 in 4 in 7 in 6 i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 i/o 0 i/o 1 i/o 2 i/o 3 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 sdi/in 0 mode/in 1 i/o 4 i/o 5 ispen reset input bus input bus lnput bus 0139f(2)-48b-isp in 8 goe 0 goe 1 in 2
specifications isplsi 1048e 3 use isplsi 1048ea for new designs absolute maximum ratings 1 supply voltage v cc . ................................. -0.5 to +7.0v input voltage applied ........................ -2.5 to v cc +1.0v off-state output voltage applied ..... -2.5 to v cc +1.0v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating conditions capacitance (t a =25 o c, f=1.0 mhz) data retention specifications c symbol table 2-0006/1048e c parameter y0 clock capacitance 15 units typical test conditions 1 2 8 dedicated input, i/o, y1, y2, y3, clock capacitance pf pf v = 5.0v, v = 2.0v v = 5.0v, v = 2.0v cc cc pin pin t a = 0 c to + 70 c t a = -40 c to + 85 c symbol table 2-0005/1048e v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 4.75 4.5 2.0 0 5.25 5.5 v cc +1 0.8 v v v v commercial industrial table 2-0008/1048e parameter data retention minimum maximum units erase/reprogram cycles 20 10000 ? ? years cycles
specifications isplsi 1048e 4 use isplsi 1048ea for new designs switching test conditions dc electrical characteristics over recommended operating conditions output load conditions (see figure 2) figure 2. test load input pulse levels table 2-0003/1048e input rise and fall time input timing reference levels output timing reference levels output load gnd to 3.0v 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. 3 ns 10% to 90% + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a test condition r1 r2 cl a 470 ? 390 ? 35pf b 390 ? 35pf 470 ? 390 ? 35pf active high active low c 470 ? 390 ? 5pf 390 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004a v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using twelve 16-bit counters. 3. typical values are at v = 5v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007/1048e 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current ispen input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 3.5v v v 0v v v (max.) 0v v v 0v v v v = 5v, v = 0.5v v = 0.0v, v = 3.0v f = 1 mhz ol oh in il in cc in il in il cc out clock il ih condition min. typ. max. units 3 ? 2.4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 175 175 0.4 ? 10 -10 -150 -150 -200 ? ? v v a a a a ma ma ma cc a out cc cc commercial industrial
specifications isplsi 1048e 5 use isplsi 1048ea for new designs external timing parameters over recommended operating conditions t pd1 units test cond. 1. unless noted otherwise, all parameters use a grp load of 4 glbs, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2-0030a/1048e 1 4 3 1 tsu2 + tco1 ( ) -90 min. max. description # 2 parameter a1 data propagation delay, 4pt bypass, orp bypass ? 10.0 ns t pd2 a2 data propagation delay, worst case path ? ns f max (int.) a3 clock frequency with internal feedback 90.9 ? mhz f max (ext.) ? 4 clock frequency with external feedback ? mhz f max (tog.) ? 5 clock frequency, max. toggle ? mhz t su1 ? 6 glb reg. setup time before clock,4 pt bypass ? ns t co1 a7 glb reg. clock to output delay, orp bypass ? ns t h1 ? 8 glb reg. hold time after clock, 4 pt bypass ? ns t su2 ? 9 glb reg. setup time before clock ? ns t co2 ? 10 glb reg. clock to output delay ? ns t h2 ? 11 glb reg. hold time after clock ? ns t r1 a1 2 ext. reset pin to output delay ? ns t rw1 ? 13 ext. reset pulse duration ? ns t ptoeen b1 4 input to output enable ? ns t ptoedis c1 5 input to output disable ? ns t wh ? 18 external synchronous clock pulse duration, high 4.0 ns t wl ? 19 external synchronous clock pulse duration, low 4.0 ns t su3 ? 20 i/o reg. setup time before ext. sync clock (y2, y3) ? ns t h3 ? 21 i/o reg. hold time after ext. sync. clock (y2, y3) ? ns 71.0 125.0 6.5 0.0 7.5 0.0 6.5 4.0 0.0 12.5 6.5 7.5 13.5 15.0 15.0 ? ? ( ) 1 twh + twl t goeen b1 6 global oe output enable ? ns 9.0 t goedis c1 7 global oe output disable ? ns -125 min. max. ? 7.5 ? 125.0 ? ? ? ? ? 0.0 6.5 ? 0.0 ? 5.0 ? ? 3.0 3.0 3.0 ? 0.0 ? 91.0 167.0 5.5 4.5 ? ? 5.5 ? 10.0 ? 12.0 12.0 ? ? 10.0 ? 7.0 ? 7.0 9.0 -100 min. max. ? 10.0 ? 100.0 ? ? ? ? ? ? ? ? ? ? ? ? ? 4.0 4.0 ? ? 71.0 125.0 6.5 0.0 7.5 0.0 6.5 3.5 0.0 12.5 6.5 7.5 13.5 15.0 15.0 ? ? ? 9.0 ? 9.0
specifications isplsi 1048e 6 use isplsi 1048ea for new designs external timing parameters over recommended operating conditions t pd1 units test cond. 1. unless noted otherwise, all parameters use a grp load of 4 glbs, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2-0030b/1048e 1 4 3 1 tsu2 + tco1 ( ) -50 min. max. description # 2 parameter a1 data propagation delay, 4pt bypass, orp bypass ? 20.0 ns t pd2 a2 data propagation delay, worst case path ? ns f max (int.) a3 clock frequency with internal feedback 50.0 ? mhz f max (ext.) ? 4 clock frequency with external feedback ? mhz f max (tog.) ? 5 clock frequency, max. toggle ? mhz t su1 ? 6 glb reg. setup time before clock,4 pt bypass ? ns t co1 a7 glb reg. clock to output delay, orp bypass ? ns t h1 ? 8 glb reg. hold time after clock, 4 pt bypass ? ns t su2 ? 9 glb reg. setup time before clock ? ns t co2 ? 10 glb reg. clock to output delay ? ns t h2 ? 11 glb reg. hold time after clock ? ns t r1 a1 2 ext. reset pin to output delay ? ns t rw1 ? 13 ext. reset pulse duration ? ns t ptoeen b1 4 input to output enable ? ns t ptoedis c1 5 input to output disable ? ns t wh ? 18 external synchronous clock pulse duration, high 6.5 ns t wl ? 19 external synchronous clock pulse duration, low 6.5 ns t su3 ? 20 i/o reg. setup time before ext. sync clock (y2, y3) ? ns t h3 ? 21 i/o reg. hold time after ext. sync. clock (y2, y3) ? ns 42.0 77.0 12.0 0.0 14.5 0.0 13.0 6.5 0.0 24.5 9.5 12.0 20.5 24.0 24.0 ? ? ( ) 1 twh + twl t goeen b1 6 global oe output enable ? ns 16.0 t goedis c1 7 global oe output disable ? ns 16.0 -70 min. max. ? 15.0 ? 70.0 ? ? ? ? ? ? ? ? ? ? ? ? ? 5.0 5.0 ? ? 56.0 100.0 9.0 0.0 11.0 0.0 10.0 4.0 0.0 18.5 7.0 9.0 15.0 18.0 18.0 ? ? ? 12.0 ? 12.0
specifications isplsi 1048e 7 use isplsi 1048ea for new designs internal timing parameters 1 t iobp 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036a/1048e inputs units -100 min. -90 min. max. max. description # 2 parameter 22 i/o register bypass ? ? 0.5 ns t iolat 23 i/o latch delay ? ? 2.5 ns t grp1 29 grp delay, 1 glb load ? ? 2.2 ns glb t 1ptxor 36 1 product term/xor path delay ? ? 6.5 ns t 20ptxor 37 20 product term/xor path delay ? ? 6.5 ns t xoradj 38 xor adjacent path delay ? ? 7.3 ns t gbp 39 glb register bypass delay ? ? 0.4 ns t gsu 40 glb register setup time before clock ? 0.1 ? ns t gh 41 glb register hold time after clock ? 6.4 ? ns t gco 42 glb register clock to output delay ? ? 2.0 ns 3 t gro 43 glb register reset to output delay ? ? 6.3 ns t ptre 44 glb product term reset to register delay ? ? 5.0 ns t ptoe 45 glb product term output enable to i/o cell delay ? ? 5.7 ns t ptck 46 glb product term clock delay 4.0 5.2 ns orp 0.3 2.3 grp 1.9 t 4ptbpc 34 4 product term bypass path delay (combinatorial) ? ? 5.4 ns 4.6 5.8 6.3 1.0 5.3 t 4ptbpr 35 4 product term bypass path delay (registered) ? ? 6.3 ns 5.3 0.5 5.3 2.5 6.2 4.5 7.2 3.5 4.7 t orp 47 orp delay ? ? 1.0 ns t orpbp 48 orp bypass delay ? ? 0.0 ns 1.0 0.0 t iosu 24 i/o register setup time before clock 3.5 4.0 ? ns ? t ioh 25 i/o register hold time after clock 0.0 -0.5 ? ns ? t ioco 26 i/o register clock to out delay ? ? 5.0 ns 5.0 t ior 27 i/o register reset to out delay ? ? 5.0 ns 5.0 t din 28 dedicated input delay ? ? 2.9 ns 2.7 t grp4 30 grp delay, 4 glb loads ? ? 2.4 ns t grp8 31 grp delay, 8 glb loads ? ? 2.7 ns t grp16 32 grp delay, 16 glb loads ? ? 3.3 ns t grp48 33 grp delay, 48 glb loads ? ? 5.7 ns 2.4 2.6 3.0 5.4 -125 min. max. ? ? ? ? ? ? ? ? ? ? ? ? ? 0.3 1.9 1.8 ? 3.6 5.0 5.0 0.4 3.9 ? 4.0 0.1 4.5 2.3 4.9 3.9 5.4 2.9 4.0 ? ? 1.0 0.0 3.0 ? 0.0 ? ? 4.6 ? 4.6 ? 2.3 ? ? ? ? 2.0 2.3 2.8 4.9
specifications isplsi 1048e 8 use isplsi 1048ea for new designs internal timing parameters 1 t iobp 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036b/1048e inputs units -70 min. -50 min. max. max. description # 2 parameter 22 i/o register bypass ? ? 0.7 ns t iolat 23 i/o latch delay ? ? 4.7 ns t grp1 29 grp delay, 1 glb load ? ? 5.1 ns glb t 1ptxor 36 1 product term/xor path delay ? ? 10.5 ns t 20ptxor 37 20 product term/xor path delay ? ? 10.5 ns t xoradj 38 xor adjacent path delay ? ? 11.7 ns t gbp 39 glb register bypass delay ? ? 2.2 ns t gsu 40 glb register setup time before clock ? 0.0 ? ns t gh 41 glb register hold time after clock ? 11.5 ? ns t gco 42 glb register clock to output delay ? ? 3.0 ns 3 t gro 43 glb register reset to output delay ? ? 7.3 ns t ptre 44 glb product term reset to register delay ? ? 7.9 ns t ptoe 45 glb product term output enable to i/o cell delay ? ? 10.0 ns t ptck 46 glb product term clock delay 6.9 8.3 ns orp 0.6 3.6 grp 3.5 t 4ptbpc 34 4 product term bypass path delay (combinatorial) ? ? 10.7 ns 8.4 8.4 9.4 1.6 8.5 t 4ptbpr 35 4 product term bypass path delay (registered) ? ? 9.2 ns 7.4 0.1 8.5 2.0 6.3 6.1 6.8 5.1 6.4 t orp 47 orp delay ? ? 2.5 ns t orpbp 48 orp bypass delay ? ? 0.0 ns 2.0 0.0 t iosu 24 i/o register setup time before clock 4.1 6.5 ? ns ? t ioh 25 i/o register hold time after clock -0.6 -0.7 ? ns ? t ioco 26 i/o register clock to out delay ? ? 7.0 ns 6.0 t ior 27 i/o register reset to out delay ? ? 7.0 ns 6.0 t din 28 dedicated input delay ? ? 6.1 ns 4.3 t grp4 30 grp delay, 4 glb loads ? ? 5.4 ns t grp8 31 grp delay, 8 glb loads ? ? 5.8 ns t grp16 32 grp delay, 16 glb loads ? ? 6.6 ns t grp48 33 grp delay, 48 glb loads ? ? 9.8 ns 3.7 4.1 4.8 7.5
specifications isplsi 1048e 9 use isplsi 1048ea for new designs internal timing parameters 1 t ob 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. table 2-0037a/1048e outputs units -100 min. -90 min. max. max. description # parameter 49 output buffer delay ? ? 1.7 ns t oen 51 i/o cell oe to output enabled ? ? 6.4 ns t gy0 54 clock delay, y0 to global glb clock line (ref. clock) 2.0 2.8 2.8 ns global reset 2.0 5.1 clocks 2.0 t gr 59 global reset to glb and i/o registers ? ? 4.5 ns 4.3 t odis 52 i/o cell oe to output disabled ? ? 6.4 ns 5.1 t gy1/2 55 clock delay, y1 or y2 to global glb clock line 2.0 2.8 2.8 ns 2.0 t gcp 56 clock delay, clock glb to global glb clock line 0.8 0.8 1.8 ns 1.8 t ioy2/3 57 clock delay, y2 or y3 to i/o cell global clock line 0.0 0.0 0.5 ns 0.0 t iocp 58 clock delay, clock glb to i/o cell global clock line 0.8 0.8 1.8 ns 1.8 t goe 53 global oe ? ? 2.6 ns 3.9 t sl 50 output slew limited delay adder ? ? 12.0 ns 10.0 -125 min. max. ? ? 0.9 1.3 4.3 0.9 ? 2.8 ? 4.3 0.9 0.9 0.8 1.8 0.0 0.0 0.8 1.8 ? 2.7 ? 10.0
specifications isplsi 1048e 10 use isplsi 1048ea for new designs internal timing parameters 1 t ob 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. table 2-0037b/1048e outputs units -70 min. -50 min. max. max. description # parameter 49 output buffer delay ? ? 3.2 ns t oen 51 i/o cell oe to output enabled ? ? 7.9 ns t gy0 54 clock delay, y0 to global glb clock line (ref. clock) 2.8 3.3 3.3 ns global reset 2.2 6.9 clocks 2.8 t gr 59 global reset to glb and i/o registers ? ? 7.5 ns 4.5 t odis 52 i/o cell oe to output disabled ? ? 7.9 ns 6.9 t gy1/2 55 clock delay, y1 or y2 to global glb clock line 2.8 3.3 3.3 ns 2.8 t gcp 56 clock delay, clock glb to global glb clock line 0.8 0.8 1.8 ns 1.8 t ioy2/3 57 clock delay, y2 or y3 to i/o cell global clock line 0.1 0.0 0.7 ns 0.6 t iocp 58 clock delay, clock glb to i/o cell global clock line 0.8 0.8 1.8 ns 1.8 t goe 53 global oe ? ? 8.1 ns 5.1 t sl 50 output slew limited delay adder ? ? 12.0 ns 12.0
specifications isplsi 1048e 11 use isplsi 1048ea for new designs glb reg delay i/o pin (output) orp delay 0491 feedback reg 4 pt bypass 20 pt xor delays control pts input register clock distribution i/o pin (input) y0 y1,2,3 d q grp4 glb reg bypass orp bypass dq rst re oe ck i/o reg bypass i/o cell orp glb grp i/o cell #23 - 27 #30 #35 #34 comb 4 pt bypass #36 - 38 #55 - 58 #44 - 46 #54 #53 #47 #48 reset ded. in goe 0,1 #28 #22 rst #59 #59 #39 #40 - 43 #51, 52 #49, 50 grp loading delay #29, 31-33 derivations of t su, t h and t co from the product term clock 1 = = = = t su 2.2 ns logic + reg su - clock (min) ( t iobp + t grp4 + t 20ptxor) + ( t gsu) ? ( t iobp + t grp4 + t ptck(min)) (#22 + #30 + #37) + (#40) ? (#22 + #30 + #46) (0.3 + 2.0 + 5.0) + (0.1) ? (0.3 + 2.0 + 2.9) = = = = t h clock (max) + reg h - logic ( t iobp + t grp4 + t ptck(max)) + ( t gh) ? ( t iobp + t grp4 + t 20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 2.0 + 4.0) + (4.5) ? (0.3 + 2.0 + 5.0) = = = = t co clock (max) + reg co + output ( t iobp + t grp4 + t ptck(max)) + ( t gco) + ( t orp + t ob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3) table 2-0042/1048e derivations of t su, t h and t co from the clock glb 1 = = = = t su logic + reg su - clock (min) ( t iobp + t grp4 + t 20ptxor) + ( t gsu) ? ( t gy0(min) + t gco + t gcp(min)) (#22 + #30 + #37) + (#40) ? (#54 + #42 + #56) (0.3 + 2.0 + 5.0) + (0.1) ? (0.9 + 2.3 + 0.8) = = = = t h clock (max) + reg h - logic ( t gy0(max) + t gco + t gcp(max)) + ( t gh) ? ( t iobp + t grp4 + t 20ptxor) (#54 + #42 + #56) + (#41) ? (#22 + #30 + #37) (0.9 + 2.3 + 1.8) + (4.5) ? (0.3 + 2.0 + 5.0) = = = = t co clock (max) + reg co + output ( t gy0(max) + t gco + t gcp(max)) + ( t gco) + ( t orp + t ob) (#54 + #42 + #56) + (#42) + (#47 + #49) (0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3) 3.5 ns 10.9 ns 3.4 ns 2.2 ns 9.6 ns 1. calculations are based upon timing specifications for the isplsi 1048e-125. isplsi 1048e timing model
specifications isplsi 1048e 12 use isplsi 1048ea for new designs maximum grp delay vs. glb loads 3 1 8 16 32 glb loads grp delay (ns) 2 1 4 5 6 7 4 0127a/1048e 8 48 isplsi 1048e-50 isplsi 1048e-70 isplsi 1048e-90/100 isplsi 1048e-125 9 10 i cc can be estimated for the isplsi 1048e using the following equation: i cc = 20 + (# of pts * 0.42) + (# of nets * max. freq * 0.010) where: # of pts = number of product terms used in design # of nets = number of signals used in device max. freq = highest clock frequency to the device the i cc estimate is based on typical conditions (v cc = 5.0v, room temperature) and an assumption of 4 glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 0127b/1048e notes: configuration of twelve 16-bit counters, typical current at 5v, 25 c 180 220 260 300 340 380 02040608 0 100 120 140 f max (mhz) i cc (ma) isplsi 1048e power consumption power consumption in the isplsi 1048e device depends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 3 shows the relationship between power and operating speed. figure 3. typical device power consumption vs fmax
specifications isplsi 1048e 13 use isplsi 1048ea for new designs pin description dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb on the device. dedicated clock input. this clock input is connected to one of the clock inputs of all of the glbs on the device. input/output pins - these are the general purpose i/o pins used by the logic array. name table 2 - 0002c-48e pqfp / tqfp pin numbers description 21, 27, 34, 40, 52, 58, 66, 72, 85, 91, 98, 104, 117, 123, 2, 8, 22, 28, 35, 41, 53, 59, 67, 73, 86, 92, 99, 105, 118, 124, 3, 9, 23, 29, 36, 42, 54, 60, 68, 74, 87, 93, 100, 106, 119, 125, 4, 10, i/o 0 - i/o 5 i/o 6 - i/o 11 i/o 12 - i/o 17 i/o 18 - i/o 23 i/o 24 - i/o 29 i/o 30 - i/o 35 i/o 36 - i/o 41 i/o 42 - i/o 47 i/o 48 - i/o 53 i/o 54 - i/o 59 i/o 60 - i/o 65 i/o 66 - i/o 71 i/o 72 - i/o 77 i/o 78 - i/o 83 i/o 84 - i/o 89 i/o 90 - i/o 95 24, 30, 37, 43, 55, 61, 69, 75, 88, 94, 101, 107, 120, 126, 5, 11, 25, 31, 38, 44, 56, 62, 70, 76, 89, 95, 102, 108, 121, 127, 6, 12, 83 y1 15 y0 46 mode/in 1 1 input - this pin performs two functions. when ispen is logic low, it functions as pin to control the operation of the isp state machine. when ispen is high, it functions as a dedicated input pin. ground (gnd) gnd v vcc 1. pins have dual function capability. cc 26, 32, 39, 45, 57, 63, 71, 77, 90, 96, 103, 109, 122, 128, 7, 13 global output enable input pins. goe0, goe1 dedicated input pins to the device. in 2, in 4 64, 114 47, 51 84, 110, 111, in 6 - in 11 115, 116, 14 input - dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. when low, the mode, sdi, sdo and sclk controls become active. 18 ispen input - this pin performs two functions. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi/in 0 also is used as one of the two control pins for the isp state machine. when ispen is high, it functions as a dedicated input pin. 20 sdi/in 0 1 50 sdo/in 3 1 output/input - this pin performs two functions. when ispen is logic low, it functions as an output pin to read serial shift register data. when ispen is high, it functions as a dedicated input pin. 78 sclk/in 5 1 input - this pin performs two functions. when ispen is logic low, it functions as a clock pin for the serial shift register. when ispen is high, it functions as a dedicated input pin. active low (0) reset pin which resets all of the glb and i/o registers in the device. 19 reset dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or any i/o cell on the device. 80 y2 dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any i/o cell on the device. 79 y3 1, 97, 17, 112 33, 49, 65, 81, 16, 48, 82, 113
specifications isplsi 1048e 14 use isplsi 1048ea for new designs i/o 84 i/o 85 i/o 86 i/o 87 i/o 88 i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 in 11 y0 vcc gnd ispen reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 gnd i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 6 y1 vcc gnd y2 sclk/in 5 1 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 i/o 83 i/o 82 i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 in 10 in 9 vcc in 8 in 7 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 i/o 63 i/o 62 i/o 61 i/o 60 gnd i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 1 mode/in 1 vcc gnd 1 sdo/in 3 in 4 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 isplsi 1048e top view i/o 10 1 sdi/in 0 i/o 59 gnd y3 gnd gnd in 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 64 96 122 goe 0 goe 1 0124-48c 1. pins have dual function capability. pin configuration isplsi 1048e 128-pin pqfp pinout diagram
specifications isplsi 1048e 15 use isplsi 1048ea for new designs pin configuration isplsi 1048e 128-pin tqfp pinout diagram i/o 84 i/o 85 i/o 86 i/o 87 i/o 88 i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 in 11 y0 vcc gnd ispen reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 gnd i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 6 y1 vcc gnd y2 sclk/in 5 1 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 i/o 83 i/o 82 i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 in 10 in 9 vcc in 8 in 7 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 i/o 63 i/o 62 i/o 61 i/o 60 gnd i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 1 mode/in 1 vcc gnd 1 sdo/in 3 in 4 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 isplsi 1048e top view i/o 10 1 sdi/in 0 i/o 59 gnd y3 gnd gnd in 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 64 96 122 goe 0 goe 1 1. pins have dual function capability. 0124-48/tqfp
specifications isplsi 1048e 16 use isplsi 1048ea for new designs part number description isplsi 1048e ordering information grade blank = commercial i = industrial device number 1048e xxx x x x speed 125 = 125 mhz f max 100 = 100 mhz f max 90 = 90 mhz f max 70 = 70 mhz f max 50 = 50 mhz f max power l = low package q = pqfp t = tqfp ? device family 0212/1048e isplsi 50 50 128-pin pqfp 20 20 isplsi 1048e-50lq 128-pin tqfp isplsi 1048e-50lt table 2-0041a/1048e family f max (mhz) 90 90 70 ordering number package 128-pin pqfp 128-pin tqfp t pd (ns) 10 10 15 isplsi isplsi 1048e-90lq isplsi 1048e-90lt 128-pin pqfp isplsi 1048e-70lq 70 128-pin tqfp 15 isplsi 1048e-70lt 125 125 100 128-pin pqfp 128-pin tqfp 7.5 7.5 10 isplsi 1048e-125lq isplsi 1048e-125lt 128-pin pqfp isplsi 1048e-100lq 100 128-pin tqfp 10 isplsi 1048e-100lt commercial 70 128-pin pqfp 15 isplsi 1048e-70lqi* 50 128-pin pqfp 20 isplsi 1048e-50lqi* table 2-0041b/1048e family f max (mhz) ordering number package t pd (ns) isplsi industrial *use 1048e-70 for new 1048e-50 designs. package thermal characteristics for the isplsi 1048e-125lt, it is strongly recommended that the actual icc be verified to ensure that the maximum junction temperature (t j ) with power supplied is not exceeded. depending on the specific logic design and clock speed, airflow may be required to satisfy the maxi- mum allowable junction temperature (t j ) specification. please refer to the thermal management section of the lattice semiconductor data book or cd-rom for addi- tional information on calculating t j .

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