product selection guide parameter WS57C71C-45 WS57C71C-55 WS57C71C-70 address access time (max) 45 ns 55 ns 70 ns cs to output valid time (max) 20 ns 20 ns 30 ns WS57C71C 4-13 military high speed 32k x 8 cmos prom/rprom key features ultra-fast access time immune to latch-up ?45 ns ?up to 200 ma low power consumption esd protection exceeds 2000v fast programming available in 300 and 600 mil dip and cllcc general description the WS57C71C is a high performance 256k uv erasable electrically r e-p rogrammable r ead o nly m emory (rprom). it is manufactured in an advanced cmos technology and utilizes wsi's patented self-aligned split gate eprom cell. the industry standard prom pin configuration of the WS57C71C provides an easy upgrade path from a 16k x 8 device. this rprom is capable of operating at speeds as fast as 35 ns address access time, which enables it to be used directly with today's fast microprocessors and dsp processors without introducing any wait states. all inputs and outputs are ttl compatible. the WS57C71C is a low power device even when operated at its fastest speed. the dip version is packaged in a 300 mil wide dip package saving board space for the user. mode pins cs1/ cs2 cs3 v cc outputs v pp read v il v ih v il v cc d out output disable v ih xxv cc high z output xv il xv cc high z disable output xxv ih v cc high z disable program v pp xv ih v cc d in program verify v il v ih v il v cc d out program inhibit v pp xv il v cc high z v cc a 10 a 11 a 12 a 13 a 14 cs3 cs2 cs1/v pp o 7 o 6 o 5 o 4 o 3 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a 12 a 13 a 14 nc cs3 cs2 cs1/v pp o 7 o 6 a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc o 0 a 7 a 8 a 9 nc v cc a 10 a 11 o 1 o 2 nc o 3 o 4 o 5 1 432 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 gnd top view chip carrier cerdip mode selection pin configuration return to main menu
WS57C71C 4-14 ordering information operating wsi part number temperature manufacturing range procedure WS57C71C-45tmb 45 28 pin cerdip, 0.3" t2 military mil-std-883c WS57C71C-55cmb 55 32 pad cllcc c2 military mil-std-883c WS57C71C-55dmb 55 28 pin cerdip, 0.6" d2 military mil-std-883c WS57C71C-55tmb 55 28 pin cerdip, 0.3" t2 military mil-std-883c WS57C71C-70tmb 70 28 pin cerdip, 0.3" t2 military mil-std-883c speed package package (ns) type drawing programming/algorithms/erasure/programmers refer to page 5-1 the WS57C71C is programmed using algorithm d shown on page 5-9. note: 9. the actual part marking will not include the initials "ws." for complete data sheet and electrical specifications see page 2-55. return to main menu
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