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pd780024as, 780034as subseries 8-bit single-chip microcontrollers pd780021as pd780022as pd780023as pd780024as pd780031as pd780032as pd780033as pd780034as pd78f0034bs document no. u16035ej1v0um00 (1st edition) date published june 2002 n cp(k) preliminary user's manual printed in japan ? 2002
2 preliminary user? manual u16035ej1v0um [memo]
3 preliminary user? manual u16035ej1v0um fip, eeprom, and iebus are trademarks of nec corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. ethernet is a trademark of xerox corporation. osf/motif is a trademark of opensoftware foundation, inc. tron stands for the realtime operating system nucleus. itron is an abbreviation of industrial tron. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
4 preliminary user? manual u16035ej1v0um license not needed: pd78f0034bsgb-8et the customer must judge the need for a license for the following products: pd780021asgb-xxx-8et, 780022asgb-xxx-8et, 780023asgb-xxx-8et, 780024asgb-xxx-8et, 780031asgb-xxx-8et, 780032asgb-xxx-8et, 780033asgb-xxx-8et, 780034asgb-xxx-8et the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? not all devices/types available in every country. please check with local nec representative for availability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5d 98. 12
5 preliminary user s manual u16035ej1v0um regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j02.4 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ?sucursal en espa?a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v ? lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 ?succursale fran?aise ?filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 ?branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ?branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 ?united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290
6 preliminary user? manual u16035ej1v0um introduction readers this manual has been prepared for user engineers who understand the functions of the pd780024as, 780034as subseries and wish to design and develop application systems and programs for these devices. pd780024as subseries: pd780021as, 780022as, 780023as, 780024as pd780034as subseries: pd780031as, 780032as, 780033as, 780034as, 78f0034bs purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the pd780024as, 780034as subseries manual is separated into two parts: this manual and the instructions edition (common to the 78k/0 series). pd780024as, 780034as subseries 78k/0 series user? manual user? manual (this manual) instructions ? pin functions ? cpu functions ? internal block functions ? instruction set ? interrupt ? explanation of each instruction ? other on-chip peripheral functions how to read this manual it is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to gain a general understanding of functions: read this manual in the order of the contents . how to interpret the register format: for the bit number enclosed in square, the bit name is defined as a reserved word in ra78k0, and in cc78k0, already defined in the header file named sfrbit.h. to check the details of a register when you know the register name. refer to appendix d register index. differences between pd780024as and 780034as subseries the resolution of the a/d converter differ between the pd780024as and 780034as subseries products. subseries pd780024as pd780034as item a/d converter 8-bit resolution 10-bit resolution
7 preliminary user s manual u16035ej1v0um conventions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary or b decimal hexadecimal h
8 preliminary user s manual u16035ej1v0um related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042e pd780021a(a), 780022a(a), 780023a(a), 780024a(a), 780021ay(a), 780022ay(a), 780023ay(a), u15131e 780024ay(a) data sheet pd780031a, 780032a, 780033a, 780034a, 780031ay, 780032ay, 780033ay, 780034ay data sheet u14044e pd780031a(a), 780032a(a), 780033a(a), 780034a(a), 780031ay(a), 780032ay(a), 780033ay(a), u15132e 780034ay(a) data sheet pd78f0034a, 78f0034ay data sheet u14040e 78k/0 series instructions user s manual u12326e 78k/0 series basic (i) application note u12704e documents related to development software tools (user? manuals) document name document no. ra78k0 assembler package operation u14445e language u14446e structured assembly language u11789e cc78k0 c compiler operation u14297e language u14298e sm78k0s, sm78k0 system simulator ver. 2.10 or later operation u14611e windows tm based sm78k series system simulator ver. 2.10 or later external part user open interface specifications u15006e id78k0-ns integrated debugger ver. 2.00 or later operation u14379e windows based id78k0 integrated debugger windows based reference u11539e guide u11649e rx78k0 real-time os fundamentals u11537e installation u11536e mx78k0 embedded os windows based fundamental u12257e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
9 preliminary user s manual u16035ej1v0um documents related to development hardware tools (user? manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-780034-ns-em1 emulation board u14642e documents related to flash memory writing document name document no. pg-fp3 flash memory programmer user s manual u13502e other related documents document name document no. semiconductor selection guide - products & packages - x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
10 preliminary user? manual u16035ej1v0um contents chapter 1 outline ........................................................................................................... ............ 24 1.1 features .................................................................................................................. .................. 24 1.2 applications .............................................................................................................. ............... 25 1.3 ordering information ...................................................................................................... ......... 25 1.4 pin configuration (top view) .............................................................................................. ... 26 1.5 78k/0 series lineup ....................................................................................................... .......... 28 1.6 block diagram ............................................................................................................. ............. 30 1.7 outline of function ....................................................................................................... ........... 31 chapter 2 pin function ..................................................................................................... ....... 33 2.1 pin function list ......................................................................................................... ............. 33 2.2 description of pin functions .............................................................................................. .... 36 2.2.1 p00 to p03 (port 0) ..................................................................................................... ................... 36 2.2.2 p10 to p13 (port 1) ..................................................................................................... ................... 36 2.2.3 p20 to p25 (port 2) ..................................................................................................... ................... 37 2.2.4 p34 to p36 (port 3) ..................................................................................................... ................... 37 2.2.5 p40 to p47 (port 4) ..................................................................................................... ................... 38 2.2.6 p50 to p57 (port 5) ..................................................................................................... ................... 38 2.2.7 p70 to p75 (port 7) ..................................................................................................... ................... 39 2.2.8 av ref ............................................................................................................................... .............. 39 2.2.9 av dd ............................................................................................................................... ............... 39 2.2.10 av ss ............................................................................................................................... .............. 39 3.2.11 reset .................................................................................................................. ...................... 39 2.2.12 x1 and x2 .............................................................................................................. ..................... 40 2.2.13 xt1 and xt2 ............................................................................................................ ................... 40 2.2.14 v dd0 and v dd1 .............................................................................................................................. 4 0 2.2.15 v ss0 and v ss1 ............................................................................................................................... 40 2.2.16 v pp (flash memory versions only) ................................................................................................ 40 2.2.17 ic (mask rom version only) ............................................................................................. .......... 40 2.3 pin i/o circuits and recommended connection of unused pins ....................................... 41 chapter 3 cpu architecture ................................................................................................. 43 3.1 memory spaces ............................................................................................................. .......... 43 3.1.1 internal program memory space ........................................................................................... ........ 48 3.1.2 internal data memory space .............................................................................................. ............ 49 3.1.3 special function register (sfr) area .................................................................................... ......... 49 3.1.4 external memory space ................................................................................................... ............. 49 3.1.5 data memory addressing .................................................................................................. ............ 50 3.2 processor registers ....................................................................................................... ......... 55 3.2.1 control registers ....................................................................................................... ..................... 55 3.2.2 general-purpose registers ............................................................................................... ............. 58 3.2.3 special function register (sfr) ......................................................................................... ............ 59
11 preliminary user? manual u16035ej1v0um 3.3 instruction address addressing ............................................................................................ 62 3.3.1 relative addressing ..................................................................................................... .................. 62 3.3.2 immediate addressing .................................................................................................... ............... 63 3.3.3 table indirect addressing ............................................................................................... ................ 64 3.3.4 register addressing ..................................................................................................... ................. 64 3.4 operand address addressing ................................................................................................ 65 3.4.1 implied addressing ...................................................................................................... .................. 65 3.4.2 register addressing ..................................................................................................... ................. 66 3.4.3 direct addressing ....................................................................................................... ................... 67 3.4.4 short direct addressing ................................................................................................. ................ 68 3.4.5 special function register (sfr) addressing .............................................................................. ..... 69 3.4.6 register indirect addressing ............................................................................................ .............. 70 3.4.7 based addressing ........................................................................................................ ................. 71 3.4.8 based indexed addressing ................................................................................................ ............ 72 3.4.9 stack addressing ........................................................................................................ ................... 72 chapter 4 port functions ................................................................................................... ... 73 4.1 port functions ............................................................................................................ ............. 73 4.2 configuration of ports .................................................................................................... ......... 75 4.2.1 port 0 .................................................................................................................. ........................... 75 4.2.2 port 1 .................................................................................................................. ........................... 76 4.2.3 port 2 .................................................................................................................. ........................... 77 4.2.4 port 3 .................................................................................................................. ........................... 79 4.2.5 port 4 .................................................................................................................. ........................... 81 4.2.6 port 5 .................................................................................................................. ........................... 82 4.2.7 port 7 .................................................................................................................. ........................... 83 4.3 registers to control port function ........................................................................................ 85 4.4 operations of port function ............................................................................................... .... 89 4.4.1 writing to i/o port ..................................................................................................... ..................... 89 4.4.2 reading from i/o port ................................................................................................... ................. 89 4.4.3 operations on i/o port .................................................................................................. ................. 89 chapter 5 clock generator ................................................................................................. 9 0 5.1 functions of clock generator .............................................................................................. .. 90 5.2 configuration of clock generator .......................................................................................... 90 5.3 registers to control clock generator ................................................................................... 92 5.4 system clock oscillator ................................................................................................... ....... 94 5.4.1 main system clock oscillator ............................................................................................ .............. 94 5.4.2 subsystem clock oscillator .............................................................................................. .............. 95 5.4.3 divider ................................................................................................................. .......................... 98 5.4.4 when no subsystem clocks are used ....................................................................................... ..... 98 5.5 clock generator operations ................................................................................................ ... 99 5.5.1 main system clock operations ............................................................................................ ........... 100 5.5.2 subsystem clock operations .............................................................................................. ............ 101 5.6 changing system clock and cpu clock settings ................................................................ 101 5.6.1 time required for switchover between system clock and cpu clock ............................................. 101
12 preliminary user? manual u16035ej1v0um 5.6.2 system clock and cpu clock switching procedure ........................................................................ 10 3 chapter 6 16-bit timer/event counter 0 .......................................................................... 104 6.1 functions of 16-bit timer/event counter 0 ........................................................................... 104 6.2 configuration of 16-bit timer/event counter 0 .................................................................... 105 6.3 registers to control 16-bit timer/event counter 0 .............................................................. 108 6.4 operations of 16-bit timer/event counter 0 ......................................................................... 114 6.4.1 interval timer operations ............................................................................................... ................. 114 6.4.2 ppg output operations ................................................................................................... ............... 116 6.4.3 pulse width measurement operations ...................................................................................... ..... 117 6.4.4 external event counter operation ........................................................................................ .......... 124 6.4.5 square-wave output operation ............................................................................................ .......... 125 6.5 cautions for 16-bit timer/event counter 0 ........................................................................... 128 chapter 7 8-bit timer/event counters 50 and 51 .......................................................... 132 7.1 functions of 8-bit timer/event counters 50 and 51 ............................................................ 132 7.2 configurations of 8-bit timer/event counters 50 and 51 .................................................... 134 7.3 registers to control 8-bit timer/event counters 50 and 51 ............................................... 135 7.4 operations of 8-bit timer/event counters 50 and 51 ........................................................... 140 7.4.1 interval timer (8-bit) operation ........................................................................................ ............... 140 7.4.2 external event counter operation ........................................................................................ .......... 144 7.4.3 square-wave output (8-bit resolution) operation ......................................................................... .. 145 7.4.4 8-bit pwm output operation .............................................................................................. ............. 146 7.4.5 interval timer (16-bit) operation ....................................................................................... .............. 149 7.5 cautions for 8-bit timer/event counters 50 and 51 ............................................................. 150 chapter 8 watch timer ...................................................................................................... ...... 152 8.1 functions of watch timer .................................................................................................. ..... 152 8.2 configuration of watch timer .............................................................................................. .. 153 8.3 register to control watch timer ........................................................................................... . 154 8.4 operations of watch timer ................................................................................................. .... 155 8.4.1 watch timer operation ................................................................................................... ................ 155 8.4.2 interval timer operation ................................................................................................ .................. 155 chapter 9 watchdog timer ................................................................................................... . 157 9.1 functions of watchdog timer ............................................................................................... . 157 9.2 configuration of watchdog timer .......................................................................................... 1 59 9.3 registers to control watchdog timer ................................................................................... 159 9.4 watchdog timer operations ................................................................................................. .. 163 9.4.1 watchdog timer operation ................................................................................................ ............. 163 9.4.2 interval timer operation ................................................................................................ .................. 164 chapter 10 clock output/buzzer output controller ............................................ 165 10.1 functions of clock output/buzzer output controller ........................................................ 165
13 preliminary user? manual u16035ej1v0um 10.2 configuration of clock output/buzzer output controller ................................................. 166 10.3 registers to control clock output/buzzer output controller ........................................... 166 10.4 operations of clock output/buzzer output controller ...................................................... 169 10.4.1 operation as clock output .............................................................................................. .............. 169 10.4.2 operation as buzzer output ............................................................................................. ............ 169 chapter 11 8-bit a/d converter ( pd780024as subseries) ......................................... 170 11.1 functions of a/d converter ............................................................................................... ... 170 11.2 configuration of a/d converter ........................................................................................... . 172 11.3 registers to control a/d converter ..................................................................................... 17 4 11.4 operations of a/d converter .............................................................................................. .. 177 11.4.1 basic operations of a/d converter ...................................................................................... ......... 177 11.4.2 input voltage and conversion results ................................................................................... ........ 179 11.4.3 a/d converter operation mode ........................................................................................... ......... 180 11.5 how to read a/d converter characteristics table ............................................................ 183 11.6 cautions for a/d converter ............................................................................................... ... 186 chapter 12 10-bit a/d converter ( pd780034as subseries) ...................................... 193 12.1 functions of a/d converter ............................................................................................... ... 193 12.2 configuration of a/d converter ........................................................................................... . 194 12.3 registers to control a/d converter ..................................................................................... 19 5 12.4 operations of a/d converter .............................................................................................. .. 198 12.4.1 basic operations of a/d converter ...................................................................................... ......... 198 12.4.2 input voltage and conversion results ................................................................................... ........ 200 12.4.3 a/d converter operation mode ........................................................................................... ......... 201 12.5 how to read a/d converter characteristics table ............................................................ 203 12.6 cautions for a/d converter ............................................................................................... ... 206 chapter 13 serial interface (uart0) ................................................................................. 213 13.1 functions of serial interface ........................................................................................... .... 213 13.2 configuration of serial interface ....................................................................................... .. 215 13.3 registers to control serial interface .................................................................................. 2 16 13.4 operations of serial interface .......................................................................................... .... 220 13.4.1 operation stop mode .................................................................................................... ............... 220 13.4.2 asynchronous serial interface (uart) mode .............................................................................. 221 13.4.3 infrared data transfer mode ............................................................................................ ............. 233 chapter 14 serial interface (sio3) .................................................................................... 236 14.1 functions of serial interface ........................................................................................... .... 236 14.2 configuration of serial interface ....................................................................................... .. 237 14.3 registers to control serial interface .................................................................................. 2 38 14.4 operations of serial interface .......................................................................................... .... 242 14.4.1 operation stop mode .................................................................................................... ............... 242 14.4.2 3-wire serial i/o mode ................................................................................................. ................ 243
14 preliminary user? manual u16035ej1v0um chapter 15 interrupt functions ......................................................................................... 246 15.1 interrupt function types ................................................................................................. ..... 246 15.2 interrupt sources and configuration ................................................................................... 246 15.3 registers to control interrupt function .............................................................................. 250 15.4 interrupt servicing operations ........................................................................................... .. 256 15.4.1 non-maskable interrupt request acknowledge operation ............................................................ 256 15.4.2 maskable interrupt request acknowledge operation .................................................................... 259 15.4.3 software interrupt request acknowledge operation .................................................................... 26 1 15.4.4 nesting interrupt servicing ............................................................................................ ............... 262 15.4.5 interrupt request hold ................................................................................................. ................. 265 chapter 16 standby function ............................................................................................... 2 66 16.1 standby function and configuration .................................................................................. 266 16.1.1 standby function ....................................................................................................... ................... 266 16.1.2 standby function control register ...................................................................................... ........... 267 16.2 operations of standby function .......................................................................................... 2 68 16.2.1 halt mode .............................................................................................................. ................... 268 16.2.2 stop mode .............................................................................................................. ................... 271 chapter 17 reset function .................................................................................................. .. 274 17.1 reset function ........................................................................................................... ............ 274 chapter 18 pd78f0034bs ........................................................................................................... 278 18.1 memory size switching register ......................................................................................... 27 9 18.2 flash memory programming ................................................................................................ 2 80 18.2.1 selection of communication mode ........................................................................................ ...... 280 18.2.2 flash memory programming function ...................................................................................... .... 281 18.2.3 connection of flashpro iii ............................................................................................. .............. 282 chapter 19 instruction set ................................................................................................. .. 284 19.1 conventions .............................................................................................................. ............. 285 19.1.1 operand identifiers and specification methods .......................................................................... . 285 19.1.2 description of ?peration column ...................................................................................... .......... 286 19.1.3 description of ?lag operation column ................................................................................. ........ 286 19.2 operation list ........................................................................................................... ............. 287 19.3 instructions listed by addressing type ............................................................................. 295 appendix a differences between pd780024a, 780024as, 780034a, and 780034as subseries ...................................................................................... 299 appendix b development tools ........................................................................................... 300 b.1 language processing software ............................................................................................. 3 02
15 preliminary user? manual u16035ej1v0um b.2 flash memory writing tools ................................................................................................ .. 303 b.3 debugging tools ........................................................................................................... .......... 304 b.3.1 hardware ................................................................................................................ ...................... 304 b.3.2 software ................................................................................................................ ........................ 305 appendix c embedded software .......................................................................................... 306 appendix d register index .................................................................................................. .... 307 d.1 register name index ....................................................................................................... ........ 307 d.2 register symbol index ..................................................................................................... ...... 309
16 preliminary user? manual u16035ej1v0um list of figures (1/6) figure no. title page 2-1 pin i/o circuit list ........................................................................................................ ........................ 42 3-1 memory map ( pd780021as, 780031as) .......................................................................................... 43 3-2 memory map ( pd780022as, 780032as) .......................................................................................... 44 3-3 memory map ( pd780023as, 780033as) .......................................................................................... 45 3-4 memory map ( pd780024as, 780034as) .......................................................................................... 46 3-5 memory map ( pd78f0034bs) .......................................................................................................... 47 3-6 data memory addressing ( pd780021as, 780031as) ...................................................................... 50 3-7 data memory addressing ( pd780022as, 780032as) ...................................................................... 51 3-8 data memory addressing ( pd780023as, 780033as) ...................................................................... 52 3-9 data memory addressing ( pd780024as, 780034as) ...................................................................... 53 3-10 data memory addressing ( pd78f0034bs) ....................................................................................... 54 3-11 format of program counter .................................................................................................. ............... 55 3-12 format of program status word .............................................................................................. ............ 55 3-13 format of stack pointer .................................................................................................... ................... 57 3-14 data to be saved to stack memory ........................................................................................... .......... 57 3-15 data to be restored from stack memory ...................................................................................... ...... 57 3-16 configuration of general-purpose register .................................................................................. ....... 58 4-1 port types .................................................................................................................. .......................... 73 4-2 block diagram of p00 to p03 ................................................................................................. .............. 76 4-3 block diagram of p10 to p13 ................................................................................................. .............. 76 4-4 block diagram of p20, p22, p23, and p25 ..................................................................................... ..... 77 4-5 block diagram of p21 and p24 ................................................................................................ ............ 78 4-6 block diagram of p34 and p36 ................................................................................................ ............ 79 4-7 block diagram of p35 ........................................................................................................ .................. 80 4-8 block diagram of p40 to p47 ................................................................................................. .............. 81 4-9 block diagram of falling edge detector ...................................................................................... ........ 81 4-10 block diagram of p50 to p57 ................................................................................................ ............... 82 4-11 block diagram of p70 to p73 ................................................................................................ ............... 83 4-12 block diagram of p74 and p75 ............................................................................................... ............. 84 4-13 format of port mode register (pm0, pm2 to pm5, pm7) .................................................................... 86 4-14 format of pull-up resistor option register (pu0, pu2 to pu5, pu7) ................................................ 88 5-1 block diagram of clock generator ............................................................................................ ........... 91 5-2 subsystem clock feedback resistor ........................................................................................... ....... 92 5-3 format of processor clock control register (pcc) ............................................................................ 93 5-4 external circuit of main system clock oscillator ............................................................................ ..... 94 5-5 external circuit of subsystem clock oscillator .............................................................................. ...... 95 5-6 examples of incorrect resonator connection .................................................................................. ... 96 5-7 main system clock stop function ............................................................................................. .......... 100
17 preliminary user? manual u16035ej1v0um list of figures (2/6) figure no. title page 5-8 system clock and cpu clock switching ........................................................................................ ..... 103 6-1 block diagram of 16-bit timer/event counter 0 ............................................................................... ... 105 6-2 format of 16-bit timer mode control register 0 (tmc0) .................................................................... 109 6-3 format of capture/compare control register 0 (crc0) ..................................................................... 110 6-4 format of 16-bit timer output control register 0 (toc0) .................................................................. 111 6-5 format of prescaler mode register 0 (prm0) .................................................................................. ... 112 6-6 format of port mode register 7 (pm7) ........................................................................................ ........ 113 6-7 control register settings for interval timer operation ...................................................................... .. 114 6-8 interval timer configuration diagram ........................................................................................ .......... 115 6-9 timing of interval timer operation .......................................................................................... ............. 115 6-10 control register settings for ppg output operation ......................................................................... .. 116 6-11 control register settings for pulse width measurement with free-running counter and one capture register ....................................................................................................... ............ 117 6-12 configuration diagram for pulse width measurement by free-running counter ................................ 118 6-13 timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) ...................................................................... 118 6-14 control register settings for measurement of two pulse widths with free-running counter ............ 119 6-15 cr01 capture operation with rising edge specified .......................................................................... 120 6-16 timing of pulse width measurement operation with free-running counter (with both edges specified) .................................................................................................... ............. 120 6-17 control register settings for pulse width measurement with free-running counter and two capture registers ............................................................................. 121 6-18 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) .................................................................... 122 6-19 control register settings for pulse width measurement by means of restart ................................... 123 6-20 timing of pulse width measurement operation by means of restart (with rising edge specified) .......... 123 6-21 control register settings in external event counter mode ................................................................. 12 4 6-22 external event counter configuration diagram ............................................................................... .... 125 6-23 external event counter operation timings (with rising edge specified) ............................................ 125 6-24 control register settings in square-wave output mode ..................................................................... 12 6 6-25 square-wave output operation timing ........................................................................................ ....... 127 6-26 16-bit timer counter 0 (tm0) start timing .................................................................................. ........ 128 6-27 timings after change of compare register during timer count operation ....................................... 128 6-28 capture register data retention timing ..................................................................................... ........ 129 6-29 operation timing of ovf0 flag .............................................................................................. ............. 130 7-1 block diagram of 8-bit timer/event counter 50 ............................................................................... ... 133 7-2 block diagram of 8-bit timer/event counter 51 ............................................................................... ... 133 7-3 format of timer clock select register 50 (tcl50) ............................................................................ . 135 7-4 format of timer clock select register 51 (tcl51) ............................................................................ . 136
18 preliminary user? manual u16035ej1v0um list of figures (3/6) figure no. title page 7-5 format of 8-bit timer mode control register 5n (tmc5n) .................................................................. 137 7-6 format of port mode register 7 (pm7) ........................................................................................ ........ 139 7-7 interval timer operation timings ............................................................................................ ............. 141 7-8 external event counter operation timing (with rising edge specified) ............................................. 144 7-9 square-wave output operation timing ......................................................................................... ...... 145 7-10 pwm output operation timing ................................................................................................ ............ 147 7-11 timing of operation by cr5n transition ..................................................................................... ......... 148 7-12 16-bit resolution cascade connection mode .................................................................................. ... 150 7-13 8-bit timer counter start timing ........................................................................................... .............. 150 7-14 timing after change of compare register during timer count operation ......................................... 151 8-1 block diagram of watch timer ................................................................................................ ............. 152 8-2 format of watch timer operation mode register (wtm) ................................................................... 154 8-3 operation timing of watch timer/interval timer .............................................................................. .... 156 9-1 block diagram of watchdog timer ............................................................................................. .......... 157 9-2 format of watchdog timer clock select register (wdcs) ................................................................. 160 9-3 format of watchdog timer mode register (wdtm) ............................................................................ 161 9-4 format of oscillation stabilization time select register (osts) ........................................................ 162 10-1 block diagram of clock output/buzzer output controller ................................................................... 16 5 10-2 format of clock output select register (cks) ............................................................................... ..... 167 10-3 format of port mode register 7 (pm7) ....................................................................................... ......... 168 10-4 remote control output application example .................................................................................. .... 169 11-1 block diagram of 8-bit a/d converter ....................................................................................... .......... 171 11-2 format of a/d converter mode register 0 (adm0) ............................................................................. 175 11-3 format of analog input channel specification register 0 (ads0) ...................................................... 176 11-4 format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) ....................................................................... 176 11-5 basic operation of 8-bit a/d converter ..................................................................................... .......... 178 11-6 relationship between analog input voltage and a/d conversion result ............................................ 179 11-7 a/d conversion by hardware start (when falling edge is specified) ................................................. 181 11-8 a/d conversion by software start ........................................................................................... ............ 182 11-9 overall error .............................................................................................................. ........................... 183 11-10 quantization error ........................................................................................................ ........................ 183 11-11 zero scale offset ......................................................................................................... ........................ 184 11-12 full scale offset ......................................................................................................... .......................... 184 11-13 integral linearity error .................................................................................................. ....................... 184 11-14 differential linearity error .............................................................................................. ...................... 184 11-15 example of method of reducing current consumption in standby mode ........................................... 186
19 preliminary user? manual u16035ej1v0um list of figures (4/6) figure no. title page 11-16 analog input pin connection ............................................................................................... ................ 187 11-17 a/d conversion end interrupt request generation timing ................................................................. 188 11-18 timing of reading conversion result (when conversion result is undefined) ................................. 189 11-19 timing of reading conversion result (when conversion result is normal) ...................................... 189 11-20 av dd pin connection ................................................................................................................ ........... 190 11-21 example of connecting capacitor to av ref pin ................................................................................... 190 11-22 internal equivalent circuit of pins ani0 to ani3 .......................................................................... ........ 191 11-23 example of connection if signal source impedance is high .............................................................. 192 12-1 block diagram of 10-bit a/d converter ...................................................................................... ......... 193 12-2 format of a/d converter mode register 0 (adm0) ............................................................................. 196 12-3 format of analog input channel specification register 0 (ads0) ...................................................... 197 12-4 format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) ....................................................................... 197 12-5 basic operation of 10-bit a/d converter .................................................................................... ......... 199 12-6 relationship between analog input voltage and a/d conversion result ............................................ 200 12-7 a/d conversion by hardware start (when falling edge is specified) ................................................. 201 12-8 a/d conversion by software start ........................................................................................... ............ 202 12-9 overall error .............................................................................................................. ........................... 203 12-10 quantization error ........................................................................................................ ........................ 203 12-11 zero scale offset ......................................................................................................... ........................ 204 12-12 full scale offset ......................................................................................................... .......................... 204 12-13 integral linearity error .................................................................................................. ....................... 204 12-14 differential linearity error .............................................................................................. ...................... 204 12-15 example of method of reducing current consumption in standby mode ........................................... 206 12-16 analog input pin connection ............................................................................................... ................ 207 12-17 a/d conversion end interrupt request generation timing ................................................................. 208 12-18 timing of reading conversion result (when conversion result is undefined) ................................. 209 12-19 timing of reading conversion result (when conversion result is normal) ...................................... 209 12-20 av dd pin connection ................................................................................................................ ........... 210 12-21 example of connecting capacitor to av ref pin ................................................................................... 210 12-22 internal equivalent circuit of pins ani0 to ani3 .......................................................................... ........ 211 12-23 example of connection if signal source impedance is high .............................................................. 212 13-1 block diagram of serial interface (uart0) .................................................................................. ........ 214 13-2 block diagram of baud rate generator ....................................................................................... ....... 214 13-3 format of asynchronous serial interface mode register 0 (asim0) ................................................... 217 13-4 format of asynchronous serial interface status register 0 (asis0) .................................................. 218 13-5 format of baud rate generator control register 0 (brgc0) ............................................................. 219 13-6 baud rate error tolerance (when k = 0), including sampling errors .................................................. 227 13-7 format of transmit/receive data in asynchronous serial interface .................................................... 228
20 preliminary user? manual u16035ej1v0um list of figures (5/6) figure no. title page 13-8 timing of asynchronous serial interface transmit completion interrupt request ............................... 230 13-9 timing of asynchronous serial interface receive completion interrupt request ............................... 231 13-10 receive error timing ...................................................................................................... ..................... 232 13-11 data format comparison between infrared data transfer mode and uart mode ............................ 233 14-1 block diagram of serial interface (sio3n) .................................................................................. ......... 236 14-2 format of serial operation mode register 30 (csim30) ..................................................................... 23 9 14-3 format serial operation mode register 31 (csim31) ......................................................................... 2 41 14-4 timing of 3-wire serial i/o mode ........................................................................................... ............. 245 15-1 basic configuration of interrupt function .................................................................................. .......... 248 15-2 format of interrupt request flag register (if0l, if0h, if1l) ............................................................. 25 1 15-3 format of interrupt mask flag register (mk0l, mk0h, mk1l) ........................................................... 252 15-4 format of priority specification flag register (pr0l, pr0h, pr1l) .................................................. 253 15-5 format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) ....................................................................... 254 15-6 format of memory expansion mode register (mem) ......................................................................... 254 15-7 format of program status word .............................................................................................. ............ 255 15-8 non-maskable interrupt request generation to acknowledge flowchart ........................................... 257 15-9 non-maskable interrupt request acknowledge timing ....................................................................... 257 15-10 non-maskable interrupt request acknowledge operation .................................................................. 258 15-11 interrupt request acknowledge processing algorithm ........................................................................ 260 15-12 interrupt request acknowledge timing (minimum time) .................................................................... 261 15-13 interrupt request acknowledge timing (maximum time) ................................................................... 261 15-14 nesting examples .......................................................................................................... ...................... 263 15-15 interrupt request hold .................................................................................................... ..................... 265 16-1 format of oscillation stabilization time select register (osts) ........................................................ 267 16-2 halt mode release by interrupt request generation ........................................................................ 26 9 16-3 halt mode release by reset input ........................................................................................... ...... 270 16-4 stop mode release by interrupt request generation ....................................................................... 272 16-5 stop mode release by reset input ........................................................................................... ..... 273 17-1 block diagram of reset function ............................................................................................ ............ 274 17-2 timing of reset by reset input ............................................................................................. ............ 275 17-3 timing of reset due to watchdog timer overflow ............................................................................. .275 17-4 timing of reset in stop mode by reset input ................................................................................ .275 18-1 format of memory size switching register (ims) ............................................................................. .. 279 18-2 format of communication mode selection ..................................................................................... ..... 281 18-3 connection of flashpro iii in 3-wire serial i/o mode ....................................................................... ... 282
21 preliminary user? manual u16035ej1v0um list of figures (6/6) figure no. title page 18-4 connection of flashpro iii in 3-wire serial i/o mode (using handshake) .......................................... 282 18-5 connection of flashpro iii in uart mode .................................................................................... ....... 282 18-6 connection of flashpro iii in pseudo 3-wire serial i/o mode ............................................................. 283 b-1 development tool configuration ............................................................................................. ............. 301
22 preliminary user? manual u16035ej1v0um list of tables (1/2) table no. title page 2-1 pin i/o circuit types ....................................................................................................... ...................... 41 3-1 internal rom capacity ....................................................................................................... ................. 48 3-2 vector table ................................................................................................................ ......................... 48 3-3 internal high-speed ram capacity ............................................................................................ ......... 49 3-4 internal high-speed ram area ................................................................................................ ........... 56 3-5 special function register list .............................................................................................. ............... 60 4-1 port functions .............................................................................................................. ........................ 74 4-2 configuration of ports ...................................................................................................... .................... 75 5-1 configuration of clock generator ............................................................................................ ............ 90 5-2 relationship of cpu clock and minimum instruction execution time ................................................. 94 5-3 maximum time required for cpu clock switchover ........................................................................... 102 6-1 configuration of 16-bit timer/event counter 0 ............................................................................... ..... 105 6-2 ti00/to0/p70 pin valid edge and cr00, cr01 capture trigger ........................................................ 106 6-3 ti01/p71 pin valid edge and cr00 capture trigger ........................................................................... 1 06 7-1 configuration of 8-bit timer/event counters 50 and 51 ...................................................................... 1 34 8-1 interval timer interval time ................................................................................................ ................. 153 8-2 configuration of watch timer ................................................................................................ ............... 153 8-3 interval timer interval time ................................................................................................ ................. 155 9-1 watchdog timer program loop detection time .................................................................................. 158 9-2 interval time ............................................................................................................... ......................... 158 9-3 configuration of watchdog timer ............................................................................................. ............ 159 9-4 watchdog timer program loop detection time .................................................................................. 163 9-5 interval timer interval time ................................................................................................ ................. 164 10-1 configuration of clock output/buzzer output controller ..................................................................... 166 11-1 configuration of a/d converter ............................................................................................. ............... 172 11-2 resistance and capacitance of equivalent circuit (reference values) ............................................... 191 12-1 configuration of a/d converter ............................................................................................. ............... 194 12-2 resistance and capacitance of equivalent circuit (reference values) ............................................... 211 13-1 configuration of serial interface (uart0) .................................................................................. ......... 215 13-2 relationship between 5-bit counters source clock and ? value ..................................................... 225 13-3 relationship between main system clock and baud rate ................................................................. 226 13-4 causes of receive errors ................................................................................................... ................. 232 13-5 bit rate and pulse width values ............................................................................................ ............. 234
23 preliminary user? manual u16035ej1v0um list of tables (2/2) table no. title page 14-1 configuration of serial interface (sio3n) .................................................................................. ........... 237 15-1 interrupt source list ...................................................................................................... ...................... 247 15-2 flags corresponding to interrupt request sources ........................................................................... . 250 15-3 times from generation of maskable interrupt until servicing ............................................................. 259 15-4 interrupt request enabled for nesting during interrupt servicing ....................................................... 262 16-1 halt mode operating status ................................................................................................. ............. 268 16-2 operation after halt mode release .......................................................................................... ......... 270 16-3 stop mode operating status ................................................................................................. ............ 271 16-4 operation after stop mode release .......................................................................................... ........ 273 17-1 hardware statuses after reset .............................................................................................. ............. 276 18-1 differences among pd78f0034bs and mask rom versions ........................................................... 278 18-2 memory size switching register settings .................................................................................... ....... 279 18-3 communication mode list .................................................................................................... ............... 280 18-4 main functions of flash memory programming ................................................................................. . 281 19-1 operand identifiers and specification methods .............................................................................. ..... 285 a-1 major differences between pd780024a, 780024as, 780034a, and 780034as subseries ............. 299
24 preliminary user? manual u16035ej1v0um chapter 1 outline 1.1 features internal memory type program memory data memory part number (rom/flash memory) (high-speed ram) pd780021as, 780031as 8 kb 512 bytes pd780022as, 780032as 16 kb pd780023as, 780033as 24 kb 1024 bytes pd780024as, 780034as 32 kb pd78f0034bs 32 kb note 1024 bytes note note the capacities of internal flash memory and internal high-speed ram can be changed by means of the memory size switching register (ims). external memory expansion space: 64 kb minimum instruction execution time changeable from high speed (0.24 s: @ 8.38 mhz operation with main system clock) to ultra-low speed (122 s: @ 32.768 khz operation with subsystem clock) instruction set suited to system control bit manipulation possible in all address spaces multiply and divide instructions i/o ports: 39 8-bit resolution a/d converter: 8 channels ( pd780024as subseries only) 10-bit resolution a/d converter: 8 channels ( pd780034as subseries only) serial interface: 3 channels 3-wire serial i/o mode: 2 channels uart mode: 1 channel timer: five channels 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel vectored interrupt sources: 20 two types of on-chip clock oscillators (main system clock and subsystem clock) power supply voltage: v dd = 1.8 to 5.5 v
25 chapter 1 outline preliminary user? manual u16035ej1v0um 1.2 applications home electric appliances, pagers, av equipment, car audios, car electric equipment, office automation equipment, etc. 1.3 ordering information part number package internal rom pd780021asgb- -8et 52-pin plastic lqfp (10 10) mask rom pd780022asgb- -8et 52-pin plastic lqfp (10 10) mask rom pd780023asgb- -8et 52-pin plastic lqfp (10 10) mask rom pd780024asgb- -8et 52-pin plastic lqfp (10 10) mask rom pd780031asgb- -8et 52-pin plastic lqfp (10 10) mask rom pd780032asgb- -8et 52-pin plastic lqfp (10 10) mask rom pd780033asgb- -8et 52-pin plastic lqfp (10 10) mask rom pd780034asgb- -8et 52-pin plastic lqfp (10 10) mask rom pd78f0034bsgb-8et 52-pin plastic lqfp (10 10) flash memory remark indicates rom code suffix.
26 chapter 1 outline preliminary user? manual u16035ej1v0um 1.4 pin configuration (top view) 52-pin plastic lqfp (10 10) pd780021asgb- -8et, 780022asgb- -8et, pd780023asgb- -8et, 780024asgb- -8et, pd780031asgb- -8et, 780032asgb- -8et, pd780033asgb- -8et, 780034asgb- -8et, pd780034bsgb-8et 1 2 3 4 5 6 7 8 9 10 11 12 13 p50 p51 p52 p53 p54 p55 p56 p57 v ss0 v dd0 p34/si31 p35/so31 p36/sck31 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref p47 p46 p45 p44 p43 p42 p41 p40 p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 p71/ti01 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic (v pp ) xt1 xt2 reset av dd cautions 1. connect ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect av ss pin to v ss0 . remarks 1. when these devices are used in applications that require the reduction of noise generated from an on-chip microcontroller, the implementation of noise measures is recommended, such as supplying v dd0 and v dd1 independently, connecting v ss0 and v ss1 independently to ground lines, and so on. 2. pin connection in parentheses is intended for the pd78f0034bs.
27 chapter 1 outline preliminary user s manual u16035ej1v0um adtrg: ad trigger input p70 to p75: port 7 ani0 to ani3: analog input pcl: programmable clock asck0: asynchronous serial clock reset: reset av dd : analog power supply rxd0: receive data av ref : analog reference voltage sck30, sck31: serial clock av ss : analog ground si30, si31: serial input buz: buzzer clock so30, so31: serial output ic: internally connected ti00, ti01, ti50, ti51: timer input intp0 to intp3: external interrupt input to0, to50, to51: timer output p00 to p03: port 0 txd0: transmit data p10 to p13: port 1 v dd0 , v dd1 : power supply p20 to p25: port 2 v pp : programming power supply p34 to p36: port 3 v ss0 , v ss1 : ground p40 to p47: port 4 x1, x2: crystal (main system clock) p50 to p57: port 5 xt1, xt2: crystal (subsystem clock)
28 chapter 1 outline preliminary user s manual u16035ej1v0um 1.5 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries name. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78054 with iebus tm controller pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited function pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter control circuit and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd780208 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin on-chip iebus controller 80-pin on-chip controller compliant with j1850 (class 2) pd780833y pd780948 on-chip can controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 on-chip can controller specialized for can controller function 80-pin pd780703y pd780702y 64-pin pd780816
29 chapter 1 outline preliminary user s manual u16035ej1v0um the major functional differences among the subseries are listed below. function rom timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k 4 ch (uart: 1 ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd78014h 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1 ch) 33 inverter pd780988 16 k to 60 k 3 ch note 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v control vfd pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pd780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd pd780338 48 k to 60 k 3 ch 2 ch 1 ch 1 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 1.8 v drive pd780328 62 pd780318 70 pd780308 48 k to 60 k 2 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1 ch) pd78064 16 k to 32 k bus pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v interface pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v supported pd780816 32 k to 60 k 2 ch 12 ch 2 ch (uart: 1 ch) 46 4.0 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v control dash- pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v board control pd780828b 32 k to 60 k 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel v dd min. value capacity (bytes)
30 chapter 1 outline preliminary user s manual u16035ej1v0um 1.6 block diagram 16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 watchdog timer watch timer serial interface 30 serial interface 31 uart0 a/d converter interrupt control buzzer output clock output control ti00/to0/p70 ti01/p71 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 si31/p34 so31/p35 sck31/p36 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref buz/p75 pcl/p74 ani0/p10 to ani3/p13 intp0/p00 to intp3/p03 v dd0 v dd1 v ss0 v ss1 ic (v pp ) 78k/0 cpu core rom ram port 0 p00 to p03 port 1 p10 to p13 port 2 p20 to p25 port 3 p34 to p36 port 4 p40 to p47 port 5 p50 to p57 port 7 p70 to p75 system control reset x1 x2 xt1 xt2 remarks 1. the internal rom and ram capacities depend on the product. 2. pin connection in parentheses is intended for the pd78f0034bs.
31 chapter 1 outline preliminary user s manual u16035ej1v0um 1.7 outline of function part number pd780021as pd780022as pd780023as pd780024as pd78f0034bs item pd780031as pd780032as pd780033as pd780034as internal memory rom 8 kb 16 kb 24 kb 32 kb 32 kb note (mask rom) (mask rom) (mask rom) (mask rom) (flash memory) high-speed ram 512 bytes 1024 bytes 1024 bytes note memory space 64 kb general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction minimum instruction execution time changeable function execution time when main system 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38 mhz operation) clock selected when subsystem 122 s (@ 32.768 khz operation) clock selected instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulate (set, reset, test, and boolean operation) bcd adjust, etc. i/o port total: 39 cmos input: 4 cmos i/o: 35 a/d converter 8-bit resolution 4 channels ( pd780021as, 780022as, 780023as, 780024as) 10-bit resolution 4 channels ( pd780031as, 780032as, 780033as, 780034as, 78f0034bs) low-voltage operation: av dd = 1.8 to 5.5 v serial interface 3-wire serial i/o mode: 2 channels uart mode: 1 channel timer 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer output three outputs (8-bit pwm output enable: 2) clock output 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (8.38 mhz with main system clock) 32.768 khz (32.768 khz with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (8.38 mhz with main system clock) vectored interrupt maskable internal: 13, external: 5 source non-maskable internal: 1 software 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = 40 to +85 c package 52-pin plastic lqfp (10 10) note the capacities of internal flash memory and internal high-speed ram can be changed by means of the memory size switching register (ims).
32 chapter 1 outline preliminary user s manual u16035ej1v0um the outline of the timer/event counter is as follows (for details, refer to chapter 6 16-bit timer/event counter 0 , chapter 7 8-bit timer/event counters 50 and 51 , chapter 8 watch timer , and chapter 9 watchdog timer ). 16-bit timer/ 8-bit timer/ watch timer watchdog timer event counter event counter operation interval timer 1 channel 2 channels 1 channel note 1 1 channel note 2 mode external event counter ? function timer output ? ppg output pwm output pulse width measurement square-wave output ? interrupt request ? notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer can perform either the watchdog timer function or the interval timer function.
33 preliminary user? manual u16035ej1v0um pin name i/o function after reset alternate function p00 i/o input intp0 p01 intp1 p02 intp2 p03 intp3/adtrg p10 to p13 input port 1 input ani0 to ani3 4-bit input-only port. p20 i/o input si30 p21 so30 p22 sck30 p23 rxd0 p24 txd0 p25 asck0 p34 i/o input si31 p35 so31 p36 sck31 p40 to p47 i/o port 4 input 8-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input 8-bit i/o port leds can be driven directly. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. p70 i/o input ti00/to0 p71 ti01 p72 ti50/to50 p73 ti51/to51 p74 pcl p75 buz chapter 2 pin function 2.1 pin function list (1) port pins port 0 4-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 2 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 3 3-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 7 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings.
34 chapter 2 pin function preliminary user? manual u16035ej1v0um pin name i/o function after reset alternate function intp0 input input p00 intp1 p01 intp2 p02 intp3 p03/adtrg si30 input serial interface serial data input input p20 si31 p34 so30 output serial interface serial data output input p21 so31 p35 sck30 i/o serial interface serial clock input/output input p22 sck31 p36 rxd0 input asynchronous serial interface serial data input input p23 txd0 output asynchronous serial interface serial data output input p24 asck0 input asynchronous serial interface serial clock input input p25 ti00 input external count clock input to 16-bit timer/event counter 0 input p70/to0 capture trigger input to 16-bit timer/event counter 0 capture register (cr00, cr01) ti01 capture trigger input to 16-bit timer/event counter 0 p71 capture register (cr00) ti50 external count clock input to 8-bit timer/event counter 50 p72/to50 ti51 external count clock input to 8-bit timer/event counter 51 p73/to51 to0 output 16-bit timer/event counter 0 output input p70/ti00 to50 8-bit timer/event counter 50 output input p72/ti50 (also used for 8-bit pwm output) to51 8-bit timer/event counter 51 output p73/ti51 (also used for 8-bit pwm output) pcl output clock output (for main system clock and subsystem clock input p74 trimming) buz output buzzer output input p75 ani0 to ani3 input a/d converter analog input input p10 to p13 adtrg input a/d converter trigger signal input input p03/intp3 av ref input a/d converter reference voltage input av dd a/d converter analog power supply. connect to v dd0 or v dd1 . av ss a/d converter ground potential. connect to v ss0 or v ss1 . reset input system reset input input x1 input crystal connection for main system clock oscillation x2 xt1 input crystal connection for subsystem clock oscillation xt2 v dd0 positive power supply for ports v dd1 positive power supply other than ports (2) non-port pins (1/2) external interrupt request input with specifiable valid edges (rising edge, falling edge, both rising and falling edges)
35 chapter 2 pin function preliminary user? manual u16035ej1v0um pin name i/o function after reset alternate function v ss0 ground potential for ports v ss1 ground potential other than ports ic internally connected. connect directly to v ss0 or v ss1 . v pp high-voltage application for program write/verify. connect directly to v ss0 or v ss1 in normal operating mode. (2) non-port pins (2/2)
36 chapter 2 pin function preliminary user? manual u16035ej1v0um 2.2 description of pin functions 2.2.1 p00 to p03 (port 0) these are 4-bit i/o ports. besides serving as i/o ports, they function as an external interrupt input, and a/d converter external trigger input. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 4-bit i/o ports. p00 to p03 can be specified as input or output ports in 1-bit units with port mode register 0 (pm0). on-chip pull- up resistors can be used by setting pull-up resistor option register 0 (pu0). (2) control mode these ports function as an external interrupt request input, and a/d converter external trigger input. (a) intp0 to intp3 intp0 to intp3 are external interrupt request input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). (b) adtrg a/d converter external trigger input pin. caution when p03 is used as an a/d converter external trigger input, specify the valid edge by bits 1, 2 (ega00, ega01) of a/d converter mode register (adm0) and set interrupt mask flag (pmk3) to 1. 2.2.2 p10 to p13 (port 1) these are 4-bit input-only ports. besides serving as input ports, they function as an a/d converter analog input. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 4-bit input-only ports. (2) control mode these ports function as a/d converter analog input pins (ani0 to ani3).
37 chapter 2 pin function preliminary user? manual u16035ej1v0um 2.2.3 p20 to p25 (port 2) these are 6-bit i/o ports. besides serving as i/o ports, they function as serial interface data i/o and clock i/o. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 6-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 2 (pm2). on-chip pull-up resistors can be used by setting pull-up resistor option register 2 (pu2). (2) control mode these ports function as serial interface data i/o and clock i/o. (a) si30 and so30 serial interface serial data i/o pins. (b) sck30 serial interface serial clock i/o pin. (c) r x d0 and t x d0 asynchronous serial interface serial data i/o pins. (d) asck0 asynchronous serial interface serial clock input pin. 2.2.4 p34 to p36 (port 3) these are 3-bit i/o ports. besides serving as i/o ports, they function as serial interface data i/o and clock i/o. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 3-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 3 (pm3). on-chip pull-up resistors can be used by setting pull-up resistor option register 3 (pu3). (2) control mode these ports function as serial interface data i/o and clock i/o. (a) si31 and so31 serial interface serial data i/o pins. (b) sck31 serial interface serial clock i/o pin.
38 chapter 2 pin function preliminary user? manual u16035ej1v0um 2.2.5 p40 to p47 (port 4) these are 8-bit i/o ports. the interrupt request flag (krif) can be set to 1 by detecting a falling edge. the following operating mode can be specified in 1-bit units. caution when using the falling edge detection interrupt (intkr), be sure to set the memory expansion mode register (mem) to 01h. (1) port mode these ports function as 8-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 4 (pm4). on-chip pull-up resistors can be used by setting pull-up resistor option register 4 (pu4). 2.2.6 p50 to p57 (port 5) these are 8-bit i/o ports. port 5 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 8-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 5 (pm5). on-chip pull-up resistors can be used by setting pull-up resistor option register 5 (pu5).
39 chapter 2 pin function preliminary user? manual u16035ej1v0um 2.2.7 p70 to p75 (port 7) these are 6-bit i/o ports. besides serving as i/o ports, they function as a timer i/o, clock output, and buzzer output. the following operating modes can be specified in 1-bit units. (1) port mode port 7 functions as a 6-bit i/o port. they can be specified as an input port or output port in 1-bit units with port mode register 7 (pm7). on-chip pull-up resistors can be used by setting pull-up resistor option register 7 (pu7). p70 and p71 are also 16-bit timer/event counter capture trigger signal input pins with a valid edge input. (2) control mode port 7 functions as timer i/o, clock output, and buzzer output. (a) ti00 external count clock input pin to 16-bit timer/event counter and capture trigger signal input pin to 16-bit timer/ event counter capture register (cr01). (b) ti01 capture trigger signal input pin to 16-bit timer/event counter capture register (cr00). (c) ti50 and ti51 external count clock input pins to 8-bit timer/event counter. (d) to0, to50, and to51 timer output pins. (e) pcl clock output pin. (f) buz buzzer output pin. 2.2.8 av ref this is an a/d converter reference voltage input pin. when no a/d converter is used, connect this pin to v ss0 . 2.2.9 av dd this is an analog power supply pin of a/d converter. always use the same potential as that of the v dd0 pin or v dd1 pin even when no a/d converter is used. 2.2.10 av ss this is a ground potential pin of a/d converter. always use the same potential as that of the v ss0 pin or v ss1 pin even when no a/d converter is used. 2.2.11 reset this is a low-level active system reset input pin.
40 chapter 2 pin function preliminary user? manual u16035ej1v0um 2.2.12 x1 and x2 crystal resonator connect pins for main system clock oscillation. for external clock supply, input clock signal to x1 and its inverted signal to x2. 2.2.13 xt1 and xt2 crystal resonator connect pins for subsystem clock oscillation. for external clock supply, input the clock signal to xt1 and its inverted signal to xt2. 2.2.14 v dd0 and v dd1 v dd0 is a positive power supply port pin. v dd1 is a positive power supply pin other than port pin. 2.2.15 v ss0 and v ss1 v ss0 is a ground potential port pin. v ss1 is a ground potential pin other than port pin. 2.2.16 v pp (flash memory versions only) high-voltage apply pin for flash memory programming mode setting and program write/verify. connect directly to v ss0 or v ss1 in the normal operating mode. 2.2.17 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the pd780024as, 780034as subseries at delivery. connect it directly to the v ss0 or v ss1 pin with the shortest possible wire in the normal operating mode. when a potential difference is produced between the ic pin and v ss0 pin or v ss1 pin, because the wiring between those two pins is too long or an external noise is input to the ic pin, the user? program may not operate normally. ? connect ic pins to v ss0 pins or v ss1 pins directly. as short as possible ic v ss0 or v ss1
41 chapter 2 pin function preliminary user s manual u16035ej1v0um 2.3 pin i/o circuits and recommended connection of unused pins table 2-1 shows the types of pin i/o circuit and the recommended connections of unused pins. refer to figure 2-1 for the configuration of the i/o circuit of each type. table 2-1. pin i/o circuit types pin name i/o circuit type i/o recommended connection of unused pins p00/intp0 to p02/intp2 8-c i/o input: independently connect to v ss0 via a resistor. p03/intp3/adtrg output: leave open p10/ani0 to p13/ani3 25 input connect to v dd0 or v ss0 . p20/si30 8-c i/o input: independently connect to v dd0 or v ss0 via a p21/so30 5-h resistor. p22/sck30 8-c output: leave open. p23/rxd0 p24/txd0 5-h p25/asck0 8-c p34/si31 8-c i/o input: independently connect to v dd0 or v ss0 via a p35/so31 5-h resistor. p36/sck31 8-c output: leave open. p40 to p47 5-h i/o input: independently connect to v dd0 via a resistor. output: leave open. p50 to p57 5-h i/o input: independently connect to v dd0 or v ss0 via a p70/ti00/to0 8-c i/o resistor. p71/ti01 output: leave open. p72/ti50/to50 p73/ti51/to51 p74/pcl 5-h p75/buz reset 2 input xt1 16 connect to v dd0 . xt2 leave open. av dd connect to v dd0 or v dd1 . av ref connect to v ss0 or v ss1 . av ss ic (for mask rom version) connect directly to v ss0 or v ss1 . v pp (for flash memory version)
42 chapter 2 pin function preliminary user s manual u16035ej1v0um figure 2-1. pin i/o circuit list type 2 schmitt-triggered input with hysteresis characteristics in type 8-c data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pullup enable type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pullup enable type 25 v ss0 v ss0 input enable comparator + p-ch n-ch v ref (threshold voltage) v ss0 in p-ch feedback cut-off xt1 xt2 type 16
43 preliminary user? manual u16035ej1v0um chapter 3 cpu architecture 3.1 memory spaces pd780024as, 780034as subseries can access 64 kb memory space respectively. figures 3-1 to 3-5 show memory maps. caution in case of the internal memory capacity, the initial value of memory size switching register (ims) of all products ( pd780024as, 780034as subseries) is fixed (cfh). therefore, set the value corresponding to each products indicated below. pd780021as, 780031as: 42h pd780022as, 780032as: 44h pd780023as, 780033as: c6h pd780024as, 780034as: c8h pd78f0034bs: value for mask rom version figure 3-1. memory map ( pd780021as, 780031as) 0000h data memory space general-purpose registers 32 8 bits internal rom 8192 8 bits 1fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area program memory space 2000h 1fffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits special function registers (sfrs) 256 8 bits reserved fd00h fcffh
44 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um figure 3-2. memory map ( pd780022as, 780032as) 0000h data memory space general-purpose registers 32 8 bits internal rom 16384 8 bits 3fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area program memory space 4000h 3fffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits special function registers (sfrs) 256 8 bits reserved fd00h fcffh
45 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um figure 3-3. memory map ( pd780023as, 780033as) 0000h data memory space general-purpose registers 32 8 bits internal rom 24576 8 bits 5fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area program memory space 6000h 5fffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh
46 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um figure 3-4. memory map ( pd780024as, 780034as) 0000h data memory space internal rom 32768 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area program memory space 8000h 7fffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh general-purpose registers 32 8 bits
47 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um figure 3-5. memory map ( pd78f0034bs) 0000h data memory space general-purpose registers 32 8 bits flash memory 32768 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area program memory space 8000h 7fffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh
48 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.1.1 internal program memory space the internal program memory space contains the program and table data. normally, it is addressed with the program counter (pc). the pd780024as, 780034as subseries products incorporate an on-chip rom (or flash memory), as listed below. table 3-1. internal rom capacity part number type capacity pd780021as, 780031as mask rom 8192 8 bits (0000h to 1fffh) pd780022as, 780032as 16384 8 bits (0000h to 3fffh) pd780023as, 780033as 24576 8 bits (0000h to 5fffh) pd780024as, 780034as 32768 8 bits (0000h to 7fffh) pd78f0034bs flash memory 32768 8 bits (0000h to 7fffh) the internal program memory space is divided into the following three areas. (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. of the 16- bit address, lower 8 bits are stored at even addresses and higher 8 bits are stored at odd addresses. table 3-2. vector table vector table address interrupt source vector table address interrupt source 0000h reset input 0016h intcsi31 0004h intwdt 001ah intwti 0006h intp0 001ch inttm00 0008h intp1 001eh inttm01 000ah intp2 0020h inttm50 000ch intp3 0022h inttm51 000eh intser0 0024h intad0 0010h intsr0 0026h intwt 0012h intst0 0028h intkr 0014h intcsi30 003eh brk (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf).
49 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.1.2 internal data memory space the pd780024as, 780034as subseries products incorporate an internal high-speed ram, as listed below. table 3-3. internal high-speed ram capacity part number internal high-speed ram pd780021as, 780031as 512 8 bits (fd00h to feffh) pd780022as, 780032as pd780023as, 780033as 1024 8 bits (fb00h to feffh) pd780024as, 780034as pd78f0034bs the 32-byte area fee0h to feffh is allocated four general-purpose register banks composed of eight 8-bit registers. the internal high-speed ram can also be used as a stack memory. 3.1.3 special function register (sfr) area an on-chip peripheral hardware special function register (sfr) is allocated in the area ff00h to ffffh (refer to 3.2.3 special function register (sfr) table 3-5 special function register list ). caution do not access addresses where the sfr is not assigned. 3.1.4 external memory space the external memory space is accessible with memory expansion mode register (mem). external memory space can store program, table data, etc., and allocate peripheral devices.
50 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.1.5 data memory addressing addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. the address of an instruction to be executed next is addressed by the program counter (pc) (for details, see 3.3 instruction address addressing ). several addressing modes are provided for addressing the memory relevant to the execution of instructions for the pd780024as, 780034as subseries, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. data memory addressing is illustrated in figures 3-6 to 3-10. for the details of each addressing mode, see 3.4 operand address addressing . figure 3-6. data memory addressing ( pd780021as, 780031as) 0000h general-purpose registers 32 8 bits internal rom 8192 8 bits 2000h 1fffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits reserved fd00h fcffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
51 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um figure 3-7. data memory addressing ( pd780022as, 780032as) 0000h general-purpose registers 32 8 bits internal rom 16384 8 bits 4000h 3fffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits reserved fd00h fcffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
52 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um figure 3-8. data memory addressing ( pd780023as, 780033as) 0000h general-purpose registers 32 8 bits internal rom 24576 8 bits 6000h 5fffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
53 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um figure 3-9. data memory addressing ( pd780024as, 780034as) 0000h general-purpose registers 32 8 bits internal rom 32768 8 bits 8000h 7fffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
54 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um figure 3-10. data memory addressing ( pd78f0034bs) 0000h general-purpose registers 32 8 bits flash memory 32768 8 bits 8000h 7fffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
55 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.2 processor registers the pd780024as, 780034as subseries products incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-11. format of program counter 15 0 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-12. format of program status word 70 psw ie z rbs1 ac rbs0 0 isp cy
56 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when 0, the ie is set to the disable interrupt (di) state, and only non-maskable interrupt request becomes acknowledgeable. other interrupt requests are all disabled. when 1, the ie is set to the enable interrupt (ei) state and interrupt request acknowledge enable is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources and a priority specification flag. the ie is reset (0) upon di instruction execution or interrupt acknowledgement and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when this flag is 0, low- level vectored interrupt requests specified with a priority specification flag register (pr0l, pr0h, pr1l) (refer to 15.3 (3) priority specification flag registers (pr0l, pr0h, pr1l) ) are disabled for acknowledgement. when it is 1, all interrupts are acknowledgeable. actual request acknowledgement is controlled with the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. the internal high-speed ram areas of each product are as follows. table 3-4. internal high-speed ram area part number internal high-speed ram area pd780021as, 780022as, 780031as, 780032as fd00h to feffh pd780023as, 780024as, 780033as, 780034as, fb00h to feffh 78f0034bs
57 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um figure 3-15. data to be restored from stack memory interrupt and brk instructions psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 reti and retb instructions psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7 to pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3 figure 3-13. format of stack pointer 15 0 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 3-14 and 3-15. caution since reset input makes sp contents undefined, be sure to initialize the sp before instruction execution. figure 3-14. data to be saved to stack memory
58 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h 3.2.2 general-purpose registers a general-purpose register is mapped at particular addresses (fee0h to feffh) of the data memory. it consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can also be used as an 8-bit register. two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. figure 3-16. configuration of general-purpose register (a) absolute name
59 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.2.3 special function register (sfr) unlike a general-purpose register, each special function register has special functions. it is allocated in the ff00h to ffffh area. the special function register can be manipulated like the general-purpose register, with the operation, transfer and bit manipulation instructions. manipulatable bit units, 1, 8, and 16, depend on the special function register type. each manipulation bit unit can be specified as follows. 1-bit manipulation describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 3-5 gives a list of special function registers. the meaning of items in the table is as follows. symbol symbol indicating the address of a special function register. it is a reserved word in the ra78k0, and is defined via the header file sfrbit.h in the cc78k0. when using the ra78k0, id78k0-ns, id78k0, or sm78k0, symbols can be written as an instruction operand. r/w indicates whether the corresponding special function register can be read or written. r/w: read/write enable r: read only w: write only manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). indicates a bit unit for which manipulation is not possible. after reset indicates each register status upon reset input.
60 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um table 3-5. special function register list (1/2) address special function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff00h port 0 p0 r/w ? 00h ff01h port 1 p1 r ? ff02h port 2 p2 r/w ? ff03h port 3 p3 ? ff04h port 4 p4 ? ff05h port 5 p5 ? ff07h port 7 p7 ? ff0ah 16-bit timer capture/compare register 00 cr00 undefined ff0bh ff0ch 16-bit timer capture/compare register 01 cr01 ff0dh ff0eh 16-bit timer counter 0 tm0 r 0000h ff0fh ff10h 8-bit timer compare register 50 cr50 r/w undefined ff11h 8-bit timer compare register 51 cr51 ff12h 8-bit timer counter 50 tm5 tm50 r ? 00h ff13h 8-bit timer counter 51 tm51 ff16h a/d conversion result register 0 adcr0 ff17h ff18h transmit shift register 0 txs0 w ffh receive buffer register 0 rxb0 r ff1ah serial i/o shift register 30 sio30 r/w undefined ff1bh serial i/o shift register 31 sio31 ff20h port mode register 0 pm0 ? ffh ff22h port mode register 2 pm2 ? ff23h port mode register 3 pm3 ? ff24h port mode register 4 pm4 ? ff25h port mode register 5 pm5 ? ff27h port mode register 7 pm7 ? ff30h pull-up resistor option register 0 pu0 ? 00h ff32h pull-up resistor option register 2 pu2 ? ff33h pull-up resistor option register 3 pu3 ? ff34h pull-up resistor option register 4 pu4 ? ff35h pull-up resistor option register 5 pu5 ? ff37h pull-up resistor option register 7 pu7 ? ff40h clock output select register cks ? ff41h watch timer operation mode register wtm ? ff42h watchdog timer clock select register wdcs
61 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um table 3-5. special function register list (2/2) address special function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff47h memory expansion mode register mem r/w ? 00h ff48h external interrupt rising edge enable register egp ? ff49h external interrupt falling edge enable register egn ? ff60h 16-bit timer mode control register 0 tmc0 ? ff61h prescaler mode register 0 prm0 ff62h capture/compare control register 0 crc0 ? ff63h 16-bit timer output control register 0 toc0 ? ff70h 8-bit timer mode control register 50 tmc50 ? ff71h timer clock select register 50 tcl50 ff78h 8-bit timer mode control register 51 tmc51 ? ff79h timer clock select register 51 tcl51 ff80h a/d converter mode register 0 adm0 ? ff81h analog input channel specification register 0 ads0 ffa0h asynchronous serial interface mode register 0 asim0 ? ffa1h asynchronous serial interface status register 0 asis0 r ffa2h baud rate generator control register 0 brgc0 r/w ffb0h serial operation mode register 30 csim30 ? ffb8h serial operation mode register 31 csim31 ? ffd0h external access area note 1 ? undefined to ffdfh ffe0h interrupt request flag register 0l if0 if0l ?? 00h ffe1h interrupt request flag register 0h if0h ? ffe2h interrupt request flag register 1l if1l ? ffe4h interrupt mask flag register 0l mk0 mk0l ?? ffh ffe5h interrupt mask flag register 0h mk0h ? ffe6h interrupt mask flag register 1l mk1l ? ffe8h priority level specification flag register 0l pr0 pr0l ?? ffe9h priority level specification flag register 0h pr0h ? ffeah priority level specification flag register 1l pr1l ? fff0h memory size switching register ims cfh note 2 fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time select register osts 04h fffbh processor clock control register pcc ? notes 1. the external access area cannot be accessed by sfr addressing. access it with the direct addressing method. 2. the default is cfh, but set the value corresponding to each respective product as indicated below. pd780021as, 780031as: 42h pd780022as, 780032as: 44h pd780023as, 780033as: c6h pd780024as, 780034as: c8h pd78f0034bs: value for mask rom version
62 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of instructions, refer to 78k/0 series instructions user s manual (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two s complement data ( 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists in relative branching from the start address of the following instruction to the 128 to +127 range. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ...
63 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branched to the entire memory space. the callf !addr11 instruction is branched to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions in the case of callf !addr11 instruction 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10 8 11 10 00001 643 callf fa 7 0
64 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. this instruction references the address stored in the memory table from 40h to 7fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4 0 operation code 70 rp 07 ax 15 0 pc 87
65 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.4 operand address addressing the following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register which functions as an accumulator (a and ax) in the general-purpose register is automatically (implicitly) addressed. of the pd780024as, 780034as subseries instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data which undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing.
66 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.4.2 register addressing [function] the general-purpose register to be specified is accessed as an operand with the register specify code (rn and rpn) of an instruction word in the registered bank specified with the register bank select flag (rbs0 and rbs1). register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 01100010 register specify code incw de; when selecting de register pair as rp operation code 10000100 register specify code
67 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.4.3 direct addressing [function] the memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op code 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code
68 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. an internal ram and a special function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. if the sfr area (ff00h to ff1fh) where short direct addressing is applied, ports which are frequently accessed in a program and a compare register of the timer/event counter and a capture register of the timer/event counter are mapped and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to the [illustration] on the next page. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh immediate data (even address only) [description example] mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h operation code 00010001 op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) [illustration] when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset
69 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 3.4.5 special function register (sfr) addressing [function] the memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 op code 00100000 20h (sfr-offset) [illustration]
70 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.4.6 register indirect addressing [function] register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory to be manipulated. this addressing can be carried out for all the memory spaces. [operand format] identifier description [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de
71 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified with the register bank select flag (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000
72 chapter 3 cpu architecture preliminary user s manual u16035ej1v0um 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction are added to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified with the register bank select flag (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] operation code 10101011 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. [description example] in the case of push de operation code 10110101
73 preliminary user s manual u16035ej1v0um chapter 4 port functions 4.1 port functions the pd780024as, 780034as subseries products incorporate four input ports and 35 i/o ports. figure 4-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as on-chip hardware i/o pins. figure 4-1. port types ? ? ? ? ? port 0 p00 port 1 p10 p13 ? ? ? ? ? ? ? port 2 p20 p25 port 3 p34 p36 ? ? ? ? ? ? ? ? ? port 5 p50 p57 ? ? ? ? ? ? ? port 7 p70 p75 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? port 4 p40 p47 p03
74 chapter 4 port functions preliminary user s manual u16035ej1v0um table 4-1. port functions alternate function intp0 intp1 intp2 intp3/adtrg ani0 to ani3 si30 so30 sck30 rxd0 txd0 asck0 si31 so31 sck31 ti00/to0 ti01 ti50/to50 ti51/to51 pcl buz pin name p00 p01 p02 p03 p10 to p13 p20 p21 p22 p23 p24 p25 p34 p35 p36 p40 to p47 p50 to p57 p70 p71 p72 p73 p74 p75 function port 0 4-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 1 4-bit input-only port. port 2 6-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 3 3-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be specified by software settings. port 4 8-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be specified by software settings. interrupt request flag (krif) is set to 1 by falling edge detection. port 5 8-bit i/o port. leds can be driven directly. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 7 6-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings.
75 chapter 4 port functions preliminary user? manual u16035ej1v0um 4.2 configuration of ports a port consists of the following hardware. table 4-2. configuration of ports item configuration control register port mode register (pmm: m = 0, 2 to 5, 7) pull-up resistor option register (pum,: m = 0, 2 to 5, 7) port total: 39 ports (4 inputs, 35 inputs/outputs) pull-up resistor total: 39 (software control) 4.2.1 port 0 port 0 is a 4-bit i/o port with output latch. p00 to p03 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (pm0). an on-chip pull-up resistor of p00 to p03 pins can be used for them in 1-bit units with a pull-up resistor option register 0 (pu0). this port can also be used as an external interrupt request input, and a/d converter external trigger input. reset input sets port 0 to input mode. figure 4-2 shows a block diagram of port 0. caution because port 0 also serves for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1.
76 chapter 4 port functions preliminary user? manual u16035ej1v0um figure 4-2. block diagram of p00 to p03 internal bus v dd0 p-ch p00/intp0 to p02/intp2, p03/intp3/adtrg wr pu rd wr port wr pm pu00 to pu03 alternate function output latch (p00 to p03) pm00 to pm03 selector pu: pull-up resistor option register pm: port mode register rd: port 0 read signal wr: port 0 write signal 4.2.2 port 1 port 1 is an 4-bit input-only port. this port can also be used as an a/d converter analog input. figure 4-3 shows a block diagram of port 1. figure 4-3. block diagram of p10 to p13 rd p10/ani0 to p13/ani3 internal bus rd: port 1 read signal caution when port 1 is used as a input port, the input value can be read using an 8-bit memory manipulation instruction. however, in this case, do not use the higher 4 bits (p17 to p14) because they are undefined. also, do not read the higher 4 bits using a 1-bit memory manipulation instruction.
77 chapter 4 port functions preliminary user s manual u16035ej1v0um 4.2.3 port 2 port 2 is a 6-bit i/o port with output latch. p20 to p25 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (pm2). an on-chip pull-up resistor of p20 to p25 pins can be used for them in 1-bit units with a pull-up resistor option register 2 (pu2). this port has also alternate functions as serial interface data i/o and clock i/o. reset input sets port 2 to input mode. figures 4-4 and 4-5 show block diagrams of port 2. figure 4-4. block diagram of p20, p22, p23, and p25 internal bus v dd0 p-ch p20/si30, p22/sck30, p23/rxd0, p25/asck0 wr pu rd wr port wr pm pu20, pu22, pu23, pu25 alternate function output latch (p20, p22, p23, p25) pm20, pm22, pm23, pm25 selector pu: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal
78 chapter 4 port functions preliminary user s manual u16035ej1v0um figure 4-5. block diagram of p21 and p24 rd p21/so30, p24/txd0 p-ch wr pu wr port wr pm pu21, pu24 output latch (p21, p24) pm21, pm24 selector v dd0 internal bus alternate function pu: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal
79 chapter 4 port functions preliminary user? manual u16035ej1v0um 4.2.4 port 3 port 3 is a 3-bit i/o port with output latch. p34 to p36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (pm3). use of an on-chip pull-up resistor can be specified for the p34 to p36 pins in 1- bit units by pull-up resistor option register 3 (pu3). port 3 can also be used for serial interface data i/o and clock i/o. reset input sets port 3 to input mode. figures 4-6 and 4-7 show block diagrams of port 3. cautions 1. when reading port 3 using an 8-bit memory manipulation instruction, do not use the lower 4 bits (p33 to p30) because they are undefined. when writing port 3 using an 8-bit memory manipulation instruction, any values can be written to the lower 4 bits. execution of a 1-bit memory manipulation instruction for the lower 4 bits is prohibited. 2. be sure to set the lower 4 bits (pm33 to pm30) of port mode register 3 (pm3) to 1. figure 4-6. block diagram of p34 and p36 internal bus v dd0 p-ch p34/si31, p36/sck31 wr pu rd wr port wr pm pu34, pu36 alternate function output latch (p34, p36) pm34, pm36 selector pu: pull-up resistor option register pm: port mode register rd: port 3 read signal wr: port 3 write signal
80 chapter 4 port functions preliminary user s manual u16035ej1v0um figure 4-7. block diagram of p35 rd p35/so31 p-ch wr pu wr port wr pm pu35 output latch (p35) pm35 selector v dd0 internal bus alternate function pu: pull-up resistor option register pm: port mode register rd: port 3 read signal wr: port 3 write signal
81 chapter 4 port functions preliminary user s manual u16035ej1v0um 4.2.5 port 4 port 4 is an 8-bit i/o port with output latch. the p40 to p47 pins can specify the input mode/output mode in 1- bit units with port mode register 4 (pm4). an on-chip pull-up resistor of p40 to p47 pins can be used for them in 1- bit units with pull-up resistor option register 4 (pu4). the interrupt request flag (krif) can be set to 1 by detecting falling edges. reset input sets port 4 to input mode. figures 4-8 and 4-9 show a block diagram of port 4 and block diagram of the falling edge detector, respectively. caution when using the falling edge detection interrupt (intkr), be sure to set the memory expansion mode register (mem) to 01h. figure 4-8. block diagram of p40 to p47 rd p40/ad0 to p47/ad7 p-ch wr pu wr port wr pm pu40 to pu47 output latch (p40 to p47) pm40 to pm47 selector v dd0 internal bus selector memory expansion mode register (mem) pu: pull-up resistor option register pm: port mode register rd: port 4 read signal wr: port 4 write signal figure 4-9. block diagram of falling edge detector p40 p41 p42 p43 p44 p45 p46 p47 intkr falling edge detector 1 when mem = 01h
82 chapter 4 port functions preliminary user s manual u16035ej1v0um 4.2.6 port 5 port 5 is an 8-bit i/o port with output latch. the p50 to p57 pins can specify the input mode/output mode in 1- bit units with port mode register 5 (pm5). an on-chip pull-up resistor of p50 to p57 pins can be used for them in 1- bit units with pull-up resistor option register 5 (pu5). port 5 can drive leds directly. reset input sets port 5 to input mode. figure 4-10 shows a block diagram of port 5. figure 4-10. block diagram of p50 to p57 rd p50/a8 to p57/a15 p-ch wr pu wr port wr pm pu50 to pu57 output latch (p50 to p57) pm50 to pm57 selector v dd0 internal bus selector memory expansion mode register (mem) pu: pull-up resistor option register pm: port mode register rd: port 5 read signal wr: port 5 write signal
83 chapter 4 port functions preliminary user s manual u16035ej1v0um 4.2.7 port 7 port 7 is a 6-bit i/o port with output latch. the p70 to p75 pins can specify the input mode/output mode in 1-bit units with port mode register 7 (pm7). an on-chip pull-up resistor of p70 to p75 pins can be used for them in 1-bit units with pull-up resistor option register 7 (pu7). this port can also be used as a timer i/o, clock output, and buzzer output. reset input sets port 7 to input mode. figures 4-11 and 4-12 show block diagrams of port 7. figure 4-11. block diagram of p70 to p73 internal bus v dd0 p-ch p70/ti00/to0, p71/ti01, p72/ti50/to50, p73/ti51/to51 wr pu rd wr port wr pm pu70 to pu73 alternate function output latch (p70 to p73) pm70 to pm73 selector alternate function pu: pull-up resistor option register pm: port mode register rd: port 7 read signal wr: port 7 write signal
84 chapter 4 port functions preliminary user s manual u16035ej1v0um figure 4-12. block diagram of p74 and p75 rd p74/pcl, p75/buz p-ch wr pu wr port wr pm pu74, pu75 pm74, pm75 selector v dd0 alternate function output latch (p74, p75) internal bus pu: pull-up resistor option register pm: port mode register rd: port 7 read signal wr: port 7 write signal
85 chapter 4 port functions preliminary user s manual u16035ej1v0um 4.3 registers to control port function the following two types of registers control the ports. port mode registers (pm0, pm2 to pm5, pm7) pull-up resistor option registers (pu0, pu2 to pu5, pu7) (1) port mode registers (pm0, pm2 to pm5, pm7) these registers are used to set port input/output in 1-bit units. pm0, pm2 to pm5, and pm7 are independently set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. cautions 1. pins p10 to p17 are input-only pins. 2. if a port has an alternate function pin and it is used as an alternate output function, set the output latches (p0 and p2 to p7) to 0.
86 chapter 4 port functions preliminary user s manual u16035ej1v0um figure 4-13. format of port mode register (pm0, pm2 to pm5, pm7) address: ff20h after reset: ffh r/w symbol 76543210 pm0 1111 pm03 pm02 pm01 pm00 address: ff22h after reset: ffh r/w symbol 76543210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 address: ff23h after reset: ffh r/w symbol 76543210 pm3 1 pm36 pm35 pm34 1 note 1 note 1 note 1 note address: ff24h after reset: ffh r/w symbol 76543210 pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 address: ff25h after reset: ffh r/w symbol 76543210 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 address: ff27h after reset: ffh r/w symbol 76543210 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pmmn pmn pin i/o mode selection (m = 0, 2 to 5, 7; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) note since the lower 4 bits (pm33 to pm30) of pm3 are not fixed to 1, be sure to set the lower 4 bits to 1 when setting by an 8-bit memory manipulation instruction.
87 chapter 4 port functions preliminary user s manual u16035ej1v0um (2) pull-up resistor option registers (pu0, pu2 to pu5, pu7) these registers are used to set whether to use an on-chip pull-up resistor at each port or not. by setting pu0, pu2 to pu5, and pu7, the on-chip pull-up resistors of the port pins corresponding to the bits in pu0, pu2 to pu5, and pu7 can be used. pu0, pu2 to pu5, and pu7 are independently set by a 1-bit or 8-bit memory manipulation instruction. reset input sets registers to 00h. cautions 1. the p10 to p13 pins do not incorporate a pull-up resistor. 2. when pum is set to 1, the on-chip pull-up resistor is connected irrespective of the input/ output mode. when using in output mode, therefore, set the bit of pum to 0 (m = 0, 2 to 5, 7).
88 chapter 4 port functions preliminary user s manual u16035ej1v0um figure 4-14. format of pull-up resistor option register (pu0, pu2 to pu5, pu7) address: ff30h after reset: 00h r/w symbol 76543210 pu0 0000 pu03 pu02 pu01 pu00 address: ff32h after reset: 00h r/w symbol 76543210 pu2 0 0 pu25 pu24 pu23 pu22 pu21 pu20 address: ff33h after reset: 00h r/w symbol 76543210 pu3 0 pu36 pu35 pu34 0000 address: ff34h after reset: 00h r/w symbol 76543210 pu4 pu47 pu46 pu45 pu44 pu43 pu42 pu41 pu40 address: ff35h after reset: 00h r/w symbol 76543210 pu5 pu57 pu56 pu55 pu54 pu53 pu52 pu51 pu50 address: ff37h after reset: 00h r/w symbol 76543210 pu7 0 0 pu75 pu74 pu73 pu72 pu71 pu70 pumn pmn pin on-chip pull-up resistor selection (m = 0, 2 to 5, 7; n = 0 to 7) 0 on-chip pull-up resistor not used 1 on-chip pull-up resistor used
89 chapter 4 port functions preliminary user s manual u16035ej1v0um 4.4 operations of port function port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 4.4.2 reading from i/o port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
90 preliminary user s manual u16035ej1v0um chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are available. (1) main system clock oscillator this circuit oscillates at frequencies of 1 to 8.38 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). (2) subsystem clock oscillator the circuit oscillates at a frequency of 32.768 khz. oscillation cannot be stopped. if the subsystem clock oscillator is not used, the internal feedback resistor can be disabled by the processor clock control register (pcc). this enables to reduce the power consumption in the stop mode. 5.2 configuration of clock generator the clock generator consists of the following hardware. table 5-1. configuration of clock generator item configuration control register processor clock control register (pcc) oscillators main system clock oscillator subsystem clock oscillator
91 chapter 5 clock generator preliminary user s manual u16035ej1v0um figure 5-1. block diagram of clock generator frc subsystem clock oscillator f xt x1 x2 main system clock oscillator f x prescaler f x 2 f x 2 2 f x 2 3 f x 2 4 f xt 2 1/2 prescaler watch timer, clock output function clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller 3 stop mcc frc cls css pcc2 pcc1 pcc0 processor clock control register (pcc) internal bus selector xt1 xt2
92 chapter 5 clock generator preliminary user s manual u16035ej1v0um 5.3 registers to control clock generator the clock generator is controlled by the processor clock control register (pcc). the pcc sets whether to use cpu clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor. the pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the pcc to 04h. figure 5-2. subsystem clock feedback resistor frc p-ch feedback resistor xt1 xt2
93 chapter 5 clock generator preliminary user s manual u16035ej1v0um figure 5-3. format of processor clock control register (pcc) address: fffbh after reset: 04h r/w note 1 symbol 76543210 pcc mcc frc cls css 0 pcc2 pcc1 pcc0 mcc main system clock oscillation control note 2 0 oscillation possible 1 oscillation stopped frc subsystem clock feedback resistor selection note 3 0 internal feedback resistor used 1 internal feedback resistor not used cls cpu clock status 0 main system clock 1 subsystem clock css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 1000f xt /2 001 010 011 100 other than above setting prohibited notes 1. bit 5 is read only. 2. when the cpu is operating on the subsystem clock, mcc should be used to stop the main system clock oscillation. a stop instruction should not be used. 3. the feedback resistor is required to adjust the bias point of the oscillation waveform to close to the middle of the power supply voltage. setting frc to 1 can further reduce the current consumption in the stop mode, but only when the subsystem clock is not used. cautions 1. be sure to set bit 3 to 0. 2. when the external clock is input, mcc should not be set. this is because the x2 pin is connected to v dd1 via a pull-up resistor. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
94 chapter 5 clock generator preliminary user s manual u16035ej1v0um the fastest instructions of pd780024as, 780034as subseries are carried out in two cpu clocks. the relationship of cpu clock (f cpu ) and minimum instruction execution time is shown in table 5-2. table 5-2. relationship of cpu clock and minimum instruction execution time cpu clock (f cpu ) minimum instruction execution time: 2/f cpu f x 0.24 s f x /2 0.48 s f x /2 2 0.95 s f x /2 3 1.91 s f x /2 4 3.81 s f xt /2 122 s f x = 8.38 mhz, f xt = 32.768 khz f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 5.4 system clock oscillator 5.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (8.38 mhz typ.) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the x1 pin and an inverted-phase clock signal to the x2 pin. figure 5-4 shows an external circuit of the main system clock oscillator. figure 5-4. external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock crystal resonator or ceramic resonator x2 x1 pd74hcu04 external clock x2 x1 ic v ss1 caution do not execute the stop instruction and do not set mcc (bit 7 of processor clock control register (pcc)) to 1 if an external clock is input. this is because when the stop instruction or mcc is set to 1, the main system clock operation stops and the x2 pin is connected to v dd1 via a pull-up resistor.
95 chapter 5 clock generator preliminary user s manual u16035ej1v0um 5.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (32.768 khz typ.) connected to the xt1 and xt2 pins. external clocks can be input to the subsystem clock oscillator. in this case, input a clock signal to the xt1 pin and an inverted-phase clock signal to the xt2 pin. figure 5-5 shows an external circuit of the subsystem clock oscillator. figure 5-5. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 ic xt1 32.768 khz xt1 xt2 pd74hcu04 external clock v ss1 cautions are listed on the next page.
96 chapter 5 clock generator preliminary user s manual u16035ej1v0um cautions 1. when using the main system clock oscillator and a subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in figures 5-4 and 5-5 to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that current consumption is maintained at low levels. figure 5-6 shows examples of incorrect resonator connection. figure 5-6. examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line x1 ic x2 x2 ic x1 portn (n = 0 to 7) v ss1 v ss1 remark when using a subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. further, insert resistors in series on the side of xt2.
97 chapter 5 clock generator preliminary user s manual u16035ej1v0um figure 5-6. examples of incorrect resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) ic x2 x1 ic x2 x1 ab c pmn v dd0 high current high current v ss1 v ss1 (e) signals are fetched ic x2 x1 v ss1 remark when using a subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. cautions 2. when x2 and xt1 are wired in parallel, the crosstalk noise of x2 may increase with xt1, resulting in malfunctioning. to prevent that from occurring, it is recommended to wire x2 and xt1 so that they are not in parallel, and to connect the ic pin between x2 and xt1 directly to v ss1 .
98 chapter 5 clock generator preliminary user s manual u16035ej1v0um 5.4.3 divider the divider divides the main system clock oscillator output (f x ) and generates various clocks. 5.4.4 when no subsystem clocks are used if it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the xt1 and xt2 pins as follows. xt1: connect to v dd0 xt2: open in this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. to minimize leakage current, the above internal feedback resistor can be removed with bit 6 (frc) of the processor clock control register (pcc). in this case also, connect the xt1 and xt2 pins as described above.
99 chapter 5 clock generator preliminary user s manual u16035ej1v0um 5.5 clock generator operations the clock generator generates the following various types of clocks and controls the cpu operating mode including the standby mode. main system clock f x subsystem clock f xt cpu clock f cpu clock to peripheral hardware the following clock generator functions and operations are determined with the processor clock control register (pcc). (a) upon generation of reset signal, the lowest speed mode of the main system clock (3.81 s @ 8.38 mhz operation) is selected (pcc = 04h). main system clock oscillation stops while low level is applied to reset pin. (b) with the main system clock selected, one of the five cpu clock types (0.24 s, 0.48 s, 0.95 s, 1.91 s, 3.81 s, @ 8.38 mhz operation) can be selected by setting the pcc. (c) with the main system clock selected, two standby modes, the stop and halt modes, are available. to reduce current consumption in the stop mode, the subsystem clock feedback resistor can be disconnected to stop the subsystem clock. (d) the pcc can be used to select the subsystem clock and to operate the system with low-current consumption (122 s @ 32.768 khz operation). (e) with the subsystem clock selected, main system clock oscillation can be stopped with the pcc. the halt mode can be used. however, the stop mode cannot be used (subsystem clock oscillation cannot be stopped). (f) the main system clock is divided and supplied to the peripheral hardware. the subsystem clock is supplied to the watch timer and clock output functions only. thus the watch function and the clock output function can also be continued in the standby state. however, since all other peripheral hardware operate with the main system clock, the peripheral hardware also stops if the main system clock is stopped (except external input clock operation).
100 chapter 5 clock generator preliminary user s manual u16035ej1v0um 5.5.1 main system clock operations when operated with the main system clock (with bit 5 (cls) of the processor clock control register (pcc) set to 0), the following operations are carried out by pcc setting. (a) because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (pcc0 to pcc2) of the pcc. (b) if bit 7 (mcc) of the pcc is set to 1 when operated with the main system clock, the main system clock oscillation does not stop. when bit 4 (css) of the pcc is set to 1 and the operation is switched to subsystem clock operation (cls = 1) after that, the main system clock oscillation stops (see figure 5-7 ). figure 5-7. main system clock stop function (1/2) (a) operation when mcc is set after setting css with main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock (b) operation when mcc is set in case of main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock l l oscillation does not stop.
101 chapter 5 clock generator preliminary user s manual u16035ej1v0um figure 5-7. main system clock stop function (2/2) (c) operation when css is set after setting mcc with main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock 5.5.2 subsystem clock operations when operated with the subsystem clock (with bit 5 (cls) of the processor clock control register (pcc) set to 1), the following operations are carried out. (a) the minimum instruction execution time remains constant (122 s @ 32.768 khz operation) irrespective of bits 0 to 2 (pcc0 to pcc2) of the pcc. (b) watchdog timer counting stops. caution do not execute the stop instruction while the subsystem clock is in operation. 5.6 changing system clock and cpu clock settings 5.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by means of bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc, but operation continues on the pre-switchover clock for several instructions (see table 5-3 ). determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 (cls) of the pcc register.
102 chapter 5 clock generator preliminary user? manual u16035ej1v0um table 5-3. maximum time required for cpu clock switchover set value before set value after switchover switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 0000 00 01001000 1101001 0000 16 instructions 16 instructions 16 instructions 16 instructions f x /2f xt instruction (128 instructions) 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions f x /4f xt instruction (64 instructions) 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions f x /8f xt instruction (32 instructions) 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions f x /16f xt instruction (16 instructions) 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction f x /32f xt instruction (8 instructions) 1 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction remarks 1. one instruction is the minimum instruction execution time with the pre-switchover cpu clock. 2. figures in parentheses are for operation with f x = 8.38 mhz and f xt = 32.768 khz. caution selection of the cpu clock cycle dividing factor (pcc0 to pcc2) and switchover from the main system clock to the subsystem clock (changing css from 0 to 1) should not be set simultaneously. simultaneous setting is possible, however, for selection of the cpu clock cycle dividing factor (pcc0 to pcc2) and switch over from the subsystem clock to the main system clock (changing css from 1 to 0).
103 chapter 5 clock generator preliminary user s manual u16035ej1v0um 5.6.2 system clock and cpu clock switching procedure this section describes switching procedure between the system clock and cpu clock. figure 5-8. system clock and cpu clock switching system clock cpu clock interrupt request signal reset v dd f x f x f xt f x lowest- speed operation highest- speed operation subsystem clock operation high-speed operation wait (15.6 ms: @8.38 mhz operation) internal reset operation <1> the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, main system clock starts oscillation. at this time, oscillation stabilization time (2 17 /f x ) is secured automatically. after that, the cpu starts executing the instruction at the minimum speed of the main system clock (3.81 s @ 8.38 mhz operation). <2> after the lapse of a sufficient time for the v dd voltage to increase to enable operation at maximum speeds, the pcc is rewritten and maximum-speed operation is carried out. <3> upon detection of a decrease of the v dd voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). <4> upon detection of v dd voltage reset due to an interrupt, 0 is set to bit 7 (mcc) of the pcc and oscillation of the main system clock is started. after the lapse of time required for stabilization of oscillation, the pcc is rewritten and the maximum-speed operation is resumed. caution when subsystem clock is being operated while the main system clock is stopped, if switching to the main system clock is done again, be sure to switch after securing oscillation stabilization time by program.
104 preliminary user? manual u16035ej1v0um chapter 6 16-bit timer/event counter 0 6.1 functions of 16-bit timer/event counter 0 the 16-bit timer/event counter 0 has the following functions. interval timer ppg output pulse width measurement external event counter square-wave output (1) interval timer tm0 generates interrupt request at the preset time interval. (2) ppg output tm0 can output a square wave whose frequency and output pulse can be set freely. (3) pulse width measurement tm0 can measure the pulse width of an externally input signal. (4) external event counter tm0 can measure the number of pulses of an externally input signal. (5) square-wave output tm0 can output a square wave with any selected frequency.
105 chapter 6 16-bit timer/event counter 0 preliminary user? manual u16035ej1v0um 6.2 configuration of 16-bit timer/event counter 0 16-bit timer/event counter 0 consists of the following hardware. table 6-1. configuration of 16-bit timer/event counter 0 item configuration timer/counter 16 bits 1 (tm0) register 16-bit timer capture/compare register: 16 bits 2 (cr00, cr01) timer output 1 (to0) control registers 16-bit timer mode control register 0 (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register 0 (toc0) prescaler mode register 0 (prm0) port mode register 7 (pm7) note note see figure 4-11 block diagram of p70 to p73 and figure 4-12 block diagram of p74 and p75. figure 6-1 shows a block diagram. figure 6-1. block diagram of 16-bit timer/event counter 0 internal bus capture/compare control register 0 (crc0) ti01/p71 f x f x /2 2 f x /2 6 f x /2 3 ti00/to0/p70 prescaler mode register 0 (prm0) 2 prm01 prm00 crc02 16-bit timer capture/compare register 01 (cr01) match match 16-bit timer counter 0 (tm0) clear noise elimi- nator crc02 crc01 crc00 inttm00 to0/ti00/ p70 inttm01 16-bit timer output control register 0 (toc0) 16-bit timer mode control register 0 (tmc0) internal bus tmc03 tmc02 tmc01 ovf0 toc04 lvs0 lvr0 toc01 toe0 selector 16-bit timer capture/compare register 00 (cr00) selector selector selector noise elimi- nator noise elimi- nator output controller
106 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um (1) 16-bit timer counter 0 (tm0) tm0 is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of an input clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases: <1> at reset input <2> if tmc03 and tmc02 are cleared <3> if valid edge of ti00 is input in the clear & start mode by inputting valid edge of ti00 <4> if tm0 and cr00 match in the clear & start mode on match between tm0 and cr00 (2) 16-bit timer capture/compare register 00 (cr00) cr00 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare register is set by bit 0 (crc00) of capture/compare control register 0 (crc0). when cr00 is used as a compare register the value set in the cr00 is constantly compared with the 16-bit timer counter 0 (tm0) count value, and an interrupt request (inttm00) is generated if they match. it can also be used as the register which holds the interval time when tm0 is set to interval timer operation. when cr00 is used as a capture register it is possible to select the valid edge of the ti00/to0/p70 pin or the ti01/p71 pin as the capture trigger. setting of the ti00 or ti01 valid edge is performed by means of prescaler mode register 0 (prm0). if cr00 is specified as a capture register and capture trigger is specified to be the valid edge of the ti00/to0/ p70 pin, the situation is as shown in table 6-2. on the other hand, when capture trigger is specified to be the valid edge of the ti01/p71 pin, the situation is as shown in table 6-3. table 6-2. ti00/to0/p70 pin valid edge and cr00, cr01 capture trigger es01 es00 ti00/to0/p70 pin valid edge cr00 capture trigger cr01 capture trigger 0 0 falling edge rising edge falling edge 0 1 rising edge falling edge rising edge 1 0 setting prohibited setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation both rising and falling edges table 6-3. ti01/p71 pin valid edge and cr00 capture trigger es11 es10 ti01/p71 pin valid edge cr00 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges
107 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um cr00 is set by a 16-bit memory manipulation instruction. after reset input, the value of cr00 is undefined. cautions 1. set a value other than 0000h in cr00 in the clear & start mode on match between tm0 and cr00. however, in the free-running mode and in the clear mode using the valid edge of ti00, if 0000h is set to cr00, an interrupt request (inttm00) is generated following overflow (ffffh). 2. if the value after cr00 is changed is smaller than that of 16-bit timer counter 0 (tm0), tm0 continues counting, overflows and then restarts counting from 0. thus, if the value after cr00 is changed is smaller than the value before it was changed, it is necessary to restart the timer after changing cr00. 3. when p70 is used as the valid edge of ti00, it cannot be used as timer output (to0). moreover, when p70 is used as to0, it cannot be used as the valid edge of ti00. (3) 16-bit timer capture/compare register 01 (cr01) cr01 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare register is set by bit 2 (crc02) of capture/compare control register 0 (crc0). when cr01 is used as a compare register the value set in the cr01 is constantly compared with the 16-bit timer counter 0 (tm0) count value, and an interrupt request (inttm01) is generated if they match. when cr01 is used as a capture register it is possible to select the valid edge of the ti00/to0/p70 pin as the capture trigger. the ti00/to0/p70 valid edge is set by means of prescaler mode register 0 (prm0). cr01 is set by a 16-bit memory manipulation instruction. after reset input, the value of cr01 is undefined. caution set other than 0000h to cr01. this means 1-pulse count operation cannot be performed when cr01 is used as the event counter. however, in the free-running mode and in the clear mode using the valid edge of ti00, if 0000h is set to cr01, an interrupt request (inttm01) is generated following overflow (ffffh).
108 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um 6.3 registers to control 16-bit timer/event counter 0 the following five types of registers are used to control the 16-bit timer/event counter 0. 16-bit timer mode control register 0 (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register 0 (toc0) prescaler mode register 0 (prm0) port mode register 7 (pm7) (1) 16-bit timer mode control register 0 (tmc0) this register sets the 16-bit timer operating mode, the 16-bit timer counter 0 (tm0) clear mode, and output timing, and detects an overflow. tmc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc0 value to 00h. caution the 16-bit timer counter 0 (tm0) starts operation at the moment a value other than 0, 0 (operation stop mode) is set in tmc02 and tmc03, respectively. set 0, 0 in tmc02 and tmc03 to stop the operation.
109 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um figure 6-2. format of 16-bit timer mode control register 0 (tmc0) tmc03 tmc02 tmc01 operating mode to0 output timing selection interrupt request generation and clear mode selection 0 0 0 operation stop no change not generated 0 0 1 (tm0 cleared to 0) 0 1 0 free-running mode match between tm0 and cr00 or match between tm0 and cr01 0 1 1 match between tm0 and cr00, match between tm0 and cr01 or ti00 valid edge 1 0 0 clear & start on ti00 valid 101 edge 1 1 0 clear & start on match match between tm0 and between tm0 and cr00 cr00 or match between tm0 and cr01 1 1 1 match between tm0 and cr00, match between tm0 and cr01 or ti00 valid edge ovf0 16-bit timer counter 0 (tm0) overflow detection 0 overflow not detected 1 overflow detected cautions 1. timer operation must be stopped before writing to bits other than the ovf0 flag. 2. set the valid edge of the ti00/to0/p70 pin with prescaler mode register 0 (prm0). 3. if clear & start mode on match between tm0 and cr00 is selected, when the set value of cr00 is ffffh and the tm0 value changes from ffffh to 0000h, ovf0 flag is set to 1. remark to0: 16-bit timer/event counter output pin ti00: 16-bit timer/event counter input pin tm0: 16-bit timer counter 0 cr00: 16-bit timer capture/compare register 00 cr01: 16-bit timer capture/compare register 01 generated on match between tm0 and cr00, or match between tm0 and cr01 7 0 6 0 5 0 4 0 3 tmc03 2 tmc02 1 tmc01 0 ovf0 symbol tmc0 address ff60h after reset: 00h r/w
110 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um (2) capture/compare control register 0 (crc0) this register controls the operation of the 16-bit timer capture/compare registers (cr00, cr01). crc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets crc0 value to 00h. figure 6-3. format of capture/compare control register 0 (crc0) address: ff62h after reset: 00h r/w symbol 76543210 crc0 00000 crc02 crc01 crc00 crc02 cr01 operating mode selection 0 operates as compare register 1 operates as capture register crc01 cr00 capture trigger selection 0 captures on valid edge of ti01 1 captures on valid edge of ti00 by reverse phase crc00 cr00 operating mode selection 0 operates as compare register 1 operates as capture register cautions 1. timer operation must be stopped before setting crc0. 2. when clear & start mode on a match between tm0 and cr00 is selected with the 16-bit timer mode control register 0 (tmc0), cr00 should not be specified as a capture register. 3. if both the rising and falling edges have been selected as the valid edges of ti00, capture is not performed. 4. to ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0 (prm0).
111 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um (3) 16-bit timer output control register 0 (toc0) this register controls the operation of the 16-bit timer/event counter 0 output controller. it sets r-s type flip-flop (lv0) setting/resetting, output inversion enabling/disabling, and 16-bit timer/event counter 0 timer output enabling/disabling. toc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets toc0 value to 00h. figure 6-4 shows the toc0 format. figure 6-4. format of 16-bit timer output control register 0 (toc0) address: ff63h after reset: 00h r/w symbol 76543210 toc0 0 0 0 toc04 lvs0 lvr0 toc01 toe0 toc04 timer output f/f control by match of cr01 and tm0 0 inversion operation disabled 1 inversion operation enabled lvs0 lvr0 16-bit timer/event counter timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc01 timer output f/f control by match of cr00 and tm0 0 inversion operation disabled 1 inversion operation enabled toe0 16-bit timer/event counter output control 0 output disabled (output set to level 0) 1 output enabled cautions 1. timer operation must be stopped before setting toc0. 2. if lvs0 and lvr0 are read after data is set, they will be 0.
112 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um (4) prescaler mode register 0 (prm0) this register is used to set 16-bit timer counter 0 (tm0) count clock and ti00, ti01 input valid edges. prm0 is set by an 8-bit memory manipulation instruction. reset input sets prm0 value to 00h. figure 6-5. format of prescaler mode register 0 (prm0) address: ff61h after reset: 00h r/w symbol 76543210 prm0 es11 es10 es01 es00 0 0 prm01 prm00 es11 es10 ti01 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es01 es00 ti00 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm01 prm00 count clock selection 00f x (8.38 mhz) 01f x /2 2 (2.09 mhz) 10f x /2 6 (131 khz) 1 1 ti00 valid edge note note the external clock requires a pulse two times longer than internal clock (f x /2 3 ). cautions 1. if the valid edge of ti00 is to be set to the count clock, do not set the clear & start mode and the capture trigger at the valid edge of ti00. moreover, do not use the p70/ti00/to0 pins as timer outputs (to0). 2. always set data to prm0 after stopping the timer operation. 3. if the ti00 or ti01 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti00 pin or ti01 pin to enable the operation of the 16-bit timer counter 0 (tm0). please be careful when pulling up the ti00 pin or the ti01 pin. however, when re- enabling operation after the operation has been stopped once, the rising edge is not detected. remarks 1. f x : main system clock oscillation frequency 2. ti00, ti01: 16-bit timer/event counter input pin 3. figures in parentheses are for operation with f x = 8.38 mhz.
113 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um (5) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p70/to0/ti00 pin for timer output, set pm70 and the output latch of p70 to 0. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 value to ffh. figure 6-6. format of port mode register 7 (pm7) 7 1 6 1 5 pm75 4 pm74 3 pm73 2 pm72 1 pm71 0 pm70 symbol pm7 address: ff27h after reset: ffh r/w pm7n 0 1 p7n pin i/o mode selection (n = 0 to 5) output mode (output buffer on) input mode (output buffer off)
114 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um 6.4 operations of 16-bit timer/event counter 0 6.4.1 interval timer operations setting the 16-bit timer mode control register 0 (tmc0) and capture/compare control register 0 (crc0) as shown in figure 6-7 allows operation as an interval timer. interrupt request is generated repeatedly using the count value set in 16-bit timer capture/compare register 00 (cr00) beforehand as the interval. when the count value of the 16-bit timer counter 0 (tm0) matches the value set to cr00, counting continues with the tm0 value cleared to 0 and the interrupt request signal (inttm00) is generated. count clock of the 16-bit timer/event counter can be selected with bits 0 and 1 (prm00, prm01) of the prescaler mode register 0 (prm0). see 6.5 cautions for 16-bit timer/event counter 0 (2) about the operation when the compare register value is changed during timer count operation. figure 6-7. control register settings for interval timer operation (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see figures 6-2 and 6-3 . 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on match between tm0 and cr00
115 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um figure 6-8. interval timer configuration diagram 16-bit timer capture/compare register 00 (cr00) 16-bit timer counter 0 (tm0) ovf0 clear circuit inttm00 f x f x /2 2 f x /2 6 ti00/to0/p70 selector noise eliminator f x /2 3 figure 6-9. timing of interval timer operation remark interval time = (n + 1) t n = 0001h to ffffh count clock t tm0 count value cr00 inttm00 to0 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n count start clear clear interrupt request acknowledged interrupt request acknowledged interval time interval time interval time
116 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um 6.4.2 ppg output operations setting the 16-bit timer mode control register 0 (tmc0) and capture/compare control register 0 (crc0) as shown in figure 6-10 allows operation as ppg (programmable pulse generator) output. in the ppg output operation, square waves are output from the to0/ti00/p70 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit timer capture/compare register 01 (cr01) and in 16-bit timer capture/compare register 00 (cr00), respectively. figure 6-10. control register settings for ppg output operation (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 1 tmc02 1 tmc01 0 ovf0 0 tmc0 clears and starts on match between tm0 and cr00 (b) capture/compare control register 0 (crc0) 00000 crc02 0 crc01 crc00 0 crc0 cr00 as compare register cr01 as compare register (c) 16-bit timer output control register 0 (toc0) 000 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output reverses output on match between tm0 and cr00 specifies initial value of to0 output f/f reverses output on match between tm0 and cr01 cautions 1. values in the following range should be set in cr00 and cr01: 0000h < cr01 < cr00 ffffh 2. the cycle of the pulse generated through ppg output (cr00 setting value + 1) has a duty of (cr01 setting value + 1)/(cr00 setting value + 1). remark : don t care
117 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um 6.4.3 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00/to0/p70 pin and ti01/p71 pin using the 16-bit timer counter 0 (tm0). there are two measurement methods: measuring with tm0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the ti00/to0/p70 pin. (1) pulse width measurement with free-running counter and one capture register when the 16-bit timer counter 0 (tm0) is operated in free-running mode (see register settings in figure 6-11 ), and the edge specified by prescaler mode register 0 (prm0) is input to the ti00/to0/p70 pin, the value of tm0 is taken into 16-bit timer capture/compare register 01 (cr01) and an external interrupt request signal (inttm01) is set. any of three edge can be selected rising, falling, or both edges specified by means of bits 4 and 5 (es00 and es01) of prm0. for valid edge detection, sampling is performed at the count clock selected by prm0, and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 6-11. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 0/1 crc00 0 crc0 cr00 as compare register cr01 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see figures 6-2 and 6-3 .
118 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um figure 6-12. configuration diagram for pulse width measurement by free-running counter f x f x /2 2 f x /2 6 ti00/to0/p70 16-bit timer counter 0 (tm0) ovf0 16-bit timer capture/compare register 01 (cr01) internal bus inttm01 selector figure 6-13. timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 count clock tm0 count value ti00 pin input cr01 capture value inttm01 ovf0 (d1 d0) t (d3 d2) t (10000h d1 + d2) t d1 d2 d3 d2 d3 d0 + 1 d1 d1 + 1
119 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um (2) measurement of two pulse widths with free-running counter when the 16-bit timer counter 0 (tm0) is operated in free-running mode (see register settings in figure 6-14 ), it is possible to simultaneously measure the pulse widths of the two signals input to the ti00/to0/p70 pin and the ti01/p71 pin. when the edge specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0) is input to the ti00/to0/p70 pin, the value of tm0 is taken into 16-bit timer capture/compare register 01 (cr01) and an interrupt request signal (inttm01) is set. also, when the edge specified by bits 6 and 7 (es10 and es11) of prm0 is input to the ti01/p71 pin, the value of tm0 is taken into 16-bit timer capture/compare register 00 (cr00) and an interrupt request signal (inttm00) is set. any of three edge can be selected rising, falling, or both edges as the valid edges for the ti00/to0/p70 pin and the ti01/p71 pin specified by means of bits 4 and 5 (es00 and es01) and bits 6 and 7 (es10 and es11) of prm0, respectively. for valid edge detection of ti00/to0/p70 and ti01/p71 pins, sampling is performed at the interval selected by means of the prescaler mode register 0 (prm0), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 6-14. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 0 crc00 1 crc0 cr00 as capture register captures valid edge of ti01/p71 pin to cr00 cr01 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. for details, see figure 6-2 .
120 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um capture operation (free-running mode) capture register operation in capture trigger input is shown. figure 6-15. cr01 capture operation with rising edge specified figure 6-16. timing of pulse width measurement operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 ti01 pin input cr00 capture value inttm01 inttm00 ovf0 (d1 d0) t (d3 d2) t (10000h d1 + d2) t (10000h d1 + (d2 + 1)) t d1 d2 + 1 d1 d2 d2 d3 d0 + 1 d1 d1 + 1 d2 + 1 d2 + 2 count clock tm0 count value ti00 pin input cr01 capture value count clock tm0 ti00 rising edge detection cr01 inttm01 n 3n 2n 1 n n+1 n
121 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um (3) pulse width measurement with free-running counter and two capture registers when the 16-bit timer counter 0 (tm0) is operated in free-running mode (see register settings in figure 6-17 ), it is possible to measure the pulse width of the signal input to the ti00//to0/p70 pin. when the edge specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0) is input to the ti00/to0/p70 pin, the value of tm0 is taken into 16-bit timer capture/compare register 01 (cr01) and an interrupt request signal (inttm01) is set. also, on the inverse edge input of that of the capture operation into cr01, the value of tm0 is taken into 16- bit timer capture/compare register 00 (cr00). either of two edge can be selected rising or falling as the valid edges for the ti00/to0/p70 pin specified by means of bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). for ti00/to0/p70 pin valid edge detection, sampling is performed at the interval selected by means of the prescaler mode register 0 (prm0), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00/to0/p70 pin is specified to be both rising and falling edges, the 16- bit timer capture/compare register 00 (cr00) cannot perform the capture operation. figure 6-17. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 as capture register captures to cr00 at edge reverse to valid edge of ti00/to0/p70. cr01 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details.
122 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um figure 6-18. timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) (4) pulse width measurement by means of restart when input of a valid edge to the ti00/to0/p70 pin is detected, the count value of the 16-bit timer counter 0 (tm0) is taken into 16-bit timer capture/compare register 01 (cr01), and then the pulse width of the signal input to the ti00/to0/p70 pin is measured by clearing tm0 and restarting the count (see register settings in figure 6-19 ). the edge specification can be selected from two types, rising and falling edges by bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0). in a valid edge detection, the sampling is performed by a cycle selected by the prescaler mode register 0 (prm0) and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00/to0/p70 pin is specified to be both rising and falling edges, the 16- bit timer capture/compare register 00 (cr00) cannot perform the capture operation. t 0000h 0000h ffffh 0001h d0 d0 inttm01 ovf0 d2 d1 d3 d2 d3 d0 + 1 d2 + 1 d1 d1 + 1 cr00 capture value count clock tm0 count value ti00 pin input cr01 capture value (d1 d0) t (d3 d2) t (10000h d1 + d2) t
123 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um figure 6-19. control register settings for pulse width measurement by means of restart (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 1 tmc02 0 tmc01 0/1 ovf0 0 tmc0 clears and starts at valid edge of ti00/to0/p70 pin. (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 as capture register captures to cr00 at edge reverse to valid edge of ti00/to0/p70. cr01 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see figure 6-2 . figure 6-20. timing of pulse width measurement operation by means of restart (with rising edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 inttm01 d1 t d2 t d2 d1 d2 d1 cr00 capture value count clock tm0 count value ti00 pin input cr01 capture value
124 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um 6.4.4 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti00/to0/p70 pin with the 16-bit timer counter 0 (tm0). tm0 is incremented each time the valid edge specified with the prescaler mode register 0 (prm0) is input. when the tm0 counted value matches the 16-bit timer capture/compare register 00 (cr00) value, tm0 is cleared to 0 and the interrupt request signal (inttm00) is generated. input the value except 0000h to cr00 (count operation with a pulse cannot be carried out). the rising edge, the falling edge, or both edges can be selected with bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). because operation is carried out only after the valid edge is detected twice by sampling with the internal clock (f x / 2 3 ), noise with short pulse widths can be eliminated. caution when used as an external event counter, the p70/ti00/to0 pin cannot be used as timer output (to0). figure 6-21. control register settings in external event counter mode (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on match between tm0 and cr00 (b) capture/compare control register 0 (crc0) 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see figures 6-2 and 6-3 .
125 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um figure 6-22. external event counter configuration diagram 16-bit timer capture/compare register 00 (cr00) internal bus match clear ovf0 inttm00 f x /2 2 f x /2 6 f x noise eliminator f x /2 3 valid edge of ti00 16-bit timer counter 0 (tm0) 16-bit timer capture/compare register 01 (cr01) selector noise eliminator figure 6-23. external event counter operation timings (with rising edge specified) ti00 pin input tm0 count value cr00 inttm00 0000h 0001h 0002h 0003h 0004h 0005h n 1n 0000h 0001h 0002h 0003h n caution when reading the external event counter count value, tm0 should be read. 6.4.5 square-wave output operation a square wave with any selected frequency to be output at intervals of the count value preset to the 16-bit timer capture/compare register 00 (cr00) operates. the to0 pin output status is reversed at intervals of the count value preset to cr00 by setting bit 0 (toe0) and bit 1 (toc01) of the 16-bit timer output control register 0 (toc0) to 1. this enables a square wave with any selected frequency to be output.
126 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um figure 6-24. control register settings in square-wave output mode (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on match between tm0 and cr00 (b) capture/compare control register 0 (crc0) 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register (c) 16-bit timer output control register 0 (toc0) 000 toc04 0 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output reverses output on match between tm0 and cr00 specifies initial value of to0 output f/f does not reverse output on match between tm0 and cr01 remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see figures 6-2 , 6-3 , and 6-4 .
127 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um figure 6-25. square-wave output operation timing count clock tm0 count value cr00 inttm00 to0 pin output 0000h 0001h 0002h n 1n 0000h 0001h 0002h n 1n 0000h n
128 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um 6.5 cautions for 16-bit timer/event counter 0 (1) timer start errors an error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. this is because the 16-bit timer counter 0 (tm0) is started asynchronously with the count clock. figure 6-26. 16-bit timer counter 0 (tm0) start timing tm0 count value 0000h 0001h 0002h 0004h count clock timer start 0003h (2) 16-bit timer compare register setting (in clear & start mode on match between tm0 and cr00) set other than 0000h to 16-bit timer capture/compare registers 00, 01 (cr00, cr01). this means 1-pulse count operation cannot be performed when it is used as the event counter. (3) operation after compare register change during timer count operation if the value after the 16-bit timer capture/compare register 00 (cr00) is changed is smaller than that of 16-bit timer counter 0 (tm0), tm0 continues counting, overflows and then restarts counting from 0. thus, if the value (m) after cr00 is changed is smaller than the value (n) before it was changed, it is necessary to reset and restart the timer after changing cr00. figure 6-27. timings after change of compare register during timer count operation cr00 nm count clock tm0 count value x 1 x ffffh 0000h 0001h 0002h remark n > x > m
129 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um (4) capture register data retention timings if the valid edge of the ti00/to0/p70 pin is input during 16-bit timer capture/compare register 01 (cr01) read, cr01 carries out capture operation but the capture value at this time is not guaranteed. however, the interrupt request flag (tmif01) is set upon detection of the valid edge. figure 6-28. capture register data retention timing count clock tm0 count value edge input interrupt request flag capture read signal cr01 interrupt value n n + 1 n + 2 m m + 1 m + 2 x n + 1 captured but not guaranteed capture operation (5) valid edge setting set the valid edge of the ti00/to0/p70 pin after setting bits 2 and 3 (tmc02 and tmc03) of the 16-bit timer mode control register 0 (tmc0) to 0, 0, respectively, and then stopping timer operation. valid edge is set with bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0).
130 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um (6) operation of ovf0 flag <1> ofv0 flag is set to 1 in the following case. either the clear & start mode on match between tm0 and cr00 or the free-running mode that clears and starts at the valid edge of tin is selected. cr00 is set to ffffh. when tm0 is counted up from ffffh to 0000h. figure 6-29. operation timing of ovf0 flag count clock cr00 tm0 ovf0 inttm00 ffffh fffeh ffffh 0000h 0001h <2> even if the ovf0 flag is cleared before the next count clock (before tm0 becomes 0001h) after the occurrence of tm0 overflow, the ovf0 flag is reset newly and clear is disabled. (7) contending operations <1> the contending operation between the read time of 16-bit timer capture/compare register (cr00/cr01) and capture trigger input (cr00/cr01 used as capture register) capture trigger input is prior to the other. the data read from cr00/cr01 is not defined. <2> the match timing of contending operation between the write period of 16-bit timer capture/compare register (cr00/cr01) and 16-bit timer counter 0 (tm0) (cr00/cr01 used as a compare register) the match discrimination is not performed normally. do not write any data to cr00/cr01 near the match timing. (8) timer operation <1> even if the 16-bit timer counter 0 (tm0) is read, the value is not captured by 16-bit timer capture/compare register 01 (cr01). <2> regardless of the cpu s operation mode, when the timer stops, the input signals to pins ti00/ti01 are not acknowledged.
131 chapter 6 16-bit timer/event counter 0 preliminary user s manual u16035ej1v0um (9) capture operation <1> if ti00 is specified as the valid edge of the count clock, capture operation by the capture register specified as the trigger for ti00 is not possible. <2> if both the rising and falling edges are selected as the valid edges of ti00, capture is not performed. <3> to ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0 (prm0). <4> the capture operation is performed at the fall of the count clock. an interrupt request input (inttm0n), however, is generated at the rise of the next count clock. (10) compare operation <1> when the 16-bit timer capture/compare register (cr00/cr01) is overwritten during timer operation, match interrupt may be generated or clear operation may not be performed normally if that value is close to the timer value and larger than the timer value. <2> capture operation may not be performed for cr00/cr01 set in compare mode even if a capture trigger has been input. (11) edge detection <1> if the ti00 pin or the ti01 pin is high level immediately after system reset and rising edge or both the rising and falling edges are specified as the valid edge for the ti00 pin or ti01 pin to enable the 16-bit timer counter 0 (tm0) operation, a rising edge is detected immediately after. be careful when pulling up the ti00 pin or the ti01 pin. however, the rising edge is not detected at restart after the operation has been stopped once. <2> the sampling clock used to eliminate noise differs when a ti00 valid edge is used as count clock and when it is used as a capture trigger. in the former case, the count clock is f x /2 3 , and in the latter case the count clock is selected by prescaler mode register 0 (prm0). when a valid edge is detected twice by sampling, the capture operation is started, therefore noise with short pulse widths can be eliminated.
132 preliminary user s manual u16035ej1v0um chapter 7 8-bit timer/event counters 50 and 51 7.1 functions of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 (tm50, tm51) have the following two modes. mode using 8-bit timer/event counters alone (single mode) mode using the cascade connection (16-bit resolution: cascade connection mode) these two modes are described next. (1) mode using 8-bit timer/event counters alone (single mode) the timer operates as an 8-bit timer/event counter. it has the following functions. interval timer external event counter square wave output pwm output (2) mode using the cascade connection (16-bit resolution: cascade connection mode) the timer operates as a 16-bit timer/event counter by connecting in cascade. it has the following functions. interval timer with 16-bit resolution external event counter with 16-bit resolution square wave output with 16-bit resolution figures 7-1 and 7-2 show 8-bit timer/event counter block diagrams.
133 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um figure 7-1. block diagram of 8-bit timer/event counter 50 figure 7-2. block diagram of 8-bit timer/event counter 51 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/p72 f x /2 4 f x /2 6 f x /2 8 f x /2 10 f x f x /2 2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/ti50/p72 selector 8-bit timer counter 50 (tm50) selector internal bus ti51/to51/p73 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 match mask circuit ovf clear 3 tcl512 tcl511 tcl510 timer clock select register 51 (tcl51) internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r q r inv selector inttm51 to51/ti51/p73 selector selector selector 8-bit timer compare register 51 (cr51) 8-bit timer counter 51 (tm51) s f x /2 11
134 chapter 7 8-bit timer/event counters 50 and 51 preliminary user? manual u16035ej1v0um 7.2 configurations of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 consist of the following hardware. table 7-1. configuration of 8-bit timer/event counters 50 and 51 item configuration timer register 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer output 2 (to5n) control registers timer clock select register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 7 (pm7) note note see figure 4-11 block diagram of p70 to p73. remark n = 0, 1 (1) 8-bit timer counter 5n (tm5n: n = 0, 1) tm5n is an 8-bit read-only register which counts the count pulses. the counter is incremented in synchronization with the rising edge of a count clock. tm50 and tm51 can be connected in cascade and used as a 16-bit timer. when tm50 and tm51 can be connected in cascade and used as a 16-bit timer, they can be read by a 16-bit memory operation instruction. however, since they are connected by an internal 8-bit bus, tm50 and tm51 are read separately in two times. thus, take read during count change into consideration and compare them in two times reading. when count value is read during operation, count clock input is temporary stopped, and then the count value is read. in the following situations, count value is set to 00h. <1> reset input <2> when tce5n is cleared <3> when tm5n and cr5n match in clear & start mode on match between tm5n and cr5n. caution in cascade connection mode, the count value is reset to 00h when the lowest timer tce5n is cleared. remark n = 0, 1 (2) 8-bit timer compare register 5n (cr5n: n = 0, 1) the value set in cr5n is constantly compared with the 8-bit timer counter (tm5n) count value, and an interrupt request (inttm5n) is generated if they match (except pwm mode). it is possible to rewrite the value of cr5n within 00h to ffh during count operation. when tm50 and tm51 can be connected in cascade and used as a 16-bit timer, cr50 and cr51 operate as the 16-bit compare register. it compares count value with register value, and if the values are matched, an interrupt request (inttm50) is generated. inttm51 interrupt request is also generated at this time. thus, when tm50 and tm51 are used as cascade connection, mask inttm51 interrupt request. caution when changing the set value of 8-bit compare register 5n (cr5n) in cascade connection mode, change the value after stopping the timer operation of cascade-connected 8-bit timer counter 5n (tm5n). remark n = 0, 1
135 chapter 7 8-bit timer/event counters 50 and 51 preliminary user? manual u16035ej1v0um 7.3 registers to control 8-bit timer/event counters 50 and 51 the following three types of registers are used to control 8-bit timer/event counters 50 and 51. timer clock select register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 7 (pm7) n = 0, 1 (1) timer clock select register 5n (tcl5n: n = 0, 1) this register sets count clocks of 8-bit timer/event counter 5n and the valid edge of ti50, ti51 input. tcl5n is set by an 8-bit memory manipulation instruction. reset input sets tcl5n to 00h. figure 7-3. format of timer clock select register 50 (tcl50) address: ff71h after reset: 00h r/w symbol 76543210 tcl50 00000 tcl502 tcl501 tcl500 tcl502 tcl501 tcl500 count clock selection 0 0 0 ti50 falling edge 0 0 1 ti50 rising edge 010f x (8.38 mhz) 011f x /2 2 (2.09 mhz) 100f x /2 4 (523 khz) 101f x /2 6 (131 khz) 110f x /2 8 (32.7 khz) 111f x /2 10 (8.18 khz) cautions 1. when rewriting tcl50 to other data, stop the timer operation beforehand. 2. be sure to set bits 3 to 7 to 0. remarks 1. when cascade connection is used, only the settings of tcl502 to tcl00 are valid. 2. f x : main system clock oscillation frequency 3. figures in parentheses are for operation with f x = 8.38 mhz
136 chapter 7 8-bit timer/event counters 50 and 51 preliminary user? manual u16035ej1v0um figure 7-4. format of timer clock select register 51 (tcl51) address: ff79h after reset: 00h r/w symbol 76543210 tcl51 00000 tcl512 tcl511 tcl510 tcl512 tcl511 tcl510 count clock selection 0 0 0 ti51 falling edge 0 0 1 ti51 rising edge 010f x /2 (4.19 mhz) 011f x /2 3 (1.04 mhz) 100f x /2 5 (261 khz) 101f x /2 7 (65.4 khz) 110f x /2 9 (16.3 khz) 111f x /2 11 (4.09 khz) cautions 1. when rewriting tcl51 to other data, stop the timer operation beforehand. 2. be sure to set bits 3 to 7 to 0. remarks 1. when cascade connection is used, the settings of tcl5n0 to tcl5n2 (n = 0, 1) are valid only for the lowermost timer. 2. f x : main system clock oscillation frequency 3. figures in parentheses are for operation with f x = 8.38 mhz (2) 8-bit timer mode control register 5n (tmc5n: n = 0, 1) tmc5n is a register which sets up the following six types. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection <3> single mode/cascade connection mode selection <4> timer output f/f (flip flop) status setting <5> active level selection in timer f/f control or pwm (free-running) mode <6> timer output control tmc5n is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc5n to 00h. figure 7-5 shows the tmc5n format.
137 chapter 7 8-bit timer/event counters 50 and 51 preliminary user? manual u16035ej1v0um figure 7-5. format of 8-bit timer mode control register 5n (tmc5n) address: ff70h (tmc50) ff78h (tmc51) after reset: 00h r/w symbol 76543210 tmc5n tce5n tmc5n6 0 tmc5n4 lvs5n lvr5n tmc5n1 toe5n tce5n tm5n count operation control 0 after clearing to 0, count operation disabled (prescaler disabled) 1 count operation start tmc5n6 tm5n operating mode selection 0 clear and start mode by matching between tm5n and cr5n 1 pwm (free-running) mode tmc5n4 single mode/cascade connection mode selection 0 single mode (use the lowest timer) 1 cascade connection mode (connect to lower timer) lvs5n lvr5n timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited tmc5n1 in other modes (tmc5n6 = 0) in pwm mode (tmc5n6 = 1) timer f/f control active level selection 0 inversion operation disabled active high 1 inversion operation enabled active low toe5n timer output control 0 output disabled (port mode) 1 output enabled
138 chapter 7 8-bit timer/event counters 50 and 51 preliminary user? manual u16035ej1v0um caution before clearing tce5n to 0, set the interrupt mask flag (tmmk5n) to 1. this is because an interrupt may occur after tce5n has been cleared. clear tce5n to 0 using the following procedure. tmmk5n = 1 ; mask set tce5n = 0 ; timer clear tmif5n = 0 ; interrupt request flag clear tmmk5n = 0 ; mask clear tce5n = 1 ; timer start remarks 1. in pwm mode, pwm output will be inactive because of tce5n = 0. 2. if lvs5n and lvr5n are read after data is set, 0 is read. 3. n = 0, 1 . . . . . .
139 chapter 7 8-bit timer/event counters 50 and 51 preliminary user? manual u16035ej1v0um (3) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p72/to50/ti50 and p73/ti51/to51 pins for timer output, set pm72, pm73, and output latches of p72 and p73 to 0. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 to ffh. figure 7-6. format of port mode register 7 (pm7) address: ff27h after reset: ffh r/w symbol 76543210 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pm7n p7n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
140 chapter 7 8-bit timer/event counters 50 and 51 preliminary user? manual u16035ej1v0um 7.4 operations of 8-bit timer/event counters 50 and 51 7.4.1 interval timer (8-bit) operation the 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (cr5n). when the count values of the 8-bit timer counter 5n (tm5n) match the values set to cr5n, counting continues with the tm5n values cleared to 0 and the interrupt request signals (inttm5n) are generated. the count clock of the tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of the timer clock select register 5n (tcl5n). see 7.5 cautions for 8-bit timer/event counters 50 and 51 (2) about the operation when the compare register value is changed during timer count operation. [setting] <1> set the registers. tcl5n: select count clock cr5n: compare value tmc5n: clear and start mode by match of tm5n and cr5n (tmc5n = 0000 0b = don? care) <2> after tce5n = 1 is set, count operation starts. <3> if the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> inttm5n generates repeatedly at the same interval. set tce5n to 0 to stop count operation. remark n = 0, 1
141 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um figure 7-7. interval timer operation timings (1/3) (a) basic operation remarks 1. interval time = (n + 1) t n = 00h to ffh 2. n = 0, 1 t count clock tm5n count value cr5n tce5n inttm5n to5n start count clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt request acknowledged interrupt request acknowledged interval time interval time interval time
142 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um figure 7-7. interval timer operation timings (2/3) (b) when cr5n = 00h t count clock tm5 cr5n tce5n inttm5n to5n interval time 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n to5n 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt request acknowledged interrupt request acknowledged n = 0, 1
143 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um figure 7-7. interval timer operation timings (3/3) (d) operated by cr5n transition (m < n) count clock tm5 cr5n tce5n inttm5n to5n 00h n n m n ffh 00h m 00h m cr5n transition tm5n overflows since m < n h (e) operated by cr5n transition (m > n) count clock tm5 cr5n tce5n inttm5n to5n n 1n n 00h 01h n m 1 m 00h 01h m cr5n transition h n = 0, 1
144 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um 7.4.2 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti5n by the 8-bit timer counter 5n (tm5n). tm5n is incremented each time the valid edge specified with the timer clock select register 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n counted values match the values of 8-bit timer compare register 5n (cr5n), tm5n is cleared to 0 and the interrupt request signal (inttm5n) is generated. whenever the tm5n counted value matches the value of cr5n, inttm5n is generated. remark n = 0, 1 figure 7-8. external event counter operation timing (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00 01 02 03 04 05 n 1 n 00 01 02 03 n n = 00h to ffh n = 0, 1
145 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um 7.4.3 square-wave output (8-bit resolution) operation a square wave with any selected frequency is output at intervals of the value preset to the 8-bit timer compare register 5n (cr5n). to5n pin output status is reversed at intervals of the count value preset to cr5n by setting bit 0 (toe5n) of 8- bit timer mode control register 5n (tmc5n) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). [setting] <1> set each register. set port latch and port mode register to 0 tcl5n: select count clock cr5n: compare value tmc5n: clear and start mode by match of tm5n and cr5n lvs5n lvr5n timer output f/f status setting 1 0 high-level output 0 1 low-level output timer output f/f reverse enable timer output enable toe5n = 1 <2> after tce5n = 1 is set, count operation starts. <3> timer output f/f is reversed by match of tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h. <4> timer output f/f is reversed at the same interval and square wave is output from to5n. remark n = 0, 1 figure 7-9. square-wave output operation timing count clock tmn count value cr5n to5n note count start 00h 01h 02h n 1n 00h 01h 02h n 1n 00h n note to5n output initial value can be set by bits 2 and 3 (lvr5n, lvs5n) of the 8-bit timer mode control register 5n (tmc5n). remark n = 0, 1
146 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um 7.4.4 8-bit pwm output operation 8-bit timer/event counter operates as pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty rate pulse determined by the value set to 8-bit timer compare register 5n (cr5n) is output from to5n. set the active level width of pwm pulse to cr5n, and the active level can be selected with bit 1 of tmc5n (tmc5n1). count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register 5n (tcl5n). enable/disable for pwm output can be selected with bit 0 of tmc5n (toe5n). caution rewrite of cr5n in pwm mode is allowed only once in a cycle. remark n = 0, 1 (1) pwm output basic operation [setting] <1> set port latch (p72, p73) and port mode register 7 (pm72, pm73) to 0. <2> set active level width with 8-bit timer compare register (cr5n). <3> select count clock with timer clock select register 5n (tcl5n). <4> set active level with bit 1 of tmc5n (tmc5n1). <5> count operation starts when bit 7 of tmc5n (tce5n) is set to 1. set tce5n to 0 to stop count operation. [pwm output operation] <1> pwm output (output from to5n) outputs inactive level after count operation starts until overflow is generated. <2> when overflow is generated, the active level set in <1> of setting is output. the active level is output until cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> after the cr5n matches the count value, pwm output outputs the inactive level again until overflow is generated. <4> operations <2> and <3> are repeated until the count operation stops. <5> when the count operation is stopped with tce5n = 0, pwm output comes to inactive level. remark n = 0, 1
147 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um figure 7-10. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h n active level active level inactive level (b) cr5n = 0 (c) cr5n = ffh n = 0, 1 count clock tm5n cr5n tce5n inttm5n to5n l inactive level inactive level 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h 00h n+2 tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h ffh n+2 inactive level active level inactive level active level inactive level
148 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um (2) operated by cr5n transition figure 7-11. timing of operation by cr5n transition (a) cr5n value transits from n to m before overflow of tm5n count clock tm5n cr5n tce5n inttm5n to5n cr5n transition (n m) n n+1 n+2 ffh 00h 01h m m+1 m+2 ffh 00h 01h 02h m m+1 m+2 n 02h m h (b) cr5n value transits from n to m after overflow of tm5n count clock tm5n cr5n tce5n inttm5n to5n n n+1 n+2 ffh 00h 01h n n+1 n+2 ffh 00h 01h 02h n 02h n h 03h m m m+1 m+2 cr5n transition (n m) (c) cr5n value transits from n to m between two clocks (00h and 01h) after overflow of tm5n count clock tm5n cr5n tce5n inttm5n to5n n n+1 n+2 ffh 00h 01h n n+1 n+2 ffh 00h 01h 02h n 02h n h m m m+1 m+2 cr5n transition (n m) n = 0, 1
149 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um 7.4.5 interval timer (16-bit) operation when 1 is set in bit 4 (tmc514) of 8-bit timer mode control register 51 (tmc51), the 16-bit resolution timer/counter mode is entered. the 8-bit timer/event counter operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to the 8-bit timer compare registers (cr50, cr51). [setting] <1> set each register. tcl50: select count clock in tm50. cascade-connected tm51 need not be selected. cr50, cr51: compare value (each value can be set at 00h to ffh) tmc50, tmc51: select the clear & start mode by match of tm50 and cr50 (tm51 and cr51). tm50 tmc50 = 0000 0b : don t care tm51 tmc51 = 0001 0b : don t care <2> when tmc51 is set to tce51 = 1 and then, tmc50 is set to tce50 = 1, count operation starts. <3> when the values of tm50 and cr50 of cascade-connected timer match, inttm50 of tm50 is generated (tm50 and tm51 are cleared to 00h). <4> inttm50 generates repeatedly at the same interval. cautions 1. stop timer operation without fail before setting compare register (cr50, cr51). 2. inttm51 of tm51 is generated when tm51 count value matches cr51, even if cascade connection is used. ensure to mask tm51 to disable interrupt. 3. set tce50 and tce51 in a sequential order of tm51 and tm50. 4. count restart/stop can only be controlled by setting tce50 of tm50 to 1/0. figure 7-12 shows an example of 16-bit resolution cascade connection mode timing.
150 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um figure 7-12. 16-bit resolution cascade connection mode count clock tm50 tm51 cr50 cr51 tce50 tce51 inttm50 to50 operation enable count start interval time 00h 01h n n+1 ffh 00h ffh 00h ffh 00h 01h n 00h 01h a 00h 00h 01h 02h m 1 m 00h b 00h n m interrupt request generation level reverse counter clear operation stop 7.5 cautions for 8-bit timer/event counters 50 and 51 (1) timer start errors an error with the maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. this is because the 8-bit timer counter 5n (tm5n) is started asynchronously with the count pulse. figure 7-13. 8-bit timer counter start timing count pulse tm5n count value 00h 01h 02h 03h 04h timer start n = 0, 1
151 chapter 7 8-bit timer/event counters 50 and 51 preliminary user s manual u16035ej1v0um (2) operation after compare register change during timer count operation if the value after the 8-bit timer compare register 5n (cr5n) is changed is smaller than the value of 8-bit timer counter 5n (tm5n), tm5n continues counting, overflows and then restarts counting from 0. thus, if the value (m) after cr5n is changed is smaller than the value (n) before it was changed, it is necessary to restart the timer after changing cr5n. figure 7-14. timing after change of compare register during timer count operation count pulse cr5n tm5 count value nm x 1 x ffh 00h 01h 02h caution except when the ti5n input is selected, always set tce5n = 0 before setting the stop state. remarks 1. n > x > m 2. n = 0, 1 (3) tm5n (n = 0, 1) reading during timer operation when reading tm5n during operation, select count clock having high/low level waveform longer than two cycles of cpu clock because count clock stops temporary. for example, in the case where cpu clock (f cpu ) is f x , when the selected count clock is f x /4 or below, it can be read. remark n = 0, 1
152 preliminary user s manual u16035ej1v0um chapter 8 watch timer 8.1 functions of watch timer the watch timer has the following functions. watch timer interval timer the watch timer and the interval timer can be used simultaneously. figure 8-1 shows the watch timer block diagram. figure 8-1. block diagram of watch timer f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer operation mode register (wtm) internal bus selector selector
153 chapter 8 watch timer preliminary user s manual u16035ej1v0um (1) watch timer when the main system clock or subsystem clock is used, interrupt requests (intwt) are generated at 2 14 /f w second intervals. remark f w : watch timer clock frequency (f x /2 7 or f xt ) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency (2) interval timer interrupt requests (intwti) are generated at the preset time interval. table 8-1. interval timer interval time interval time when operated at when operated at when operated at f x = 8.38 mhz f x = 4.19 mhz f xt = 32.768 khz 2 11 1/f x 2 4 1/f xt 244 s 489 s 488 s 2 12 1/f x 2 5 1/f xt 489 s 978 s 977 s 2 13 1/f x 2 6 1/f xt 978 s 1.96 ms 1.95 ms 2 14 1/f x 2 7 1/f xt 1.96 ms 3.91 ms 3.91 ms 2 15 1/f x 2 8 1/f xt 3.91 ms 7.82 ms 7.81 ms 2 16 1/f x 2 9 1/f xt 7.82 ms 15.6 ms 15.6 ms remark f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 8.2 configuration of watch timer the watch timer consists of the following hardware. table 8-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer operation mode register (wtm)
154 chapter 8 watch timer preliminary user s manual u16035ej1v0um 8.3 register to control watch timer watch timer operation mode register (wtm) is a register to control watch timer. watch timer operation mode register (wtm) this register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control. wtm is set by an 8-bit memory manipulation instruction. reset input sets wtm to 00h. figure 8-2. format of watch timer operation mode register (wtm) address: ff41h after reset: 00h r/w symbol 76543210 wtm wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm7 watch timer count clock selection 0f x /2 7 (65.4 khz) 1f xt (32.768 khz) wtm6 wtm5 wtm4 prescaler interval time selection 0002 4 /f w 0012 5 /f w 0102 6 /f w 0112 7 /f w 1002 8 /f w 1012 9 /f w other than above setting prohibited wtm1 5-bit counter operation control 0 clear after operation stop 1 start wtm0 watch timer operation enable 0 operation stop (clear both prescaler and timer) 1 operation enable caution do not change the count clock and interval time (by setting bits 4 to 7 (wtm4 to wtm7) of wtm) during watch timer operation. remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. figures in parentheses apply to operation with f x = 8.38 mhz, f xt = 32.768 khz.
155 chapter 8 watch timer preliminary user s manual u16035ej1v0um 8.4 operations of watch timer 8.4.1 watch timer operation the watch timer generates an interrupt request (intwt) at a specific time interval (2 14 /f w seconds) by using the main system clock or subsystem clock. the interrupt request is generated at the following time interval. if main system clock (8.38 mhz) is selected: 0.25 seconds if subsystem clock (32.768 khz) is selected: 0.5 seconds the watch timer generates an interrupt request (intwt) at a specific time interval. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer operation mode register (wtm) are set to 1, the count operation starts. when these bits are set to 0, the 5-bit counter is cleared and the count operation stops. when the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by setting wtm1 to 0. in this case, however, the 9-bit prescaler is not cleared. therefore, an error up to 2 9 1/f w seconds occurs in the first overflow (intwt) after zero-second start. remark f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency (f x /2 7 or f xt ) 8.4.2 interval timer operation the watch timer operates as interval timer which generates interrupt requests (intwti) repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm4 to wtm6) of the watch timer operation mode register (wtm). table 8-3. interval timer interval time wtm6 wtm5 wtm4 interval time when operated at when operated at when operated at f x = 8.38 mhz f x = 4.19 mhz f xt = 32.768 khz 0002 4 1/f w 244 s 489 s 488 s 0012 5 1/f w 489 s 978 s 977 s 0102 6 1/f w 978 s 1.96 ms 1.95 ms 0112 7 1/f w 1.96 ms 3.91 ms 3.91 ms 1002 8 1/f w 3.91 ms 7.82 ms 7.81 ms 1012 9 1/f w 7.82 ms 15.6 ms 15.6 ms other than above setting prohibited remark f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency (f x /2 7 or f xt )
156 chapter 8 watch timer preliminary user? manual u16035ej1v0um figure 8-3. operation timing of watch timer/interval timer caution when operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (wtm) (by setting bits 0 (wtm0) and 1 (wtm1) of wtm to 1), the interval until the first interrupt request (intwt) is generated after the register is set does not exactly match the specification made with bit 3 (wtm3) of wtm. this is because there is a delay of one 9-bit prescaler output cycle until the 5-bit counter starts counting. subsequently, however, the intwt signal is generated at the specified intervals. remark f w : watch timer clock frequency n: the number of times of interval timer operations figures in parentheses are for operation with f w = 32.768 khz 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (0.5 s) interval time (t) t interrupt time of watch timer (0.5 s) n x t n x t
157 preliminary user? manual u16035ej1v0um chapter 9 watchdog timer 9.1 functions of watchdog timer the watchdog timer has the following functions. watchdog timer interval timer oscillation stabilization time selection caution select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (wdtm) (the watchdog timer and the interval timer cannot be used simultaneously). figure 9-1 shows a block diagram of the watchdog timer. figure 9-1. block diagram of watchdog timer f x /2 8 run clock input controller intwdt reset wdt mode signal 3 osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 run wdtm4 internal bus divider divided clock selection circuit output controller division mode selection circuit wdtm3 oscillation stabilization time select register (osts) watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) f x
158 chapter 9 watchdog timer preliminary user s manual u16035ej1v0um (1) watchdog timer mode a program loop is detected. upon detection of the program loop, a non-maskable interrupt request or reset can be generated. table 9-1. watchdog timer program loop detection time program loop detection time 2 12 1/f x (489 s) 2 13 1/f x (978 s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz (2) interval timer mode interrupt requests are generated at the preset time intervals. table 9-2. interval time interval time 2 12 1/f x (489 s) 2 13 1/f x (978 s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz
159 chapter 9 watchdog timer preliminary user s manual u16035ej1v0um 9.2 configuration of watchdog timer the watchdog timer consists of the following hardware. table 9-3. configuration of watchdog timer item configuration control registers watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) oscillation stabilization time select register (osts) 9.3 registers to control watchdog timer the following three types of registers are used to control the watchdog timer. watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) oscillation stabilization time select register (osts)
160 chapter 9 watchdog timer preliminary user s manual u16035ej1v0um (1) watchdog timer clock select register (wdcs) this register sets overflow time of the watchdog timer and the interval timer. wdcs is set by an 8-bit memory manipulation instruction. reset input sets wdcs to 00h. figure 9-2. format of watchdog timer clock select register (wdcs) address: ff42h after reset: 00h r/w symbol 76543210 wdcs 00000 wdcs2 wdcs1 wdcs0 wdcs2 wdcs1 wdcs0 overflow time of watchdog timer/interval timer 0002 12 /f x (489 s) 0012 13 /f x (978 s) 0102 14 /f x (1.96 ms) 0112 15 /f x (3.91 ms) 1002 16 /f x (7.82 ms) 1012 17 /f x (15.6 ms) 1102 18 /f x (31.3 ms) 1112 20 /f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz
161 chapter 9 watchdog timer preliminary user s manual u16035ej1v0um (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 9-3. format of watchdog timer mode register (wdtm) address: fff9h after reset: 00h r/w symbol 76543210 wdtm run 0 0 wdtm4 wdtm3 0 0 0 run watchdog timer operation mode selection note 1 0 count stop 1 counter is cleared and counting starts wdtm4 wdtm3 watchdog timer operation mode selection note 2 0 interval timer mode note 3 (maskable interrupt request occurs upon generation of an overflow) 1 0 watchdog timer mode 1 (non-maskable interrupt request occurs upon generation of an overflow) 1 1 watchdog timer mode 2 (reset operation is activated upon generation of an overflow) notes 1. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. 2. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 3. the watchdog timer starts operations as the interval timer when 1 is set to run. caution when 1 is set to run so that the watchdog timer is cleared, the actual overflow time is up to 2 8 /f x seconds shorter than the time set by watchdog timer clock select register (wdcs). remark : don t care
162 chapter 9 watchdog timer preliminary user s manual u16035ej1v0um (3) oscillation stabilization time select register (osts) a register to select oscillation stabilization time from reset time or stop mode released time to the time when oscillation is stabilized. osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. thus, when releasing the stop mode by reset input, the time required to release is 2 17 /f x . figure 9-4. format of oscillation stabilization time select register (osts) address: fffah after reset: 04h r/w symbol 76543210 osts 00000 osts2 osts1 osts0 osts2 osts1 osts0 selection of oscillation stabilization time 0002 12 /f x (488 s) 0012 14 /f x (1.95 ms) 0102 15 /f x (3.91 ms) 0112 16 /f x (7.81 ms) 1002 17 /f x (15.6 ms) other than the above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz
163 chapter 9 watchdog timer preliminary user s manual u16035ej1v0um 9.4 watchdog timer operations 9.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer is operated to detect any program loops. the program loop detection time interval is selected with bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set program loop time interval. the watchdog timer can be cleared and counting is started by setting run to 1. if run is not set to 1 and the program loop detection time is exceeded, system reset or a non-maskable interrupt request is generated according to wdtm bit 3 (wdtm3) value. the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruction. cautions 1. the actual program loop detection time may be shorter than the set time by a maximum of 2 8 /f x seconds. 2. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. table 9-4. watchdog timer program loop detection time program loop detection time 2 12 1/f x (489 s) 2 13 1/f x (978 s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz.
164 chapter 9 watchdog timer preliminary user s manual u16035ej1v0um 9.4.2 interval timer operation the watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 0. the interval time of interval timer is selected with bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). when 1 is set to bit 7 (run) of wdtm, the watchdog timer operates as the interval timer. when the watchdog timer operated as the interval timer, the interrupt mask flag (wdtmk) and priority specify flag (wdtpr) are validated and the maskable interrupt request (intwdt) can be generated. among maskable interrupts, intwdt has the highest priority at default. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set run to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (this selects the watchdog timer mode), the interval timer mode is not set unless reset input is applied. 2. the interval time just after setting by wdtm may be shorter than the set time by a maximum of 2 8 /f x seconds. 3. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. table 9-5. interval timer interval time interval time 2 12 1/f x (489 s) 2 13 1/f x (978 s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz.
165 preliminary user? manual u16035ej1v0um chapter 10 clock output/buzzer output controller 10.1 functions of clock output/buzzer output controller the clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsis. the clock selected with the clock output select register (cks) is output. in addition, the buzzer output is intended for square wave output of buzzer frequency selected with cks. figure 10-1 shows the block diagram of clock output/buzzer output controller. figure 10-1. block diagram of clock output/buzzer output controller 8 4 bzoe bcs0, bcs1 clock controller cloe buz/p75 pcl/p74 internal bus selector bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 clock output select register (cks) selector prescaler f x /2 10 to f x /2 13 f x to f x /2 7 f xt f x
166 chapter 10 clock output/buzzer output controller preliminary user s manual u16035ej1v0um 10.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller consists of the following hardware. table 10-1. configuration of clock output/buzzer output controller item configuration control registers clock output select register (cks) port mode register (pm7) note note see figure 4-12 block diagram of p74 and p75 . 10.3 registers to control clock output/buzzer output controller the following two types of registers are used to control the clock output/buzzer output controller. clock output select register (cks) port mode register (pm7) (1) clock output select register (cks) this register sets output enable/disable for clock output (pcl) and for the buzzer frequency output (buz), and sets the output clock. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets cks to 00h.
167 chapter 10 clock output/buzzer output controller preliminary user s manual u16035ej1v0um figure 10-2. format of clock output select register (cks) address: ff40h after reset: 00h r/w symbol 76543210 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 stop clock division circuit operation. buz fixed to low level. 1 enable clock division circuit operation. buz output enabled. bcs1 bcs0 buz output clock selection 00f x /2 10 (8.18 khz) 01f x /2 11 (4.09 khz) 10f x /2 12 (2.04 khz) 11f x /2 13 (1.02 khz) cloe pcl output enable/disable specification 0 stop clock division circuit operation. pcl fixed to low level. 1 enable clock division circuit operation. pcl output enabled. ccs3 ccs2 ccs1 ccs0 pcl output clock selection 0000f x (8.38 mhz) 0001f x /2 (4.19 mhz) 0010f x /2 2 (2.09 mhz) 0011f x /2 3 (1.04 mhz) 0100f x /2 4 (524 khz) 0101f x /2 5 (262 khz) 0110f x /2 6 (131 khz) 0111f x /2 7 (65.5 khz) 1000f xt (32.768 khz) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. figures in parentheses are for operation with f x = 8.38 mhz or f xt = 32.768 khz.
168 chapter 10 clock output/buzzer output controller preliminary user s manual u16035ej1v0um (2) port mode register (pm7) this register sets port 7 input/output in 1-bit units. when using the p74/pcl pin for clock output and the p75/buz pin for buzzer output, set pm74, pm75 and the output latch of p74, p75 to 0. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 to ffh. figure 10-3. format of port mode register 7 (pm7) address: ff27h after reset: ffh r/w symbol 76543210 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pm7n p7n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
169 chapter 10 clock output/buzzer output controller preliminary user s manual u16035ej1v0um 10.4 operations of clock output/buzzer output controller 10.4.1 operation as clock output the clock pulse is output as the following procedure. <1> select the clock pulse output frequency with bits 0 to 3 (ccs0 to ccs3) of the clock output select register (cks) (clock pulse output in disabled status). <2> set bit 4 (cloe) of cks to 1 to enable clock output. remark the clock output controller is designed not to output pulses with a small width during output enable/ disable switching of the clock output. as shown in figure 10-4, be sure to start output from the low period of the clock (marked with * in the figure). when stopping output, do so after securing high level of the clock. figure 10-4. remote control output application example cloe clock output ** 10.4.2 operation as buzzer output the buzzer frequency is output as the following procedure. <1> select the buzzer output frequency with bits 5 and 6 (bcs0, bcs1) of the clock output select register (cks) (buzzer output in disabled status). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output.
170 preliminary user? manual u16035ej1v0um chapter 11 8-bit a/d converter ( pd780024as subseries) 11.1 functions of a/d converter a/d converter is an 8-bit resolution converter that converts analog inputs into digital values. it can control up to 4 analog input channels (ani0 to ani3). (1) hardware start conversion is started by trigger input (adtrg: rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting the a/d converter mode register 0 (adm0). select one channel for analog input from ani0 to ani3 to perform a/d conversion. in the case of hardware start, a/d conversion stops when an a/d conversion operation ends and an interrupt request (intad0) is generated. in the case of software start, a/d conversion is repeated. each time an a/d conversion operation ends, an interrupt request (intad0) is generated. caution although the pd78f0034bs incorporate a 10-bit a/d converter, this converter can be operated as an 8-bit a/d converter by using the device file df780024.
171 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user? manual u16035ej1v0um figure 11-1. block diagram of 8-bit a/d converter note the valid edge is specified by bit 3 of the egp and egn registers (see figure 11-4 format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) ). ani0/p10 ani1/p11 ani2/p12 ani3/p13 sample & hold circuit voltage comparator successive approximation register (sar) controller edge detector adtrg/intp3/p03 3 a/d conversion result register 0 (adcr0) av dd av ref av ss intad0 intp3 trigger enable a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) internal bus ads02 ads01 ads00 adsc0 trg0 fr02 fr01 fr00 ega01 ega00 selector tap selector edge detector note series resistor string
172 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um 11.2 configuration of a/d converter the a/d converter consists of the following hardware. table 11-1. configuration of a/d converter item configuration analog input 4 channels (ani0 to ani3) registers successive approximation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is held (end of a/d conversion), the sar contents are transferred to the a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) the adcr0 is an 8-bit register that stores the a/d conversion result. each time a/d conversion ends, the conversion result is loaded from the successive approximation register. adcr0 is read by an 8-bit memory manipulation instruction. reset input sets adcr0 to 00h. caution when writing is performed to the a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0), the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0, ads0. using a timing other than the above may cause an incorrect conversion result to be read. (3) sample & hold circuit the sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is connected between av ref and av ss , and generates a voltage to be compared to the analog input.
173 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user? manual u16035ej1v0um (6) ani0 to ani3 pins these are four analog input pins to input analog signals to undergo a/d conversion to the a/d converter. ani0 to ani3 are alternate-function pins that can also be used for digital input. cautions 1. use ani0 to ani3 input voltages within the specification range. if a voltage higher than av ref or lower than av ss is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. 2. analog input (ani0 to ani3) pins are alternate function pins that can also be used as input port (p10 to p13) pins. when a/d conversion is performed by selecting any one of ani0 to ani3, do not execute any input instruction to port 1 during conversion. it may cause the lower conversion resolution. when a digital pulse is applied to a pin adjacent to the pin in the process of a/d conversion, a/d conversion values may not be obtained as expected due to coupling noise. thus, do not apply any pulse to a pin adjacent to the pin in the process of a/d conversion. (7) av ref pin this pin inputs the a/d converter reference voltage. it converts signals input to ani0 to ani3 into digital signals according to the voltage applied between av ref and av ss . caution a series resistor string of several 10 k ? is connected between the av ref pin and av ss pin. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in series. this may cause a greater reference voltage error. (8) av ss pin this is the ground potential pin of the a/d converter. always keep it at the same potential as the v ss0 or v ss1 pin even when not using the a/d converter. (9) av dd pin this is the a/d converter analog power supply pin. always keep it at the same potential as the v dd0 or v dd1 pin even when not using the a/d converter.
174 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user? manual u16035ej1v0um 11.3 registers to control a/d converter the following 4 types of registers are used to control the a/d converter. a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) (1) a/d converter mode register 0 (adm0) this register sets the conversion time for analog input to be a/d converted, conversion start/stop, and external trigger. adm0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adm0 to 00h.
175 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user? manual u16035ej1v0um figure 11-2. format of a/d converter mode register 0 (adm0) address: ff80h after reset: 00h r/w symbol 76543210 adm0 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 0 adcs0 a/d conversion operation control 0 stop conversion operation. 1 enable conversion operation. trg0 software start/hardware start selection 0 software start 1 hardware start fr02 fr01 fr00 conversion time selection note 1 0 0 0 144/f x (17.1 s) 0 0 1 120/f x (14.3 s) 0 1 0 96/f x (setting prohibited note 2 ) 1 0 0 72/f x (setting prohibited note 2 ) 1 0 1 60/f x (setting prohibited note 2 ) 1 1 0 48/f x (setting prohibited note 2 ) other than above setting prohibited ega01 ega00 external trigger signal, edge specification 0 0 no edge detection 0 1 falling edge detection 1 0 rising edge detection 1 1 both falling and rising edge detection notes 1. set so that the a/d conversion time is 14 s or more. 2. setting prohibited because a/d conversion time is less than 14 s. caution when rewriting fr00 to fr02 to other than the same data, stop a/d conversion operations once prior to performing rewrite. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz.
176 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user? manual u16035ej1v0um (2) analog input channel specification register 0 (ads0) this register specifies the analog voltage input port for a/d conversion. ads0 is set by an 8-bit memory manipulation instruction. reset input sets ads0 to 00h. figure 11-3. format of analog input channel specification register 0 (ads0) address: ff81h after reset: 00h r/w symbol 76543210 ads0 000000 note ads01 ads00 ads01 ads00 analog input channel specification 0 0 ani0 0 1 ani1 1 0 ani2 1 1 ani3 note be sure to set bit 2 to 0. (3) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp3. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets egp and egn to 00h. figure 11-4. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 76543210 egp 0000 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 76543210 egn 0000 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 3) 0 0 interrupt disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges
177 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user? manual u16035ej1v0um 11.4 operations of a/d converter 11.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with the analog input channel specification register 0 (ads0). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> bit 7 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <5> the voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set. if the analog input is smaller than (1/2) av ref , the msb is reset. <6> next, bit 6 of sar is automatically set, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 7, as described below. bit 7 = 1: (3/4) av ref bit 7 = 0: (1/4) av ref the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated as follows. analog input voltage voltage tap: bit 6 = 1 analog input voltage < voltage tap: bit 6 = 0 <7> comparison is continued in this way up to bit 0 of sar. <8> upon completion of the comparison of 8 bits, an effective digital result value remains in sar, and the result value is transferred to and latched in the a/d conversion result register 0 (adcr0). at the same time, the a/d conversion end interrupt request (intad0) can also be generated. caution the first a/d conversion value just after a/d conversion operations start may not fall within the rating.
178 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user? manual u16035ej1v0um figure 11-5. basic operation of 8-bit a/d converter conversion time sampling time sampling a/d conversion undefined 80h c0h or 40h conversion result a/d converter operation sar adcr0 intad0 conversion result a/d conversion operations are performed continuously until bit 7 (adcs0) of the a/d converter mode register 0 (adm0) is reset (0) by software. if a write operation is performed to the adm0 or the analog input channel specification register 0 (ads0) during an a/d conversion operation, the conversion operation is initialized, and if the adcs0 bit is set (1), conversion starts again from the beginning. reset input sets the a/d conversion result register 0 (adcr0) to 0000h.
179 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um 11.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani3) and the a/d conversion result (stored in the a/d conversion result register 0 (adcr0)) is shown by the following expression. adcr0 = int ( v in 256 + 0.5) av ref or (adcr0 0.5) av ref v in < (adcr0 + 0.5) av ref 256 256 where, int( ): function which returns integer part of value in parentheses v in : analog input voltage av ref :av ref pin voltage adcr0: a/d conversion result register 0 (adcr0) value figure 11-6 shows the relationship between the analog input voltage and the a/d conversion result. figure 11-6. relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr0) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av ref
180 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um 11.4.3 a/d converter operation mode select one analog input channel from among ani0 to ani3 by the analog input channel specification register 0 (ads0) to start a/d conversion. a/d conversion can be started in either of the following two ways. hardware start: conversion is started by trigger input (rising edge, falling edge, or both rising and falling edges specified). software start: conversion is started by specifying the a/d converter mode register 0 (adm0). the a/d conversion result is stored in the a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is simultaneously generated. (1) a/d conversion by hardware start when bit 6 (trg0) and bit 7 (adcs0) of the a/d converter mode register 0 (adm0) are set to 1, the a/d conversion standby state is set. when the external trigger signal (adtrg) is input, a/d conversion of the voltage applied to the analog input pins specified by the analog input channel specification register 0 (ads0) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and ended, the next conversion operation is not started until a new external trigger signal is input. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion and waits for a new external trigger signal to be input. when the external trigger input signal is reinput, a/d conversion is carried out from the beginning. if ads0 is rewritten during a/d conversion waiting, a/d conversion starts when the following external trigger input signal is input. if data with adcs0 set to 0 is written to adm0 during a/d conversion, the a/d conversion operation stops immediately. caution when p03/intp3/adtrg is used as the external trigger input (adtrg), specify the valid edge by bits 1 and 2 (ega00, ega01) of the a/d converter mode register 0 (adm0) and set the interrupt mask flag (pmk3) to 1.
181 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um figure 11-7. a/d conversion by hardware start (when falling edge is specified) a/d conversion adcr0 adtrg intad0 adm0 set adcs0 = 1, trg0 = 1 standby state anin anin anin anim anim anim anin anin anin anim anim standby state standby state ads0 rewrite remarks 1. n = 0, 1, ......, 3 2. m = 0, 1, ......, 3
182 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um (2) a/d conversion by software start when bit 6 (trg0) and bit 7 (adcs0) of the a/d converter mode register 0 (adm0) are set to 0 and 1, respectively, a/d conversion of the voltage applied to the analog input pin specified by the analog input channel specification register 0 (ads0) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and ended, the next conversion operation is immediately started. a/d conversion operations are repeated until new data is written to ads0. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion and a/d conversion of the newly selected analog input channel is started. if data with adcs0 set to 0 is written to adm0 during a/d conversion, the a/d conversion operation stops immediately. figure 11-8. a/d conversion by software start adm0 set adcs0 = 1, trg0 = 0 ads0 rewrite adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion suspended; conversion results are not stored remarks 1. n = 0, 1, ......, 3 2. m = 0, 1, ......, 3
183 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um 11.5 how to read a/d converter characteristics table here we will explain the special terms unique to a/d converters. (1) resolution this is the minimum analog input voltage that can be identified. that is, the percentage of the analog input voltage per 1 bit of digital output is called 1lsb (least significant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). when the resolution is 8 bits, 1lsb = 1/2 8 = 1/256 = 0.4%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero scale offset, full scale offset, integral linearity error, differential linearity error and errors which are combinations of these express overall error. furthermore, quantization error is not included in overall error in the characteristics table. (3) quantization error when analog values are converted to digital values, there naturally occurs a 1/2lsb error. in an a/d converter, an analog input voltage in a range of 1/2lsb are converted to the same digital code, so a quantization error cannot be avoided. furthermore, it is not included in the overall error, zero scale offset, full scale offset, integral linearity error, and differential linearity error in the characteristics table. figure 11-9. overall error figure 11-10. quantization error ideal line 0 0 1 1 digital output overall error analo g input av dd 0 0 0 1 1 digital output quantization error 1/2lsb 1/2lsb analog input av dd 0
184 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um (4) zero scale offset this shows the difference between the actual measured value of the analog input voltage and the theoretical value (1/2lsb) when the digital output changes from 0 000 to 0 001. if the actual measured value is greater than the theoretical value, it shows the difference between the actual measured value of the analog input voltage and the theoretical value (3/2lsb) when the digital output changes from 0 001 to 0 010. (5) full scale offset this shows the difference between the actual measured value of the analog input voltage and the theoretical value (full scale 3/2lsb) when the digital output changes from 1 110 to 1 111. (6) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measured value and the ideal straight line when the zero scale offset and full scale offset are 0. (7) differential linearity error although the ideal output width for a given code is 1lsb, this value shows the difference between the actual measured value and the ideal value of the width when outputting a particular code. figure 11-11. zero scale offset figure 11-12. full scale offset figure 11-13. integral linearity error figure 11-14. differential linearity error 111 011 010 001 zero scale offset ideal line 000 01 2 3 av dd digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av dd av dd 1 av dd 2 av dd 3 digital output (lower 3 bits) analog input (lsb) ideal line full scale offset 0 av dd digital output analog input integral linearity error ideal line 1 1 0 0 0 av dd digital output 1 ...... 1 0 ...... 0 ideal width of 1lsb differential linearity error analog input
185 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um (8) conversion time this expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. sampling time is included in the conversion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. sampling time conversion time
186 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um 11.6 cautions for a/d converter (1) current consumption in standby mode a/d converter stops operating in the standby mode. at this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (adcs0) of the a/d converter mode register 0 (adm0) to 0). figure 11-15 shows how to reduce the current consumption in the standby mode. figure 11-15. example of method of reducing current consumption in standby mode av ref av ss p-ch series resistor string adcs0 (2) input range of ani0 to ani3 the input voltages of ani0 to ani3 should be within the specification range. in particular, if a voltage higher than av ref or lower than av ss is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) contending operations <1> contention between a/d conversion result register 0 (adcr0) write and adcr0 read by instruction upon the end of conversion adcr0 read is given priority. after the read operation, the new conversion result is written to adcr0. <2> contention between adcr0 write and external trigger signal input upon the end of conversion the external trigger signal is not accepted during a/d conversion. therefore, the external trigger signal is not accepted during adcr0 write. <3> contention between adcr0 write and a/d converter mode register 0 (adm0) write or analog input channel specification register 0 (ads0) write upon the end of conversion adm0 or ads0 write is given priority. adcr0 write is not performed, nor is the conversion end interrupt request signal (intad0) generated.
187 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um (4) noise countermeasures to maintain the 8-bit resolution, attention must be paid to noise input to pin av ref and pins ani0 to ani3. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 11-16 to reduce noise. figure 11-16. analog input pin connection reference voltage input c = 100 to 1000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref v dd0 av dd av ss v ss0 ani0 to ani3 (5) ani0 to ani3 the analog input pins (ani0 to ani3) also function as input port pins (p10 to p13). when a/d conversion is performed with any of pins ani0 to ani3 selected, do not execute an input instruction to port 1 while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/ d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (6) av ref pin input impedance a series resistor string of several 10 k ? is connected between the av ref pin and the av ss pin. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in series. this may cause a greater reference voltage error.
188 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um (7) interrupt request flag (adif0) the interrupt request flag (adif0) is not cleared even if the analog input channel specification register 0 (ads0) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads0 rewrite. caution is therefore required since, at this time, when adif0 is read immediately just after the ads0 rewrite, adif0 is set despite the fact that the a/d conversion for the post-change analog input has not ended. when the a/d conversion is restarted after it is stopped, clear adif0 before restart. figure 11-17. a/d conversion end interrupt request generation timing adm0 rewrite (start of anin conversion) a/d conversion adcr0 intad0 anin anin anim anim anin anin anim anim ads0 rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0, 1, ......, 3 2. m = 0, 1, ......, 3 (8) conversion results just after a/d conversion start the first a/d conversion value just after a/d conversion operations start may not fall within the rating. polling a/d conversion end interrupt request (intad0) and take measures such as removing the first conversion results. (9) a/d conversion result register 0 (adcr0) read operation when writing is performed to the a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0), the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0, ads0. using a timing other than the above may cause an incorrect conversion result to be read.
189 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um (10) timing at which a/d conversion result is undefined the a/d conversion value may be undefined if the timing of completion of a/d conversion and the timing of stopping the a/d conversion conflict with each other. therefore, read the a/d conversion result during the a/ d conversion operation. to read the conversion result after stopping the a/d conversion operation, be sure to stop the a/d conversion before the next conversion ends. figures 11-18 and 11-19 show the timing of reading the conversion result. figure 11-18. timing of reading conversion result (when conversion result is undefined) figure 11-19. timing of reading conversion result (when conversion result is normal) (11) notes on board design locate analog circuits as far away from digital circuits as possible on the board because the analog circuits may be affected by the noise of the digital circuits. in particular, do not cross an analog signal line with a digital signal line, or wire an analog signal line in the vicinity of a digital signal line. otherwise, the a/d conversion characteristics may be affected by the noise of the digital line. connect av ss0 and v ss0 at one location on the board where the voltages are stable. normal conversion result undefined value a/d conversion completes a/d conversion completes normal conversion result is read. a/d conversion is stopped. undefined value is read. adcr0 intad0 adcs0 normal conversion result a/d conversion completes normal conversion result is read. a/d conversion is stopped. adcr0 intad0 adcs0
190 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um (12) av dd pin the av dd pin is the analog circuit power supply pin. it supplies power to the input circuits of the ani0 to ani3 pins. therefore, be sure to apply the same potential as v dd0 to this pin even for applications designed to switch to a backup battery for power supply. figure 11-20. av dd pin connection main power supply capacitor for backup av ref v dd0 av ss av dd v ss0 (13) av ref pin connect a capacitor to the av ref pin to minimize conversion errors due to noise. if an a/d conversion operation has been stopped and then is started, the voltage applied to the av ref pin becomes unstable, causing the accuracy of the a/d conversion to drop. to prevent this, also connect a capacitor to the av ref pin. figure 11-21 shows an example of connecting a capacitor. figure 11-21. example of connecting capacitor to av ref pin av ref av ss c 2 c 1 remark c1: 4.7 f to 10 f (reference value) c2: 0.01 f to 0.1 f (reference value) connect c2 as close to the pin as possible.
191 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um (14) internal equivalent circuit of ani0 to ani3 pins and permissible signal source impedance to complete sampling within the sampling time with sufficient a/d conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low. figure 11-22 shows the internal equivalent circuit of the ani0 to ani3 pins. if the impedance of the signal source is high, connect capacitors with a high capacitance to the pins ani0 to ani3. an example of this is shown in figure 11-23. in this case, however, the microcontroller cannot follow an analog signal with a high differential coefficient because a lowpass filter is created. to convert a high-speed analog signal or to convert an analog signal in the scan mode, insert a low-impedance buffer. figure 11-22. internal equivalent circuit of pins ani0 to ani3 c3 c2 r2 r1 c1 anin remark n = 0 to 3 table 11-2. resistance and capacitance of equivalent circuit (reference values) av ref r1 r2 c1 c2 c3 1.8 v 75 k ? 30 k ? 8 pf 4 pf 2 pf 2.7 v 12 k ? 8 k ? 8 pf 3 pf 2 pf 4.5 v 4 k ? 2.7 k ? 8 pf 1.4 pf 2 pf caution the resistance and capacitance in table 11-2 are not guaranteed values.
192 chapter 11 8-bit a/d converter ( pd780024as subseries) preliminary user s manual u16035ej1v0um figure 11-23. example of connection if signal source impedance is high c3 c2 r2 r1 r0 c0 0.1 f anin c1 c0 lowpass filter is created. output impedance of sensor remark n = 0 to 3
193 preliminary user? manual u16035ej1v0um chapter 12 10-bit a/d converter ( pd780034as subseries) 12.1 functions of a/d converter a/d converter is a 10-bit resolution converter that converts analog inputs into digital signals. it can control up to 4 analog input channels (ani0 to ani3). (1) hardware start conversion is started by trigger input (adtrg: rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting the a/d converter mode register 0 (adm0). select one channel for analog input from ani0 to ani3 to start a/d conversion. in the case of hardware start, the a/d converter stops when a/d conversion is completed, and an interrupt request (intad0) is generated. in the case of software start, a/d conversion is repeated. each time as a/d conversion operation ends, an interrupt request (intad0) is generated. figure 12-1. block diagram of 10-bit a/d converter note the valid edge is specified by bit 3 of the egp and egn registers (see figure 12-4 format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) ). sample & hold circuit series resistor string voltage comparator controller edge detector adtrg/intp3/p03 3 a/d conversion result register 0 (adcr0) av dd av ref av ss intad0 intp3 trigger enable a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) internal bus ads02 ads01 ads00 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 selector tap selector edge detector note successive approximation register (sar) ani0/p10 ani1/p11 ani2/p12 ani3/p13 selector
194 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um 12.2 configuration of a/d converter a/d converter consists of the following hardware. table 12-1. configuration of a/d converter item configuration analog input 4 channels (ani0 to ani3) registers successive approximation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is hold (end of a/d conversion), the sar contents are transferred to the a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) the adcr0 is a 16-bit register that stores the a/d conversion results. lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion result is loaded from the successive approximation register. adcr0 is read by a 16-bit memory manipulation instruction. reset input sets adcr0 to 00h. caution when writing is performed to the a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0), the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0, ads0. using a timing other than the above may cause an incorrect conversion result to be read. (3) sample & hold circuit the sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is connected between av ref and av ss , and generates a voltage to be compared to the analog input.
195 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um (6) ani0 to ani3 pins these are four analog input pins to input analog signals to undergo a/d conversion to the a/d converter. ani0 to ani3 are alternate-function pins that can also be used for digital input. cautions 1. use ani0 to ani3 input voltages within the specification range. if a voltage higher than av ref or lower than av ss is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. 2. analog input (ani0 to ani3) pins are alternate function pins that can also be used as input port (p10 to p13) pins. when a/d conversion is performed by selecting any one of ani0 to ani3, do not execute any input instruction to port 1 during conversion. it may cause the lower conversion resolution. when a digital pulse is applied to a pin adjacent to the pin in the process of a/d conversion, a/d conversion values may not be obtained as expected due to coupling noise. thus, do not apply any pulse to a pin adjacent to the pin in the process of a/d conversion. (7) av ref pin this pin inputs the a/d converter reference voltage. it converts signals input to ani0 to ani3 into digital signals according to the voltage applied between av ref and av ss . caution a series resistor string of several 10 k ? is connected between the av ref and av ss pins. therefore, when output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in series. this may cause a greater reference voltage error. (8) av ss pin this is the ground potential pin of the a/d converter. always keep it at the same potential as the v ss0 or v ss1 pin when not using the a/d converter. (9) av dd pin this is the a/d converter analog power supply pin. always keep it at the same potential as the v dd0 or v dd1 pin even when not using the a/d converter. 12.3 registers to control a/d converter the following 4 types of registers are used to control the a/d converter. a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) (1) a/d converter mode register 0 (adm0) this register sets the conversion time for analog input to be a/d converted, conversion start/stop, and external trigger. adm0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adm0 to 00h.
196 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um figure 12-2. format of a/d converter mode register 0 (adm0) address: ff80h after reset: 00h r/w symbol 76543210 adm0 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 0 adcs0 a/d conversion operation control 0 stop conversion operation. 1 enable conversion operation. trg0 software start/hardware start selection 0 software start 1 hardware start fr02 fr01 fr00 conversion time selection note 1 0 0 0 144/f x (17.1 s) 0 0 1 120/f x (14.3 s) 0 1 0 96/f x (setting prohibited note 2 ) 1 0 0 72/f x (setting prohibited note 2 ) 1 0 1 60/f x (setting prohibited note 2 ) 1 1 0 48/f x (setting prohibited note 2 ) other than above setting prohibited ega01 ega00 external trigger signal, edge specification 0 0 no edge detection 0 1 falling edge detection 1 0 rising edge detection 1 1 both falling and rising edge detection notes 1. set so that the a/d conversion time is 14 s or more. 2. setting prohibited because a/d conversion time is less than 14 s. caution when rewriting fr00 to fr02 to other than the same data, stop a/d conversion operations once prior to performing rewrite. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz.
197 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um (2) analog input channel specification register 0 (ads0) this register specifies the analog voltage input port for a/d conversion. ads0 is set by an 8-bit memory manipulation instruction. reset input sets ads0 to 00h. figure 12-3. format of analog input channel specification register 0 (ads0) address: ff81h after reset: 00h r/w symbol 76543210 ads0 000000 note ads01 ads00 ads01 ads00 analog input channel specification 0 0 ani0 0 1 ani1 1 0 ani2 1 1 ani3 note be sure to set bit 2 to 0. (3) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp3. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets egp and egn to 00h. figure 12-4. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 76543210 egp 0000 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 76543210 egn 0000 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 3) 0 0 interrupt disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges
198 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um 12.4 operations of a/d converter 12.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with the analog input channel specification register 0 (ads0). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <5> the voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set. if the analog input is smaller than (1/2) av ref , the msb is reset. <6> next, bit 8 of sar is automatically set, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. bit 9 = 1: (3/4) av ref bit 9 = 0: (1/4) av ref the voltage tap and analog input voltage are compared and bit 8 of sar is manipulated as follows. analog input voltage voltage tap: bit 8 = 1 analog input voltage < voltage tap: bit 8 = 0 <7> comparison is continued in this way up to bit 0 of sar. <8> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to and latched in the a/d conversion result register 0 (adcr0). at the same time, the a/d conversion end interrupt request (intad0) can also be generated. caution the first a/d conversion value just after a/d conversion operations start may not fall within the rating.
199 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um figure 12-5. basic operation of 10-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr0 intad0 conversion result a/d conversion operations are performed continuously until bit 7 (adcs0) of the a/d converter mode register 0 (adm0) is reset (0) by software. if a write operation is performed to the adm0 or the analog input channel specification register 0 (ads0) during an a/d conversion operation, the conversion operation is initialized, and if the adcs0 bit is set (1), conversion starts again from the beginning. reset input sets the a/d conversion result register 0 (adcr0) to 0000h.
200 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um 12.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (stored in the a/d conversion result register 0 (adcr0)) is shown by the following expression. adcr0 = int ( v in 1024 + 0.5) av ref or (adcr0 0.5) av ref v in < (adcr0 + 0.5) av ref 1024 1024 where, int( ): function which returns integer part of value in parentheses v in : analog input voltage av ref :av ref pin voltage adcr0: a/d conversion result register 0 (adcr0) value figure 12-6 shows the relationship between the analog input voltage and the a/d conversion result. figure 12-6. relationship between analog input voltage and a/d conversion result 1023 1022 1021 3 2 1 0 a/d conversion result (adcr0) 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 input voltage/av ref
201 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um 12.4.3 a/d converter operation mode select one analog input channel from among ani0 to ani3 by the analog input channel specification register 0 (ads0) to start a/d conversion. a/d conversion can be started in either of the following two ways. hardware start: conversion is started by trigger input (rising edge, falling edge, or both rising and falling edges specified). software start: conversion is started by specifying the a/d converter mode register 0 (adm0). the a/d conversion result is stored in the a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is simultaneously generated. (1) a/d conversion by hardware start when bit 6 (trg0) and bit 7 (adcs0) of the a/d converter mode register 0 (adm0) are set to 1, the a/d conversion standby state is set. when the external trigger signal (adtrg) is input, a/d conversion of the voltage applied to the analog input pin specified by the analog input channel specification register 0 (ads0) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and ended, the next conversion operation is not started until a new external trigger signal is input. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion and waits for a new external trigger signal to be input. when the external trigger input signal is reinput, a/d conversion is carried out from the beginning. if ads0 is rewritten during a/d conversion waiting, a/d conversion starts when the following external trigger input signal is input. if data with adcs0 set to 0 is written to adm0 during a/d conversion, the a/d conversion operation stops immediately. caution when p03/intp3/adtrg is used as the external trigger input (adtrg), specify the valid edge by bits 1 and 2 (ega00, ega01) of the a/d converter mode register 0 (adm0) and set the interrupt mask flag (pmk3) to 1. figure 12-7. a/d conversion by hardware start (when falling edge is specified) a/d conversion adcr0 adtrg intad0 adm0 set adcs0 = 1, trg0 = 1 ads0 rewrite standby state anin anin standby state anin standby state anim anim anim anin anin anin anim anim remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7
202 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um (2) a/d conversion by software start when bit 6 (trg0) and bit 7 (adcs0) of the a/d converter mode register 0 (adm0) are set to 0 and 1, respectively, a/d conversion of the voltage applied to the analog input pin specified by the analog input channel specification register 0 (ads0) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and ended, the next conversion operation is immediately started. a/d conversion operations are repeated until new data is written to ads0. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion and a/d conversion of the new selected analog input channel is started. if data with adcs0 set to 0 is written to adm0 during a/d conversion, the a/d conversion operation stops immediately. figure 12-8. a/d conversion by software start adm0 set adcs0 = 1, trg0 = 0 ads0 rewrite adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion suspended; conversion results are not stored remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7
203 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um 12.5 how to read a/d converter characteristics table here we will explain the special terms unique to a/d converters. (1) resolution this is the minimum analog input voltage that can be identified. that is, the percentage of the analog input voltage per 1 bit of digital output is called 1lsb (least significant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). when the resolution is 10 bits, 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero scale offset, full scale offset, integral linearity error, differential linearity error and errors which are combinations of these express overall error. furthermore, quantization error is not included in overall error in the characteristics table. (3) quantization error when analog values are converted to digital values, there naturally occurs a 1/2lsb error. in an a/d converter, an analog input voltage in a range of 1/2lsb are converted to the same digital code, so a quantization error cannot be avoided. furthermore, it is not included in the overall error, zero scale offset, full scale offset, integral linearity error, and differential linearity error in the characteristics table. figure 12-9. overall error figure 12-10. quantization error ideal line 0 0 1 1 digital output overall error analo g input av dd 0 0 0 1 1 digital output quantization error 1/2lsb 1/2lsb analog input av dd 0
204 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um 111 011 010 001 zero scale offset ideal line 000 01 2 3 av dd digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av dd av dd 1 av dd 2 av dd 3 digital output (lower 3 bits) analog input (lsb) ideal line full scale offset 0 av dd digital output analog input integral linearity error ideal line 1 1 0 0 0 av dd digital output 1 ...... 1 0 ...... 0 ideal width of 1lsb differential linearity error analog input (4) zero scale offset this shows the difference between the actual measured value of the analog input voltage and the theoretical value (1/2lsb) when the digital output changes from 0 000 to 0 001. if the actual measured value is greater than the theoretical value, it shows the difference between the actual measured value of the analog input voltage and the theoretical value (3/2lsb) when the digital output changes from 0 001 to 0 010. (5) full scale offset this shows the difference between the actual measured value of the analog input voltage and the theoretical value (full scale 3/2lsb) when the digital output changes from 1 110 to 1 111. (6) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measured value and the ideal straight line when the zero scale offset and full scale offset are 0. (7) differential linearity error although the ideal output width for a given code is 1lsb, this value shows the difference between the actual measured value and the ideal value of the width when outputting a particular code. figure 12-11. zero scale offset figure 12-12. full scale offset figure 12-13. integral linearity error figure 12-14. differential linearity error
205 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um sampling time conversion time (8) conversion time this expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. sampling time is included in the conversion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
206 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um 12.6 cautions for a/d converter (1) current consumption in standby mode a/d converter stops operating in the standby mode. at this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (adcs0) of the a/d converter mode register 0 (adm0) to 0). figure 12-15 shows how to reduce the current consumption in the standby mode. figure 12-15. example of method of reducing current consumption in standby mode av ref av ss p-ch series resistor string adcs0 (2) input range of ani0 to ani3 the input voltages of ani0 to ani3 should be within the specification range. in particular, if a voltage higher than av ref or lower than av ss is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) contending operations <1> contention between a/d conversion result register 0 (adcr0) write and adcr0 read by instruction upon the end of conversion adcr0 read is given priority. after the read operation, the new conversion result is written to adcr0. <2> contention between adcr0 write and external trigger signal input upon the end of conversion the external trigger signal is not accepted during a/d conversion. therefore, the external trigger signal is not accepted during adcr0 write. <3> contention between adcr0 write and a/d converter mode register 0 (adm0) write or analog input channel specification register 0 (ads0) write upon the end of conversion adm0 or ads0 write is given priority. adcr0 write is not performed, nor is the conversion end interrupt request signal (intad0) generated.
207 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um (4) noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to pin av ref and pins ani0 to ani3. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 12-16 to reduce noise. figure 12-16. analog input pin connection reference voltage input c = 100 to 1000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref v dd0 av dd av ss v ss0 ani0 to ani3 (5) ani0 to ani3 the analog input pins (ani0 to ani3) also function as port pins. when a/d conversion is performed with any of pins ani0 to ani3 selected, do not execute an input instruction to port 1 while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (6) av ref pin input impedance a series resistor string of several 10 k ? is connected between the av ref pin and the av ss pin. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in series. this may cause a greater reference voltage error. (7) interrupt request flag (adif0) the interrupt request flag (adif0) is not cleared even if the analog input channel specification register 0 (ads0) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads0 rewrite. caution is therefore required since, at this time, when adif0 is read immediately just after the ads0 rewrite, adif0 is set despite the fact that the a/d conversion for the post-change analog input has not ended. when a/d conversion is restarted after it is stopped, clear adif0 before restart.
208 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um figure 12-17. a/d conversion end interrupt request generation timing adm0 rewrite (start of anin conversion) adif is set but anim conversion has not ended. a/d conversion adcr0 intad0 anin anin anim anim anin anin anim anim ads0 rewrite (start of anim conversion) remarks 1. n = 0, 1, ......, 3 2. m = 0, 1, ......, 3 (8) conversion results just after a/d conversion start the first a/d conversion value just after a/d conversion operations start may not fall within the rating. polling a/d conversion end interrupt request (intad0) and take measures such as removing the first conversion results. (9) a/d conversion result register 0 (adcr0) read operation when writing is performed to the a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0), the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0, ads0. using a timing other than the above may cause an incorrect conversion result to be read.
209 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um normal conversion result undefined value a/d conversion completes a/d conversion completes normal conversion result is read. a/d conversion is stopped. undefined value is read. adcr0 intad0 adcs0 normal conversion result a/d conversion completes normal conversion result is read. a/d conversion is stopped. adcr0 intad0 adcs0 (10) timing at which a/d conversion result is undefined the a/d conversion value may be undefined if the timing of completion of a/d conversion and the timing of stopping the a/d conversion conflict with each other. therefore, read the a/d conversion result during the a/ d conversion operation. to read the conversion result after stopping the a/d conversion operation, be sure to stop the a/d conversion before the next conversion ends. figures 12-18 and 12-19 show the timing of reading the conversion result. figure 12-18. timing of reading conversion result (when conversion result is undefined) figure 12-19. timing of reading conversion result (when conversion result is normal) (11) notes on board design locate analog circuits as far away from digital circuits as possible on the board because the analog circuits may be affected by the noise of the digital circuits. in particular, do not cross an analog signal line with a digital signal line, or wire an analog signal line in the vicinity of a digital signal line. otherwise, the a/d conversion characteristics may be affected by the noise of the digital line. connect av ss0 and v ss0 at one location on the board where the voltages are stable.
210 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um (12) av dd pin the av dd pin is the analog circuit power supply pin. it supplies power to the input circuits of the ani0 to ani3 pins. therefore, be sure to apply the same potential as v dd0 to this pin even for applications designed to switch to a backup battery for power supply. figure 12-20. av dd pin connection main power supply capacitor for backup av ref v dd0 av ss av dd v ss0 (13) av ref pin connect a capacitor to the avref pin to minimize conversion errors due to noise. if an a/d conversion operation has been stopped and then is started, the voltage applied to the av ref pin becomes unstable, causing the accuracy of the a/d conversion to drop. to prevent this, also connect a capacitor to the av ref pin . figure 12-21 shows an example of connecting a capacitor. figure 12-21. example of connecting capacitor to av ref pin av ref av ss c 2 c 1 remark c1: 4.7 f to 10 f (reference value) c2: 0.01 f to 0.1 f (reference value) connect c2 as close to the pin as possible.
211 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um (14) internal equivalent circuit of ani0 to ani3 pins and permissible signal source impedance to complete sampling within the sampling time with sufficient a/d conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low. figure 12-22 shows the internal equivalent circuit of the ani0 to ani3 pins. if the impedance of the signal source is high, connect capacitors with a high capacitance to the pins ani0 to ani3. an example of this is shown in figure 12-23. in this case, however, the microcontroller cannot follow an analog signal with a high differential coefficient because a lowpass filter is created. to convert a high-speed analog signal or to convert an analog signal in the scan mode, insert a low-impedance buffer. figure 12-22. internal equivalent circuit of pins ani0 to ani3 c3 c2 r2 r1 c1 anin rema r k n = 0 to 3 table 12-2. resistance and capacitance of equivalent circuit (reference values) av ref r 1 r 2 c1 c2 c3 1.8 v 75 k ? 30 k ? 8 pf 4 pf 2 pf 2.7 v 12 k ? 8 k ? 8 pf 3 pf 2 pf 4.5 v 4 k ? 2.7 k ? 8 pf 1.4 pf 2 pf caution the resistance and capacitance in table 12-2 are not guaranteed values.
212 chapter 12 10-bit a/d converter ( pd780034as subseries) preliminary user s manual u16035ej1v0um c3 c2 r2 r1 r0 c0 0.1 f anin c1 c0 lowpass filter is created. output impedance of sensor figu r e 12-23. example of connection if signal source impedance is high remar kn = 0 to 3
213 preliminary user s manual u16035ej1v0um chapter 13 serial interface (uart0) 13.1 functions of serial interface the serial interface (uart0) has the following three modes. (1) operation stop mode this mode is used when serial transfers are not performed to reduce power consumption. for details, see 13.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received. the on-chip baud rate generator dedicated to uart enables communications using a wide range of selectable baud rates. in addition, a baud rate can also be defined by dividing clocks input to the asck0 pin. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). for details, see 13.4.2 asynchronous serial interface (uart) mode . (3) infrared data transfer mode for details, see 13.4.3 infrared data transfer mode . figure 13-1 shows a block diagram of the serial interface (uart0).
214 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um figure 13-1. block diagram of serial interface (uart0) note for the configuration of the baud rate generator, refer to figure 13-2 . figure 13-2. block diagram of baud rate generator remark txe0: bit 7 of asynchronous serial interface mode register 0 (asim0) rxe0: bit 6 of asynchronous serial interface mode register 0 (asim0) internal bus receive buffer register 0 (rxb0) rxd0/p23 txd0/p24 pe0 fe0 ove0 asynchronous serial interface status register 0 ( asis0) intser0 intst0 baud rate generator note asck0/p25 f x /2 to f x /2 7 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 asynchronous serial interface mode register 0 ( asim0) intsr0 receive controller (parity check) transmit shift register 0 (txs0) transmit controller (parity addition) receive shift register 0 (rx0) tps0 1 tps02 5-bit counter start bit sampling clock tps00 asck0/p25 f x /2 to f x /2 7 selector internal bus 34 mdl0 3 baud rate generator control register 0 (brgc0) mdl0 2 mdl0 1 mdl00 decoder transmit clock txe0 5-bit counter receive clock rxe0 start bit detection 1/2 match match 1/2
215 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um 13.2 configuration of serial interface the serial interface (uart0) consists of the following hardware. table 13-1. configuration of serial interface (uart0) item configuration registers transmit shift register 0 (txs0) receive shift register 0 (rx0) receive buffer register 0 (rxb0) control registers asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) baud rate generator control register 0 (brgc0) (1) transmit shift register 0 (txs0) this is the register for setting transmit data. data written to txs0 is transmitted as serial data. when the data length is set as 7 bits, bits 0 to 6 of the data written to txs0 are transferred as transmit data. writing data to txs0 starts the transmit operation. txs0 can be written by an 8-bit memory manipulation instruction. it cannot be read. reset input sets txs0 to ffh. caution do not write to txs0 during a transmit operation. the same address is assigned to txs0 and the receive buffer register 0 (rxb0). a read operation reads values from rxb0. (2) receive shift register 0 (rx0) this register converts serial data input via the rxd0 pin to parallel data. when one byte of data is received at this register, the receive data is transferred to the receive buffer register 0 (rxb0). rx0 cannot be manipulated directly by a program. (3) receive buffer register 0 (rxb0) this register is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred from the receive shift register (rx0). when the data length is set as 7 bits, receive data is sent to bits 0 to 6 of rxb0. in this case, the msb of rxb0 always becomes 0. rxb0 can be read by an 8-bit memory manipulation instruction. it cannot be written to. reset input sets rxb0 to ffh. caution the same address is assigned to rxb0 and the transmit shift register 0 (txs0). during a write operation, values are written to txs0. (4) transmit controller the transmit controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to the transmit shift register 0 (txs0), based on the values set to the asynchronous serial interface mode register 0 (asim0).
216 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um (5) receive controller the receive controller controls receive operations based on the values set to the asynchronous serial interface mode register 0 (asim0). during a receive operation, it performs error checking, such as for parity errors, and sets various values to the asynchronous serial interface status register 0 (asis0) according to the type of error that is detected. 13.3 registers to control serial interface the serial interface (uart0) uses the following three types of registers for control functions. asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) baud rate generator control register 0 (brgc0) (1) asynchronous serial interface mode register 0 (asim0) this is an 8-bit register that controls serial interface (uart0) s serial transfer operations. asim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets asim0 to 00h. figure 13-3 shows the format of asim0. caution in uart mode, set the port mode register (pmxx) as follows. set the output latch of the port set to output mode (pmxx = 0) to 0. during receive operation set p23 (rxd0) to input mode (pm23 = 1) during transmit operation set p24 (txd0) to output mode (pm24 = 0) during transmit/receive operation set p23 to input mode, and p24 to output mode
217 chapter 13 serial interface (uart0) preliminary user? manual u16035ej1v0um figure 13-3. format of asynchronous serial interface mode register 0 (asim0) address: ffa0h after reset: 00h r/w symbol 76543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 0 1 uart mode serial function (rxd0) (receive only) 1 0 uart mode port function (p23) serial function (txd0) (transmit only) 1 1 uart mode serial function (rxd0) (transmit and receive) ps01 ps00 parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits sl0 stop bit length specification for transmit data 0 1 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt request is issued when an error occurs 1 receive completion interrupt request is not issued when an error occurs irdam0 operation specified for infrared data transfer mode note 1 0 uart (transmit/receive) mode 1 infrared data transfer (transmit/receive) mode note 2 notes 1. the uart/infrared data transfer mode specification is controlled by txe0 and rxe0. 2. when using infrared data transfer mode, be sure to set the baud rate generator control register 0 (brgc0) to 10h. caution do not switch the operation mode until the current serial transmit/receive operation has stopped.
218 chapter 13 serial interface (uart0) preliminary user? manual u16035ej1v0um (2) asynchronous serial interface status register 0 (asis0) when a receive error occurs during uart mode, this register indicates the type of error. asis0 can be read by an 8-bit memory manipulation instruction. reset input sets asis0 to 00h. figure 13-4. format of asynchronous serial interface status register 0 (asis0) address: ffa1h after reset: 00h r symbol 76543210 asis0 00000pe0fe0 ove0 pe0 parity error flag 0 no parity error 1 parity error (transmit data parity not matched) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register 0 (rxb0)) notes 1. even if a stop bit length is set to 2 bits by setting bit 2 (sl0) in the asynchronous serial interface mode register 0 (asim0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register 0 (rxb0) when an overrun error has occurred. until the contents of rxb0 are read, further overrun errors will occur when receiving data. (3) baud rate generator control register 0 (brgc0) this register sets the serial clock for serial interface. brgc0 is set by an 8-bit memory manipulation instruction. reset input sets brgc0 to 00h. figure 13-5 shows the format of brgc0.
219 chapter 13 serial interface (uart0) preliminary user? manual u16035ej1v0um figure 13-5. format of baud rate generator control register 0 (brgc0) address: ffa2h after reset: 00h r/w symbol 76543210 brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 (f x = 8.38 mhz) tps02 tps01 tps00 source clock selection for 5-bit counter n 0 0 0 p25/asck0 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 mdl03 mdl02 mdl01 mdl00 input clock selection for baud rate generator k 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibited cautions 1. writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc0 during a communication operation. 2. set 10h to brgc0 when using in infrared data transfer mode. remarks 1. f sck : source clock for 5-bit counter 2. n: value set via tps00 to tps02 (0 n 7) 3. k: value set via mdl00 to mdl03 (0 k 14)
220 chapter 13 serial interface (uart0) preliminary user? manual u16035ej1v0um 13.4 operations of serial interface this section explains the three modes of the serial interface (uart0). 13.4.1 operation stop mode because serial transfer is not performed during this mode, the power consumption can be reduced. in addition, pins can be used as normal ports. (1) register settings operation stop mode is set by the asynchronous serial interface mode register 0 (asim0). asim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets asim0 to 00h. address: ffa0h after reset: 00h r/w symbol 76543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 0 1 uart mode serial function (rxd0) (receive only) 1 0 uart mode port function (p23) serial function (txd0) (transmit only) 1 1 uart mode serial function (rxd0) (transmit and receive) caution do not switch the operation mode until the current serial transmit/receive operation has stopped.
221 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um 13.4.2 asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data after the start bit is transmitted or received. the on-chip baud rate generator dedicated to uart enables communications using a wide range of selectable baud rates. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). (1) register settings uart mode settings are performed by the asynchronous serial interface mode register 0 (asim0), asynchronous serial interface status register 0 (asis0), and the baud rate generator control register 0 (brgc0). (a) asynchronous serial interface mode register 0 (asim0) asim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets asim0 to 00h. caution in uart mode, set the port mode register (pmxx) as follows. set the output latch of the port set to output mode (pmxx = 0) to 0. during receive operation set p23 (rxd0) to input mode (pm23 = 1) during transmit operation set p24 (txd0) to output mode (pm24 = 0) during transmit/receive operation set p23 to input mode, and p24 to output mode
222 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um address: ffa0h after reset: 00h r/w symbol 76543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 0 1 uart mode serial function (rxd0) (receive only) 1 0 uart mode port function (p23) serial function (txd0) (transmit only) 1 1 uart mode serial function (rxd0) (transmit and receive) ps01 ps00 parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits sl0 stop bit length specification for transmit data 0 1 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt request is issued when an error occurs 1 receive completion interrupt request is not issued when an error occurs irdam0 operation specified for infrared data transfer mode note 1 0 uart (transmit/receive) mode 1 infrared data transfer (transmit/receive) mode note 2 notes 1. the uart/infrared data transfer mode specification is controlled by txe0 and rxe0. 2. when using infrared data transfer mode, be sure to set the baud rate generator control register 0 (brgc0) to 10h. caution do not switch the operation mode until the current serial transmit/receive operation has stopped.
223 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um (b) asynchronous serial interface status register 0 (asis0) asis0 can be read by an 8-bit memory manipulation instruction. reset input sets asis0 to 00h. address: ffa1h after reset: 00h r symbol 76543210 asis0 00000pe0fe0 ove0 pe0 parity error flag 0 no parity error 1 parity error (transmit data parity not matched) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register 0 (rxb0)) notes 1. even if a stop bit length is set to 2 bits by setting bit 2 (sl0) in the asynchronous serial interface mode register 0 (asim0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register 0 (rxb0) when an overrun error has occurred. until the contents of rxb0 are read, further overrun errors will occur when receiving data.
224 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um (c) baud rate generator control register 0 (brgc0) brgc0 is set by an 8-bit memory manipulation instruction. reset input sets brgc0 to 00h. address: ffa2h after reset: 00h r/w symbol 76543210 brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 (f x = 8.38 mhz) tps02 tps01 tps00 source clock selection for 5-bit counter n 0 0 0 p25/asck0 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 mdl03 mdl02 mdl01 mdl00 input clock selection for baud rate generator k 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibited cautions 1. writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc0 during a communication operation. 2. set 10h to brgc0 when using infrared data transfer mode. remarks 1. f sck : source clock for 5-bit counter 2. n: value set via tps00 to tps02 (0 n 7) 3. k: value set via mdl00 to mdl03 (0 k 14)
225 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um the transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. transmit/receive clock generation for baud rate by using main system clock the main system clock is divided to generate the transmit/receive clock. the baud rate generated from the main system clock is determined according to the following formula. [baud rate] = f x [hz] 2 n+1 (k + 16) f x : main system clock oscillation frequency when asck0 is selected as the source clock of the 5-bit counter, substitute the input clock frequency to asck0 pin for f x in the above expression. n: value set via tps00 to tps02 (0 n 7) for details, see table 13-2 . k: value set via mdl00 to mdl03 (0 k 14) table 13-2 shows the relationship between the 5-bit counter s source clock assigned to bits 4 to 6 (tps00 to tps02) of brgc0 and the n value in the above formula. table 13-3 shows the relationship between the main system clock and the baud rate. table 13-2. relationship between 5-bit counter? source clock and ??value tps02 tps01 tps00 5-bit counter s source clock selected n 0 0 0 p25/asck0 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 remark f x : main system clock oscillation frequency
226 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um table 13-3. relationship between main system clock and baud rate baud rate f x = 8.386 mhz f x = 8.000 mhz f x = 7.3728 mhz f x = 5.000 mhz f x = 4.1943 mhz (bps) brgc0 err (%) brgc0 err (%) brgc0 err (%) brgc0 err (%) brgc0 err (%) 600 7bh 1.14 1200 7bh 1.10 7ah 0.16 78h 0 70h 1.73 6bh 1.14 2400 6bh 1.10 6ah 0.16 68h 0 60h 1.73 5bh 1.14 4800 5bh 1.10 5ah 0.16 58h 0 50h 1.73 4bh 1.14 9600 4bh 1.10 4ah 0.16 48h 0 40h 1.73 3bh 1.14 19200 3bh 1.10 3ah 0.16 38h 0 30h 1.73 2bh 1.14 31250 31h 1.3 30h 0 2dh 1.70 24h 0 21h 1.3 38400 2bh 1.10 2ah 0.16 28h 0 20h 1.73 1bh 1.14 76800 1bh 1.10 1ah 0.16 18h 0 10h 1.73 115200 12h 1.10 11h 2.12 10h 0 infrared 131031 bps 125000 bps 115200 bps 78125 bps 65536 bps data transfer mode note note the uart/infrared data transfer mode specification is controlled by txe0 and rxe0. when using the infrared data transfer mode, be sure to set the baud rate generator control register 0 (brgc0) as follows. k = 0 (mdl0 to mdl3 = 0000) n = 1 (tps00 to tps02 = 001) remark f x : main system clock oscillation frequency n: value set via tps00 to tps02 (0 n 7) k: value set via mdl00 to mdl03 (0 k 14)
227 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um error tolerance range for baud rates the tolerance range for baud rates depends on the number of bits per frame and the counter s division rate [1/(16 + k)]. figure 13-6 shows an example of a baud rate error tolerance range. figure 13-6. baud rate error tolerance (when k = 0), including sampling errors basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t ) enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t ) enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t remark t: 5-bit counter s source clock cycle baud rate error tolerance (when k = 0) = 15.5 100 = 4.8438 (%) 320
228 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um (2) communication operations (a) data format figure 13-7 shows the format of the transmit/receive data. figure 13-7. format of transmit/receive data in asynchronous serial interface d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame character bits 1 data frame consists of the following bits. start bit ............. 1 bit character bits ... 7 bits or 8 bits parity bit ........... even parity, odd parity, zero parity, or no parity stop bit(s) ......... 1 bit or 2 bits the asynchronous serial interface mode register 0 (asim0) is used to set the character bit length, parity selection, and stop bit length within each data frame. when 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to 0 . the asim0 and the baud rate generator control register 0 (brgc0) are used to set the serial transfer rate. if a receive error occurs, information about the receive error can be recognized by reading the asynchronous serial interface status register 0 (asis0).
229 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um (b) parity types and operations the parity bit is used to detect bit errors in communication data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. when zero parity or no parity is set, errors are not detected. (i) even parity during transmission the number of bits in transmit data that includes a parity bit is controlled so that there are an even number of bits whose value is 1. the value of the parity bit is as follows. if the transmit data contains an odd number of bits whose value is 1: the parity bit is 1 if the transmit data contains an even number of bits whose value is 1: the parity bit is 0 during reception the number of bits whose value is 1 is counted among the receive data that include a parity bit, and a parity error occurs when the counted result is an odd number. (ii) odd parity during transmission the number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of bits whose value is 1. the value of the parity bit is as follows. if the transmit data contains an odd number of bits whose value is 1: the parity bit is 0 if the transmit data contains an even number of bits whose value is 1: the parity bit is 1 during reception the number of bits whose value is 1 is counted among the receive data that include a parity bit, and a parity error occurs when the counted result is an even number. (iii) zero parity during transmission, the parity bit is set to 0 regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will occur regardless of whether the parity bit is a 0 or a 1 . (iv) no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will occur.
230 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um (c) transmission the transmit operation is enabled when bit 7 (txe0) of the asynchronous serial interface mode register 0 (asim0) is set (1). the transmit operation is started when transmit data is written to the transmit shift register 0 (txs0). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting the transmit operation shifts out the data in txs0, thereby emptying txs0, after which a transmit completion interrupt request (intst0) is issued. the timing of the transmit completion interrupt request is shown in figure 13-8. figure 13-8. timing of asynchronous serial interface transmit completion interrupt request (i) stop bit length: 1 bit txd0 (output) d0 d1 d2 d6 d7 parity stop start intst0 txd0 (output) d0 d1 d2 d6 d7 parity start intst0 stop caution do not rewrite to the asynchronous serial interface mode register 0 (asim0) during a transmit operation. rewriting asim0 register during a transmit operation may disable further transmit operations (in such cases, input a reset to restore normal operation). whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt request (intst0) or the interrupt request flag (stif0) that is set by intst0. (ii) stop bit length: 2 bits
231 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um (d) reception the receive operation is enabled when bit 6 (rxe0) of the asynchronous serial interface mode register 0 (asim0) is set (1), and input via the rxd0 pin is sampled. the serial clock specified by asim0 is used to sample the rxd0 pin. when the rxd0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. if sampling the rxd0 pin input with this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. after the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once reception of one data frame is completed, the receive data in the shift register is transferred to the receive buffer register 0 (rxb0) and a receive completion interrupt request (intsr0) occurs. even if an error has occurred, the receive data in which the error occurred is still transferred to rxb0. when asim0 bit 1 (isrm0) is cleared (0) upon occurrence of an error, intsr0 occurs (see figure 13-10 ). when isrm0 bit is set (1), intsr0 does not occur. if the rxe0 bit is reset (0) during a receive operation, the receive operation is stopped immediately. at this time, the contents of rxb0 and asis0 do not change, nor does intsr0 or intser0 occur. figure 13-9 shows the timing of the asynchronous serial interface receive completion interrupt request. figure 13-9. timing of asynchronous serial interface receive completion interrupt request rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr0 caution be sure to read the contents of the receive buffer register 0 (rxb0) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read.
232 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um (e) receive errors three types of errors can occur during a receive operation: parity error, framing error, or overrun error. if, as the result of data reception, an error flag is set to the asynchronous serial interface status register 0 (asis0), a receive error interrupt request (intser0) will occur. receive error interrupt requests are generated before receive completion interrupt request (intsr0). table 13-4 lists the causes behind receive errors. as part of receive error interrupt request (intser0) servicing, the contents of asis0 can be read to determine which type of error occurred during the receive operation (see table 13-4 and figure 13-10 ). the contents of asis0 are reset (0) when the receive buffer register 0 (rxb0) is read or when the next data is received (if the next data contains an error, its error flag will be set). table 13-4. causes of receive errors receive error cause asis0 value parity error parity specified during transmission does not match parity of receive data 04h framing error stop bit was not detected 02h overrun error reception of the next data was completed before data was read from the 01h receive buffer register 0 (rxb0) figure 13-10. receive error timing rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr0 note intser0 (when framing/overrun error occurs) intser0 (when parity error occurs) note if a receive error occurs when isrm0 bit has been set (1), intsr0 does not occur. cautions 1. the contents of asynchronous serial interface status register 0 (asis0) are reset (0) when the receive buffer register 0 (rxb0) is read or when the next data is received. to obtain information about the error, be sure to read the contents of asis0 before reading rxb0. 2. be sure to read the contents of the receive buffer register 0 (rxb0) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read.
233 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um 13.4.3 infrared data transfer mode in infrared data transfer mode, the following data format pulse output and pulse receiving are enabled. the relationship between the main system clock and baud rate is shown in table 13-3. (1) data format figure 16-11 compares the data format used in uart mode with that used in infrared data transfer mode. the ir (infrared) frame corresponds to the bit string of the uart frame, which consists of pulses a start bit, eight data bits, and a stop bit. the length of the electrical pulses that are used to transmit and receive in an ir frame is 3/16 the length of the cycle time for one bit (i.e., the bit time ). this pulse (whose width is 3/16 the length of one bit time) rises from the middle of the bit time (see the figure below). 0 start bit 1 d0 0 d1 1 d2 0 d3 0 d4 1 d5 1 d6 0 d7 1 stop bit uart frame data bits start bit 10100110 stop bit ir frame data bits pulse width = 3/16 bit time bit time 0 1 bit time pulse width = 3/16 bit time figure 13-11. data format comparison between infrared data transfer mode and uart mode
234 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um (2) bit rate and pulse width table 13-5 lists bit rates, bit rate error tolerances, and pulse width values. table 13-5. bit rate and pulse width values bit rate bit rate error tolerance pulse width minimum value 3/16 pulse width maximum pulse width (kbits/s) (% of bit rate) ( s) note 2 ( s) ( s) 115.2 note 1 +/ 0.87 1.41 1.63 2.71 notes 1. at the operation time with f x = 7.3728 mhz 2. when a digital noise eliminator is used in a microcontroller operating at 1.41 mhz or above. caution when using in infrared data transfer mode, set 10h to the baud rate generator control register 0 (brgc0). remark f x : main system clock oscillation frequency
235 chapter 13 serial interface (uart0) preliminary user s manual u16035ej1v0um (3) input data and internal signals transmit operation timing uart output data uart (inverted data) infrared data transfer enable signal txd0 pin output signal start bit stop bit receive operation timing data reception is delayed for one-half of the specified baud rate. uart transfer data rxd0 input edge detection sampling clock start bit stop bit receive rate conversion data sampling timing
236 preliminary user? manual u16035ej1v0um chapter 14 serial interface (sio3) the serial interface (sio3) incorporates two 3-wire serial i/o mode channels (sio30, sio31). these two channels have exactly the same functions. 14.1 functions of serial interface the serial interface (sio3n) has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. for details, see 14.4.1 operation stop mode . (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck3n), serial output line (so3n), and serial input line (si3n). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit of the serial transferred 8-bit data is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral i/o incorporating a clocked serial interface, or a display controller, etc. for details see 14.4.2 3-wire serial i/o mode . figure 14-1 shows a block diagram of the serial interface (sio3n). remark n = 0, 1 figure 14-1. block diagram of serial interface (sio3n) note si30, so30, and sck30 pins are shared with p20, p21, and p22 pins. si31, so31, and sck31 pins are shared with p34, p35, and p36 pins. remark n = 0, 1 internal bus 8 serial clock controller serial clock counter interrupt request signal generator selector serial i/o shift register 3n (sio3n) si3n note so3n note sck3n note intcsi3n f x /2 3 f x /2 4 f x /2 5
237 chapter 14 serial interface (sio3) preliminary user s manual u16035ej1v0um 14.2 configuration of serial interface the serial interface (sio3n) consists of the following hardware. table 14-1. configuration of serial interface (sio3n) item configuration register serial i/o shift register 3n (sio3n) control register serial operation mode register 3n (csim3n) remark n = 0, 1 (1) serial i/o shift register 3n (sio3n) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. sio3n is set by an 8-bit memory manipulation instruction. when 1 is set to bit 7 (csie3n) of the serial operation mode register 3n (csim3n), a serial operation can be started by writing data to or reading data from sio3n. when transmitting, data written to sio3n is output to the serial output (so3n). when receiving, data is read from the serial input (si3n) and written to sio3n. reset input makes sio3n undefined. caution do not access sio3n during a transfer operation unless the access is triggered by a transfer start (read operation is disabled when moden = 0 and write operation is disabled when moden = 1). remark n = 0, 1
238 chapter 14 serial interface (sio3) preliminary user? manual u16035ej1v0um 14.3 registers to control serial interface the serial interface (sio3n) is controlled by serial operation mode register 3n (csim3n). (1) serial operation mode register 30 (csim30) this register is used to enable or disable sio30? serial clock, operation modes, and specific operations. csim30 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim30 to 00h. caution in 3-wire serial i/o mode, set the port mode register (pmxx) as follows. set the output latch of the port set to output mode (pmxx = 0) to 0. during serial clock output pm22 = 0: sets p22 (sck30) to output mode (master transmission or master reception) p22 = 0: sets output latch of p22 to 0 during serial clock input pm22 = 1: sets p22 (sck30) to input mode (slave transmission or slave reception) transmit/receive mode pm21 = 0: sets p21 (so30) to output mode p21 = 0: sets output latch of p21 to 0 receive mode pm20 = 1: sets p20 (si30) to input mode
239 chapter 14 serial interface (sio3) preliminary user s manual u16035ej1v0um figure 14-2. format of serial operation mode register 30 (csim30) address: ffb0h after reset: 00h r/w symbol 76543210 csim30 csie30 0000 mode0 scl301 scl300 csie30 enable/disable specification for sio30 shift register operation serial counter port 0 operation disabled clear port function note 1 1 operation enabled count operation enabled serial function + port function note 2 mode0 transfer operation modes and flags operation mode transfer start trigger so30 output 0 transmit/transmit and receive mode write to sio30 normal output 1 receive-only mode read from sio30 fixed at low level scl301 scl300 clock selection 0 0 external clock input to sck30 01f x /2 3 (1.05 mhz) 10f x /2 4 (524 khz) 11f x /2 5 (262 khz) notes 1. when csie30 = 0 (sio30 operation stop status), the pins si30, so30, and sck30 can be used for port functions. 2. when csie30 = 1 (sio30 operation enabled status), the si30 pin can be used as a port pin if only the transmit function is used, and the so30 pin can be used as a port pin if only the receive-only mode is used. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz.
240 chapter 14 serial interface (sio3) preliminary user s manual u16035ej1v0um (2) serial operation mode register 31 (csim31) this register is used to enable or disable sio31 s serial clock, operation modes, and specific operations. csim31 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim31 to 00h. caution in 3-wire serial i/o mode, set the port mode register (pmxx) as follows. set the output latch of the port set to output mode (pmxx = 0) to 0. during serial clock output pm36 = 0: sets p36 (sck31) to output mode (master transmission or master reception) p36 = 0: sets output latch of p36 to 0 during serial clock input pm36 = 1: sets p36 (sck31) to input mode (slave transmission or slave reception) transmit/receive mode pm35 = 0: sets p35 (so31) to output mode p35 = 0: sets output latch of p35 to 0 receive mode pm34 = 1: sets p34 (si31) to input mode
241 chapter 14 serial interface (sio3) preliminary user s manual u16035ej1v0um figure 14-3. format serial operation mode register 31 (csim31) address: ffb8h after reset: 00h r/w symbol 76543210 csim31 csie31 0000 mode1 scl311 scl310 csie31 enable/disable specification for sio31 shift register operation serial counter port 0 operation disabled clear port function note 1 1 operation enabled count operation enabled serial function + port function note 2 mode1 transfer operation modes and flags operation mode transfer start trigger so31 output 0 transmit/transmit and receive mode write to sio31 normal output 1 receive-only mode read from sio31 fixed at low level scl311 scl310 clock selection 0 0 external clock input to sck31 01f x /2 3 (1.05 mhz) 10f x /2 4 (524 khz) 11f x /2 5 (262 khz) notes 1. when csie31 = 0 (sio31 operation stop status), the pins si31, so31, and sck31 can be used for port functions. 2. when csie31 = 1 (sio31 operation enabled status), the si31 pin can be used as a port pin if only the transmit function is used, and the so31 pin can be used as a port pin if only the receive-only mode is used. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz.
242 chapter 14 serial interface (sio3) preliminary user s manual u16035ej1v0um 14.4 operations of serial interface this section explains the two modes of the serial interface (sio3n). 14.4.1 operation stop mode because the serial transfer is not performed during this mode, the power consumption can be reduced. in addition, pins can be used as normal i/o ports. (1) register settings operation stop mode is set by the serial operation mode register 3n (csim3n). csim3n is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim3n to 00h. address: ffb0h (sio30), ffb8h (sio31) after reset: 00h r/w symbol 76543210 csim3n csie3n 0000 moden scl3n1 scl3n0 csie3n enable/disable specification for sio3n shift register operation serial counter port 0 operation disabled clear port function note 1 1 operation enabled count operation enabled serial function + port function note 2 notes 1. when csie3n = 0 (sio3n operation stop status), the pins si3n, so3n, and sck3n can be used for port functions. 2. when csie3n = 1 (sio3n operation enabled status), the si3n pin can be used as a port pin if only the transmit function is used, and the so3n pin can be used as a port pin if only the receive-only mode is used. remark n = 0, 1
243 chapter 14 serial interface (sio3) preliminary user s manual u16035ej1v0um 14.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection to a peripheral i/o incorporating a clocked serial interface, a display controller, etc. this mode executes data transfers via three lines: a serial clock line (sck3n), serial output line (so3n), and serial input line (si3n). (1) register settings 3-wire serial i/o mode is set by the serial operation mode register 3n (csim3n). csim3n is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim3n to 00h . caution in 3-wire serial i/o mode, set the port mode register (pmxx) as follows. set the output latch of the port set to output mode (pmxx = 0) to 0. during serial clock output pm22 = 0: sets p22 (sck30) to output mode (master transmission or master reception) p22 = 0: sets output latch of p22 to 0 during serial clock input pm22 = 1: sets p22 (sck30) to input mode (slave transmission or slave reception) transmit/receive mode pm21 = 0: sets p21 (so30) to output mode p21 = 0: sets output latch of p21 to 0 receive mode pm20 = 1: sets p20 (si30) to input mode during serial clock output pm36 = 0: sets p36 (sck31) to output mode (master transmission or master reception) p36 = 0: sets output latch of p36 to 0 during serial clock input pm36 = 1: sets p36 (sck31) to input mode (slave transmission or slave reception) transmit/receive mode pm35 = 0: sets p35 (so31) to output mode p35 = 0: sets output latch of p35 to 0 receive mode pm34 = 1: sets p34 (si31) to input mode
244 chapter 14 serial interface (sio3) preliminary user s manual u16035ej1v0um address: ffb0h (sio30), ffb8h (sio31) after reset: 00h r/w symbol 76543210 csim3n csie3n 0000 moden scl3n1 scl3n0 csie3n enable/disable specification for sio3n shift register operation serial counter port 0 operation disabled clear port function note 1 1 operation enabled count operation enabled serial function + port function note 2 moden transfer operation modes and flags operation mode transfer start trigger so3n output 0 transmit/transmit and receive mode write to sio3n normal output 1 receive-only mode read from sio3n fixed at low level scl3n1 scl3n0 clock selection 0 0 external clock input to sck3n 01f x /2 3 (1.05 mhz) 10f x /2 4 (524 khz) 11f x /2 5 (262 khz) notes 1. when csie3n = 0 (sio3n operation stop status), the pins si3n, so3n, and sck3n can be used for port functions. 2. when csie3n = 1 (sio3n operation enabled status), the si3n pin can be used as a port pin if only the transmit function is used, and the so3n pin can be used as a port pin if only the receive-only mode is used. remarks 1. n = 0, 1 2. f x : main system clock oscillation frequency 3. figures in parentheses are for operation with f x = 8.38 mhz.
245 chapter 14 serial interface (sio3) preliminary user s manual u16035ej1v0um (2) communication operations in the 3-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is transmitted or received in synchronization with the serial clock. the serial i/o shift register 3n (sio3n) is shifted in synchronization with the falling edge of the serial clock. transmission data is held in the so3n latch and is output from the so3n pin. data that is received via the si3n pin in synchronization with the rising edge of the serial clock is latched to sio3n. completion of an 8-bit transfer automatically stops operation of sio3n and sets interrupt request flag (csiif3n). figure 14-4. timing of 3-wire serial i/o mode remark n = 0, 1 (3) transfer start a serial transfer starts when the following two conditions have been satisfied and transfer data has been set (or read) to serial i/o shift register 3n (sio3n). sio3n operation control bit (csie3n) = 1 after an 8-bit serial transfer, either the internal serial clock is stopped or sck3n is set to high level. transmit/transmit and receive mode when csie3n = 1 and moden = 0, transfer starts when writing to sio3n. receive-only mode when csie3n = 1 and moden = 1, transfer starts when reading from sio3n. caution after data has been written to sio3n, transfer will not start even if the csie3n bit value is set to 1 . completion of an 8-bit transfer automatically stops the serial transfer operation and interrupt request flag (csiif3n) is set. remark n = 0, 1 si3n di7 di6 di5 di4 di3 di2 di1 di0 csiif3n sck3n 1 so3n do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronization with the sck3n falling edge
246 preliminary user s manual u16035ej1v0um chapter 15 interrupt functions 15.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even in an interrupt disabled state. it does not undergo priority control and is given top priority over all other interrupt requests. a standby release signal is generated. one interrupt request from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l). multiple high priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority (see table 15-1 ). a standby release signal is generated. five external interrupt requests and 13 internal interrupt requests are incorporated as maskable interrupts. (3) software interrupt this is a vectored interrupt to be generated by executing the brk instruction. it is acknowledged even in an interrupt disabled state. the software interrupt does not undergo interrupt priority control. 15.2 interrupt sources and configuration a total of 20 interrupt sources exist among non-maskable, maskable, and software interrupts (see table 15-1 ). remark two watchdog timer interrupt sources (intwdt): a non-maskable interrupt and a maskable interrupt (internal), are available, either of which can be selected.
247 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um table 15-1. interrupt source list default interrupt source internal/ vector basic interrupt external table configuration type priority note 1 name trigger address type note 2 non- intwdt watchdog timer overflow internal 0004h (a) maskable (with watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (b) (with interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intser0 serial interface uart0 reception error internal 000eh (b) generation 6 intsr0 end of serial interface uart0 reception 0010h 7 intst0 end of serial interface uart0 transmission 0012h 8 intcsi30 end of serial interface sio3 (sio30) transfer 0014h 9 intcsi31 end of serial interface sio3 (sio31) transfer 0016h 10 intwti reference time interval signal from watch timer 001ah 11 inttm00 match between tm0 and cr00 001ch (when cr00 is specified as compare register) detection of ti01 valid edge (when cr00 is specified as capture register) 12 inttm01 match between tm0 and cr01 001eh (when cr01 is specified as compare register) detection of ti00 valid edge (when cr01 is specified as capture register) 13 inttm50 match between tm50 and cr50 0020h 14 inttm51 match between tm51 and cr51 0022h 15 intad0 end of a/d converter conversion 0024h 16 intwt watch timer overflow 0026h 17 intkr port 4 falling edge detection external 0028h (d) software brk brk instruction execution 003eh (e) notes 1. the default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 17 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 15-1.
248 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um figure 15-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0 to intp3) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector internal bus interrupt request priority controller vector table address generator standby release signal internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal
249 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um figure 15-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (intkr) (e) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag mem: memory expansion mode register if mk ie pr isp internal bus interrupt request priority controller vector table address generator standby release signal falling edge detector 1 when mem = 01h internal bus interrupt request priority controller vector table address generator
250 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um 15.3 registers to control interrupt function the following 7 types of registers are used to control the interrupt functions. interrupt request flag register (if0l, if0h, if1l) interrupt mask flag register (mk0l, mk0h, mk1l) priority specification flag register (pr0l, pr0h, pr1l) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) memory expansion mode register (mem) program status word (psw) table 15-2 gives a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. table 15-2. flags corresponding to interrupt request sources interrupt source interrupt request flag interrupt mask flag priority specification flag register register register intwdt wdtif note if0l wdtmk mk0l wdtpr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intser0 serif0 sermk0 serpr0 intsr0 srif0 srmk0 srpr0 intst0 stif0 stmk0 stpr0 intcsi30 csiif30 if0h csimk30 mk0h csipr30 pr0h intcsi31 csiif31 csimk31 csipr31 intwti wtiif wtimk wtipr inttm00 tmif00 tmmk00 tmpr00 inttm01 tmif01 tmmk01 tmpr01 inttm50 tmif50 tmmk50 tmpr50 inttm51 tmif51 tmmk51 tmpr51 intad0 adif0 if1l admk0 mk1l adpr0 pr1l intwt wtif wtmk wtpr intkr krif krmk krpr note interrupt control flag when watchdog timer is used as interval timer
251 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h, and if1l are set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h are combined to form 16-bit register if0, they are set by a 16-bit memory manipulation instruction. reset input sets these registers to 00h. figure 15-2. format of interrupt request flag register (if0l, if0h, if1l) address: ffe0h after reset: 00h r/w symbol 76543210 if0l stif0 srif0 serif0 pif3 pif2 pif1 pif0 wdtif address: ffe1h after reset: 00h r/w symbol 76543210 if0h tmif51 tmif50 tmif01 tmif00 wtiif 0 csiif31 csiif30 address: ffe2h after reset: 00h r/w symbol 76543210 if1l 00000 krif wtif adif0 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request signal is generated, interrupt request status cautions 1. the wdtif flag is r/w enabled only when the watchdog timer is used as the interval timer. if watchdog timer mode 1 is used, set the wdtif flag to 0. 2. be sure to set bit 2 of if0h and bits 3 to 7 of if1l to 0. 3. when operating a timer, serial interface, or a/d converter after standby release, run it once after clearing an interrupt request flag. an interrupt request flag may be set by noise. 4. when an interrupt is acknowledged, the interrupt request flag is automatically cleared, and then processing of the interrupt routine is started.
252 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt service. mk0l, mk0h, and mk1l are set by a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h are combined to form a 16-bit register mk0, they are set by a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 15-3. format of interrupt mask flag register (mk0l, mk0h, mk1l) address: ffe4h after reset: ffh r/w symbol 76543210 mk0l stmk0 srmk0 sermk0 pmk3 pmk2 pmk1 pmk0 wdtmk address: ffe5h after reset: ffh r/w symbol 76543210 mk0h tmmk51 tmmk50 tmmk01 tmmk00 wtimk 1 csimk31 csimk30 address: ffe6h after reset: ffh r/w symbol 76543210 mk1l 11111 krmk wtmk admk0 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled cautions 1. if the watchdog timer is used in watchdog timer mode 1, the contents of the wdtmk flag become undefined when read. 2. because port 0 pins have an alternate function as external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. be sure to set bit 2 of mk0h and bits 3 to 7 of mk1l to 1.
253 chapter 15 interrupt functions preliminary user? manual u16035ej1v0um (3) priority specification flag registers (pr0l, pr0h, pr1l) the priority specification flags are used to set the corresponding maskable interrupt priority orders. pr0l, pr0h, and pr1l are set by a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h are combined to form 16-bit register pr0, they are set by a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 15-4. format of priority specification flag register (pr0l, pr0h, pr1l) address: ffe8h after reset: ffh r/w symbol 76543210 pr0l stpr0 srpr0 serpr0 ppr3 ppr2 ppr1 ppr0 wdtpr address: ffe9h after reset: ffh r/w symbol 76543210 pr0h tmpr51 tmpr50 tmpr01 tmpr00 wtipr 1 csipr31 csipr30 address: ffeah after reset: ffh r/w symbol 76543210 pr1l 11111 krpr wtpr adpr0 xxprx priority level selection 0 high priority level 1 low priority level cautions 1. when the watchdog timer is used in the watchdog timer mode 1, set 1 in the wdtpr flag. 2. be sure to set bit 2 of pr0h and bits 3 to 7 of pr1l to 1.
254 chapter 15 interrupt functions preliminary user? manual u16035ej1v0um (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp3. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. figure 15-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 76543210 egp 0000 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 76543210 egn 0000 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 3) 0 0 interrupt disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges (5) memory expansion mode register (mem) mem sets the rising edge detection function of port 4. mem is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets mem to 00h. figure 15-6. format of memory expansion mode register (mem) address: ff47h after reset: 00h r/w symbol 76543210 mem 00000mm2mm1mm0 mm2 mm1 mm0 single-chip/memory expansion mode selection 0 0 0 single-chip mode 0 0 1 port 4 falling edge detection mode other than above setting prohibited caution when using the falling edge detection function of port 4, be sure to set mem to 01h.
255 chapter 15 interrupt functions preliminary user? manual u16035ej1v0um (6) program status word (psw) the program status word is a register to hold the instruction execution result and the current status for an interrupt request. the ie flag to set maskable interrupt enable/disable and the isp flag to control nesting processing are mapped. besides 8-bit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, if the brk instruction is executed, the contents of psw are automatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with the push psw instruction. they are reset from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 15-7. format of program status word 7 ie 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disable) ie 0 1 disable priority of interrupt currently being serviced interrupt request acknowledge enable/disable used when normal instruction is executed enable interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enable) 0 1
256 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um 15.4 interrupt servicing operations 15.4.1 non-maskable interrupt request acknowledge operation a non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. it does not undergo interrupt priority control and has highest priority over all other interrupts. if a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag and isp flag are reset (0), and the contents of the vector table are loaded into pc and branched. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction is executed. however, if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt servicing program execution, only one non- maskable interrupt request is acknowledged after termination of the non-maskable interrupt servicing program execution. figures 15-8, 15-9, and 15-10 show the flowchart of the non-maskable interrupt request generation through acknowledge, acknowledge timing of non-maskable interrupt request, and acknowledge operation at multiple non- maskable interrupt request generation, respectively.
257 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um instruction instruction psw and pc save, jump to interrupt servicing interrupt service program cpu processing wdtif interrupt request generated during this interval is acknowledged at . wdtif: watchdog timer interrupt request flag start wdtm4 = 1 (with watchdog timer mode selected)? overflow in wdt? wdt interrupt servicing? interrupt control register not accessed? interval timer no reset processing no interrupt request generation start of interrupt servicing interrupt request held pending no no no yes yes yes yes yes wdtm: watchdog timer mode register wdt: watchdog timer wdtm3 = 0 (with non-maskable interrupt selected)? figure 15-8. non-maskable interrupt request generation to acknowledge flowchart figure 15-9. non-maskable interrupt request acknowledge timing
258 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um figure 15-10. non-maskable interrupt request acknowledge operation (a) if a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution main routine nmi request <1> execution of 1 instruction nmi request <2> execution of nmi request <1> nmi request <2> held pending servicing of nmi request <2> that was pended (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution main routine nmi request <1> execution of 1 instruction execution of nmi request <1> nmi request <2> held pending nmi request <3> held pending servicing of nmi request <2> that was pended nmi request <3> not acknowledged (although two or more nmi requests have been generated, onl y one re q uest is acknowled g ed. ) nmi request <2> nmi request <3>
259 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um 15.4.2 maskable interrupt request acknowledge operation a maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if in the interrupt enable state (when ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request until interrupt servicing is performed are listed in table 15-3 below. for the interrupt request acknowledge timing, see figures 15-12 and 15-13 . table 15-3. times from generation of maskable interrupt until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. if two or more maskable interrupt requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is acknowledged when it becomes acknowledgeable. figure 15-11 shows the interrupt request acknowledge algorithm. if a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into pc and branched. return from an interrupt is possible with the reti instruction.
260 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um figure 15-11. interrupt request acknowledge processing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledge of maskable interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledged, or low-priority interrupt servicing)
261 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um 33 clocks 32 clocks instruction divide instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks 8 clocks 7 clocks instruction instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks figure 15-12. interrupt request acknowledge timing (minimum time) remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 15-13. interrupt request acknowledge timing (maximum time) remark 1 clock: 1/f cpu (f cpu : cpu clock) 15.4.3 software interrupt request acknowledge operation a software interrupt request is acknowledged by brk instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vector table (003eh, 003fh) are loaded into pc and branched. return from a software interrupt is possible with the retb instruction. caution do not use the reti instruction for returning from the software interrupt.
262 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um 15.4.4 nesting interrupt servicing nesting occurs when another interrupt request is acknowledged during execution of an interrupt. nesting does not occur unless the interrupt request acknowledge enable state is selected (ie = 1) (except non- maskable interrupts). also, when an interrupt request is acknowledged, interrupt request acknowledge becomes disabled (ie = 0). therefore, to enable nesting, it is necessary to set (1) the ie flag with the ei instruction during interru pt servicing to enable interrupt acknowledge. moreover, even if interrupts are enabled, nesting may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for nesting. in the interrupt enable state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for nesting. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for nesting. interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority are held pending. when servicing of the current interrupt ends, the pended interrupt request is acknowledged following execution of one main processing instruction execution. nesting is not possible during non-maskable interrupt servicing. table 15-4 shows interrupt requests enabled for nesting and figure 15-14 shows nesting examples. table 15-4. interrupt request enabled for nesting during interrupt servicing nesting request non-maskable interrupt request maskable interrupt request pr = 0 pr = 1 interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt maskable interrupt isp = 0 isp = 1 software interrupt remarks 1. : nesting enabled 2. : nesting disabled 3. isp and ie are flags contained in psw. isp = 0: an interrupt with higher priority is being serviced. isp = 1: no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0: interrupt request acknowledge is disabled. ie = 1: interrupt request acknowledge is enabled. 4. pr is a flag contained in pr0l, pr0h, and pr1l. pr = 0: higher priority level pr = 1: lower priority level
263 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um figure 15-14. nesting examples (1/2) example 1. nesting occurs twice during servicing of interrupt intxx, two interrupt requests, intyy and intzz, are acknowledged, and nesting takes place. before each interrupt request is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledge. example 2. nesting does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and nesting does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledge disabled main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0
264 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um figure 15-14. nesting examples (2/2) example 3. nesting does not occur because interrupt is not enabled interrupt is not enabled during servicing of interrupt intxx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and nesting does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledge disabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0
265 chapter 15 interrupt functions preliminary user s manual u16035ej1v0um 15.4.5 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. these instructions (interrupt request hold instructions) are listed below. mov psw, #byte mov a, psw mov psw, a mov1 psw. bit, cy mov1 cy, psw. bit and1 cy, psw. bit or1 cy, psw. bit xor1 cy, psw. bit set1 psw. bit clr1 psw. bit retb reti push psw pop psw bt psw. bit, $addr16 bf psw. bit, $addr16 btclr psw. bit, $addr16 ei di manipulate instructions for the if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, and pr1l registers caution the brk instruction is not one of the above-listed interrupt request hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared to 0. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. however, a non-maskable interrupt request is acknowledged. figure 15-15 shows the timing with which interrupt requests are held pending. figure 15-15. interrupt request hold remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other than interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request). instruction n instruction m save psw and pc, jump to interrupt servicing interrupt servicing program cpu processing if
266 preliminary user? manual u16035ej1v0um chapter 16 standby function 16.1 standby function and configuration 16.1.1 standby function the standby function is designed to decrease power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. the system clock oscillator continues oscillating. in this mode, current consumption is not decreased as much as in the stop mode. however, the halt mode is effective to restart operation immediately upon interrupt request and to carry out intermittent operations such as watch applications. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscillator stops, stopping the whole system, thereby considerably reducing the cpu power consumption. data memory low-voltage hold (down to v dd = 1.6 v) is possible. thus, the stop mode is effective to hold data memory contents with ultra-low current consumption. because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is required to secure an oscillation stabilization time after the stop mode is cleared, select the halt mode if it is necessary to start processing immediately upon interrupt request. in either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. the i/o port output latch and output buffer statuses are also held. cautions 1. the stop mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). the halt mode can be used with either the main system clock or the subsystem clock. 2. when operation is transferred to the stop mode, be sure to stop the peripheral hardware operation and execute the stop instruction. 3. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (adcs0) of the a/d converter mode register 0 (adm0) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction.
267 chapter 16 standby function preliminary user? manual u16035ej1v0um 16.1.2 standby function control register the wait time after the stop mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register (osts). osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. figure 16-1. format of oscillation stabilization time select register (osts) address: fffah after reset: 04h r/w symbol 76543210 osts 00000 osts2 osts1 osts0 osts2 osts1 osts0 selection of oscillation stabilization time 0002 12 /f x (488 s) 0012 14 /f x (1.95 ms) 0102 15 /f x (3.91 ms) 0112 16 /f x (7.81 ms) 1002 17 /f x (15.6 ms) other than above setting prohibited caution the wait time after the stop mode is cleared does not include the time (see ??in the illustration below) from stop mode clear to clock oscillation start. the time is not included either by reset input or by interrupt request generation. stop mode clear x1 pin voltage waveform v ss a remarks 1. f x : main system clock oscillation frequency 2. values in parentheses are for operation with f x = 8.38 mhz.
268 chapter 16 standby function preliminary user s manual u16035ej1v0um 16.2 operations of standby function 16.2.1 halt mode (1) halt mode setting and operating status the halt mode is set by executing the halt instruction. it can be set with the main system clock or the subsystem clock. the operating status in the halt mode is described below. table 16-1. halt mode operating status halt mode during halt instruction execution during halt instruction execution setting using main system clock using subsystem clock without subsystem with subsystem with main system with main system item clock note 1 clock note 2 clock oscillation clock oscillation stopped clock generator both main system clock and subsystem clock can be oscillated. clock supply to cpu stops. cpu operation stops. port (output latch) status before halt mode setting is held. 16-bit timer/event operable operation stops. counter 8-bit timer/event operable operable when ti50, counter ti51 are selected as count clock. watch timer operable when f x /2 7 is operable operable when f xt is selected as count clock selected as count clock. watchdog timer operable operation stops. a/d converter operation stops. serial interface operable operable during external sck. external interrupt operable notes 1. including case when external clock is not supplied. 2. including case when external clock is supplied.
269 chapter 16 standby function preliminary user s manual u16035ej1v0um (2) halt mode release the halt mode can be released with the following three types of sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledge is enabled, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 16-2. halt mode release by interrupt request generation halt instruction wait wait operation mode halt mode operation mode oscillation clock standby release signal interrupt request remarks 1. the broken line indicates the case when the interrupt request which has released the standby mode is acknowledged. 2. wait times are as follows: when vectored interrupt service is carried out: 8 or 9 clocks when vectored interrupt service is not carried out: 2 or 3 clocks (b) release by non-maskable interrupt request when a non-maskable interrupt request is generated, the halt mode is released and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled.
270 chapter 16 standby function preliminary user? manual u16035ej1v0um (c) release by reset input when reset signal is input, halt mode is released. and, as in the case with normal reset operation, a program is executed after branch to the reset vector address. figure 16-3. halt mode release by reset input halt instruction wait (2 17 /f x : 15.6 ms) oscillation stabilization wait status operating mode halt mode operating mode oscillation stop clock reset signal oscillation oscillation reset period remarks 1. f x : main system clock oscillation frequency 2. values in parentheses are for operation with f x = 8.38 mhz. table 16-2. operation after halt mode release release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0101 next address instruction execution 01 0 0111 interrupt service execution 1 halt mode hold non-maskable interrupt request interrupt service execution reset input reset processing : don t care
271 chapter 16 standby function preliminary user s manual u16035ej1v0um 16.2.2 stop mode (1) stop mode setting and operating status the stop mode is set by executing the stop instruction. it can be set only with the main system clock. cautions 1. when the stop mode is set, the x2 pin is internally connected to v dd1 via a pull-up resistor to minimize the leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait set using the oscillation stabilization time select register (osts), the operating mode is set. the operating status in the stop mode is described below. table 16-3. stop mode operating status stop mode setting with subsystem clock without subsystem clock item clock generator only main system clock oscillation is stopped. cpu operation stops. port (output latch) status before stop mode setting is held. 16-bit timer/event counter operation stops. 8-bit timer/event counter operable only when ti50, ti51 are selected as count clock. watch timer operable when f xt is selected as count operation stops. clock. watchdog timer operation stops. clock output/buzzer output pcl and buz at low level. a/d converter operation stops. serial interface other than uart operable only when externally supplied input clock is specified as the serial clock. uart operation stops (transmit shift register 0 (txs0), receive shift register 0 (rx0), and receive buffer register 0 (rxb0) hold the value just before the clock stop). external interrupt operable
272 chapter 16 standby function preliminary user s manual u16035ej1v0um (2) stop mode release the stop mode can be released by the following two types of sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. if interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 16-4. stop mode release by interrupt request generation stop instruction wait (time set by osts) oscillation stabilization wait status operating mode stop mode operating mode oscillation clock standby release signal oscillation stop oscillation interrupt request remark the broken line indicates the case when the interrupt request which has released the standby mode is acknowledged.
273 chapter 16 standby function preliminary user? manual u16035ej1v0um (b) release by reset input the stop mode is released when reset signal is input, and after the lapse of oscillation stabilization time, reset operation is carried out. figure 16-5. stop mode release by reset input stop instruction wait (2 17 /f x : 15.6 ms) oscillation stabilization wait status operating mode stop mode operating mode oscillation stop clock reset signal oscillation oscillation reset period remarks 1. f x : main system clock oscillation frequency 2. values in parentheses are for operation with f x = 8.38 mhz. table 16-4. operation after stop mode release release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0101 next address instruction execution 01 0 0111 interrupt service execution 1 stop mode hold reset input reset processing : don t care
274 preliminary user? manual u16035ej1v0um chapter 17 reset function 17.1 reset function the following two operations are available to generate the reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop time detection external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in table 17-1. each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. when a high level is input to the reset pin, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ). the reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ) (see figures 17-2 to 17-4 ). cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pin becomes high-impedance. figure 17-1. block diagram of reset function reset count clock reset controller watchdog timer stop overflow reset signal interrupt function
275 chapter 17 reset function preliminary user s manual u16035ej1v0um figure 17-2. timing of reset by reset input delay delay hi-z normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 reset internal reset signal port pin figure 17-3. timing of reset due to watchdog timer overflow hi-z normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 watchdog timer overflow internal reset signal port pin figure 17-4. timing of reset in stop mode by reset input delay delay hi-z normal operation oscillation stabilization time wait normal operation (reset processing) x1 reset internal reset signal port pin stop status (oscillation stop) stop instruction execution reset period (oscillation stop)
276 chapter 17 reset function preliminary user s manual u16035ej1v0um table 17-1. hardware statuses after reset (1/2) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general-purpose register undefined note 2 port (output latch) 00h port mode registers (pm0, pm2 to pm5, pm7) ffh pull-up resistor option registers (pu0, pu2 to pu5, pu7) 00h processor clock control register (pcc) 04h memory size switching register (ims) cfh note 3 memory expansion mode register (mem) 00h oscillation stabilization time select register (osts) 04h 16-bit timer/event counter timer counter (tm0) 0000h capture/compare registers (cr00, cr01) undefined prescaler mode register (prm0) 00h mode control register (tmc0) 00h output control register (toc0) 00h 8-bit timer/event counter timer counters (tm50, tm51) 00h compare registers (cr50, cr51) undefined clock select registers (tcl50, tcl51) 00h mode control registers (tmc50, tmc51) 00h watch timer operation mode register (wtm) 00h watchdog timer clock select register (wdcs) 00h mode register (wdtm) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. although the initial value is cfh, use the following value to be set for each version. pd780021as, 780031as: 42h pd780022as, 780032as: 44h pd780023as, 780033as: c6h pd780024as, 780034as: c8h pd78f0034bs: value for mask rom versions
277 chapter 17 reset function preliminary user s manual u16035ej1v0um table 17-1. hardware statuses after reset (2/2) hardware status after reset clock output/buzzer output controller clock output select register (cks) 00h a/d converter conversion result register (adcr0) 00h mode register (adm0) 00h analog input channel specification register (ads0) 00h serial interface (uart0) asynchronous serial interface mode register (asim0) 00h asynchronous serial interface status register (asis0) 00h baud rate generator control register (brgc0) 00h transmit shift register (txs0) ffh receive buffer register (rxb0) serial interface (sio3) shift registers (sio30, sio31) undefined operating mode registers (csim30, csim31) 00h interrupt request flag registers (if0l, if0h, if1l) 00h mask flag registers (mk0l, mk0h, mk1l) ffh priority specification flag registers (pr0l, pr0h, pr1l) ffh external interrupt rising edge enable register (egp) 00h external interrupt falling edge enable register (egn) 00h
278 preliminary user? manual u16035ej1v0um chapter 18 pd78f0034bs the pd78f0034bs is provided as the flash memory version of the pd780024as, 780034as subseries. the pd78f0034bs replaces the internal mask rom of the pd780034bs with flash memory to which a program can be written, erased and overwritten while mounted on the board. table 18-1 lists the differences among the pd78f0034bs and the mask rom versions. table 18-1. differences among pd78f0034bs and mask rom versions item pd78f0034bs mask rom versions pd780034as subseries pd780024as subseries internal rom configuration flash memory mask rom internal rom capacity 32 kb note pd780031as: 8 kb pd780021as: 8 kb pd780032as: 16 kb pd780022as: 16 kb pd780033as: 24 kb pd780023as: 24 kb pd780034as: 32 kb pd780024as: 32 kb internal high-speed ram capacity 1024 bytes note pd780031as: 512 bytes pd780021as: 512 bytes pd780032as: 512 bytes pd780022as: 512 bytes pd780033as: 1024 bytes pd780023as: 1024 bytes pd780034as: 1024 bytes pd780024as: 1024 bytes resolution of a/d converter 10 bits 8 bits ic pin none available v pp pin available none electrical specifications refer to data sheet of each product. note the same capacity as the mask rom versions can be specified by means of the memory size switching register (ims). caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version.
279 chapter 18 pd78f0034bs preliminary user? manual u16035ej1v0um 18.1 memory size switching register the pd78f0034bs allows users to select the internal memory capacity using the memory size switching register (ims) so that the same memory map as that of the pd780021as, 780022as, 780023as, 780024as and pd780031as, 780032as, 780033as, 780034as with a different size of internal memory capacity can be achieved. ims is set by an 8-bit memory manipulation instruction. reset input sets ims to cfh. caution the initial value of ims is ?etting prohibited (cfh)? be sure to set the value of the relevant mask rom versions at initialization. figure 18-1. format of memory size switching register (ims) address: fff0h after reset: cfh r/w symbol 76543210 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal high-speed ram capacity selection 0 1 0 512 bytes 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 00108 kb 010016 kb 011024 kb 100032 kb 111160 kb (setting prohibited) other than above setting prohibited the ims settings to obtain the same memory map as mask rom versions are shown in table 18-2. table 18-2. memory size switching register settings target mask rom versions ims setting pd780021as, 780031as 42h pd780022as, 780032as 44h pd780023as, 780033as c6h pd780024as, 780034as c8h caution when using the mask rom versions, be sure to set the value indicated in table 18-2 to ims.
280 chapter 18 pd78f0034bs preliminary user? manual u16035ej1v0um 18.2 flash memory programming on-board writing of flash memory (with device mounted on target system) is supported. on-board writing is done after connecting a dedicated flash programmer (flashpro iii (fl-pr3, pg-fp3)) to the host machine and target system. moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to flashpro iii. remark fl-pr3 is a product of naito densei machida mfg. co., ltd. 18.2.1 selection of communication mode writing to flash memory is performed using flashpro iii and serial communication. select the communication mode for writing from table 18-3. for the selection of the communication mode, a format like the one shown in figure 18- 2 is used. the communication modes are selected with the v pp pulse numbers shown in table 18-3. table 18-3. communication mode list communication mode number of channels pin used note number of v pp pulses 3-wire serial i/o 1 si30/p20 0 so30/p21 sck30/p22 si30/p20 3 so30/p21 sck30/p22 hs/p25 3-wire serial i/o 1 si31/p34 1 so31/p35 sck31/p36 uart 1 rxd0/p23 8 txd0/p24 pseudo 3-wire serial i/o 1 p72/ti50/to50 12 (serial clock input) p71/ti01 (serial data output) p70/ti00/to0 (serial data input) note when the flash memory programming mode is entered, all pins that are not used for flash memory programming become the same status as the status immediately after reset. therefore, when the external device connected to each port does not acknowledge the port status immediately after reset, pin connections such as connecting to v dd0 or v dd1 via a resistor or connecting to v ss0 or v ss1 via a resistor are required. cautions 1. be sure to select the number of v pp pulses shown in table 18-3 for the communication mode. 2. if performing write operations to flash memory with the uart communication mode, set the main system clock oscillation frequency to 3 mhz or higher.
281 chapter 18 pd78f0034bs preliminary users manual u16035ej1v0um figure 18-2. format of communication mode selection 18.2.2 flash memory programming function flash memory writing is performed through command and data transmit/receive operations using the selected communication mode. the main functions are listed in table 18-4. table 18-4. main functions of flash memory programming function description reset used to detect write stop and transmission synchronization. batch verify compares entire memory contents and input data. batch erase erases the entire memory contents. batch blank check checks the deletion status of the entire memory. high-speed write performs writing to flash memory according to write start address and number of write data (bytes). continuous write performs continuous write operations using the data input with high-speed write operation. status checks the current operation mode and operation end. oscillation frequency setting inputs the resonator oscillation frequency information. erase time setting inputs the memory erase time. baud rate setting sets the communication rate when the uart mode is used. silicon signature read outputs the device name, memory capacity, and device block information. 10 v v pp reset v dd v ss v dd v ss v pp pulses flash memory write mode
282 chapter 18 pd78f0034bs preliminary user s manual u16035ej1v0um 18.2.3 connection of flashpro iii connection of the flashpro iii and the pd78f0034bs differs depending on communication mode (3-wire serial i/o and uart). each type of connection is shown in figures 18-3 to 18-6. figure 18-3. connection of flashpro iii in 3-wire serial i/o mode vpp vdd reset sck so si gnd v pp v dd reset sck3n si3n so3n v ss flashpro iii pd78f0034bs figure 18-4. connection of flashpro iii in 3-wire serial i/o mode (using handshake) vpp vdd reset sck so hs si gnd v pp v dd reset sck30 si30 so30 hs (p25) v ss flashpro iii pd78f0034bs figure 18-5. connection of flashpro iii in uart mode vpp vdd reset so si gnd v pp v dd reset rxd0 txd0 v ss flashpro iii pd78f0034bs
283 chapter 18 pd78f0034bs preliminary user s manual u16035ej1v0um figure 18-6. connection of flashpro iii in pseudo 3-wire serial i/o mode vpp vdd reset sck so si gnd v pp v dd reset p72 (serial clock input) p70 (serial data input) p71 (serial data output) v ss flashpro iii pd78f0034bs
284 preliminary user s manual u16035ej1v0um chapter 19 instruction set this chapter lists each instruction set of the pd780024as, 780034as subseries in table form. for details of its operation and operation code, refer to the separate document 78k/0 series instructions user s manual (u12326e) .
285 chapter 19 instruction set preliminary user s manual u16035ej1v0um 19.1 conventions 19.1.1 operand identifiers and specification methods operands are written in operand column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more methods, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be written as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for specification. table 19-1. operand identifiers and specification methods identifier specification method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special function register symbol note sfrp special function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even address only) addr16 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or labels addr5 0040h to 007fh immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special function register symbols, refer to table 3-5 special function register list .
286 chapter 19 instruction set preliminary user s manual u16035ej1v0um 19.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 19.1.3 description of flag operation column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored
287 chapter 19 instruction set preliminary user s manual u16035ej1v0um 19.2 operation list clock flag note 1 note 2 zaccy mov r, #byte 2 4 C r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 C 7 sfr byte a, r note 3 12 C a r r, a note 3 12 C r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 C 5a sfr sfr, a 2 C 5 sfr a a, !addr16 3 8 9 + n a (addr16) !addr16, a 3 8 9 + m (addr16) a psw, #byte 3 C 7 psw byte a, psw 2 C 5a psw psw, a 2 C 5 psw a a, [de] 1 4 5 + n a (de) [de], a 1 4 5 + m (de) a a, [hl] 1 4 5 + n a (hl) [hl], a 1 4 5 + m (hl) a a, [hl + byte] 2 8 9 + n a (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) a a, [hl + b] 1 6 7 + n a (hl + b) [hl + b], a 1 6 7 + m (hl + b) a a, [hl + c] 1 6 7 + n a (hl + c) [hl + c], a 1 6 7 + m (hl + c) a xch a, r note 3 12 C a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 C 6a ? (sfr) a, !addr16 3 8 10 + n + m a ? (addr16) a, [de] 1 4 6 + n + m a ? (de) a, [hl] 1 4 6 + n + m a ? (hl) a, [hl + byte] 2 8 10 + n + m a ? (hl + byte) a, [hl + b] 2 8 10 + n + m a ? (hl + b) a, [hl + c] 2 8 10 + n + m a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group 8-bit data transfer
288 chapter 19 instruction set preliminary user s manual u16035ej1v0um clock flag note 1 note 2 zaccy movw rp, #word 3 6 C rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 C 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 C 8 ax sfrp sfrp, ax 2 C 8 sfrp ax ax, rp note 3 14 C ax rp rp, ax note 3 14 C rp ax ax, !addr16 3 10 12 + 2n ax (addr16) !addr16, ax 3 10 12 + 2m (addr16) ax xchw ax, rp note 3 14 C ax ? rp add a, #byte 2 4 C a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 24 C a, cy a + r r, a 2 4 C r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 + n a, cy a + (addr16) a, [hl] 1 4 5 + n a, cy a + (hl) a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) a, [hl + b] 2 8 9 + n a, cy a + (hl + b) a, [hl + c] 2 8 9 + n a, cy a + (hl + c) a, #byte 2 4 C a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 24 C a, cy a + r + cy r, a 2 4 C r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 + n a, cy a + (addr16) + cy a, [hl] 1 4 5 + n a, cy a + (hl) + cy a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 + n a, cy a + (hl + b) + cy a, [hl + c] 2 8 9 + n a, cy a + (hl + c) + cy when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group 16-bit data transfer 8-bit operation
289 chapter 19 instruction set preliminary user s manual u16035ej1v0um clock flag note 1 note 2 zaccy sub a, #byte 2 4 C a, cy a C byte saddr, #byte 3 6 8 (saddr), cy (saddr) C byte a, r note 3 24 C a, cy a C r r, a 2 4 C r, cy r C a a, saddr 2 4 5 a, cy a C (saddr) a, !addr16 3 8 9 + n a, cy a C (addr16) a, [hl] 1 4 5 + n a, cy a C (hl) a, [hl + byte] 2 8 9 + n a, cy a C (hl + byte) a, [hl + b] 2 8 9 + n a, cy a C (hl + b) a, [hl + c] 2 8 9 + n a, cy a C (hl + c) a, #byte 2 4 C a, cy a C byte C cy saddr, #byte 3 6 8 (saddr), cy (saddr) C byte C cy a, r note 3 24 C a, cy a C r C cy r, a 2 4 C r, cy r C a C cy a, saddr 2 4 5 a, cy a C (saddr) C cy a, !addr16 3 8 9 + n a, cy a C (addr16) C cy a, [hl] 1 4 5 + n a, cy a C (hl) C cy a, [hl + byte] 2 8 9 + n a, cy a C (hl + byte) C cy a, [hl + b] 2 8 9 + n a, cy a C (hl + b) C cy a, [hl + c] 2 8 9 + n a, cy a C (hl + c) C cy a, #byte 2 4 C a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 C a a r r, a 2 4 C r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. mnemonic operands byte operation instruction group 8-bit operation
290 chapter 19 instruction set preliminary user s manual u16035ej1v0um clock flag note 1 note 2 zaccy or a, #byte 2 4 C a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 C a a r r, a 2 4 C r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) a, #byte 2 4 C a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 C a a r r, a 2 4 C r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) a, #byte 2 4 C a C byte saddr, #byte 3 6 8 (saddr) C byte a, r note 3 24 C a C r r, a 2 4 C r C a a, saddr 2 4 5 a C (saddr) a, !addr16 3 8 9 + n a C (addr16) a, [hl] 1 4 5 + n a C (hl) a, [hl + byte] 2 8 9 + n a C (hl + byte) a, [hl + b] 2 8 9 + n a C (hl + b) a, [hl + c] 2 8 9 + n a C (hl + c) when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. mnemonic operands byte operation instruction group 8-bit operation
291 chapter 19 instruction set preliminary user s manual u16035ej1v0um clock flag note 1 note 2 zaccy addw ax, #word 3 6 C ax, cy ax + word ax, #word 3 6 C ax, cy ax C word ax, #word 3 6 C ax C word x216 C ax a x divuw c225 C ax (quotient), c (remainder) ax c inc r12 C r r + 1 saddr 2 4 6 (saddr) (saddr) + 1 r12 C r r C 1 saddr 2 4 6 (saddr) (saddr) C 1 rp 1 4 C rp rp + 1 decw rp 1 4 C rp rp C 1 ror a, 1 1 2 C (cy, a 7 a 0 , a m C 1 a m ) 1 time a, 1 1 2 C (cy, a 0 a 7 , a m + 1 a m ) 1 time a, 1 1 2 C (cy a 0 , a 7 cy, a m C 1 a m ) 1 time a, 1 1 2 C (cy a 7 , a 0 cy, a m + 1 a m ) 1 time [hl] 2 10 12 + n + m a 3 C 0 (hl) 3 C 0 , (hl) 7 C 4 a 3 C 0 , (hl) 3 C 0 (hl) 7 C 4 rol4 [hl] 2 10 12 + n + m a 3 C 0 (hl) 7 C 4 , (hl) 3 C 0 a 3 C 0 , (hl) 7 C 4 (hl) 3 C 0 adjba 24 C decimal adjust accumulator after addition adjbs 24 C decimal adjust accumulator after subtract mov1 cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 C 7 cy sfr.bit cy, a.bit 2 4 C cy a.bit cy, psw.bit 3 C 7 cy psw.bit cy, [hl].bit 2 6 7 + n cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 C 8 sfr.bit cy a.bit, cy 2 4 C a.bit cy psw.bit, cy 3 C 8 psw.bit cy [hl].bit, cy 2 6 8 + n + m (hl).bit cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group 16-bit operation increment/ decrement bcd adjust bit manipu- late multiply/ divide rotate
292 chapter 19 instruction set preliminary user s manual u16035ej1v0um clock flag note 1 note 2 zaccy and1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 C 7 cy cy sfr.bit cy, a.bit 2 4 C cy cy a.bit cy, psw.bit 3 C 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 C 7 cy cy sfr.bit cy, a.bit 2 4 C cy cy a.bit cy, psw.bit 3 C 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 C 7 cy cy sfr.bit cy, a.bit 2 4 C cy cy a.bit cy, psw. bit 3 C 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 C 8 sfr.bit 1 a.bit 2 4 C a.bit 1 psw.bit 2 C 6 psw.bit 1 [hl].bit 2 6 8 + n + m (hl).bit 1 clr1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 C 8 sfr.bit 0 a.bit 2 4 C a.bit 0 psw.bit 2 C 6 psw.bit 0 [hl].bit 2 6 8 + n + m (hl).bit 0 set1 cy 1 2 C cy 11 clr1 cy 1 2 C cy 00 not1 cy 1 2 C cy cy when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group bit manipu- late
293 chapter 19 instruction set preliminary user s manual u16035ej1v0um uncondi- tional branch stack manipu- late conditional branch call/return clock flag note 1 note 2 zaccy call !addr16 3 7 C (sp C 1) (pc + 3) h , (sp C 2) (pc + 3) l , pc addr16, sp sp C 2 callf !addr11 2 5 C (sp C 1) (pc + 2) h , (sp C 2) (pc + 2) l , pc 15 C 11 00001, pc 10 C 0 addr11, sp sp C 2 callt [addr5] 1 6 C (sp C 1) (pc + 1) h , (sp C 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp C 2 brk 16 C (sp C 1) psw, (sp C 2) (pc + 1) h , (sp C 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp C 3, ie 0 ret 16 C pc h (sp + 1), pc l (sp), sp sp + 2 reti 16 C pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3, nmis 0 retb 16 C pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3 push psw 1 2 C (sp C 1) psw, sp sp C 1 rp 1 4 C (sp C 1) rp h , (sp C 2) rp l , sp sp C 2 pop psw 1 2 C psw (sp), sp sp + 1 r r r rp 1 4 C rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, #word 4 C 10 sp word sp, ax 2 C 8 sp ax ax, sp 2 C 8 ax sp br !addr16 3 6 C pc addr16 $addr16 2 6 C pc pc + 2 + jdisp8 ax 2 8 C pc h a, pc l x bc $addr16 2 6 C pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 C pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 C pc pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 C pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. mnemonic operands byte operation instruction group
294 chapter 19 instruction set preliminary user s manual u16035ej1v0um clock flag note 1 note 2 zaccy bt saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 C 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 C pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 C 9 pc pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 1 bf saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 C 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 C pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 C 11 pc pc + 4 + jdisp8 if psw. bit = 0 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 0 btclr saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 C 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 C pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 C 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit, $addr16 3 10 12 + n + m pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b, $addr16 2 6 C b b C 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 C c c C 1, then pc pc + 2 + jdisp8 if c 0 saddr. $addr16 3 8 10 (saddr) (saddr) C 1, then pc pc + 3 + jdisp8 if(saddr) 0 sel rbn 2 4 C rbs1, 0 n nop 12 C no operation ei 2 C 6 ie 1 (enable interrupt) di 2 C 6 ie 0 (disable interrupt) halt 26 C set halt mode stop 26 C set stop mode notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group cpu control condi- tional branch
295 chapter 19 instruction set preliminary user s manual u16035ej1v0um 19.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz
296 chapter 19 instruction set preliminary user s manual u16035ej1v0um second operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none first operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except r = a
297 chapter 19 instruction set preliminary user s manual u16035ej1v0um (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand #word ax rp note sfrp saddrp !addr16 sp none first operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1
298 chapter 19 instruction set preliminary user s manual u16035ej1v0um (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand ax !addr16 !addr11 [addr5] $addr16 first operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
299 preliminary users manual u16035ej1v0um appendix a differences between pd780024a, 780024as, 780034a, and 780034as subseries table a-1 shows the major differences between pd780024a, 780024as, 780034a, and 780034as subseries. table a-1. major differences between pd780024a, 780024as, 780034a, and 780034as subseries pd780024a pd780034a pd780024as pd780034as subseries subseries subseries subseries 8 kb/16 kb/24 kb/32 kb 512 bytes/1,024 bytes pd78f0034b pd78f0034bs pd780024ay pd780034ay none subseries subseries 0.238 s: v dd = 4.5 to 5.5 v 0.400 s: v dd = 2.7 to 5.5 v 1.60 s: v dd = 1.8 to 5.5 v 1.8 to 5.5 v total: 51 total: 39 input: 8 input: 4 i/o: 43 i/o: 35 (5 v tolerance n-ch open drain: 4) 16 bits 1 ch 8 bits 2 ch watch timer 1 ch watchdog timer 1 ch 3-wire serial i/o mode 2 ch uart mode 1 ch 8 bits 8 ch 10 bits 8 ch 8 bits 4 ch 10 bits 4 ch internal: 13, external: 5 1 1 time division method none expansion up to f7ffh is possible. pull-up resistor can be specified for p30 to p33 none ? 64-pin plastic sdip 52-pin plastic lqfp 64-pin plastic qfp 64-pin plastic tqfp 64-pin plastic lqfp ie-780034-ns-em1 ? np-64cw ? np-64gc (ev-9200gc-64) np-64gc-tq (tgc-064sap) ? np-64gk (tgk-064sbp) ? np-h64gb-tq (tgb-064sdp) df780024 df780034 df780024 df780034 ? fa-64cw fa-52gb-8et ? fa-64gc-8bs, fa64gc-ab8 ? fa-64gk-9et ? fa-64gb-8eu part number item rom capacity internal high-speed ram capacity flash memory version i 2 c bus version minimum instruction execution time operating voltage range i/o ports timer/counter serial interface a/d converter interrupt maskable non-maskable software external device expansion function mask option package emulation board emulation probe (conversion adapter) device file flash memory writing adapter np-h52gb-tq (tgb-052sbp) * a conversion board is required to connect the probe to the emulation board.
300 preliminary user s manual u16035ej1v0um appendix b development tools the following development tools are available for the development of systems that employ the pd780024as, 780034as subseries. figure b-1 shows the development tool configuration. support for pc98-nx series unless otherwise specified, products compatible with ibm pc/at tm computers are compatible with pc98-nx series computers. when using pc98-nx series computers, refer to the explanation for ibm pc/at computers. windows unless otherwise specified, windows means the following oss. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt tm ver 4.0
301 appendix b development tools preliminary user? manual u16035ej1v0um figure b-1. development tool configuration remark items in broken line boxes differ according to the development environment. see b.3.1 hardware . system simulator integrated debugger device file embedded software real-time os debugging tool assembler package c compiler package c library source file device file language processing software flash memory write adapter in-circuit emulator power supply unit emulation probe conversion socket or conversion adapter target system host machine (pc) interface adapter, pc card interface, etc. emulation board on-chip flash memory version flash memory write environment flash programmer i/o board performance board
302 appendix b development tools preliminary user s manual u16035ej1v0um b.1 language processing software sp78k0 78k/0 series software package ra78k0 assembler package cc78k0 c compiler package df780024 note df780034 note device file cc78k0-l c library source file note the df780024 and df780034 can be used in common with the ra78k0, cc78k0, sm78k0, id78k0-ns, and id78k0. remark in the part number differs depending on the host machine and os used. this is a software package that includes the development tools common to the 78k/0 series. part number: s sp78k0 this assembler converts programs written in mnemonics into object codes executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with an optional device file (df780024 or df780034). this assembler package is a dos-based application. it can also be used in windows, however, by using the project manager (included in assembler package) on windows. part number: s ra78k0 this compiler converts programs written in c language into object codes executable with a microcontroller. this compiler should be used in combination with an optional assembler package and device file. this c compiler package is a dos-based application. it can also be used in windows, however, by using the project manager (included in assembler package) on windows. part number: s cc78k0 this file contains information peculiar to the device. this device file should be used in combination with an optional tool (ra78k0, cc78k0, sm78k0, id78k0-ns, and id78k0). corresponding os and host machine differ depending on the tool to be used with. df780024: for pd780024a, 780024ay, 780024as subseries df780034: for pd780034a, 780034ay, 780034as subseries part number: s df780034 this is a source file of functions configuring the object library included in the c compiler package. this file is required to match the object library included in c compiler package to the customer s specifications. operating environment for the source file is not dependent on the os. part number: s cc78k0-l
303 appendix b development tools preliminary user s manual u16035ej1v0um s sp78k0 host machine os supply medium ab17 pc-9800 series, windows (japanese version) cd-rom bb17 ibm pc/at or compatibles windows (english version) s ra78k0 s cc78k0 host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at or compatibles windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df780024 s df780034 s cc78k0-l host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at or compatibles windows (english version) 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.4), 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt b.2 flash memory writing tools flashpro iii (part number: fl-pr3, pg-fp3) flash programmer fa-52gb-8et flash memory writing adapter remark fl-pr3 and fa-52gb-8et are products of naito densei machida mfg. co., ltd. inquiry: naito densei machida mfg. co., ltd. (tel +81-45-475-4191) flash programmer dedicated to microcontrollers with on-chip flash memory. flash memory writing adapter used connected to the flashpro iii. fa-52gb-8et: 52-pin plastic lqfp (gb-8et type)
304 appendix b development tools preliminary user s manual u16035ej1v0um b.3 debugging tools b.3.1 hardware ie-78k0-ns in-circuit emulator ie-78k0-ns-pa performance board ie-78k0-ns-a in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c interface adapter ie-70000-cd-if-a pc card interface ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-780034-ns-em1 emulation board 780034as 52pin board convension board np-h52gb-tq emulation probe tgb-052sbp conversion adapter remarks 1. np-h52gb-tq is a product of naito densei machida mfg. co., ltd. inquiry: naito densei machida mfg. co., ltd. (tel +81-45-475-4191) 2. tgb-052sbp is a product of tokyo eletech corporation. inquiry: daimaru kogyo, ltd.: tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672) 3. tgb-052sbp is sold in one units. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to integrated debugger (id78k0-ns). this emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. this board is connected to the ie-78k0-ns to expand its functions. adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. this is an in-circuit emulator that combines ie-78k0-ns and ie-78k0-ns-pa. this adapter is used for supplying power from a receptacle of 100 v to 240 v ac. this adapter is required when using the pc-9800 series computer (except notebook type) as the host machine (c bus supported). this is pc card and interface cable required when using notebook-type computer as the host machine (pcmcia socket supported). this adapter is required when using the ibm pc/at compatible computers as the host machine (isa bus supported). this adapter is required when using a computer with pci bus as the host machine. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. this conversion board is used to connect the emulation probe to the emulation board. this probe is used to connect the in-circuit emulator to a target system and is designed for use with 52-pin plastic lqfp (gb-8et type). this conversion socket connects the np-h52gb-tq to a target system board designed for a 52-pin plastic lqfp (gb-8et type).
305 appendix b development tools preliminary user s manual u16035ej1v0um b.3.2 software sm78k0 system simulator id78k0-ns integrated debugger (supporting in-circuit emulator ie-78k0-ns(-a)) remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns host machine os supply medium ab13 pc-9800 series, japanese windows 3.5-inch 2hd fd bb13 ibm pc/at or compatibles english windows ab17 japanese windows cd-rom bb17 english windows this system simulator is used to perform debugging at c source level or assembler level while simulating the operation of the target system on a host machine. this simulator runs on windows. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with the optional device file (df780024 or df780034). part number: s sm78k0 this debugger is a control program to debug 78k/0 series microcontrollers. it adopts a graphical user interface, which is equivalent visually and operationally to windows or osf/motif . it also has an enhanced debugging function for c language programs, and thus trace results can be displayed on screen in c-language level by using the windows integration function which links a trace result with its source program, disassembled display, and memory display. in addition, by incorporating function expansion modules such as task debugger and system performance analyzer, the efficiency of debugging programs, which run on real-time oss can be improved. it should be used in combination with the optional device file. part number: s id78k0-ns
306 preliminary user? manual u16035ej1v0um appendix c embedded software for efficient program development and maintenance of the pd780024as, 780034as subseries, the following embedded software products are available. real-time os rx78k0 rx78k/0 is a real-time os conforming to the itron specifications. real-time os tool (configurator) for generating nucleus of rx78k0 and plural information tables is supplied. used in combination with an optional assembler package (ra78k0) and device file (df780024 or df780034). the real-time os is a dos-based application. it should be used in the dos prompt when using in windows. part number: s rx78013- ???? caution when purchasing the rx78k0, fill in the purchase application form in advance and sign the user agreement. remark and ???? in the part number differ depending on the host machine and os used. s rx78013- ???? ???? product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k mass-production object 0.1 million units 001m 1 million units 010m 10 million units s01 source program source program for mass-produced object host machine os supply medium aa13 pc-9800 series japanese windows note 3.5-inch 2hd fd ab13 ibm pc/at or compatibles japanese windows note 3.5-inch 2hd fd bb13 english windows note 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.4), 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt note can also be operated in dos environment.
307 preliminary users manual u16035ej1v0um appendix d register index d.1 register name index [a] a/d conversion result register 0 (adcr0) 172, 194 a/d converter mode register 0 (adm0) 174, 195 analog input channel specification register 0 (ads0) 176, 195 asynchronous serial interface mode register 0 (asim0) 216 asynchronous serial interface status register 0 (asis0) 218 [b] baud rate generator control register 0 (brgc0) 218 [c] capture/compare control register 0 (crc0) 110 clock output select register (cks) 166 [e] 8-bit timer compare register 50 (cr50) 134 8-bit timer compare register 51 (cr51) 134 8-bit timer counter 50 (tm50) 135 8-bit timer counter 51 (tm51) 135 8-bit timer mode control register 50 (tmc50) 136 8-bit timer mode control register 51 (tmc51) 136 external interrupt falling edge enable register (egn) 176, 197, 254 external interrupt rising edge enable register (egp) 176, 197, 254 [i] interrupt mask flag register 0h (mk0h) 252 interrupt mask flag register 0l (mk0l) 252 interrupt mask flag register 1l (mk1l) 252 interrupt request flag register 0h (if0h) 251 interrupt request flag register 0l (if0l) 251 interrupt request flag register 1l (if1l) 251 [m] memory expansion mode register (mem) 254 memory size switching register (ims) 279 [o] oscillation stabilization time select register (osts) 162, 267 [p] port 0 (p0) 75 port 1 (p1) 76 port 2 (p2) 77
308 appendix d register index preliminary user? manual u16035ej1v0um port 3 (p3) ?79 port 4 (p4) ?81 port 5 (p5) ?82 port 7 (p7) ?83 port mode register 0 (pm0) ?85 port mode register 2 (pm2) ?85 port mode register 3 (pm3) ?85 port mode register 4 (pm4) ?85 port mode register 5 (pm5) ?85 port mode register 7 (pm7) ?85, 113, 139, 168 prescaler mode register 0 (prm0) ?112 priority specification flag register 0h (pr0h) ?253 priority specification flag register 0l (pr0l) ?253 priority specification flag register 1l (pr1l) ?253 processor clock control register (pcc) ?93 program status word (psw) ?55, 255 pull-up resistor option register 0 (pu0) ?87 pull-up resistor option register 2 (pu2) ?87 pull-up resistor option register 3 (pu3) ?87 pull-up resistor option register 4 (pu4) ?87 pull-up resistor option register 5 (pu5) ?87 pull-up resistor option register 7 (pu7) ?87 [r] receive buffer register 0 (rxb0) ?215 receive shift register 0 (rx0) ?215 [s] serial i/o shift register 30 (sio30) ?237 serial i/o shift register 31 (sio31) ?237 serial operation mode register 30 (csim30) ?238 serial operation mode register 31 (csim31) ?240 16-bit timer capture/compare register 00 (cr00) ?106 16-bit timer capture/compare register 01 (cr01) ?107 16-bit timer counter 0 (tm0) ?106 16-bit timer mode control register 0 (tmc0) ?108 16-bit timer output control register 0 (toc0) ?111 [t] timer clock select register 50 (tcl50) ?135 timer clock select register 51 (tcl51) ?135 transmit shift register 0 (txs0) ?215 [w] watch timer operation mode register (wtm) ?154 watchdog timer clock select register (wdcs) ?160 watchdog timer mode register (wdtm) ?161
309 appendix d register index preliminary users manual u16035ej1v0um d.2 register symbol index [a] adcr0: a/d conversion result register 0 172, 194 adm0: a/d converter mode register 0 174, 195 ads0: analog input channel specification register 0 176, 197 asim0: asynchronous serial interface mode register 0 216 asis0: asynchronous serial interface status register 0 218 [b] brgc0: baud rate generator control register 0 218 [c] cks: clock output select register 166 cr00: 16-bit timer capture/compare register 00 106 cr01: 16-bit timer capture/compare register 01 107 cr50: 8-bit timer compare register 50 134 cr51: 8-bit timer compare register 51 134 crc0: capture/compare control register 0 110 csim30: serial operation mode register 30 238 csim31: serial operation mode register 31 240 [e] egn: external interrupt falling edge enable register 176, 197, 254 egp: external interrupt rising edge enable register 176, 197, 254 [i] if0h: interrupt request flag register 0h 251 if0l: interrupt request flag register 0l 251 if1l: interrupt request flag register 1l 251 ims: memory size switching register 279 [m] mem: memory expansion mode register 254 mk0h: interrupt mask flag register 0h 252 mk0l: interrupt mask flag register 0l 252 mk1l: interrupt mask flag register 1l 252 [o] osts: oscillation stabilization time select register 162, 267 [p] p0: port 0 75 p1: port 1 76 p2: port 2 77 p3: port 3 79 p4: port 4 81 p5: port 5 82
310 appendix d register index preliminary users manual u16035ej1v0um p7: port 7 83 pcc: processor clock control register 93 pm0: port mode register 0 85 pm2: port mode register 2 85 pm3: port mode register 3 85 pm4: port mode register 4 85 pm5: port mode register 5 85 pm7: port mode register 7 85, 133, 139, 168 pr0h: priority specification flag register 0h 253 pr0l: priority specification flag register 0l 253 pr1l: priority specification flag register 1l 253 prm0: prescaler mode register 0 112 psw: program status word 55, 255 pu0: pull-up resistor option register 0 87 pu2: pull-up resistor option register 2 87 pu3: pull-up resistor option register 3 87 pu4: pull-up resistor option register 4 87 pu5: pull-up resistor option register 5 87 pu7: pull-up resistor option register 7 87 [r] rxb0: receive buffer register 0 215 rx0: receive shift register 0 215 [s] sio30: serial i/o shift register 30 237 sio31: serial i/o shift register 31 237 [t] tcl50: timer clock select register 50 135 tcl51: timer clock select register 51 135 tm0: 16-bit timer counter 0 106 tm50: 8-bit timer counter 50 134 tm51: 8-bit timer counter 51 134 tmc0: 16-bit timer mode control register 0 108 tmc50: 8-bit timer mode control register 50 136 tmc51: 8-bit timer mode control register 51 136 toc0: 16-bit timer output control register 0 111 txs0: transmit shift register 0 215 [w] wdcs: watchdog timer clock select register 160 wdtm: watchdog timer mode register 161 wtm: watch timer operation mode register 154
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