 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1999 mos integrated circuit pd23c64202l 64m-bit synchronous mask-programmable rom 4m-word by 16-bit (word mode) / 2m-word by 32-bit (double word mode) data sheet the mark ! ! ! ! shows major revised points. document no. m13945ej5v0ds00 (5th edition) date published august 2001 ns cp (k) printed in japan the mark ! ! ! ! shows major revised points. description the pd23c64202l is a 67,108,864 bits synchronous mask-programmable rom with multiplexed address bus. the word organization is selectable (word mode : 4,194,304 words by 16 bits, double word mode : 2,097,152 words by 32 bits). the pd23c64202l is packed in 86-pin plastic tsop (ii). features ? fully synchronous mask-rom; all signals referenced to a positive clock edge ? word organization : 4,194,304 words by 16 bits (word mode) 2,097,152 words by 32 bits (double word mode) ? operation frequency : up to 100 mhz operation supply voltage v cc clock frequency mhz access time from clk ns (max.) operating current (burst mode) ma (max.) standby current (cmos level input) a (max.) 3.3 v 0.3 v 100 6 150 100 83 8 66 9 50 9 33 9 ? programmable wrap type : sequential or interleave ? programmable burst length : 4, 8 ? programmable /cas latency : 3, 4, 5 or 6 ? programmable /ras latency : 1, 2 ? burst termination by burst stop command ? lvttl compatible inputs and outputs
data sheet m13945ej5v0ds 2 pd23c64202l ordering information part number package pd23c64202lg5- -9jh 86-pin plastic tsop (ii) (10.16 mm (400)) : rom code suffix pin configuration (marking side) /xxx indicates active low si gnal. 86-pin plastic tsop (ii) (10.16 mm (400)) [ pd23c64202lg5- -9jh ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 v cc o0 v cc q o16 o1 v ss q o17 o2 v cc q o18 o3 v ss q o19 /mr v cc dqm ic /cas /ras /cs /word a12 a11 a10 a0 a1 a2 ic v cc nc o4 v ss q o20 o5 v cc q o21 o6 v ss q o22 o7 v cc q o23 v cc v ss o31 v ss q o15 o30 v cc q o14 o29 v ss q o13 o28 v cc q o12 ic v ss nc nc nc clk cke a9 a8 a7 a6 a5 a4 a3 ic v ss nc o27 v cc q o11 o26 v ss q o10 o25 v cc q o9 o24 v ss q o8 v ss remarks 1. ic : internally connected; leave this pin unconnected or connect to gnd. nc : not internally connected; signal can be applied. 2. refer to 13. package drawing for the 1-pin index mark. data sheet m13945ej5v0ds 3 pd23c64202l pin name symbol pin name pin number clk clock input 68 cke clock enable input 67 /cs chip select 20 /ras row address strobe 19 /cas column address strobe 18 /mr mode register enable 14 /word mode select (double word / word) 21 a0 - a12 address inputs 25, 26, 27, 60, 61, 62, 63, 64, 65, 66, 24, 23, 22 o0 - o15, o16 - o31 data outputs 2, 5, 8, 11, 31, 34, 37, 40, 45, 48, 51, 54, 74, 77, 80, 83, 4, 7, 10, 13, 33, 36, 39, 42, 47, 50, 53, 56, 76, 79, 82, 85 dqm dq mask enable 16 v cc supply voltage (for internal circuit) 1, 15, 29, 43 v cc q supply voltage (for output buffer) 3, 9, 35, 41, 49, 55, 75, 81 v ss ground (for internal circuit) 44, 58, 72, 86 v ss q ground (for output buffer) 6, 12, 32, 38, 46, 52, 78, 84 nc no connection 30, 57, 69, 70, 71 ic internal connection 17, 28, 59, 73 block diagram dqm clock generator command decoder memory cell matrix 4,194,304 words by 16 bits (word mode) or 2,097,152 words by 32 bits (double word mode) mode register control logic column buffer column decoder sense amplifier output control output buffer o0 - o31 /cs /ras /cas /mr /word clk cke a0 - a12 row buffer row decoder data sheet m13945ej5v0ds 4 pd23c64202l contents 1. input / output pin functions ................................................................................................ ............ 7 2. simplified state diagram .................................................................................................... .............. 9 3. commands .................................................................................................................... .................... 10 3.1 mode register set (mrs) .................................................................................................... ............. 10 3.2 row activate (act) ......................................................................................................... ................... 10 3.3 read (read) ................................................................................................................ .......................... 10 3.4 burst stop (bst) ........................................................................................................... ...................... 10 4. truth table ................................................................................................................. ...................... 11 4.1 clock enable and command ................................................................................................... .............. 11 4.2 command truth table ........................................................................................................ .................... 11 4.3 operative command table ................................................................................................... ................ 12 5. mode register settings ...................................................................................................... ............ 13 6. word modes................................................................................................................... ................... 14 6.1 addressing map (word mode) ................................................................................................. ............ 14 6.2 data output (word mode) .................................................................................................... ................ 14 6.3 addressing map (double word mode) .......................................................................................... ... 15 6.4 data output (double word mode) ............................................................................................. ....... 15 7. relationship between clock frequency and /ras latency, /cas latency ............................... 16 8. command interval ............................................................................................................ ............... 18 8.1 relationship between frequency, parameter and command interval ............................................... 18 8.2 read to read command interval (t ccd ) .............................................................................................. 19 8.3 read to row activate command interval ...................................................................................... . 21 8.4 read to burst stop command interval ......................................................................................... ... 24 8.5 row activate to row activate command interval ..................................................................... 24 9. power-on sequence ........................................................................................................... ............ 25 10. basic operations ........................................................................................................... .................. 26 10.1 mode register set command ................................................................................................. ........ 26 10.2 dqm operation ............................................................................................................. ........................... 26 10.3 burst termination ......................................................................................................... .......................... 26 10.4 power down and clock suspend mode ...................................................................................... 27 10.4.1 power down mode ......................................................................................................... ....... 27 10.4.2 read suspend and active power down mode .............................................................. 27 11. electrical specifications .................................................................................................. ............... 28 12. timing charts .............................................................................................................. .................... 32 12.1 relationship between frequency and parameter .............................................................................. .. 32 12.1.1 row activate - read - row activate - read (1-1) ....................................................... 33 12.1.2 row activate - read - row activate - read (1-2) ....................................................... 33 12.1.3 row activate - read - row activate - read (2-1) ....................................................... 33 12.1.4 row activate - read - row activate - read (2-2) ....................................................... 34 12.1.5 row activate - read - row activate - read (2-3) ....................................................... 34 12.1.6 row activate - read - row activate - read (2-4) ....................................................... 34 12.1.7 row activate - read - row activate - read (3-1) ....................................................... 35 12.1.8 row activate - read - row activate - read (3-2) ....................................................... 35 12.1.9 row activate - read - row activate - read (4-1) ....................................................... 35 12.1.10 row activate - read - row activate - read (4-2) ....................................................... 36 12.1.11 row activate - read - row activate - read (4-3) ....................................................... 36 data sheet m13945ej5v0ds 5 pd23c64202l 12.1.12 row activate - read - row activate - read (4-4) ....................................................... 36 12.1.13 row activate - read - read (1-1) ...................................................................................... 37 12.1.14 row activate - read - read (1-2) ...................................................................................... 37 12.1.15 row activate - read - read (2-1) ...................................................................................... 37 12.1.16 row activate - read - read (2-2) ...................................................................................... 38 12.1.17 row activate - read - read (2-3) ...................................................................................... 38 12.1.18 row activate - read - read (2-4) ...................................................................................... 38 12.1.19 row activate - read - read (3-1) ...................................................................................... 39 12.1.20 row activate - read - read (3-2) ...................................................................................... 39 12.1.21 row activate - read - read (4-1) ...................................................................................... 39 12.1.22 row activate - read - read (4-2) ...................................................................................... 40 12.1.23 row activate - read - read (4-3) ...................................................................................... 40 12.1.24 row activate - read - read (4-4) ...................................................................................... 40 12.2 random row read timing .................................................................................................... ................ 41 12.2.1 at 100 mhz (2-5-1-1-1) .................................................................................................. ............. 41 12.2.2 at 100 mhz (2-5-1-1-1-1-1-1-1) .......................................................................................... ......... 41 12.2.3 at 83 mhz (2-5-1-1-1) ................................................................................................... .............. 42 12.2.4 at 83 mhz (2-5-1-1-1-1-1-1-1) ........................................................................................... .......... 42 12.2.5 at 66 mhz (2-5-1-1-1) ................................................................................................... .............. 43 12.2.6 at 66 mhz (2-5-1-1-1-1-1-1-1) ........................................................................................... .......... 43 12.2.7 at 50 mhz (1-4-1-1-1) ................................................................................................... .............. 44 12.2.8 at 50 mhz (1-4-1-1-1-1-1-1-1) ........................................................................................... .......... 44 12.2.9 at 33 mhz (1-3-1-1-1) ................................................................................................... .............. 45 12.2.10 at 33 mhz (1-3-1-1-1) .................................................................................................. ............... 45 12.2.11 at 33 mhz (1-3-1-1-1-1-1-1-1) .......................................................................................... ........... 46 12.2.12 at 33 mhz (1-3-1-1-1-1-1-1-1) .......................................................................................... ........... 46 12.3 random column read timing ................................................................................................. .............. 47 12.3.1 at 100 mhz (2-5-1-1-1) .................................................................................................. ............. 47 12.3.2 at 100 mhz (2-5-1-1-1-1-1-1-1) .......................................................................................... ......... 47 12.3.3 at 83 mhz (2-5-1-1-1) ................................................................................................... .............. 48 12.3.4 at 83 mhz (2-5-1-1-1-1-1-1-1) ........................................................................................... .......... 48 12.3.5 at 66 mhz (2-5-1-1-1) ................................................................................................... .............. 49 12.3.6 at 66 mhz (2-5-1-1-1-1-1-1-1) ........................................................................................... .......... 49 12.3.7 at 50 mhz (1-4-1-1-1) ................................................................................................... .............. 50 12.3.8 at 50 mhz (1-4-1-1-1) ................................................................................................... .............. 50 12.3.9 at 50 mhz (1-4-1-1-1-1-1-1-1) ........................................................................................... .......... 51 12.3.10 at 50 mhz (1-4-1-1-1-1-1-1-1) .......................................................................................... ........... 51 12.3.11 at 33 mhz (1-3-1-1-1) .................................................................................................. ............... 52 12.3.12 at 33 mhz (1-3-1-1-1) .................................................................................................. ............... 52 12.3.13 at 33 mhz (1-3-1-1-1-1-1-1-1) .......................................................................................... ........... 53 12.3.14 at 33 mhz (1-3-1-1-1-1-1-1-1) .......................................................................................... ........... 53 12.3.15 burst stop ............................................................................................................. ................ 54 12.3.16 clock suspend and power down ................................................................................... 54 12.4 command combination examples .............................................................................................. .......... 55 12.4.1 row activate - read (1) ................................................................................................. ..... 55 12.4.2 row activate - read (2) ................................................................................................. ..... 55 12.4.3 row activate - read (3) ................................................................................................. ..... 56 12.4.4 row activate - read (4) ................................................................................................. ..... 56 12.4.5 row activate - read (5) ................................................................................................. ..... 57 data sheet m13945ej5v0ds 6 pd23c64202l 12.4.6 row activate - row activate .......................................................................................... 57 12.4.7 read - read (1) ......................................................................................................... .............. 58 12.4.8 read - read (2) ......................................................................................................... .............. 58 12.4.9 read - read (3) ......................................................................................................... .............. 59 12.4.10 read suspend (1) ....................................................................................................... ........... 60 12.4.11 read suspend (2) ....................................................................................................... ........... 60 12.4.12 burst stop (1) ......................................................................................................... ............... 61 12.4.13 burst stop (2) ......................................................................................................... ............... 61 12.4.14 clock suspend .......................................................................................................... ........... 62 12.4.15 power down ............................................................................................................. ............. 62 12.4.16 row activate - read (1) ................................................................................................ ...... 63 12.4.17 row activate - read (2) ................................................................................................ ...... 63 12.4.18 row activate - read (3) ................................................................................................ ...... 64 12.4.19 row activate - read (4) ................................................................................................ ...... 64 12.4.20 row activate - read (5) ................................................................................................ ...... 65 12.4.21 row activate - row activate .......................................................................................... 6 5 12.4.22 read - read (1) ........................................................................................................ ............... 66 12.4.23 read - read (2) ........................................................................................................ ............... 66 12.4.24 read - read (3) ........................................................................................................ ............... 67 12.4.25 read suspend (1) ....................................................................................................... ........... 68 12.4.26 read suspend (2) ....................................................................................................... ........... 68 12.4.27 burst stop (1) ......................................................................................................... ............... 69 12.4.28 burst stop (2) ......................................................................................................... ............... 69 12.4.29 clock suspend .......................................................................................................... ........... 70 12.4.30 power down ............................................................................................................. ............. 70 12.4.31 row activate - read (1) ................................................................................................ ...... 71 12.4.32 row activate - read (2) ................................................................................................ ...... 71 12.4.33 row activate - read (3) ................................................................................................ ...... 72 12.4.34 row activate - read (4) ................................................................................................ ...... 72 12.4.35 row activate - read (5) ................................................................................................ ...... 73 12.4.36 row activate - row activate .......................................................................................... 7 3 12.4.37 read - read (1) ........................................................................................................ ............... 74 12.4.38 read - read (2) ........................................................................................................ ............... 74 12.4.39 read - read (3) ........................................................................................................ ............... 75 12.4.40 read suspend (1) ....................................................................................................... ........... 76 12.4.41 read suspend (2) ....................................................................................................... ........... 76 12.4.42 burst stop (1) ......................................................................................................... ............... 77 12.4.43 burst stop (2) ......................................................................................................... ............... 77 12.4.44 clock suspend .......................................................................................................... ........... 78 12.4.45 power down ............................................................................................................. ............. 78 13. package drawing ............................................................................................................ ................. 79 14. recommended soldering condition ............................................................................................ . 80 data sheet m13945ej5v0ds 7 pd23c64202l 1. input / output pin functions (1/2) pin name input / output function clk (clock input) input clk is the master clock input. other inputs signals are referenced to the clk rising edge. cke (clock enable input) input cke determine validity of the next clk (clock). if cke is high, the next clk rising edge is valid; otherwise, it is invalid. if the clk rising edge is invalid, the internal clock is not issued and this device suspends operation. when this device is not in burst mode and cke is negated, the device enters power down mode. during power down or read suspend mode, cke must remain low. /cs (chip select) input command control signal. for details, refer to 4.2 command truth table . /cs low starts the command input cycle. when /cs is high, commands are ignored but operations continue. /ras (row address strobe) input command control signal. for details, refer to 4.2 command truth table . row address is determined by a0 - a12 at the clk (clock) rising edge in the row activate command cycle. /cas (column address strobe) input command control signal. for details, refer to 4.2 command truth table . column address is determined by a0 - a8 at the clk rising edge in the read command cycle. column address is used differently in the word mode and the double word mode, respectively. word mode (4m words by 16 bits) column address : a0 - a8 double word mode (2m words by 32 bits) column address : a0 - a7 /mr (mode register enable) input command control signal. for details, refer to 4.2 command truth table . /word (mode select) input the pin for switching word mode and double word mode. low level : word mode (4m words by 16 bits) high level : double word mode (2m words by 32 bits) a0 - a12 (address inputs) input address input pins. a0 - a12 are used differently in the word mode and the double word mode, respectively. word mode (4m words by 16 bits) row address : a0 - a12 column address : a0 - a8 double word mode (2m words by 32 bits) row address : a0 - a12 column address : a0 - a7 also they are used as command control signal. for details, refer to 4.2 command truth table . o0 - o15, o16 - o31 (data outputs) output data output pins. o0 - o15, o16 - o31 are used differently in the word mode and the double word mode, respectively. word mode (4m words by 16 bits) 16 bits data outputs to o0 - o15, and o16 - o31 are hi-z. double word mode (2m words by 32 bits) 32 bits data outputs to o0 - o31. dqm (dq mask enable) input dqm controls the output buffers like the /oe pin of an asynchronous mask rom. dqm high and dqm low turn the output buffers off and on, respectively. dqm latency is 2 clocks. data sheet m13945ej5v0ds 8 pd23c64202l (2/2) pin name input / output function v cc (supply voltage) ? power supply pin for internal circuits. v cc q (supply voltage) ? power supply pin for the output buffers. v ss (ground) ? ground pin for internal circuits. v ss q (ground) ? ground pin for the output buffers. nc (no connection) ? not internally connected (the signal can be applied). ic (internal connection) ? internally connected (leave this pin unconnected or connect to gnd). data sheet m13945ej5v0ds 9 pd23c64202l 2. simplified state diagram cke cke act idle active active power down power on automatic sequence manual input read cke cke read suspend cke cke power down read act read bst mrs mode register set mrs data sheet m13945ej5v0ds 10 pd23c64202l 3. commands 3.1 mode register set (mrs) this device has a mode register that defines how the device operates. in this command, a0 through a6 are the data input pins. after power on, the mode register set command must be executed to initialize the device. during 2 clocks (t rsc ) following this command, this device cannot accept any other commands. figure of mode register set (mrs) /mr /cas /ras /cs cke clk h address l l l l 3.2 row activate (act) this command activates a row address selected by a0 - a12. figure of row activate (act) /mr /cas /ras /cs cke clk h address l l h row h 3.3 read (read) read data is available after /cas latency requirements have been met. this command sets the burst start address given by the column address. figure of read (read) /mr /cas /ras /cs cke clk h address l l col h h 3.4 burst stop (bst) this command terminates the current burst operation. figure of burst stop (bst) (standard) (sdram-precharge-like) /mr /cas /ras /cs cke clk h address l h h l /mr /cas /ras /cs cke clk h address l l h l data sheet m13945ej5v0ds 11 pd23c64202l 4. truth table 4.1 clock enable and command /cs /ras /cas /mr address cke clk h n ? 1 n n+1 command 4.2 command truth table function symbol cke /cs /ras /cas /mr dqm a0 - a12 /word n ? 1n mode register set mrs h llll code row activate act h llhh ra read read h lhlh ca burst stop standard bst h lhhl sdram- precharge-like h llhl power down entry pwdn h l exit l h dqm read h v no operation nop h h h lhhh organization control ? h lhlh ca h or l illegal (sdram write) ? h lhll ca (sdram refresh) ? h lllh remark h : high level l : low level : don't care (high or low level) v : valid data input ra : row address ca : column address data sheet m13945ej5v0ds 12 pd23c64202l 4.3 operative command table current state cke /cs /ras /cas /mr address command action idle l pwdn power down (power-on or hlllla0 - a6mrsm ode register accessing mode register set) h l l h h ra act row activating h l h l h ca read illegal (ignored) hlhhl bst no operation hllhl active l ? clock suspend hlllla0 - a6mrsm ode register accessing h l l h h ra act row activating h l h l h ca read read start hlhhl bst illegal (ignored) hllhl read l ? clock suspend / power down hlllla0 - a6mrsm ode register accessing h l l h h ra act row activating h l h l h ca read next read start hlhhl bst burst stop hllhl any state h l h l l ca ? illegal hlllh ? illegal hh nop no operation hlhhh nop no operation remark h : high level l : low level : don't care (high level or low level) v : valid data input ra : row address ca : column address data sheet m13945ej5v0ds 13 pd23c64202l 5. mode register settings /cs cke clk h a1 l a0 a3 a2 a5 a4 /ras l /cas l /mr l a6 a0 a1 a2 a3 a4 a5 a6 burst length 4 8 a1 0 0 1 1 a0 0 1 0 1 burst length wrap type sequential interleave a2 0 1 wrap type /cas latency 3 4 5 6 a5 0 0 0 0 1 1 1 1 a3 0 1 0 1 0 1 0 1 /cas latency a4 0 0 1 1 0 0 1 1 /ras latency 1 2 a6 0 1 /ras latency remark : inhibited lower 2 or 3 bits of column address indicate starting column address of burst read. 0 00 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 0 1 0 2 3 4 5 6 7 0 1 0 1 1 3 4 5 6 7 0 1 2 1 0 0 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 1 1 0 6 7 0 1 2 3 4 5 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 starting column address sequential interleave 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 a2 a1 a0 0 0 0 1 2 3 0 1 1 2 3 0 1 0 2 3 0 1 1 1 3 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0 burst length 4 8 burst sequence addressing sequence 4 32 10 column address burst length = 4 burst length = 8 data sheet m13945ej5v0ds 14 pd23c64202l 6. word modes 6.1 addressing map (word mode) row address column address address bits 19 18 17 16 15 14 13 12 11 10 98 7 65 4 32 10 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a12 11 10 98 7 65 4 32 10 12 5 4 32 10 6 msb lsb 21 7 20 8 6.2 data output (word mode) when /word is set to low level, the device is set to word mode and 16-bit data will be output. clk command /word read /cas latency = 6, burst length = 4 a8 o0 - o15 hi-z o16 - o31 hi-z q0 q1 q2 q3 data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bits data o14 o15 o12 o13 o10 o11 o8 o9 o7 o4 o6 o2 o3 o0 o1 0 o6 a8 = low level lower 16 bits data will be output a8 = high level upper 16 bits data will be output data outputs 0 data 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 data 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 data 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 data outputs 1 data outputs 2 data outputs 3 data sheet m13945ej5v0ds 15 pd23c64202l 6.3 addressing map (double word mode) row address column address address bits 19 18 17 16 15 14 13 12 11 10 98 7 65 4 32 10 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a12 11 10 98 7 65 4 32 10 12 msb lsb 5 4 32 10 6 20 7 6.4 data output (double word mode) when /word is set to high level, the device is set to double word mode and 32-bit data will be output. clk command /word read /cas latency = 6, burst length = 4 a8 o0 - o15 hi-z o16 - o31 hi-z q0 q1 q2 q0 q1 q2 q3 q3 data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bits data o14 o15 o12 o13 o10 o11 o8 o9 o7 o4 o6 o2 o3 o0 o1 0 o6 data outputs 0 data 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 data 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 data 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 data outputs 1 data outputs 2 data outputs 3 o30 o31 o28 o29 o26 o27 o24 o25 o23 o20 o22 o18 o19 o16 o17 o21 data sheet m13945ej5v0ds 16 pd23c64202l 7. relationship between clock frequency and /ras latency, /cas latency clock frequency (clock cycle time) /ras latency (min.) /cas latency (min.) data output cycle 33 mhz (30 ns) 1 3 1 50 mhz (20 ns) 1 4 1 66 mhz (15 ns) 2 5 1 83 mhz (12 ns) 2 5 1 100 mhz (10 ns) 2 5 1 act read 12 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 12 3 4 clk command oq /cas latency /ras latency hi-z 66 mhz (15 ns) act 1 t0 t1 t2 t3 12 3 clk command oq /cas latency hi-z 50 mhz (20 ns) t4 t5 t6 t7 t8 t9 t10 t11 read 1 t0 t1 t2 t3 1 clk command oq /cas latency hi-z 33 mhz (30 ns) t4 t5 t6 t7 read act 23 /ras latency /ras latency 1 data output cycle 1 data output cycle data output cycle 1 4 5 data sheet m13945ej5v0ds 17 pd23c64202l 12 t0 clk command oq /cas latency hi-z 83 mhz (12 ns) t1 t2 t3 t4 t5 t6 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 12 345 1 2 t0 clk command oq /cas latency hi-z 100 mhz (10 ns) t1 act read t4 t5 t2 t3 t8 t9 t6 t7 t12 t13 t10 t11 t16 t17 t14 t15 t20 t21 t18 t19 t22 t23 12 345 /ras latency /ras latency act read data output cycle data output cycle 1 1 data sheet m13945ej5v0ds 18 pd23c64202l 8. command interval 8.1 relationship between frequency, parameter and command interval frequency (t ck )burst length /ras latency /cas latency read to read command interval read to row activate command interval (min.) unit (min.) t ccd (min.) read data is not terminated read data is terminated 100 mhz (10 ns) 4 2 5 4 4 4 clk 65 5 5 85884 69 9 5 83 mhz (12 ns) 4 2 5 4 4 4 clk 65 5 5 85884 69 9 5 66 mhz (15 ns) 4 2 5 4 4 4 clk 65 5 5 85884 69 9 5 50 mhz (20 ns) 4 1 4 3 3 3 clk 54 4 4 65 5 5 84773 58 8 4 69 9 5 33 mhz (30 ns) 4 1 3 2 2 2 clk 43 3 3 54 4 4 65 5 5 83662 47 7 3 58 8 4 69 9 5 data sheet m13945ej5v0ds 19 pd23c64202l 8.2 read to read command interval (t ccd ) a minimum of t ccd interval is required between two read commands. for details, refer to 8.1 relationship between frequency, parameter and command interval . clk oq /cas latency = 3, burst length = 4 reada qa0 qa1 qb0 qb1 command readb t ccd (min.) = 2 clocks clk oq /cas latency = 4, burst length = 4 reada qa0 qa1 qa2 qb0 command readb t ccd (min.) = 3 clocks qb2 qb3 qb1 qb2 qb3 clk oq /cas latency = 5, burst length = 4 reada qa0 qa1 qa2 qb0 command readb t ccd (min.) = 4 clocks qb1 qb2 qb3 qa3 clk oq /cas latency = 6, burst length = 4 reada qa0 qa1 qa2 qb0 command readb t ccd (min.) = 5 clocks qb1 qb2 qb3 qa3 data sheet m13945ej5v0ds 20 pd23c64202l clk oq /cas latency = 3, burst length = 8 reada qa0 qa1 qa2 qa3 command readb t ccd (min.) = 6 clocks qa5 qb0 qb1 qb2 qa4 qb3 qb4 qb5 qb6 qb7 clk oq /cas latency = 4, burst length = 8 reada qa0 qa1 qa2 qa3 command readb t ccd (min.) = 7 clocks qa5 qb0 qb1 qb2 qa4 qb3 qb4 qb5 qb6 qb7 qa6 clk oq /cas latency = 5, burst length = 8 reada qa0 qa1 qa2 qa3 command readb t ccd (min.) = 8 clocks qa5 qa7 qb0 qb1 qa4 qb2 qb3 qb4 qa6 qb5 clk oq /cas latency = 6, burst length = 8 reada qa0 qa1 qa2 qa3 command readb t ccd (min.) = 9 clocks qa5 qa7 qb0 qb1 qa4 qb2 qb3 qa6 data sheet m13945ej5v0ds 21 pd23c64202l 8.3 read to row activate command interval an interval required between read and row activate command differs according to whether burst data is terminated or not, before the row activate command. a. read data not terminated when read data is not terminated before the row activate command, a required interval is as shown in 8.1 relationship between frequency, parameter and command interval . clk oq /cas latency = 3, burst length = 4 read q0 q1 q2 q3 commands act 2 clocks (min.) clk oq /cas latency = 4, burst length = 4 read q0 q1 q2 q3 command act 3 clocks (min.) clk oq /cas latency = 5, burst length = 4 read q0 q1 q2 q3 command act 4 clocks (min.) clk oq /cas latency = 6, burst length = 4 read q0 q1 q2 q3 command act 5 clocks (min.) data sheet m13945ej5v0ds 22 pd23c64202l clk oq /cas latency = 3, burst length = 8 read q0 q1 q2 q3 command act 6 clocks (min.) q5 q6 q7 q4 clk oq /cas latency = 4, burst length = 8 read q0 q1 q2 q3 command act 7 clocks (min.) q5 q7 q4 q6 clk oq /cas latency = 5, burst length = 8 read q0 q1 q2 q3 command act 8 clocks (min.) q5 q7 q4 q6 clk oq /cas latency = 6, burst length = 8 read q0 q1 q2 q3 command act 9 clocks (min.) q5 q7 q4 q6 data sheet m13945ej5v0ds 23 pd23c64202l b. read data terminated when read data is terminated before the row activate command, a required interval is one clock less than /cas latency. for details, refer to 8.1 relationship between frequency, parameter and command interval . clk oq /cas latency = 3, burst length = 4, 8 reada qa0 command act 2 clocks (min.) clk oq /cas latency = 4, burst length = 4, 8 reada qa0 command act 3 clocks (min.) bst bst clk oq /cas latency = 5, burst length = 4, 8 reada qa0 command act 4 clocks (min.) bst clk oq /cas latency = 6, burst length = 4, 8 reada qa0 command act bst 5 clocks (min.) data sheet m13945ej5v0ds 24 pd23c64202l 8.4 read to burst stop command interval a minimum of one-clock interval is required between read and burst stop command. clk command act /cas latency = 3, burst length = 4 oq hi-z 1 clock (min.) read bst q0 8.5 row activate to row activate command interval a minimum of one-clock interval is required between two row activate command. however, t rc is required between two row activate command for valid data output. see 12.1 relationship between frequency and parameter for details. clk command acta /cas latency = 3, burst length = 4 oq hi-z qb0 qb1 qb2 qb3 1 clock (min.) actb readb data sheet m13945ej5v0ds 25 pd23c64202l 9. power-on sequence this device must be powered-on in a manner as follows. ? cke and dqm must be held at high level on power-on. ? ? ? ? on power-on, the mode register is set to default values; /ras latency is set to 2, /cas latency to 6, burst length to 4 and wrap type to sequential. to change these values, mode register set command is required. ? ? ? ? in order to keep all outputs to hi-z until the mode register set command is finished, dqm must be held at high level. clk cke /ras /cs /mr a0 - a6 dqm /cas hi-z h oq a7 - a12 h t rsc (min.) 2 clocks mode register set command row activate command code note note for details of input code, refer to 5. mode register settings . data sheet m13945ej5v0ds 26 pd23c64202l 10. basic operations 10.1 mode register set command a minimum of 2 clocks are required between mode register set command and others. clk command hi-z oq t rsc = 2 clocks (min.) act mrs 10.2 dqm operation read data can be masked by setting dqm high level as follows. clk command oq (/cas latency = 3) masked by dqm after 2 clocks read oq (/cas latency = 4) oq (/cas latency = 6) hi-z hi-z q0 q3 q0 q1 q2 q1 hi-z hi-z hi-z /cas latency = 3, 4, 5, 6, burst length = 4 dqm oq (/cas latency = 5) hi-z q0 q2 q3 hi-z hi-z q1 q2 q3 10.3 burst termination during a read cycle, when the burst stop command is issued, the burst read data will be terminated and the data bus will be hi-z after the /cas latency. at least one-clock interval is required between read and burst stop command regardless of the /cas latency. clk command oq (/cas latency = 3) read hi-z hi-z hi-z /cas latency = 3, 4, 5, 6, burst length = 4 or 8 oq (/cas latency = 4) oq (/cas latency = 6) bst note hi-z hi-z hi-z hi-z hi-z q0 q2 q0 q1 q2 q0 q1 q2 q1 q0 q1 q2 oq (/cas latency = 5) note both standard and sdram-precharge-like types of the burst stop command can be used. data sheet m13945ej5v0ds 27 pd23c64202l 10.4 power down and clock suspend mode operation modes of this device is shown as follows. refer to 2. simplified state diagram for details. clk command oq idle act q0 q1 hi-z /cas latency = 3, burst length = 4 read q2 read active q3 active 10.4.1 power down mode when cke is held at low level in the idle state, the device will turn to the power down (standby) mode. clk command cke nop internal clk oq hi-z power down act command input accepted remark once the device had turned to the power down mode, row activate command is necessary in order to read data. 10.4.2 read suspend and active power down mode when cke is held at low level in read mode, the device will turn to the read suspend (active standby) mode. when cke is held at low level in active mode, the device will turn to the active power down (active standby) mode. clk command cke read /cas latency = 3, burst length = 4 internal clk oq hi-z q1 q3 q2 q0 active power down read suspend data sheet m13945ej5v0ds 28 pd23c64202l 11. electrical specifications absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc ? 0.5 note to +4.6 v voltage on any pin relative to gnd v t ? 0.5 note to v cc + 0.5 v, +4.6 v short circuit output current i o 50 ma power dissipation p d 1w operating ambient temperature t a 0 to 70 c storage temperature t stg ? 55 to +150 c note ? 1.0 v (min.) : 10 ns pulse width measured at 50% of pulse amplitude. caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc +0.3 note1 v low level input voltage v il ? 0.3 note2 +0.8 v operating ambient temperature t a 070 c notes 1. v cc + 0.5 v (max.) : 10 ns pulse width measured at 50% of pulse amplitude. 2. ? 0.5 v (min.) : 10 ns pulse width measured at 50% of pulse amplitude. capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i all input pins 5 pf output capacitance c o all output pins 7 pf data sheet m13945ej5v0ds 29 pd23c64202l dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition min. max. unit note standby current i cc3 p cke v il (max.) , t ck = 10 ns 3 ma in power down mode i cc3 ps cke = 0 v, t ck = 10 ns 100 a active standby current i cc3 n cke v ih (min.) , t ck = 10 ns, /cs v ih (min.) ,50ma in non power down mode input signals are changed one time during 10 ns. i cc3 ns cke v ih (min.) , t ck = ,10 input signals are stable. operating current (burst mode) i cc4 t ck = 10 ns, i o = 0 ma, /cas latency = 5 150 ma 1 input leakage current i i (l) v i = 0 to 3.6 v, all other pins not under test = 0 v ? 10 +10 a output leakage current i o (l) d out is disabled, v o = 0 to 3.6 v ? 10 +10 a high level output voltage v oh i o = ? 2.0 ma 2.4 v low level output voltage v ol i o = +2.0 ma 0.4 v note 1. i cc4 depends on output loading and cycle rates. specified values are obtained with output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck (min.) . data sheet m13945ej5v0ds 30 pd23c64202l ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions ? ac measurements assume t t = 1 ns. ? reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . ? if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih (min.) and v il (max.) . ? an access time is measured at 1.4 v. t ck t ch t cl 2.4 v 1.4 v 0.4 v clk 2.4 v 1.4 v 0.4 v input t setup t hold output t ac t oh 1.4 v 1.4 v output load output z = 50 ? 1.4 v 50 pf 50 ? asynchronous characteristics parameter symbol 100 mhz 83 mhz 66 mhz 50 mhz 33 mhz unit min. max. min. max. min. max. min. max. min. max. mode register set time t rsc 22222clock /ras to /cas delay time (/ras latency) t rcd 20 24 30 20 30 ns transition time t t 0.1 10.0 0.1 10.0 0.1 10.0 0.1 10.0 0.1 10.0 ns data sheet m13945ej5v0ds 31 pd23c64202l synchronous characteristics parameter symbol 100 mhz 83 mhz 66 mhz 50 mhz 33 mhz unit note min. max. min. max. min. max. min. max. min. max. clock cycle time t ck 10 12 15 20 30 ns access time from clk t ac 68999ns clk high level width t ch 44444ns clk low level width t cl 44444ns data-out hold time t oh 2.5 2.5 2.5 2.5 2.5 ns data-out low-z time t lz 00000ns data-out hi-z time t hz 2.562.582.592.592.59 ns address setup time t as 33444ns address hold time t ah 11222ns cke setup time t cks 33444ns cke hold time t ckh 11222ns cke setup time (power down exit) t cksp 4+t ck 4+t ck 4+t ck 4+t ck 4+t ck ns command setup time (/cs, /ras, /cas, /mr, /word) t cms 33444ns command hold time (/cs, /ras, /cas, /mr, /word) t cmh 11222ns ac parameters for read timing clk /cas latency = 5, burst length = 4 cke /ras /cs /mr address /word t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 /cas t cks t ch t ck t cl t cms t cmh t as t ah hi-z t ac t ac t oh t lz t hz t oh t rcd h t ckh oq t cms t cmh data sheet m13945ej5v0ds 32 pd23c64202l 12. timing charts 12.1 relationship between frequency and parameter frequency (t ck ) /ras latency (min.) /cas latency burst length t rc (min.) note1 t ccd (min.) note2 unit 100 mhz (10 ns) 2 5 4 6 4 clk 675 58108 6119 83 mhz (12 ns) 2 5 4 6 4 clk 675 58108 6119 66 mhz (15 ns) 2 5 4 6 4 clk 675 58108 6119 50 mhz (20 ns) 1 4 4 4 3 clk 554 665 4887 598 6109 33 mhz (30 ns) 1 3 4 3 2 clk 443 554 665 3876 487 598 6109 notes 1. t rc : act to act command period 2. t ccd : read to read command period data sheet m13945ej5v0ds 33 pd23c64202l 12.1.1 row activate - read - row activate - read (1-1) clk command at 100, 83, 66 mhz /ras latency = 2, /cas latency = 6, burst length = 4 invalid case case 1 case 2 readb readb readb qa0 qa1 qa2 qa3 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb1 qb0 qb0 qa1 qa3 reada invalid case case 2 case 1 invalid data act act act act t rc = 7 qb3 qb2 12.1.2 row activate - read - row activate - read (1-2) clk command at 100, 83, 66 mhz /ras latency = 2, /cas latency = 5, burst length = 4 invalid case case 1 case 2 readb readb readb qa0 qa1 qa2 qa3 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qb1 qb2 qb3 qb0 qb0 qa1 qa3 reada invalid case case 2 case 1 invalid data act act act act t rc = 6 12.1.3 row activate - read - row activate - read (2-1) clk command at 50, 33 mhz /ras latency = 1, /cas latency = 6, burst length = 4 invalid case case 1 case 2 readb qa0 qa1 qa2 qa3 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qb1 qb2 qb0 qb0 qa1 qa3 reada invalid case case 2 case 1 invalid data act act t rc = 6 readb act readb act qb3 data sheet m13945ej5v0ds 34 pd23c64202l 12.1.4 row activate - read - row activate - read (2-2) clk command at 50, 33 mhz /ras latency = 1, /cas latency = 5, burst length = 4 invalid case case 1 case 2 readb qa0 qa1 qa2 qa3 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qb1 qb2 qb0 qb0 qa1 qa3 reada invalid case case 2 case 1 invalid data act act t rc = 5 readb act readb act qb3 12.1.5 row activate - read - row activate - read (2-3) clk command at 50, 33 mhz /ras latency = 1, /cas latency = 4, burst length = 4 invalid case case 1 case 2 readb qa0 qa1 qa2 qa3 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qb1 qb2 qb0 qb0 qa1 qa3 reada invalid case case 2 case 1 act act t rc = 4 readb act readb act qb3 invalid data 12.1.6 row activate - read - row activate - read (2-4) clk command at 33 mhz /ras latency = 1, /cas latency = 3, burst length = 4 invalid case case 1 case 2 readb qa0 qa1 qa2 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qb1 qb2 qb0 qb0 qa1 reada invalid case case 2 case 1 invalid data act t rc = 3 readb act readb act qb3 qa3 act data sheet m13945ej5v0ds 35 pd23c64202l 12.1.7 row activate - read - row activate - read (3-1) clk command at 100, 83, 66 mhz /ras latency = 2, /cas latency = 6, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb readb qa0 qa1 qa2 qa3 qa0 qa2 qa1 qa3 reada invalid case 1 case 2 invalid case 2 invalid data act act act act t rc = 11 case 2 qa0 qa2 qa1 qa3 readb act case 1 qa5 qa4 qa6 qa7 qa5 qa4 qa6 qa7 qb0 qb2 qb1 qb1 qb0 qb0 qb0 qb2 qb1 qb3 qb5 qb4 qb6 12.1.8 row activate - read - row activate - read (3-2) clk command at 100, 83, 66 mhz /ras latency = 2, /cas latency = 5, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb readb qa0 qa1 qa2 qa3 qa0 qa2 qb1 qb0 qb0 qa1 qa3 reada invalid case 1 case 2 invalid case 2 invalid data act act act act t rc = 10 case 2 qa0 qa2 qb0 qa1 qa3 readb act case 1 qb2 qb1 qa5 qa4 qa6 qa7 qa5 qa4 qa6 qa7 qb0 qb2 qb1 qb3 qb5 qb4 qb6 12.1.9 row activate - read - row activate - read (4-1) clk command at 50, 33 mhz /ras latency = 1, /cas latency = 6, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb qa1 qa2 qa3 qa0 qa2 qa1 qa3 reada case 2 invalid case 2 invalid data act act act t rc = 10 case 2 qa0 qa2 qa1 qa3 readb act case 1 qa5 qa4 qa6 qa7 qa5 qa4 qa6 qa7 readb act qb0 qb2 qb1 qb0 qb1 qb0 qb0 qb2 qb3 qb5 qb4 qb1 qb6 qa0 invalid case 1 data sheet m13945ej5v0ds 36 pd23c64202l 12.1.10 row activate - read - row activate - read (4-2) clk command at 50, 33 mhz /ras latency = 1, /cas latency = 5, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb qa1 qa2 qa3 qa0 qa2 qa1 qa3 reada case 2 invalid case 2 invalid data act act act t rc = 9 case 2 qa0 qa2 qa1 qa3 readb act case 1 qa5 qa4 qa6 qa7 qa5 qa4 qa6 qa7 readb act qb0 qb2 qb1 qb3 qb4 qb0 qb1 qb2 qb1 qb0 qb0 qb2 qb3 qb5 qb4 qb1 qb7 qb6 qa0 qb2 qb3 invalid case 1 12.1.11 row activate - read - row activate - read (4-3) clk command at 50, 33 mhz /ras latency = 1, /cas latency = 4, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb qa1 qa2 qa3 qa0 qa2 qa1 qa3 reada case 2 invalid case 2 invalid data act act act t rc = 8 case 2 qa0 qa2 qa1 qa3 readb act case 1 qa5 qa4 qa6 qa7 qa5 qa4 qa6 qa7 readb act qb0 qb2 qb1 qb3 qb5 qb4 qb0 qb1 qb2 qb1 qb3 qb4 qb0 qb0 qb2 qb3 qb5 qb4 qb1 qb7 qb6 qa0 qb6 qb2 qb3 qb5 qb4 invalid case 1 12.1.12 row activate - read - row activate - read (4-4) clk command at 33 mhz /ras latency = 1, /cas latency = 3, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb qa1 qa2 qa3 qa0 qa2 qa1 qa3 reada case 2 invalid case 2 invalid data act act act t rc = 7 case 2 qa0 qa2 qa1 qa3 readb act case 1 qa5 qa4 qa6 qb7 qa5 qa4 qa6 qa7 readb act qb0 qb2 qb3 qb5 qb4 qb1 qb6 qa0 invalid case 1 qb7 qb0 qb2 qb3 qb5 qb4 qb1 qb6 qb0 qb2 qb3 qb5 qb4 qb1 qb6 qb0 qb2 qb3 qb5 qb4 qb1 qb6 qa7 data sheet m13945ej5v0ds 37 pd23c64202l 12.1.13 row activate - read - read (1-1) clk command at 100, 83, 66 mhz /ras latency = 2, /cas latency = 6, burst length = 4 invalid case case 1 case 2 readb qa0 qa1 qa2 qa3 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qb1 qb2 qb0 qb0 qa1 qa3 reada invalid case case 2 case 1 invalid data act t ccd = 5 readb readb qb3 12.1.14 row activate - read - read (1-2) clk command at 100, 83, 66 mhz /ras latency = 2, /cas latency = 5, burst length = 4 invalid case case 1 case 2 readb qa0 qa1 qa2 qa3 qa0 qa2 qb1 qb2 qb0 qb1 qb2 qb3 qb1 qb2 qb0 qb0 qa1 qa3 reada invalid case case 2 case 1 invalid data act t ccd = 4 readb readb qb3 qb3 12.1.15 row activate - read - read (2-1) clk command invalid case case 1 case 2 readb qa0 qa1 qa2 qa3 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qb1 qb2 qb0 qb0 qa1 qa3 reada invalid case case 2 case 1 invalid data act t ccd = 5 readb readb qb3 at 50, 33 mhz /ras latency = 1, /cas latency = 6, burst length = 4 data sheet m13945ej5v0ds 38 pd23c64202l 12.1.16 row activate - read - read (2-2) clk command invalid case case 1 case 2 readb qa0 qa1 qa2 qa3 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qb1 qb2 qb0 qb0 qa1 qa3 reada invalid case case 2 case 1 invalid data act t ccd = 4 readb readb qb3 at 50, 33 mhz /ras latency = 1, /cas latency = 5, burst length = 4 12.1.17 row activate - read - read (2-3) clk command invalid case case 1 case 2 readb qa0 qa1 qa2 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qb1 qb2 qb0 qb0 qa1 qa3 reada invalid case case 2 case 1 invalid data act t ccd = 3 readb readb qb3 at 50, 33 mhz /ras latency = 1, /cas latency = 4, burst length = 4 12.1.18 row activate - read - read (2-4) clk command invalid case case 1 case 2 qa0 qa1 qa0 qa2 qb1 qb2 qb3 qb0 qb1 qb2 qb3 qb1 qb2 qb0 qb0 qa1 reada invalid case case 2 case 1 invalid data act readb readb qb3 at 33 mhz /ras latency = 1, /cas latency = 3, burst length = 4 t ccd = 2 readb data sheet m13945ej5v0ds 39 pd23c64202l 12.1.19 row activate - read - read (3-1) clk command at 100, 83, 66 mhz /ras latency = 2, /cas latency = 6, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb qa1 qa2 qa3 qa0 qa2 qa1 qa3 reada case 2 invalid case 2 invalid data act t ccd = 9 case 2 qa0 qa2 qa1 qa3 readb case 1 qa5 qa4 qa6 qa7 qa5 qa4 qa6 qa7 readb qb0 qb2 qb1 qb0 qb1 qb0 qb0 qb2 qb3 qb5 qb4 qb1 qb6 qa0 invalid case 1 12.1.20 row activate - read - read (3-2) clk command at 100, 83, 66 mhz /ras latency = 2, /cas latency = 5, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb qa1 qa2 qa3 qa0 qa2 qa1 qa3 reada case 2 invalid case 2 invalid data act t ccd = 8 case 2 qa0 qa2 qa1 qa3 readb case 1 qa5 qa4 qa6 qa7 qa5 qa4 qa6 qa7 readb qb0 qb2 qb1 qb3 qb4 qb0 qb1 qb2 qb1 qb0 qb0 qb2 qb3 qb5 qb4 qb1 qb7 qb6 qa0 qb2 qb3 invalid case 1 12.1.21 row activate - read - read (4-1) clk command at 50, 33 mhz /ras latency = 1, /cas latency = 6, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb qa1 qa2 qa3 reada case 2 invalid case 2 invalid data act t ccd = 9 case 2 qa0 qa2 qa1 qa3 readb case 1 qa5 qa4 qa6 qa7 qb0 qb2 qb3 qb5 qb4 qb1 qb6 qa0 invalid case 1 qb7 qb0 qb2 qb3 qb1 readb qb1 qb0 qb2 qb1 qb0 qa0 qa2 qa1 qa3 qa5 qa4 qa6 qa7 data sheet m13945ej5v0ds 40 pd23c64202l 12.1.22 row activate - read - read (4-2) clk command at 50, 33 mhz /ras latency = 1, /cas latency = 5, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb qa1 qa2 qa3 reada case 2 invalid case 2 invalid data act t ccd = 8 case 2 qa0 qa2 qa1 qa3 readb case 1 qa5 qa4 qa6 qa7 qb0 qb2 qb3 qb5 qb4 qb1 qb6 qa0 invalid case 1 qb7 qb0 qb2 qb3 qb5 qb4 qb1 readb qb2 qb3 qb1 qb0 qb2 qb3 qb4 qb1 qb0 qa0 qa2 qa1 qa3 qa5 qa4 qa6 qa7 12.1.23 row activate - read - read (4-3) clk command at 50, 33 mhz /ras latency = 1, /cas latency = 4, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb qa1 qa2 qa3 reada case 2 invalid case 2 invalid data act case 2 qa0 qa2 qa1 qa3 readb case 1 qa5 qa4 qa6 qa7 qb0 qb2 qb3 qb5 qb4 qb1 qb6 qa0 invalid case 1 qb7 qb0 qb2 qb3 qb5 qb4 qb1 readb qb2 qb3 qb1 qb0 qb2 qb3 qb4 qb1 qb0 qa0 qa2 qa1 qa3 qa5 qa4 qa6 qb6 qb5 qb4 t ccd = 7 qb7 qb6 qb5 12.1.24 row activate - read - read (4-4) clk command at 33 mhz /ras latency = 1, /cas latency = 3, burst length = 8 invalid case 1 invalid case 2 case 1 readb readb qa1 qa2 qa3 qa0 qa2 qa1 qa3 reada case 2 invalid case 2 invalid data act t ccd = 6 case 2 qa0 qa2 qa1 qa3 readb case 1 qa5 qa4 qa5 qa4 qa6 qb2 qb3 qb5 qb4 qb1 qb6 qa0 invalid case 1 qb7 readb qb2 qb3 qb5 qb4 qb1 qb0 qb2 qb3 qb5 qb4 qb1 qb6 qb0 qb0 qb0 qb2 qb3 qb5 qb4 qb1 qb6 qb7 qb7 qb6 qb7 data sheet m13945ej5v0ds 41 pd23c64202l 12.2 random row read timing 12.2.1 at 100 mhz (2-5-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq t rc t rc = 6 (burst length = 4) 4 clocks (min.) are necessary between read and act ca0 /ras latency = 2, /cas latency = 5, burst length = 4 act read act read act read ra0 ra0 cb0 rb0 rb0 cc0 rc0 rc0 h h hi-z qa0 qa2 qa3 qb0 qb1 qb2 qb3 qa1 qc0 qc1 qc2 qc3 12.2.2 at 100 mhz (2-5-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qa3 t rc t rc = 10 (burst length = 8) qa1 ca0 /ras latency = 2, /cas latency = 5, burst length = 8 act read act read ra0 ra0 cb0 rb0 rb0 qa4 qa6 qa7 qa5 h h hi-z qb0 qb2 qb3 qb1 qb4 qb6 qb5 data sheet m13945ej5v0ds 42 pd23c64202l 12.2.3 at 83 mhz (2-5-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq t rc t rc = 6 (burst length = 4) 4 clocks (min.) are necessary between read and act ca0 /ras latency = 2, /cas latency = 5, burst length = 4 act read act read act read ra0 ra0 cb0 rb0 rb0 cc0 rc0 rc0 h h hi-z qa0 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qa1 12.2.4 at 83 mhz (2-5-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qa3 qb0 qb1 qb2 qb3 t rc t rc = 10 (burst length = 8) qa1 ca0 /ras latency = 2, /cas latency = 5, burst length = 8 act read act read ra0 ra0 cb0 rb0 rb0 qa4 qa6 qa7 qa5 qb4 qb5 h h hi-z qb6 data sheet m13945ej5v0ds 43 pd23c64202l 12.2.5 at 66 mhz (2-5-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq t rc t rc = 6 (burst length = 4) 4 clocks (min.) are necessary between read and act ca0 /ras latency = 2, /cas latency = 5, burst length = 4 act read act read act read ra0 ra0 cb0 rb0 rb0 cc0 rc0 rc0 h h hi-z qa0 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qa1 12.2.6 at 66 mhz (2-5-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qa3 qb0 qb1 qb2 qb3 t rc t rc = 10 (burst length = 8) qa1 ca0 /ras latency = 2, /cas latency = 5, burst length = 8 act read act read ra0 ra0 cb0 rb0 rb0 qa4 qa6 qa7 qa5 qb4 qb5 h h hi-z qb6 data sheet m13945ej5v0ds 44 pd23c64202l 12.2.7 at 50 mhz (1-4-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq ca0 /ras latency = 1, /cas latency = 4, burst length = 4 read ra0 ra0 rb0 rc0 read read rb0 cb0 rc0 cc0 t rc t rc = 4 (burst length = 4) 3 clocks (min.) are necessary between read and act h act act act qa0 qa2 qb3 qc0 qc1 qc2 qa1 qb0 qb2 qb1 h hi-z qa3 qc3 12.2.8 at 50 mhz (1-4-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq ca0 /ras latency = 1, /cas latency = 4, burst length = 8 ra0 ra0 rb0 read rb0 cb0 t rc t rc = 8 (burst length = 8) h qa0 qa2 qb4 qb5 qb6 qb7 qa1 qb0 qb2 qb3 qb1 qa4 qa6 qa5 qa3 act act read h hi-z qa7 data sheet m13945ej5v0ds 45 pd23c64202l 12.2.9 at 33 mhz (1-3-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qa1 ca0 /ras latency = 1, /cas latency = 3, burst length = 4 act ra0 ra0 rb0 rc0 qb0 qb1 ra0 cb0 rc0 cc0 h 2 clocks (min.) are necessary between read and act read read act read act h hi-z t rc t rc = 3 (burst length = 4) qb2 qc0 qc1 qc2 qc3 12.2.10 at 33 mhz (1-3-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq ca0 /ras latency = 1, /cas latency = 3, burst length = 4 act read ra0 ra0 rb0 rc0 read read rb0 cb0 rc0 cc0 h act act qa0 qa2 qa3 qc0 qc1 qc2 qc3 qa1 qb0 qb2 qb3 qb1 h hi-z data sheet m13945ej5v0ds 46 pd23c64202l 12.2.11 at 33 mhz (1-3-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qb4 qb5 ob6 qb7 qa1 ca0 /ras latency = 1, /cas latency = 3, burst length = 8 read ra0 ra0 rb0 qb0 qb2 qb3 qb1 read rb0 cb0 t rc t rc = 7 (burst length = 8) qa4 qa6 qa5 qa3 h act h hi-z act 12.2.12 at 33 mhz (1-3-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qb4 qb5 qb6 qb7 qa1 ca0 /ras latency = 1, /cas latency = 3, burst length = 8 read ra0 ra0 rb0 qb0 qb2 qb3 qb1 read rb0 cb0 qa4 qa6 qa7 qa5 qa3 h act h hi-z act data sheet m13945ej5v0ds 47 pd23c64202l 12.3 random column read timing 12.3.1 at 100 mhz (2-5-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq t ccd t ccd = 4 (burst length = 4) 4 clocks (min.) are necessary between read and read ca0 /ras latency = 2, /cas latency = 5, burst length = 4 act read read ra0 ra0 cc0 h cb0 h hi-z qa0 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qa1 read 12.3.2 at 100 mhz (2-5-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qb0 qb1 qb2 ob3 t ccd t ccd = 8 (burst length = 8) ca0 /ras latency = 2, /cas latency = 5, burst length = 8 act read read ra0 ra0 h cb0 qb4 qb5 qb6 qa0 qa2 qa3 qa4 qa5 qa6 qa7 qa1 h hi-z qb7 data sheet m13945ej5v0ds 48 pd23c64202l 12.3.3 at 83 mhz (2-5-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq t ccd t ccd = 4 (burst length = 4) 4 clocks (min.) are necessary between read and read ca0 /ras latency = 2, /cas latency = 5, burst length = 4 act read read ra0 ra0 cc0 h cb0 h hi-z qa0 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qa1 read 12.3.4 at 83 mhz (2-5-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qb0 qb1 qb2 ob3 t ccd t ccd = 8 (burst length = 8) ca0 /ras latency = 2, /cas latency = 5, burst length = 8 act read read ra0 ra0 h cb0 qb4 qb5 qb6 qb7 qa0 qa2 qa3 qa4 qa5 qa6 qa7 qa1 h hi-z data sheet m13945ej5v0ds 49 pd23c64202l 12.3.5 at 66 mhz (2-5-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq ca0 /ras latency = 2, /cas latency = 5, burst length = 4 act read read ra0 ra0 cc0 h cb0 h hi-z qa0 qa2 qb0 qb1 qb3 qc1 qc2 qc3 qa1 read t ccd t ccd = 4 (burst length = 4) 4 clocks (min.) are necessary between read and read qc0 qa3 qb2 12.3.6 at 66 mhz (2-5-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qb0 qb1 qb2 ob3 t ccd t ccd = 8 (burst length = 8) ca0 /ras latency = 2, /cas latency = 5, burst length = 8 act read read ra0 ra0 h cb0 qb4 qb5 qb6 qb7 qa0 qa2 qa3 qa4 qa5 qa6 qa1 h hi-z qa7 data sheet m13945ej5v0ds 50 pd23c64202l 12.3.7 at 50 mhz (1-4-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qb0 qb1 qb2 qa1 ca0 /ras latency = 1, /cas latency = 4, burst length = 4 act read read read ra0 ra0 cc0 h cb0 t ccd t ccd = 3 (burst length = 4) 3 clocks (min.) are necessary between read and read hi-z h qc0 qc2 qc3 qc1 12.3.8 at 50 mhz (1-4-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq ca0 /ras latency = 1, /cas latency = 4, burst length = 4 act read read read ra0 ra0 cc0 h cb0 h hi-z qa0 qb0 qb1 qc0 qc1 qc2 qc3 qa1 qa2 qa3 qb2 qb3 data sheet m13945ej5v0ds 51 pd23c64202l 12.3.9 at 50 mhz (1-4-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq ca0 /ras latency = 1, /cas latency = 4, burst length = 8 act read read ra0 ra0 h cb0 t ccd t ccd = 7 (burst length = 8) hi-z h qa0 qa2 qa4 qa5 qb0 qb1 qb2 qb3 qa1 qb4 qb5 qb6 qb7 qa3 qa6 12.3.10 at 50 mhz (1-4-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qa5 qa6 qa7 qb0 qb1 qb2 qb3 qa1 ca0 /ras latency = 1, /cas latency = 4, burst length = 8 act read read ra0 ra0 h cb0 qb4 qb5 qb6 qb7 qa3 hi-z h qa4 data sheet m13945ej5v0ds 52 pd23c64202l 12.3.11 at 33 mhz (1-3-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qb1 qc0 qc1 qc2 qc3 qa1 ca0 /ras latency = 1, /cas latency = 3, burst length = 4 act read read read ra0 ra0 cc0 h cb0 t ccd t ccd = 2 (burst length = 4) qb0 2 clocks (min.) are necessary between read and read h hi-z 12.3.12 at 33 mhz (1-3-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qa3 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qa1 ca0 /ras latency = 1, /cas latency = 3, burst length = 4 act read read read ra0 ra0 cc0 h cb0 qb0 hi-z h data sheet m13945ej5v0ds 53 pd23c64202l 12.3.13 at 33 mhz (1-3-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qa3 qa5 qb0 qb1 qb2 qb3 qa1 ca0 /ras latency = 1, /cas latency = 3, burst length = 8 act read read ra0 ra0 h cb0 t ccd t ccd = 6 (burst length = 8) qa4 qb4 qb5 qb6 qb7 hi-z h 12.3.14 at 33 mhz (1-3-1-1-1-1-1-1-1) clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 /word oq qa0 qa2 qa3 qa5 qa6 qa7 qb0 qb1 qb2 qb3 qa1 /ras latency = 1, /cas latency = 3, burst length = 8 read h cb0 qa4 qb4 qb5 qb6 qb7 h hi-z read ra0 ra0 act ca0 data sheet m13945ej5v0ds 54 pd23c64202l 12.3.15 burst stop clk cke /cs /ras /cas /mr a8 - a12 a0 - a7 qa0 qa3 qb0 qb1 qb2 qb3 qa1 ca0 /ras latency = 2, burst length = 8 act read bst read bst ra0 ra0 cb0 hi-z qa0 qa2 qa3 qa1 oq (/cas latency = 3) qb0 qb2 qb3 qb1 hi-z hi-z hi-z oq (/cas latency = 4) note note h qa2 note both standard and sdram-precharge-like types of the burst stop command can be used. 12.3.16 clock suspend and power down clk cke /ras /cas /mr col /ras latency = 2, /cas latency = 5, burst length = 4 row row q0 q2 q3 q1 /cs internal clk a8 - a12 act read oq a0 - a7 power down entry power down exit clock suspend entry clock suspend exit power down clock suspend h hi-z t cksp data sheet m13945ej5v0ds 55 pd23c64202l act clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada qa0 qa1 qa2 qa3 readb qb0 qb1 qb2 qb3 h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada qa0 qa1 qa2 qa3 act readb qb0 qb1 qb2 qb3 h 12.4.2 row activate - read (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.1 row activate - read (1) 12.4 command combination examples data sheet m13945ej5v0ds 56 pd23c64202l clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada qa0 qa1 qa2 qa3 readb qb0 qb1 qb2 qb3 h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada qa0 qa1 qa2 qa3 act readb qb0 qb1 qb2 qb3 h 12.4.4 row activate - read (4) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.3 row activate - read (3) act data sheet m13945ej5v0ds 57 pd23c64202l clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada readb h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada qa0 qa1 qa2 act readb qa3 qb1 qb2 qb3 h 12.4.6 row activate - row activate t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.5 row activate - read (5) act act qb0 qa0 qa1 qa2 qb0 qb1 qb2 qb3 data sheet m13945ej5v0ds 58 pd23c64202l clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada qa0 qa1 qa2 qa3 h 12.4.8 read - read (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.7 read - read (1) qa1 qa2 qa3 qb1 qb2 qb3 readb readb qb1 qb2 qb3 qb0 qa0 qb0 data sheet m13945ej5v0ds 59 pd23c64202l clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.9 read - read (3) readb qa0 qa1 qb0 qb1 qb2 qb3 data sheet m13945ej5v0ds 60 pd23c64202l clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h read q0 q1 q2 q3 h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h read q0 q1 q2 q3 h 12.4.11 read suspend (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.10 read suspend (1) data sheet m13945ej5v0ds 61 pd23c64202l clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada qb0 qb1 h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada qa0 qc0 qc1 h 12.4.13 burst stop (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.12 burst stop (1) bst act readb bst qa0 act readb bst bst readc qc2 qc3 qb0 qb1 data sheet m13945ej5v0ds 62 pd23c64202l clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 3, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.15 power down t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.14 clock suspend act act readb qa1 qa2 qa3 qa0 readb qb1 qb2 qb3 qb0 qa0 qa1 qa2 qa3 qb1 qb2 qb3 qb0 data sheet m13945ej5v0ds 63 pd23c64202l clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.17 row activate - read (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.16 row activate - read (1) act act readb qa1 qa2 qa3 qa0 readb qb1 qb2 qb3 qb0 qa0 qa1 qa2 qa3 qb1 qb2 qb3 qb0 data sheet m13945ej5v0ds 64 pd23c64202l clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.19 row activate - read (4) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.18 row activate - read (3) act act readb qa1 qa2 qa3 qa0 readb qb1 qb2 qb3 qb0 qa0 qa1 qa2 qa3 qb1 qb2 qb3 qb0 data sheet m13945ej5v0ds 65 pd23c64202l clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.20 row activate - read (5) act qa1 qa2 qa3 qa0 readb qb1 qb2 qb3 qb0 clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.21 row activate - row activate act qa1 qa2 qa3 qa0 readb qb1 qb2 qb0 act qb3 data sheet m13945ej5v0ds 66 pd23c64202l clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.22 read - read (1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 qa0 qa1 qa2 qa3 qb1 qb2 qb3 qb0 readb clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.23 read - read (2) qa1 qa2 qa3 qa0 readb qb1 qb2 qb3 qb0 data sheet m13945ej5v0ds 67 pd23c64202l clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.24 read - read (3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 qa0 qa1 qa2 qa3 qb1 qb2 qb3 qb0 readb data sheet m13945ej5v0ds 68 pd23c64202l clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h read h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h read q0 q1 q2 q3 h 12.4.26 read suspend (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.25 read suspend (1) q0 q1 q2 q3 data sheet m13945ej5v0ds 69 pd23c64202l clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada qb0 qb1 h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.28 burst stop (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.27 burst stop (1) bst act readb bst qa0 act readb bst bst readc qa0 qc0 qc1 qc2 qc3 qb0 qb1 data sheet m13945ej5v0ds 70 pd23c64202l clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 5, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.30 power down t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.29 clock suspend act act readb qa1 qa2 qa3 qa0 readb qb0 qa0 qa1 qb1 qb0 t26 t27 t26 t27 qb1 qb2 qb3 qb2 qa2 qa3 data sheet m13945ej5v0ds 71 pd23c64202l clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.32 row activate - read (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.31 row activate - read (1) act act readb qa1 qa2 qa3 qa0 readb qb1 qb2 qb0 qa0 qa1 qa2 qa3 qb1 qb2 qb3 qb0 data sheet m13945ej5v0ds 72 pd23c64202l clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.34 row activate - read (4) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.33 row activate - read (3) act act readb qa1 qa2 qa3 qa0 readb qb1 qb2 qb3 qb0 qa0 qa1 qa2 qa3 qb1 qb2 qb3 qb0 data sheet m13945ej5v0ds 73 pd23c64202l clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.35 row activate - read (5) act qa1 qa2 qa3 qa0 readb qb1 qb2 qb3 qb0 clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.36 row activate - row activate act qa1 qa2 qa3 qa0 readb qb1 qb2 qb0 act data sheet m13945ej5v0ds 74 pd23c64202l clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.37 read - read (1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 qa0 qa1 qa2 qa3 qb1 qb2 qb3 qb 0 readb clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.38 read - read (2) qa1 qa2 qa3 qa0 readb qb1 qb2 qb3 qb0 data sheet m13945ej5v0ds 75 pd23c64202l clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.39 read - read (3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 qa0 qa1 qa2 qa3 qb1 qb2 qb3 qb0 readb data sheet m13945ej5v0ds 76 pd23c64202l clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h read h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h read q0 q1 q2 q3 h 12.4.41 read suspend (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.40 read suspend (1) q0 q1 q2 q3 data sheet m13945ej5v0ds 77 pd23c64202l clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada qb0 qb1 h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.43 burst stop (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.42 burst stop (1) bst act readb bst qa0 act readb bst bst readc qa0 qc0 qc1 qc2 qc3 qb0 qb1 data sheet m13945ej5v0ds 78 pd23c64202l clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 clk /cas latency = 6, burst length = 4 cke mrs command /word oq act hi-z h reada h 12.4.45 power down t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 12.4.44 clock suspend act act readb qa1 qa2 qa3 qa0 readb qb0 qa0 qa1 qb1 qb0 t26 t27 t26 t27 qb1 qb3 qb2 qa2 qa3 data sheet m13945ej5v0ds 79 pd23c64202l 13. package drawing m 86 44 143 s p c ns b m d l k j l s g e f detail of lead end notes 1. each lead centerline is located within 0.1 mm of its true position (t.p.) at maximum material condition. r h i 2. dimension "a" does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. a item b c i 86-pin plastic tsop ( ii ) (10.16 mm (400)) a d e f g h j k l millimeters 0.5 (t.p.) 0.765 max. 10.16 0.10 22.22 0.05 0.10 0.05 0.22 1.1 0.1 11.76 0.20 1.00 + 0.06 ? 0.04 0.80 0.20 0.145 + 0.025 ? 0.015 0.50 0.1 m n p 0.10 3 + 5 ? 3 0.25 r s 0.60 0.15 s86g5-50-9jh1-1 data sheet m13945ej5v0ds 80 pd23c64202l 14. recommended soldering condition please consult with our sales offices for soldering conditions of the pd23c64202l. type of surface mount device pd23c64202lg5-9jh : 86-pin plastic tsop (ii) (10.16 mm (400)) data sheet m13945ej5v0ds 81 pd23c64202l [ memo ] data sheet m13945ej5v0ds 82 pd23c64202l [ memo ] data sheet m13945ej5v0ds 83 pd23c64202l notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. pd23c64202l the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of august, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ? |
Price & Availability of UPD23C64202LG5-XXX-9JH
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |