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? 1998 microchip technology inc. preliminary ds21223c-page 1 m 25aa640/25lc640 device selection table features low power cmos technology - write current: 3 ma typical - read current: 500 m a typical - standby current: 500 na typical 8192 x 8 bit organization 32 byte page write cycle time: 5ms max. self-timed erase and write cycles block write protection - protect none, 1/4, 1/2, or all of array built-in write protection - power on/off data protection circuitry - write enable latch - write protect pin sequential read high reliability - data retention: > 200 years - esd protection: > 4000 v 8-pin pdip, soic, and tssop packages temperature ranges supported: description the microchip technology inc. 25aa640/25lc640 (25xx640 * ) is a 64k bit serial electrically erasable prom [eeprom]. the memory is accessed via a sim- ple serial peripheral interface (spi) compatible serial bus. the bus signals required are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input. communication to the device can be paused via the hold pin (hold ). while the device is paused, transi- tions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. package types block diagram part number v cc range max clock frequency temp ranges 25aa640 1.8-5.5v 1 mhz c,i 25lc640 2.5-5.5v 2 mhz c,i 25lc640 4.5-5.5v 3/2.5 mhz c,i/e - commercial (c): 0 c to +70 c - industrial (i): -40 c to +85 c - automotive (e): -40 c to +125 c 25xx640 tssop 1 2 3 4 8 7 6 5 sck si v ss wp hold v cc cs so 25xx640 pdip/soic 1 2 3 4 8 7 6 5 v cc hold sck si cs so wp v ss si so sck cs hold wp status register i/o control memory control logic x dec hv generator eeprom array page latches y decoder sense amp. r/w control logic v cc v ss 64k spi bus serial eeprom *25xx640 is used in this document as a generic part number for the 25aa640/25lc640 devices. spi is a trademark of motorola.
25aa640/25lc640 ? 1998 microchip technology inc. preliminary ds21223c-page 2 1.0 electrical characteristics 1.1 maxim um ratings* vcc ...................................................................................7.0v all inputs and outputs w.r.t. vss.................. -0.6v to vcc+1.0v storage temperature ....................................... -65?c to 150?c ambient temperature under bias..................... -65?c to 125?c soldering temperature of leads (10 seconds) ............. +300?c esd protection on all pins................................................. 4kv *notice: stresses above those listed under ?aximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?ation is not implied. exposure to maximum rating conditions for an extended period of time may affect device reliability table 1-1: pin function table figure 1-1: ac test circuit 1.2 a c t est conditions name function cs chip select input so serial data output si serial data input sck serial clock input wp write protect pin v ss ground v cc supply voltage hold hold input ac waveform: v lo = 0.2v v hi = v cc - 0.2v (note 1) v hi = 4.0v (note 2) timing measurement reference level input 0.5 v cc output 0.5 v cc note 1: for v cc 4.0v 2: for v cc > 4.0v v cc so 100 pf 1.8 k 2.25 k table 1-2: dc characteristics all parameters apply over the speci?d operating ranges unless otherwise noted. commercial (c): t amb = 0 c to +70 c v cc = 1.8v to 5.5v industrial (i): t amb = -40 c to +85 c v cc = 1.8v to 5.5v automotive (e): t amb = -40 c to +125 c v cc = 4.5v to 5.5v parameter symbol min max units test conditions high level input voltage v ih 1 2.0 v cc +1 v v cc 3 2.7v (note) v ih 2 0.7 v cc v cc +1 v v cc < 2.7v (note) low level input voltage v il 1 -0.3 0.8 v v cc 3 2.7v (note) v il 2 -0.3 0.2 v cc vv cc < 2.7v (note) low level output voltage v ol 0.4 v i ol = 2.1 ma v ol 0.2 v i ol = 1.0 ma, v cc < 2.5v high level output voltage v oh v cc -0.5 v i oh =-400 m a input leakage current i li -10 10 m acs = v cc , v in = v ss to v cc output leakage current i lo -10 10 m acs = v cc , v out = v ss to v cc internal capacitance (all inputs and outputs) c int 7 pf t amb = 25?c, clk = 1.0 mhz, v cc = 5.0v (note) operating current i cc read 1 500 ma m a v cc = 5.5v; f clk =3.0 mhz; so = open v cc = 2.5v; f clk =2.0 mhz; so = open i cc write 5 3 ma ma v cc = 5.5v v cc = 2.5v standby current i ccs 5 1 m a m a cs = vcc = 5.5v, inputs tied to v cc or v ss cs = vcc = 2.5v, inputs tied to v cc or v ss note: this parameter is periodically sampled and not 100% tested.
25aa640/25lc640 ds21223c-page 3 preliminary ? 1998 microchip technology inc. table 1-3: ac characteristics all parameters apply over the speci?d operating ranges unless otherwise noted. commercial (c): t amb = 0 c to +70 cv cc = 1.8v to 5.5v industrial (i): t amb = -40 c to +85 cv cc = 1.8v to 5.5v automotive (e): t amb = -40 c to +125 cv cc = 4.5v to 5.5v parameter symbol min max units test conditions clock frequency f clk 3 2 1 mhz mhz mhz v cc = 4.5v to 5.5v (note 2) v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v cs setup time t css 100 250 500 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v cs hold time t csh 150 250 475 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v cs disable time t csd 500 ns data setup time t su 30 50 50 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v data hold time t hd 50 100 100 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v clk rise time t r ? m s (note 1) clk fall time t f ? m s (note 1) clock high time t hi 150 250 475 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v clock low time t lo 150 250 475 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v clock delay time t cld 50 ns clock enable time t cle 50 ns output valid from clock low t v 150 250 475 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v output hold time t ho 0 ns (note 1) output disable time t dis 200 250 500 ns ns ns v cc = 4.5v to 5.5v (note 1) v cc = 2.5v to 4.5v (note 1) v cc = 1.8v to 2.5v (note 1) hold setup time t hs 100 100 200 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v hold hold time t hh 100 100 200 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v hold low to output high-z t hz 100 150 200 ns ns ns v cc = 4.5v to 5.5v (note 1) v cc = 2.5v to 4.5v (note 1) v cc = 1.8v to 2.5v (note 1) hold high to output valid t hv 100 150 200 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v internal write cycle time t wc ? ms endurance 100k e/w cycles (note 3) note 1: this parameter is periodically sampled and not 100% tested. 2: f clk max. = 2.5 mhz for t amb > 85 c 3: this parameter is not tested but guaranteed by characterization. for endurance estimates in a speci? application, please consult the total endurance model which can be obtained on microchips website.
25aa640/25lc640 ? 1998 microchip technology inc. preliminary ds21223c-page 4 figure 1-2: hold timing figure 1-3: serial input timing figure 1-4: serial output timing cs sck so si hold t hh t hs t hs t hh t hv t hz don? care t su high impedance n+2 n+1 n n-1 n n+2 n+1 n n n-1 cs sck si so t css t hd tsu t f t r t csd t cld t csh lsb in msb in high impedance t cle mode 1,1 mode 0,0 cs sck so t lo t hi t ho t v msb out lsb out t csh t dis don? care si mode 1,1 mode 0,0
25aa640/25lc640 ds21223c-page 5 preliminary ? 1998 microchip technology inc. 2.0 pin descriptions 2.1 chip select ( cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. however, a programming cycle which is already initi- ated or in progress will be completed, regardless of the cs input signal. if cs is brought high during a pro- gram cycle, the device will go in standby mode as soon as the programming cycle is complete. as soon as the device is deselected, so goes to the high impedance state, allowing multiple parts to share the same spi bus. a low to high transition on cs after a valid write sequence initiates an internal write cycle. after power-up, a high to low transition on cs is required prior to any sequence being initiated. 2.2 serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses, and data. data is latched on the rising edge of the serial clock. 2.3 serial output (so) the so pin is used to transfer data out of the 25xx640. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 2.4 serial cloc k (sck) the sck is used to synchronize the communication between a master and the 25xx640. instructions, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 2.5 write pr otect ( wp ) this pin is used in conjunction with the wpen bit in the status register to prohibit writes to the non-volatile bits in the status register. when wp is low and wpen is high, writing to the non-volatile bits in the status reg- ister is disabled. all other operations function nor- mally. when wp is high, all functions, including writes to the non-volatile bits in the status register operate normally. if the wpen bit is set, wp low during a sta- tus register write sequence will disable writing to the status register. if an internal write cycle has already begun, wp going low will have no effect on the write. the wp pin function is blocked when the wpen bit in the status register is low. this allows the user to install the 25aa640/25lc640 in a system with wp pin grounded and still be able to write to the status regis- ter. the wp pin functions will be enabled when the wpen bit is set high. 2.6 hold ( hold ) the hold pin is used to suspend transmission to the 25xx640 while in the middle of a serial sequence with- out having to re-transmit the entire sequence over at a later time. it must be held high any time this function is not being used. once the device is selected and a serial sequence is underway, the hold pin may be pulled low to pause further serial communication with- out resetting the serial sequence. the hold pin must be brought low while sck is low, otherwise the hold function will not be invoked until the next sck high to low transition. the 25xx640 must remain selected dur- ing this sequence. the si, sck, and so pins are in a high impedance state during the time the part is paused and transitions on these pins will be ignored. to resume serial communication, hold must be brought high while the sck pin is low, otherwise serial communication will not resume. lowering the hold line at any time will tri-state the so line. 3.0 functional description 3.1 principles of opera tion the 25xx640 is a 8192 byte serial eeprom designed to interface directly with the serial peripheral interface (spi) port of many of todays popular microcontroller families, including microchips pic16c6x/7x micro- controllers. it may also interface with microcontrollers that do not have a built-in spi port by using discrete i/o lines programmed properly with the software. the 25xx640 contains an 8-bit instruction register. the part is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low and the hold pin must be high for the entire opera- tion. table 3-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses, and data are transferred msb ?st, lsb last. data is sampled on the ?st rising edge of sck after cs goes low. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input and place the 25xx640 in ?old mode. after releasing the hold pin, operation will resume from the point when the hold was asserted. :pic is a registered tradmark of microchip technology inc.
25aa640/25lc640 ? 1998 microchip technology inc. preliminary ds21223c-page 6 3.2 read sequence the part is selected by pulling cs low. the 8-bit read instruction is transmitted to the 25xx640 followed by the 16-bit address with the three msbs of the address being don? care bits. after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. the internal address pointer is automatically incre- mented to the next higher address after each byte of data is shifted out. when the highest address is reached (1fffh), the address counter rolls over to address 0000h allowing the read cycle to be continued inde?itely. the read operation is terminated by raising the cs pin (figure 3-1). 3.3 write sequence prior to any attempt to write data to the 25xx640 array or status register, the write enable latch must be set by issuing the wren instruction (figure 3-4). this is done by setting cs low and then clocking out the proper instruction into the 25xx640. after all eight bits of the instruction are transmitted, the cs must be brought high to set the write enable latch. if the write operation is initiated immediately after the wren instruction without cs being brought high, the data will not be written to the array because the write enable latch will not have been properly set. once the write enable latch is set, the user may pro- ceed by setting the cs low, issuing a write instruction, followed by the address, and then the data to be writ- ten. up to 32 bytes of data can be sent to the 25xx640 before a write cycle is necessary. the only restriction is that all of the bytes must reside in the same page. a page address begins with xxx0 0000 and ends with xxx1 1111. if the internal address counter reaches xxx1 1111 and the clock continues, the counter will roll back to the ?st address of the page and overwrite any data in the page that may have been written. for the data to be actually written to the array, the cs must be brought high after the least signi?ant bit (d0) of the n th data byte has been clocked in. if cs is brought high at any other time, the write operation will not be completed. refer to figure 3-2 and figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. while the write is in progress, the status register may be read to check the status of the wpen, wip, wel, bp1, and bp0 bits (figure 3-6). a read attempt of a memory array location will not be possible during a write cycle. when the write cycle is completed, the write enable latch is reset. figure 3-1: read sequence table 3-1: instruction set instruction name instruction format description read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address wren 0000 0110 set the write enable latch (enable write operations) wrdi 0000 0100 reset the write enable latch (disable write operations) rdsr 0000 0101 read status register wrsr 0000 0001 write status register so si sck cs 0 234567891011 21222324252627282930 31 1 01 0 0 0 0 0 1 15 14 13 12 210 76543210 instruction 16 bit address data out high impedance
25aa640/25lc640 ds21223c-page 7 preliminary ? 1998 microchip technology inc. figure 3-2: byte write sequence figure 3-3: page write sequence 3.4 write enab le (wren) and write disab le (wrdi) the 25xx640 contains a write enable latch. see table 3-3 for the write protect functionality matrix. this latch must be set before any write operation will be completed internally. the wren instruction will set the latch, and the wrdi will reset the latch. the following is a list of conditions under which the write enable latch will be reset: power-up wrdi instruction successfully executed wrsr instruction successfully executed write instruction successfully executed figure 3-4: write enable sequence so si cs 00 0 0 0 0 0 1 15 14 13 12 210 76543210 instruction 16 bit address data byte high impedance tw c si cs 91011 21222324252627282930 31 00 0 0 0 0 0 1 15 14 13 12 210 76543210 instruction 16 bit address data byte 1 sck 0 234567 1 8 si cs 41 42 43 46 47 76543210 data byte n (32 max) sck 32 34 35 36 37 38 39 33 40 76543210 data byte 3 76543210 data byte 2 44 45 sck 0 234567 1 si high impedance so cs 01 0000 0 1
25aa640/25lc640 ? 1998 microchip technology inc. preliminary ds21223c-page 8 figure 3-5: write disable sequence 3.5 read status register (rdsr) the rdsr instruction provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is format- ted as follows: the write-in-process (wip) bit indicates whether the 25xx640 is busy with a write operation. when set to a ? a write is in progress, when set to a ? no write is in progress. this bit is read only. the write enable latch (wel) bit indicates the sta- tus of the write enable latch. when set to a ? the latch allows writes to the array and status register, when set to a ? the latch prohibits writes to the array and status register. the state of this bit can always be updated via the wren or wrdi commands regardless of the state of write protection on the status register. this bit is read only. the block protection (bp0 and bp1) bits indicate which blocks are currently write protected. these bits are set by the user issuing the wrsr instruction. these bits are non-volatile. see figure 3-6 for rdsr timing sequence 3.6 write status register (wrsr) the wrsr instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the status register. the array is divided up into four segments. the user has the ability to write protect none, one, two, or all four of the seg- ments of the array. the partitioning is controlled as illustrated in table 3-2. the write protect enable (wpen) bit is a non-volatile bit that is available as an enable bit for the wp pin. the write protect (wp ) pin and the write protect enable (wpen) bit in the status register control the programmable hardware write protect feature. hard- ware write protection is enabled when wp pin is low and the wpen bit is high. hardware write protection is disabled when either the wp pin is high or the wpen bit is low. when the chip is hardware write pro- tected, only writes to non-volatile bits in the status reg- ister are disabled. see table 3-3 for a matrix of functionality on the wpen bit. see figure 3-7 for wrsr timing sequence table 3-2: array protection sck 0 234567 1 si high impedance so cs 01 0000 0 1 0 7 654 3 2 1 0 wpen x x x bp1 bp0 wel wip bp1 bp0 array addresses write protected 0 0 none 01 upper 1/4 (1800h - 1fffh) 10 upper 1/2 (1000h - 1fffh) 11 all (0000h - 1fffh) m
25aa640/25lc640 ds21223c-page 9 preliminary ? 1998 microchip technology inc. figure 3-6: read status register sequence figure 3-7: write status register sequence 3.7 data pr otection the following protection has been implemented to pre- vent inadvertent writes to the array: the write enable latch is reset on power-up. a write enable instruction must be issued to set the write enable latch. after a byte write, page write, or status register write, the write enable latch is reset. ?s must be set high after the proper number of clock cycles to start an internal write cycle. access to the array during an internal write cycle is ignored and programming is continued. 3.8 p o wer on state the 25xx640 powers on in the following state: the device is in low power standby mode (cs = 1). the write enable latch is reset. so is in high impedance state. a high to low transition on cs is required to enter the active state. . so si cs 9101112131415 11 0 0 0 0 00 7654 2 10 instruction data from status register high impedance sck 0 234567 1 8 3 so si cs 9101112131415 01 0 0 0 0 00 7654 210 instruction data to status register high impedance sck 0 234567 1 8 3 table 3-3: write protect functionality matrix wpen wp wel protected blocks unprotected blocks status register x x 0 protected protected protected 0 x 1 protected writable writable 1 low 1 protected writable protected x high 1 protected writable writable
25aa640/25lc640 ? 1998 microchip technology inc. preliminary ds21223c-page 10 notes:
25aa640/25lc640 ds21223c-page 11 preliminary ? 1998 microchip technology inc. 25aa640/25lc640 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales of?e. sales and suppor t package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead st = tssop, 8-lead temperature range: blank = 0 c to +70 c i = ?0 c to +85 c e = ?0 c to +125 c devices: 25aa640 64k bit 1.8v spi serial eeprom 25aa640t 64k bit 1.8v spi serial eeprom tape and reel 25aa640x 64k bit 1.8v spi serial eeprom in alternate pinout (st only) 25aa640xt 64k bit 1.8v spi serial eeprom in alternate pinout tape and reel (st only) 25lc640 64k bit 2.5v spi serial eeprom 25lc640t 64k bit 2.5v spi serial eeprom tape and reel 25lc640x 64k bit 2.5v spi serial eeprom in alternate pinout (st only) 25lc640xt 64k bit 2.5v spi serial eeprom in alternate pinout tape and reel (st only) 25xx640 /p data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales of?e 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip worldwide web site (www.microchip.com)
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip t echnology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectua l property rights arising from such use or otherwise. use of microchip s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or other wise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip t echnology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds21223c-page 12 ? 1998 microchip technology inc. all rights reserved. ?1998, microchip technology incorporated, usa. 6/98 printed on recycled paper. m americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602-786-7200 fax: 602-786-7277 technical support: 602 786-7627 web: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972-991-7177 fax: 972-991-8588 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714-263-1888 fax: 714-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 516-273-5305 fax: 516-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia paci? rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology inc. india liaison of?e no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?n road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 asia/pacific (continued) taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-1189-21-5858 fax: 44-1189-21-5835 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 m?chen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-39-6899939 fax: 39-39-6899883 4/3/98 w orldwide s ales and s ervice microchip received iso 9001 quality system certi?ation for its worldwide headquarters, design, and wafer fabrication facilities in january, 1997. our ?ld-programmable picmicro 8-bit mcus, serial eeproms, related specialty memory products and development systems conform to the stringent quality standards of the international standard organization (iso).

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