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order number: 290645, revision: 022 january 2005 intel? advanced+ boot block flash memory (c3) 28f800c3, 28f160c3, 28f320c3, 28f640c3 (x16) datasheet product features the intel ? advanced+ book block flash memory (c3) device, manufactured on intel?s latest 0.13 m and 0.18 m technologies, represents a feature-rich solution for low-power applications. the c3 device incorporates low-voltage capability (3 v read, program, and erase) with high-speed, low-power operation. flexible block locking allows any block to be independently locked or unlocked. add to this the intel ? flash data integrator (intel ? fdi) software and you have a cost-effective, flexible, monolithic code plus data storage solution. intel ? advanced+ boot block flash memory (c3) products are available in 48-lead tsop, 48- ball csp, and 64-ball easy bga packages. additional information on this product family can be obtained from the intel ? flash website: http://www.intel.com/design/flash. flexible smartvoltage technology ? 2.7 v? 3.6 v read/program/erase ? 12 v for fast production programming 1.65 v to 2.5 v or 2.7 v to 3.6 v i/o option ? reduces overall system power high performance ? 2.7 v? 3.6 v: 70 ns max access time optimized architecture for code plus data storage ? eight 4 kword blocks, top or bottom parameter boot ? up to 127 x 32 kword blocks ? fast program suspend capability ? fast erase suspend capability flexible block locking ? lock/unlock any block ? full protection on power-up ? write protect(wp#) pin for hardware block protection low power consumption ? 9 ma typical read ? 7 ua typical standby with automatic power savings feature extended temperature operation ? -40 c to +85 c 128-bit protection register ? 64 bit unique device identifier ? 64 bit user programmable otp cells extended cycling capability ? minimum 100,000 block erase cycles software ?intel ? flash data integrator ? supports top or bottom boot storage, streaming data (for example, voice) ? intel basic command set ? common flash interface standard surface mount packaging ? 48-ball bga*/vfbga ? 64-ball easy bga packages ? 48-tsop package etox? viii (0.13 m ) flash technology ? 8, 16, 32 mbit etox? vii (0.18 m ) flash technology ? 16, 32, 64 mbit etox? vi (0.25 m ) flash technology ? 8, 16 and 32 mbit
january 2005 intel? advanced+ boot block flash memory (c3) datasheet 2 order number: 290645, revision: 022 legal lines and disclaimers information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation. all rights reserved.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 3 contents 1.0 introduction ............................................................................................................................... .....7 1.1 nomenclature ................................................................................................................ .......7 1.2 conventions................................................................................................................. .........7 2.0 functional overview .....................................................................................................................8 2.1 product overview ............................................................................................................ .....8 2.2 block diagram ............................................................................................................... .......9 2.3 memory map.................................................................................................................. .......9 3.0 package information ...................................................................................................................12 3.1 mbga* and vf bga package............................................................................................12 3.2 tsop package ................................................................................................................ ...13 3.3 easy bga package ............................................................................................................ 14 4.0 ballout and signal descriptions ................................................................................................15 4.1 48-lead tsop package .....................................................................................................15 4.2 64-ball easy bga package ................................................................................................18 4.3 signal descriptions ......................................................................................................... ....18 5.0 maximum ratings and operating conditions ...........................................................................20 5.1 absolute maximum ratings ................................................................................................20 5.2 operating conditions ........................................................................................................ ..20 6.0 electrical specifications .............................................................................................................22 6.1 current characteristics ..................................................................................................... ..22 6.2 dc voltage characteristics.................................................................................................2 4 7.0 ac characteristics ......................................................................................................................25 7.1 ac read characteristics ....................................................................................................2 5 7.2 ac write characteristics.................................................................................................... .29 7.3 erase and program timings ...............................................................................................33 7.4 ac i/o test conditions ...................................................................................................... .33 7.5 device capacitance.......................................................................................................... ..34 8.0 power and reset specifications ................................................................................................35 8.1 active power (program/erase/read)..................................................................................35 8.2 automatic power savings (aps) ........................................................................................35 8.3 standby power ............................................................................................................... ....35 8.4 deep power-down mode....................................................................................................35 8.5 power and reset considerations .......................................................................................36 8.5.1 power-up/down characteristics ............................................................................36 8.5.2 rp# connected to system reset ..........................................................................36 8.5.3 vcc, vpp and rp# transitions ............................................................................36 8.5.4 reset specifications ..............................................................................................37 8.6 power supply decoupling...................................................................................................37 9.0 device operations .......................................................................................................................39
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 4 order number: 290645, revision: 022 9.1 bus operations .............................................................................................................. ..... 39 9.1.1 read ...................................................................................................................... 39 9.1.2 write ..................................................................................................................... .39 9.1.3 output disable ....................................................................................................... 39 9.1.4 standby.................................................................................................................. 4 0 9.1.5 reset ..................................................................................................................... 40 10.0 modes of operation ..................................................................................................................... 41 10.1 read mode .................................................................................................................. ....... 41 10.1.1 read array............................................................................................................. 41 10.1.2 read identifier ....................................................................................................... 41 10.1.3 cfi query .............................................................................................................. 42 10.1.4 read status register............................................................................................. 42 10.1.4.1 clear status register............................................................................. 43 10.2 program mode ............................................................................................................... ..... 43 10.2.1 12-volt production programming........................................................................... 43 10.2.2 suspending and resuming program..................................................................... 44 10.3 erase mode ................................................................................................................. ....... 44 10.3.1 suspending and resuming erase ......................................................................... 45 11.0 security modes ............................................................................................................................ 49 11.1 flexible block locking ..................................................................................................... ... 49 11.1.1 locking operation.................................................................................................. 50 11.1.1.1 locked state .......................................................................................... 50 11.1.1.2 unlocked state....................................................................................... 50 11.1.1.3 lock-down state.................................................................................... 50 11.2 reading block-lock status................................................................................................. 5 0 11.3 locking operations during erase suspend ........................................................................ 51 11.4 status register error checking .......................................................................................... 51 11.5 128-bit protection register................................................................................................ .51 11.5.1 reading the protection register............................................................................ 52 11.5.2 programming the protection register.................................................................... 52 11.5.3 locking the protection register............................................................................. 52 11.6 v pp program and erase voltages ...................................................................................... 52 11.6.1 program protection................................................................................................ 53 appendix a write state machine states .............................................................................................54 appendix b flow charts ......................................................................................................................56 appendix c common flash interface .................................................................................................62 appendix d additional information ....................................................................................................70 appendix e ordering information .......................................................................................................71
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 5 revision history date of revision version description 05/12/98 -001 original version 07/21/98 -002 48-lead tsop package diagram change bga package diagrams change 32-mbit ordering information change (section 6) cfi query structure output table change (table c2) cfi primary-vendor specific extended query table change for optional features and command support change (table c8) protection register address change i ppd test conditions clarification (section 4.3) bga package top side mark information clarification (section 6) 10/03/98 -003 byte-wide protection register address change v ih specification change (section 4.3) v il maximum specification change (section 4.3) i ccs test conditions clarification (section 4.3) added command sequence error note (table 7) datasheet renamed from 3 volt advanced boot block, 8-, 16-, 32-mbit flash memory family. 12/04/98 -004 added t bhwh /t bheh and t qvbl (section 4.6) programming the protection register clarification (section 3.4.2) 12/31/98 -005 removed all references to x8 configurations 02/24/99 -006 removed reference to 40-lead tsop from front page 06/10/99 -007 added easy bga package (section 1.2) removed 1.8 v i/o references locking operations flowchart changed (appendix b) added t whgl (section 4.6) cfi primary vendor-specific extended query changed (appendix c) 03/20/00 -008 max i ccd changed to 25 a table 10, added note indicating v cc max = 3.3 v for 32-mbit device 04/24/00 -009 added specifications for 0.18 micron product offerings throughout document added 64- mbit density 10/12/00 -010 changed references of 32mbit 80ns devices to 70ns devices to reflect the faster product offering. changed vccmax=3.3v reference to indicate that the affected product is the 0.25 m 32mbit device. minor text edits throughout document. 7/20/01 -011 added 1.8v i/o operation documentation where applicable added tsop pcn ?pin-1? indicator information changed references in 8 x 8 bga pinout diagrams from ?gnd? to ?vssq? added ?vssq? to pin descriptions information removed 0.4 m references in dc characteristics table corrected 64mb package ordering information from 48-ubga to 48-vfbga corrected ?bottom? parameter block sizes to on 8mb device to 8 x 4kwords minor text edits throughout document 10/02/01 -012 added specifications for 0.13 micron product offerings throughout document 2/05/02 -013 corrected iccw / ippw / icces /ippes values. added mechanicals for 16mb and 64mb minor text edits throughout document.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 6 order number: 290645, revision: 022 4/05/02 -014 updated 64mb product offerings. updated 16mb product offerings. revised and corrected dc characteristics table. added mechanicals for easy bga. minor text edits throughout document. 3/06/03 -016 complete technical update. 10/01/03 -017 corrected information in the device geometry details table, address 0x34. 5/20/04 -018 updated the layout of the datasheet. 9/1/04 -019 fixed typo for standby power on cover page. 9/14/04 -020 added lead-free line items to table 37 ?product information ordering matrix? on page 72 . 9/27/04 -021 added specification for 8mb 0.13 micron device. added 0.13 micron to table 37 ?product information ordering matrix? on page 72 . 1/26/05 -022 converted datasheet to new template. deleted description in table 4. deleted note in figure 5. date of revision version description
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 7 1.0 introduction this datasheet contains the specifications for the intel ? advanced+ boot block flash memory (c3) device family, hereafter called the c3 flash memory device. these flash memories add features such as instant block locking and protection registers that can be used to enhance the security of systems. 1.1 nomenclature 0x hexadecimal prefix 0b binary prefix byte 8 bits word 16 bits kw or kword 1024 words mword 1,048,576 words kb 1024 bits kb 1024 bytes mb 1,048,576 bits mb 1,048,576 bytes aps automatic power savings csp chip scale package cui command user interface otp one time programmable pr protection register prd protection register data plr protection lock register rfu reserved for future use sr status register srd status register data wsm write state machine 1.2 conventions the terms pin and signal are often used interchangeably to refer to the external signal connections on the package; for chip scale package (csp) the term ball is used. group membership brackets: square brackets will be used to designate group membership or to define a group of signals with similar function (i.e. a[21:1], sr[4:1]) set : when referring to registers, the term set means the bit is a logical 1. clear: when referring to registers, the term clear means the bit is a logical 0. block: a group of bits (or words) that erase simultaneously with one block erase instruction. main block : a block that contains 32 kwords. parameter block : a block that contains 4 kwords.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 8 order number: 290645, revision: 022 2.0 functional overview this section provides an overview of the intel ? advanced+ boot block flash memory (c3) device features and architecture. 2.1 product overview the c3 flash memory device provides high-performance asynchronous reads in package- compatible densities with a 16 bit data bus. individually-erasable memory blocks are optimally sized for code and data storage. eight 4 kword parameter blocks are located in the boot block at either the top or bottom of the device?s memory map. the rest of the memory array is grouped into 32 kword main blocks. the device supports read-array mode operations at various i/o voltages (1.8 v and 3 v) and erase and program operations at 3 v or 12 v vpp. with the 3 v i/o option, vcc and vpp can be tied together for a simple, ultra-low-power design. in addition to i/o voltage flexibility, the dedicated vpp input provides complete data protection when v pp v pplk . the intel? advanced+ boot block flash memory (c3) device features a 128-bit protection register enabling security techniques and data protection schemes through a combination of factory-programmed and user-programmable otp data registers. zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. additional block lock-down capability provides hardware protection where software commands alone cannot change the block?s protection status. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence issued to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. the device offers three low-power saving features: automatic power savings (aps), standby mode, and deep power-down mode. the device automatically enters aps mode following read cycle completion. standby mode begins when the system deselects the flash memory by deasserting chip enable, ce#. the deep power-down mode begins when reset deep power- down, rp# is asserted, which deselects the memory and places the outputs in a high-impedance state, producing ultra-low power savings. combined, these three power-savings features significantly enhanced power consumption flexibility.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 9 2.2 block diagram 2.3 memory map the intel? advanced+ boot block flash memory (c3) device is asymmetrically blocked, which enables system code and data integration within a single flash device. the bulk of the array is divided into 32 kword main blocks that can store code or data, and 4 kword boot blocks to facilitate storage of boot code or for frequently changing small parameters. see table 1, ?top boot memory map? on page 10 and table 2, ?bottom boot memory map? on page 11 for details. figure 1. c3 flash memory device block diagram output m ulti ple xer 4-kword para mete r b loc k 32- kw ord main block 32- kw ord main block 4-kword para mete r b loc k y-g at ing/ sensing write state machine program/ erase voltage switch dat a comparat or status regist er identifier regist er da ta re gi st er i/o logic address lat ch address count er x-decoder y-decoder power reduct ion cont rol input buffer output buffer gnd v cc v pp ce# we# oe# rp# command user interface input buffer dq 0 -dq 15 v ccq wp# a[max:min]
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 10 order number: 290645, revision: 022 table 1. top boot memory map size (kw) blk 8-mbit memory addressing (hex) size (kw) blk 16-mbit memory addressing (hex) size (kw) blk 32-mbit memory addressing (hex) size (kw) blk 64-mbit memory addressing (hex) 422 7f000- 7ffff 4 38 ff000-fffff 470 1ff000- 1fffff 4 134 3ff000-3fffff 421 7e000- 7efff 4 37 fe000-fefff 469 1fe000- 1fefff 4 133 3fe000-3fefff 420 7d000- 7dfff 4 36 fd000-fdfff 468 1fd000- 1fdfff 4 132 3fd000-3fdfff 419 7c000- 7cfff 4 35 fc000-fcfff 467 1fc000- 1fcfff 4 131 3fc000-3fcfff 418 7b000- 7bfff 4 34 fb000-fbfff 466 1fb000- 1fbfff 4 130 3fb000-3fbfff 417 7a000- 7afff 4 33 fa000-fafff 465 1fa000- 1fafff 4 129 3fa000-3fafff 4 16 79000-79fff 4 32 f9000-f9fff 464 1f9000- 1f9fff 4 128 3f9000-3f9fff 4 15 78000-78fff 4 31 f8000-f8fff 463 1f8000- 1f8fff 4 127 3f8000-3f8fff 32 14 70000-77fff 32 30 f0000-f7fff 32 62 1f0000- 1f7fff 32 126 3f0000-3f7fff 32 13 68000-6ffff 32 29 e8000-effff 32 61 1e8000- 1effff 32 125 3e8000-3effff 32 12 60000-67fff 32 28 e0000-e7fff 32 60 1e0000- 1e7fff 32 124 3e0000-3e7fff 32 11 58000-5ffff 32 27 d8000-dffff 32 59 1d8000- 1dffff 32 123 3d8000-3dffff ... ... ... ... ... ... ... ... ... ... ... ... 32 2 10000-17fff 32 2 10000-17fff 32 2 10000-17fff 32 2 10000-17fff 32 1 8000-0ffff 32 1 08000-0ffff 32 1 08000-0ffff 32 1 08000-0ffff 32 0 0000-07fff 32 0 00000-07fff 32 0 00000-07fff 32 0 00000-07fff
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 11 table 2. bottom boot memory map size (kw) blk 8-mbit memory addressing (hex) size (kw) blk 16-mbit memory addressing (hex) size (kw) blk 32-mbit memory addressing (hex) size (kw) blk 64-mbit memory addressing (hex) 32 22 78000-7ffff 32 38 f8000-fffff 32 70 1f8000-1fffff 32 134 3f8000-3fffff 32 21 70000-77fff 32 37 f0000-f7fff 32 69 1f0000-1f7fff 32 133 3f0000-3f7fff 32 20 68000-6ffff 32 36 e8000-effff 32 68 1e8000-1effff 32 132 3e8000-3effff 32 19 60000-67fff 32 35 e0000-e7fff 32 67 1e0000-1e7fff 32 131 3e0000-3e7fff ... ... ... ... ... ... ... ... ... .... ... 32 10 18000-1ffff 32 10 18000-1ffff 32 10 18000-1ffff 32 10 18000-1ffff 32 9 10000-17fff 32 9 10000-17fff 32 9 10000-17fff 32 9 10000-17fff 32 8 08000-0ffff 32 8 08000-0ffff 32 8 08000-0ffff 32 8 08000-0ffff 4 7 07000-07fff 4 7 07000-07fff 4 7 07000-07fff 4 7 07000-07fff 4 6 06000-06fff 4 6 06000-06fff 4 6 06000-06fff 4 6 06000-06fff 4 5 05000-05fff 4 5 05000-05fff 4 5 05000-05fff 4 5 05000-05fff 4 4 04000-04fff 4 4 04000-04fff 4 4 04000-04fff 4 4 04000-04fff 4 3 03000-03fff 4 3 03000-03fff 4 3 03000-03fff 4 3 03000-03fff 4 2 02000-02fff 4 2 02000-02fff 4 2 02000-02fff 4 2 02000-02fff 4 1 01000-01fff 4 1 01000-01fff 4 1 01000-01fff 4 1 01000-01fff 4 0 00000-00fff 4 0 00000-00fff 4 0 00000-00fff 4 0 00000-00fff
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 12 order number: 290645, revision: 022 3.0 package information 3.1 bga* and vf bga package figure 2. bga* and vf bga package drawing and dimensions bottom view -bump side up e b s1 ball a1 corner top view - bump side down ball a1 corner e d side view a a2 a 1 seating y a b c d e f s2 plan 1 2 3 4 5 6 7 8 a b c d e f 123 4 5678 note: drawing not to scale millimeters inches dimens ions symbol min nom max min nom max package height a 1.000 0.0394 ball height a1 0.150 0.0059 package body thicknes s a2 0.665 0.0262 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length 8m (.25) d 7.810 7.910 8.010 package body length 16m (.25/.18/.13) 32m (.25/.18/.13) d 7.186 7.286 7.386 0.2829 0.2868 0.2908 package body length 64m (.18) d 7.600 7.700 7.800 0.2992 0.3031 0.3071 package body w idth 8m (.25) e 6.400 6.500 6.600 0.2520 0.2559 0.2598 package body w idth 16m (.25/.18/.13) 32m (.18/.13) e 6.864 6.964 7.064 0.2702 0.2742 0.2781 package body w idth 32m (.25) e 10.750 10.850 10.860 0.4232 0.4272 0.4276 package body w idth 64m (.18) e 8.900 9.000 9.100 0.3504 0.3543 0.3583 pitch e 0.750 0.0295 ball (lead) count 8m, 16m n 46 46 ball (lead) count 32m n 47 47 ball (lead) count 64m n 48 48 seating plane coplanarity y 0.100 0.0039 corner to ball a1 dis tance along d 8m (.25) s1 1.230 1.330 1.430 0.0484 0.0524 0.0563 corner to ball a1 dis tance along d 16m (.25/.18/.13) 32m (.18/.13) s1 0.918 1.018 1.118 0.0361 0.0401 0.0440 corner to ball a1 dis tance along d 64m (.18) s1 1.125 1.225 1.325 0.0443 0.0482 0.0522 corner to ball a1 dis tance along e 8m (.25) s2 1.275 1.375 1.475 0.0502 0.0541 0.0581 corner to ball a1 dis tance along e 16m (.25/.18/.13) 32m (.18/.13) s2 1.507 1.607 1.707 0.0593 0.0633 0.0672 corner to ball a1 dis tance along e 32m (.25) s2 3.450 3.550 3.650 0.1358 0.1398 0.1437 corner to ball a1 dis tance along e 64m (.18) s2 2.525 2.625 2.725 0.0994 0.1033 0.1073
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 13 3.2 tsop package notes: 1. one dimple on package denotes pin 1. 2. if two dimples, then the larger dimple denotes pin 1. 3. pin 1 will always be in the upper left corner of the package, in reference to the product mark. figure 3. tsop package drawing and dimensions dimensions a5568-02 a 0 l detail a y d c z pin 1 e d 1 b det ail b see det ail a e see d etail b a 1 a 2 seating plane see not es 1, 2, 3 and 4 family: thin small out -line package symbol millimeters inches min nom max notes min nom max notes package height a 1.200 0.047 standoff a1 0.050 0.002 package body thickness a2 0.950 1.000 1.050 0.037 0.039 0.041 lead width b 0.150 0.200 0.300 0.006 0.008 0.012 lead thickness c 0.100 0.150 0.200 0.004 0.006 0.008 plastic body length d1 18.200 18.400 18.600 0.717 0.724 0.732 package body width e 11.800 12.000 12.200 0.465 0.472 0.480 lead pitch e 0.500 0.0197 terminal dimension d 19.800 20.000 20.200 0.780 0.787 0.795 lead tip length l 0.500 0.600 0.700 0.020 0.024 0.028 lead count n 48 48 lead tip angle ? 0 3 5 0 3 5 seating plane coplanarity y 0.100 0.004 lead to package offset z 0.150 0.250 0.350 0.006 0.010 0.014
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 14 order number: 290645, revision: 022 3.3 easy bga package figure 4. easy bga package drawing and dimension millimeters inches symbol min nom max notes min nom max package height a 1.200 0.0472 ball height a 1 0.250 0.0098 package body thickness a 2 0.780 0.0307 ball (lead) width b 0.330 0.430 0.530 0.0130 0.0169 0.0209 package body width d 9.900 10.000 10.100 1 0.3898 0. 3937 0.3976 package body length e 12.900 13.000 13.100 1 0.5079 0. 5118 0.5157 pitch [e] 1.000 0.0394 ball (lead) count n 64 64 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d s 1 1.400 1.500 1.600 1 0.0551 0.0591 0.0630 corner to ball a1 distance along e s 2 2.900 3.000 3.100 1 0.1142 0.1181 0.1220 dimensions table note: (1) package dimensions are for reference only. these dimensions are estimates based on die size, and are sub j ect to chan g e. e seating plane s1 s2 e top view - ball side down bottom view - ball side up y a a1 d ball a1 corner a2 note: drawing not to scale a b c d e f g h 87654321 8 7 6 5 4 3 2 1 a b c d e f g h b ball a1 corner side view
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 15 4.0 ballout and signal descriptions the c3 device is available in 48-lead tsop, 48-ball vf bga, 48-ball bga, and easy bga packages. see figure 5 on page 15 , figure 7 on page 17 , and figure 8 on page 18 , respectively. 4.1 48-lead tsop package figure 5. 48-lead tsop package advanced+ boot block 48-lead tsop 12 mm x 20 mm top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a 16 v ccq gnd dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 21 a 20 we# rp# v pp wp# a 19 a 18 a 17 a 7 a 6 a 5 21 22 23 24 oe# gnd ce# a 0 28 27 26 25 a 4 a 3 a 2 a 1 32 m 16 m 64 m
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 16 order number: 290645, revision: 022 figure 6. mark for pin-1 indicator on 48-lead 8-mb, 16-mb and 32-mb tsop note: the topside marking on 8 mb, 16 mb, and 32 mb intel ? advanced and advanced + boot block 48l tsop products will convert to a white ink triangle as a pin 1 indicator. products without the white triangle will continue to use a dimple as a pin 1 indicator. there are no other changes in package size, materials, functionality, customer handling, or manufacturability. product will continue to meet intel stringent quality requirements. products affected are intel ordering codes shown in table 3 . table 3. 48-lead tsop extended 64 mbit extended 32 mbit extended 16 mbit extended te28f640c3tc80 te28f640c3bc80 te28f320c3td70 te28f320c3bd70 te28f160c3td70 te28f160c3bd70 te28f800c3ta90 te28f800c3ba90 te28f320c3tc70 te28f320c3bc70 te28f160c3tc80 te28f160c3bc80 te28f800c3ta110 te28f800c3ba110 te28f320c3tc90 te28f320c3bc90 te28f160c3ta90 te28f160c3ba90 te28f320c3ta100 te28f320c3ba100 te28f160c3ta110 te28f160c3ba110 te28f320c3ta110 te28f320c3ba110 current mark: new mark:
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 17 notes: 1. shaded connections indicate the upgrade address connections. intel recommends to not use routing in this area. 2. a19 denotes 16 mbit; a20 denotes 32 mbit; a21 denotes 64 mbit. 3. unused address balls are not populated. figure 7. 48-ball bga* and 48-ball vf bga chip scale package (top view, ball down) 1,2,3 13 25 47 68 a b c d e f a13 a14 a15 a16 v ccq a11 a10 a12 d14 d15 a8 we# a9 d5 d6 vpp rp# a21 d11 d12 wp# a18 a20 d2 d3 a19 a17 a6 d8 d9 a7 a5 a3 ce# d0 a4 a2 a1 a0 gnd gnd d7 d13 d4 vcc d10 d1 oe# 16m 32m 64m
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 18 order number: 290645, revision: 022 4.2 64-ball easy bga package figure 8. 64-ball easy bga package 1,2 notes: 1.a19 denotes 16 mbit; a20 denotes 32 mbit; a21 denotes 64 mbit. 2. unused address balls are not populated. 4.3 signal descriptions 1 2 3 4 5 6 7 8 a b c d e f g h top view - ball side bottom view - ball side a 1 a 6 a 18 v pp v cc gnd a 10 a 15 a 2 a 17 a 19 (1) rp# du a 20 (1) a 11 a 14 a 3 a 7 wp# we# du a 21 (1) a 12 a 13 a 4 a 5 du dq 8 dq 1 dq 9 dq 3 dq 12 dq 6 du du ce# dq 0 dq 10 dq 11 dq 5 dq 14 du du a 0 v ssq dq 2 dq 4 dq 13 dq 15 v ssq a 16 a 22 (2) oe# v ccq v cc v ssq dq 7 v ccq du du du du a 8 a 9 8 7 6 5 4 3 2 1 a b c d e f g h a 15 a 10 gnd v cc v pp a 18 a 6 a 1 a 14 a 11 a 20 (1) du rp# a 19 (1) a 17 a 2 a 13 a 12 a 21 (1) du we# wp# a 7 a 3 a 9 a 8 du du du dq 6 dq 12 dq 3 dq 9 dq 1 dq 8 du du dq 14 dq 5 dq 11 dq 10 dq 0 ce# a 16 v ssq d 15 d 13 dq 4 dq 2 v ssq a 0 du v ccq d 7 v ssq v cc v ccq oe# a 22 (2) du du du a 5 a 4 table 4. signal descriptions symbol type description a[max:0] input address inputs for memory addresses. address are internally latched during a program or erase cycle. 8 mbit: amax= a18 16 mbit: amax = a19 32 mbit: amax = a20 64 mbit: amax = a21 dq[15:0] input/ output data inputs/outputs: inputs data and commands during a write cycle; outputs data during read cycles. inputs commands to the command user interface when ce# and we# are active. data is internally latched. the data pins float to tri-state when the chip is de-selected or the outputs are disabled. ce# input chip enable: active-low input. activates the internal control logic, input buffers, decoders and sense amplifiers. ce# is active low. ce# high de-selects the memory device and reduces power consumption to standby levels. oe# input output enable: active-low input. enables the device?s outputs through the data buffers during a read operation.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 19 rp# input reset/deep power-down: active-low input. when rp# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to high-z, resets the write state machine, and minimizes current levels (i ccd ). when rp# is at logic high, the device is in standard operation. when rp# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. we# input write enable: active-low input. we# controls writes to the device. address and data are latched on the rising edge of the we# pulse. wp# input write protect: active-low input. when wp# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. when wp# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are now locked and can be unlocked and locked through software. after wp# goes low, any blocks previously marked lock-down revert to the lock-down state. see section 11.0, ?security modes? on page 49 for details on block locking. vpp input/ power program/erase power supply: operates as an input at logic levels to control complete device protection. supplies power for accelerated program and erase operations in 12 v 5% range. do not leave this pin floating. lower vpp vpplk to protect all contents against program and erase commands. set vpp = vcc for in-system read, program and erase operations. in this configuration, vpp can drop as low as 1.65 v to allow for resistor or diode drop from the system supply. apply vpp to 12 v 5% for faster program and erase in a production environment. applying 12 v 5% to vpp can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the boot blocks. vpp can be connected to 12 v for a total of 80 hours maximum. see section 11.6 for details on vpp voltage configurations. vcc power device core power supply: supplies power for device operations. vccq power output power supply: output-driven source voltage. this ball can be tied directly to v cc if operating within v cc range. gnd power ground: for all internal circuitry. all ground inputs must be connected. du ? do not use: do not use this ball. this ball must not be connected to any power supplies, signals or other balls,; it must be left floating. nc ? no connect table 4. signal descriptions symbol type description
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 20 order number: 290645, revision: 022 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these ratings are stress ratings only. operation beyond the ?operating conditions? is not recommended, and extended exposure beyond the ?operating conditions? may affect device reliability. . 5.2 operating conditions notice: specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design . parameter maximum rating notes extended operating temperature during read ?40 c to +85 c during block erase and program ?40 c to +85 c temperature under bias ?40 c to +85 c storage temperature ?65 c to +125 c voltage on any pin (except v cc and v pp ) with respect to gnd ?0.5 v to +3.7 v 1 v pp voltage (for block erase and program) with respect to gnd ?0.5 v to +13.5 v 1,2,3 v cc and v ccq supply voltage with respect to gnd ?0.2 v to +3.6 v output short circuit current 100 ma 4 notes: 1.minimum dc voltage is ?0.5 v on input/output pins. during transitions, this level may undershoot to ?2.0 v for periods <20 ns. maximum dc voltage on input/output pins is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 2.maximum dc voltage on v pp may overshoot to +14.0 v for periods <20 ns. 3.v pp program voltage is normally 1.65 v?3.6 v. connection to a 11.4 v?12.6 v supply can be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. v pp may be connected to 12 v for a total of 80 hours maximum. 4.output shorted for no more than one second. no more than one output shorted at a time. table 5. temperature and voltage operating conditions symbol parameter notes min max units t a operating temperature ?40 +85 c v cc1 v cc supply voltage 1, 2 2.7 3.6 volts v cc2 1, 2 3.0 3.6 v ccq1 i/o supply voltage 12.73.6 volts v ccq2 1.65 2.5 v ccq3 1.8 2.5 v pp1 supply voltage 1 1.65 3.6 volts
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 21 v pp2 1, 3 11.4 12.6 volts cycling block erase cycling 3 100,000 cycles notes: 1.v cc and v ccq must share the same supply when they are in the v cc1 range. 2.v cc max = 3.3 v for 0.25 m 32-mbit devices. 3.applying v pp = 11.4 v?12.6 v during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. table 5. temperature and voltage operating conditions symbol parameter notes min max units
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 22 order number: 290645, revision: 022 6.0 electrical specifications 6.1 current characteristics table 6. dc current characteristics (sheet 1 of 2) sym parameter v cc 2.7 v?3.6 v 2.7 v?2.85 v 2.7 v?3.3 v unit test conditions v ccq 2.7 v?3.6 v 1.65 v?2.5 v 1.8 v?2.5 v note typ max typ max typ max i li input load current 1,2 1 1 1a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i lo output leakage current 1,2 10 10 10 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i ccs v cc standby current for 0.13 and 0.18 micron product 1 7 15 20 50 150 250 a v cc = v cc max ce# = rp# = v ccq or during program/ erase suspend wp# = v ccq or gnd v cc standby current for 0.25 micron product 1 10 25 20 50 150 250 a i ccd v cc power-down current for 0.13 and 0.18 micron product 1,2715720720a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd rp# = gnd 0.2 v v cc power-down current for 0.25 product 1,2725725725a i ccr v cc read current for 0.13 and 0.18 micron product 1,2,3 9 18 8 15 9 15 ma v cc = v cc max v ccq = v ccq max oe# = v ih , ce# =v il f = 5 mhz, i out =0 ma inputs = v il or v ih v cc read current for 0.25 micron product 1,2,3 10 18 8 15 9 15 ma i ppd v pp deep power- down current 1 0.2 5 0.2 5 0.2 5 a rp# = gnd 0.2 v v pp v cc i ccw v cc program current 1,4 18 55 18 55 18 55 ma v pp =v pp1, program in progress 82210301030ma v pp = v pp2 (12v) program in progress i cce v cc erase current 1,4 16 45 21 45 21 45 ma v pp = v pp1, erase in progress 81516451645ma v pp = v pp2 (12v) , erase in progress
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 23 i cces / i ccws v cc erase suspend current for 0.13 and 0.18 micron product 1,4,5 7 15 50 200 50 200 a ce# = v ih, erase suspend in progress v cc erase suspend current for 0.25 micron product 10 25 50 200 50 200 a i ppr v pp read current 1,4 2 15 2 15 2 15 a v pp v cc 50 200 50 200 50 200 a v pp > v cc i ppw v pp program current 1,4 0.05 0.1 0.05 0.1 0.05 0.1 ma v pp =v pp1, program in progress 822 8 22 8 22ma v pp = v pp2 (12v) program in progress i ppe v pp erase current 1,4 0.05 0.1 0.05 0.1 0.05 0.1 ma v pp = v pp1, erase in progress 82216 451645ma v pp = v pp2 (12v) , erase in progress i ppes / i ppws v cc erase suspend current 1,4 0.2 5 0.2 5 0.2 5 a v pp = v pp1, program or erase suspend in progress 50 200 50 200 50 200 a v pp = v pp2 (12v) , program or erase suspend in progress notes: 1.all currents are in rms unless otherwise noted. typical values at nominal v cc , t a = +25 c. 2.the test conditions v cc max, v ccq max, v cc min, and v ccq min refer to the maximum or minimum v cc or v ccq voltage listed at the top of each column. v cc max = 3.3 v for 0.25 m 32-mbit devices. 3.automatic power savings (aps) reduces i ccr to approximately standby levels in static operation (cmos inputs). 4.sampled, not 100% tested. 5.i cces or i ccws is specified with device de-selected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . if the device is read while in program suspend, current draw is the sum of i ccws and i ccr . table 6. dc current characteristics (sheet 2 of 2) sym parameter v cc 2.7 v?3.6 v 2.7 v?2.85 v 2.7 v?3.3 v unit test conditions v ccq 2.7 v?3.6 v 1.65 v?2.5 v 1.8 v?2.5 v note typ max typ max typ max
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 24 order number: 290645, revision: 022 6.2 dc voltage characteristics table 7. dc voltage characteristics sym parameter v cc 2.7 v?3.6 v 2.7 v?2.85 v 2.7 v?3.3 v unit test conditions v ccq 2.7 v?3.6 v 1.65 v?2.5 v 1.8 v?2.5 v note min max min max min max v il input low voltage ?0.4 v cc * 0.22 v ?0.4 0.4 ?0.4 0.4 v v ih input high voltage 2.0 v ccq +0.3v v ccq ? 0.4v v ccq +0.3v v ccq ? 0.4v v ccq +0.3v v v ol output low voltage ?0.1 0.1 -0.1 0.1 -0.1 0.1 v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high voltage v ccq ?0.1v v ccq ? 0.1v v ccq ? 0.1v v v cc = v cc min v ccq = v ccq min i oh = ?100 a v pplk v pp lock- out voltage 1 1.0 1.0 1.0 v complete write protection v pp1 v pp during program / erase operations 1 1.65 3.6 1.65 3.6 1.65 3.6 v v pp2 1,2 11.4 12.6 11.4 12.6 11.4 12.6 v v lko v cc prog/ erase lock voltage 1.5 1.5 1.5 v v lko2 v ccq prog/ erase lock voltage 1.2 1.2 1.2 v notes: 1. erase and program are inhibited when v pp < v pplk and not guaranteed outside the valid v pp ranges of v pp1 and v pp2 . 2.applying v pp = 11.4 v?12.6 v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 25 7.0 ac characteristics 7.1 ac read characteristics table 8. read operations?8-mbit density #symparameter density 8 mbit product 70 ns 90 ns 110 ns v cc 2.7 v ? 3.6 v 3.0 v ? 3.6 v 2.7 v ? 3.6 v 3.0 v ? 3.6 v 2.7 v ? 3.6 v note min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) r1 t avav read cycle time 3,4 70 80 90 100 110 r2 t avqv address to output delay 3,4 70 80 90 100 110 r3 t elqv ce# to output delay 1,3,4 70 80 90 100 110 r4 t glqv oe# to output delay 1,3,4 20 30 30 30 30 r5 t phqv rp# to output delay 3,4 150 150 150 150 150 r6 t elqx ce# to output in low z 2,3,40 0 0 0 0 r7 t glqx oe# to output in low z 2,3,40 0 0 0 0 r8 t ehqz ce# to output in high z 2,3,4 20 20 20 20 20 r9 t ghqz oe# to output in high z 2,3,4 20 20 20 20 20 r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 2,3,40 0 0 0 0 notes: 1.oe# may be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2.sampled, but not 100% tested. 3.see figure 9, ?read operation waveform? on page 28 . 4.see figure 11, ?ac input/output reference waveform? on page 33 for timing measurements and maximum allowable input slew rate.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 26 order number: 290645, revision: 022 table 9. read operations?16-mbit density #symparameter density 16 mbit notes product 70 ns 80 ns 90 ns 110 ns v cc 2.7 v?3.6 v 2.7 v?3.6 v 3.0 v?3.6 v 2.7 v?3.6 v 3.0 v?3.6v 2.7 v?3.6v min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) r1 t avav read cycle time 70 80 80 90 100 110 3,4 r2 t avqv address to output delay 70 80 80 90 100 110 3,4 r3 t elqv ce# to output delay 70 80 80 90 100 110 1,3,4 r4 t glqv oe# to output delay 20 20 30 30 30 30 1,3,4 r5 t phqv rp# to output delay 150 150 150 150 150 150 3,4 r6 t elqx ce# to output in low z 000000 2,3,4 r7 t glqx oe# to output in low z 000000 2,3,4 r8 t ehqz ce# to output in high z 20 20 20 20 20 20 2,3,4 r9 t ghqz oe# to output in high z 20 20 20 20 20 20 2,3,4 r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 000000 2,3,4 notes: 1.oe# may be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2.sampled, but not 100% tested. 3.see figure 9, ?read operation waveform? on page 28 . 4. see figure 11, ?ac input/output reference waveform? on page 33 for timing measurements and maximum allowable input slew rate.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 27 table 10. read operations?32-mbit density # sym parameter density 32 mbit notes product 70 ns 90 ns 100 ns 110 ns v cc 2.7 v?3.6 v 2.7 v?3.6 v 3.0 v?3.3 v 2.7 v?3.3 v 3.0 v?3.3 v 2.7 v?3.3 v min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) r1 t avav read cycle time 70 90 90 100 100 110 3,4 r2 t avqv address to output delay 70 90 90 100 100 110 3,4 r3 t elqv ce# to output delay 70 90 90 100 100 110 1,3,4 r4 t glqv oe# to output delay 20 20 30 30 30 30 1,3,4 r5 t phqv rp# to output delay 150 150 150 150 150 150 3,4 r6 t elqx ce# to output in low z 000000 2,3,4 r7 t glqx oe# to output in low z 000000 2,3,4 r8 t ehqz ce# to output in high z 20 20 20 20 20 20 2,3,4 r9 t ghqz oe# to output in high z 20 20 20 20 20 20 2,3,4 r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 000000 2,3,4 notes: 1.oe# may be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2.sampled, but not 100% tested. 3.see figure 9, ?read operation waveform? on page 28 . 4. see figure 11, ?ac input/output reference waveform? on page 33 for timing measurements and maximum allowable input slew rate.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 28 order number: 290645, revision: 022 table 11. read operations ? 64-mbit density #sym parameter density 64 mbit unit product 70 ns 80 ns v cc 2.7 v?3.6 v 2.7 v?3.6 v note min max min max r1 t avav read cycle time 3,4 70 80 ns r2 t avqv address to output delay 3,4 70 80 ns r3 t elqv ce# to output delay 1,3,4 70 80 ns r4 t glqv oe# to output delay 1,3,4 20 20 ns r5 t phqv rp# to output delay 3,4 150 150 ns r6 t elqx ce# to output in low z 2,3,4 0 0 ns r7 t glqx oe# to output in low z 2,3,4 0 0 ns r8 t ehqz ce# to output in high z 2,3,4 20 20 ns r9 t ghqz oe# to output in high z 2,3,4 20 20 ns r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 2,3,4 0 0 ns notes: 1.oe# may be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2.sampled, but not 100% tested. 3.see figure 9, ?read operation waveform? on page 28 . 4.see figure 11, ?ac input/output reference waveform? on page 33 for timing measurements and maximum allowable input slew rate. figure 9. read operation waveform r5 r10 r7 r6 r9 r4 r8 r3 r1 r2 r1 a d d re ss [ a ] ce# [e] oe# [g] we# [w] data [d/q] rst# [p]
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 29 7.2 ac write characteristics table 12. write operations?8-mbit density #sym parameter density 8 mbit product 70ns 90 ns 110 ns v cc 3.0 v ? 3.6 v 80 100 2.7 v ? 3.6 v 70 90 110 note min (ns) min (ns) min (ns) min (ns) min (ns) w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 150 150 150 150 w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5 0 0 0 0 0 w3 t wlwh / t eleh we# (ce#) pulse width 4,5 45 50 60 70 70 w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,5 40 50 50 60 60 w5 t avwh / t aveh address setup to we# (ce#) going high 2,4,5 50 50 60 70 70 w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5 0 0 0 0 0 w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,5 0 0 0 0 0 w8 t whax / t ehax address hold time from we# (ce#) high 2,4,5 0 0 0 0 0 w9 t whwl / t ehel we# (ce#) pulse width high 2,4,5 25 30 30 30 30 w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 200 200 200 200 w11 t qvvl v pp hold from valid srd 3,4 0 0 0 0 0 w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4 0 0 0 0 0 w13 t qvbl wp# hold from valid srd 3,4 0 0 0 0 0 w14 t whgl we# high to oe# going low 3,4 30 30 30 30 30 notes: 1.write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 2.refer to table 22, ?command bus operations? on page 46 for valid a in or d in . 3.sampled, but not 100% tested. 4.see figure 11, ?ac input/output reference waveform? on page 33 for timing measurements and maximum allowable input slew rate. 5.see figure 10, ?write operations waveform? on page 32 .
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 30 order number: 290645, revision: 022 table 13. write operations?16-mbit density #symparameter density 16 mbit unit product 70 ns 80 ns 90 ns 110 ns v cc 3.0 v ? 3.6 v 80 100 2.7 v ? 3.6 v 70 80 90 110 note min min min min min min w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 150 150 150 150 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5 0 0 0 0 0 0 ns w3 t wlwh / t eleh we# (ce#) pulse width 1,4,5 45 50 50 60 70 70 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,5 40 40 50 50 60 60 ns w5 t avwh / t aveh address setup to we# (ce#) going high 2,4,5 50 50 50 60 70 70 ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5 0 0 0 0 0 0 ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,5 0 0 0 0 0 0 ns w8 t whax / t ehax address hold time from we# (ce#) high 2,4,5 0 0 0 0 0 0 ns w9 t whwl / t ehel we# (ce#) pulse width high 1,4,5 25 30 30 30 30 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 200 200 200 200 200 ns w11 t qvvl v pp hold from valid srd 3,4 0 0 0 0 0 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4 0 0 0 0 0 0 ns w13 t qvbl wp# hold from valid srd 3,4 0 0 0 0 0 0 ns w14 t whgl we# high to oe# going low 3,4 30 30 30 30 30 30 ns notes: 1.write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 2.refer to table 22, ?command bus operations? on page 46 for valid a in or d in . 3.sampled, but not 100% tested. 4.see figure 11, ?ac input/output reference waveform? on page 33 for timing measurements and maximum allowable input slew rate. 5.see figure 10, ?write operations waveform? on page 32 .
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 31 table 14. write operations?32-mbit density #sym parameter density 32 mbit unit product 70 ns 90 ns 100 ns 110 ns v cc 3.0 v ? 3.6 v 6 90 100 2.7 v ? 3.6 v 70 90 100 110 note min min min min min min w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 150 150 150 150 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5000000ns w3 t wlwh / t eleh we# (ce#) pulse width 1,4,5 45 60 60 70 70 70 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,5 40 40 50 60 60 60 ns w5 t avwh / t aveh address setup to we# (ce#) going high 2,4,5 50 60 60 70 70 70 ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5000000ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,5 0 0 0 0 0 0 ns w8 t whax / t ehax address hold time from we# (ce#) high 2,4,5 0 0 0 0 0 0 ns w9 t whwl / t ehel we# (ce#) pulse width high 1,4,5 25 30 30 30 30 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 200 200 200 200 200 ns w11 t qvvl v pp hold from valid srd 3,4 0 0 0 0 0 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4000000ns w13 t qvbl wp# hold from valid srd 3,4 0 0 0 0 0 0 ns w14 t whgl we# high to oe# going low 3,4 30 30 30 30 30 30 ns notes: 1.write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 2.refer to table 22, ?command bus operations? on page 46 for valid a in or d in . 3.sampled, but not 100% tested. 4.see figure 11, ?ac input/output reference waveform? on page 33 for timing measurements and maximum allowable input slew rate. 5.see figure 10, ?write operations waveform? on page 32 . 6.v cc max = 3.3 v for 32-mbit 0.25 micron product.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 32 order number: 290645, revision: 022 table 15. write operations?64-mbit density # symbol parameter density 64 mbit unit product 80 ns v cc 2.7 v ? 3.6 v note min w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5 0 ns w3 t wlwh / t eleh we# (ce#) pulse width 1,4,5 60 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,5 40 ns w5 t avwh / t aveh address setup to we# (ce#) going high 2,4,5 60 ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5 0 ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,5 0 ns w8 t whax / t ehax address hold time from we# (ce#) high 2,4,5 0 ns w9 t whwl / t ehel we# (ce#) pulse width high 1,4,5 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 ns w11 t qvvl v pp hold from valid srd 3,4 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4 0 ns w13 t qvbl wp# hold from valid srd 3,4 0 ns w14 t whgl we# high to oe# going low 3,4 30 ns notes: 1.write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 2.refer to table 22, ?command bus operations? on page 46 for valid a in or d in . 3.sampled, but not 100% tested. 4.see figure 11, ?ac input/output reference waveform? on page 33 for timing measurements and maximum allowable input slew rate. 5.see figure 10, ?write operations waveform? on page 32 . figure 10. write operations waveform w10 w1 w7 w4 w9 w9 w3 w3 w2 w6 w8 w5 a ddress [a] ce# [e] we# [w] oe# [g] data [d/q] rp# [p] vpp [v]
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 33 7.3 erase and program timings table 16. erase and program timings 7.4 ac i/o test conditions note: input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst-case speed conditions are when v cc = v cc min. symbol parameter v pp 1.65 v?3.6 v 11.4 v?12.6 v unit note typ max typ max t bwpb 4-kw parameter block word program time 1, 2, 3 0.10 0.30 0.03 0.12 s t bwmb 32-kw main block word program time 1, 2, 3 0.8 2.4 0.24 1 s t whqv1 / t ehqv1 word program time for 0.13 and 0.18 micron product 1, 2, 3 12 200 8 185 s word program time for 0.25 micron product 1, 2, 3 22 200 8 185 s t whqv2 / t ehqv2 4-kw parameter block erase time 1, 2, 3 0.5 4 0.4 4 s t whqv3 / t ehqv3 32-kw main block erase time 1, 2, 3 1 5 0.6 5 s t whrh1 / t ehrh1 program suspend latency 1,3 5 10 5 10 s t whrh2 / t ehrh2 erase suspend latency 1,3 5 20 5 20 s notes: 1.typical values measured at t a = +25 c and nominal voltages. 2.excludes external system-level overhead. 3.sampled, but not 100% tested. figure 11. ac input/output reference waveform v ccq 0v v ccq /2 v ccq /2 t e s t p o i n t s input outpu t
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 34 order number: 290645, revision: 022 note: see table 17 for component values. 7.5 device capacitance t a = 25 c, f = 1 mhz figure 12. transient equivalent testing load circuit device under test v ccq c l r 2 r 1 ou t table 17. test configuration component values for worst-case speed conditions test configuration c l (pf) r 1 (k ? )r 2 (k ? ) v ccq min standard test 50 25 25 note: c l includes jig capacitance. table 18. device capacitance symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v sampled, not 100% tested.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 35 8.0 power and reset specifications intel ? flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. the automatic power savings (aps) feature reduces power consumption when the device is selected but idle. if ce# is deasserted, the flash enters its standby mode, where current consumption is even lower. if rp# is deasserted, the flash enter deep power- down mode for ultra-low current consumption. the combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 8.1 active power (program/erase/read) with ce# at a logic - low level and rp# at a logic - high level, the device is in the active mode. refer to the dc characteristic tables for i cc current values. active power is the largest contributor to overall system power consumption. minimizing the active current could have a profound effect on system power consumption, especially for battery - operated devices. 8.2 automatic power savings (aps) automatic power savings provides low - power operation during read mode. after data is read from the memory array and the address lines are idle, aps circuitry places the device in a mode where typical current is comparable to i ccs . the flash stays in this static state with outputs valid until a new location is read. 8.3 standby power when ce# is at a logic - high level (v ih ), the flash memory is in standby mode, which disables much of the device?s circuitry and substantially reduces power consumption. outputs are placed in a high - impedance state independent of the status of the oe# signal. if ce# transitions to a logic - high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. system engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. this approach will provide a more accurate measure of application - specific power and energy requirements. 8.4 deep power-down mode the deep power-down mode is activated when rp# = v il . during read modes, rp# going low de- selects the memory and places the outputs in a high-impedance state. recovery from deep power- down requires a minimum time of t phqv for read operations, and t phwl /t phel for write operations. during program or erase modes, rp# transitioning low aborts the in-progress operation. the memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. during deep power-down, all internal circuits are switched to a low-power savings mode (rp# transitioning to v il or turning off power to the device clears the status register).
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 36 order number: 290645, revision: 022 8.5 power and reset considerations 8.5.1 power-up/down characteristics to prevent any condition that may result in a spurious write or erase operation, intel recommends to power-up vcc and vccq together. converse ly, vcc and vccq must power-down together. intel also recommends that you power-up vpp with or after vcc has reached vcc min . conversely, vpp must powerdown with or slightly before vcc. if vccq and/or vpp are not connected to the vcc supply, then vcc must attain vcc min before applying vccq and vpp. device inputs must not be driven before supply voltage reaches vcc min . power supply transitions must only occur when rp# is low. 8.5.2 rp# connected to system reset the use of rp# during system reset is important with automated program/erase devices since the system reads from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. intel recommends connecting rp# to the system cpu reset# signal to allow proper cpu/flash initialization following system reset. system designers must guard against spurious writes when v cc voltages are above v lko . because both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture pr ovides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset during power-up/ down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 8.5.3 v cc , v pp and rp# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from reset mode or after v cc transitions above v lko (lockout voltage), is read-array mode. after any program or block-erase operation is complete (even after v pp transitions down to v pplk ), the cui must be reset to read-array mode by the read array command if access to the flash-memory array is desired.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 37 8.5.4 reset specifications 8.6 power supply decoupling flash memory power-switching characteristics require careful device decoupling. system designers should consider the following three supply current issues: ? standby current levels (i ccs ) ? read current levels (i ccr ) ? transient peaks produced by falling and rising edges of ce#. table 19. reset specifications symbol parameter v cc 2.7 v ? 3.6 v unit notes min max t plph rp# low to reset during read (if rp# is tied to v cc , this specification is not applicable) 100 ns 1, 2 t plrh1 rp# low to reset during block erase 22 s 3 t plrh2 rp# low to reset during program 12 s 3 notes: 1.if t plph is < 100 ns the device may still reset but this is not guaranteed. 2.if rp# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 3.sampled, but not 100% tested. figure 13. reset operations waveforms ih v il v rp# (p) plph t ih v il v rp# (p) plph t (a) reset during read mode abort complete phqv t phw l t phel t phqv t phwl t phel t (b) reset during program or block erase, < plph t plrh t plrh t ih v il v rp# (p) plph t abort complete phqv t phw l t phel t plrh t deep power- down (c ) r eset p rogram or b lock e rase, > plph t plrh t
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 38 order number: 290645, revision: 022 transient current magnitudes depend on the device outputs? capacitive and inductive loading. two- line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and vss. these high-frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 39 9.0 device operations the intel? advanced+ boot block flash memory (c3) device uses a cui and automated algorithms to simplify program and erase operations. the cui allows for 100% cmos - level control inputs and fixed power supp lies during erasure and programming. the internal wsm completely automates program and erase operations while the cui signals the start of an operation and the status register reports device status. the cui handles the we# interface to the data and address latches as well as system status requests during wsm operation. 9.1 bus operations the intel? advanced+ boot block flash memory (c3) device performs read, program, and erase operations in - system through the local cpu or microcontroller. four control pins (ce#, oe#, we#, and rp#) manage the data flow in and out of the flash device. table 20 on page 39 summarizes these bus operations. 9.1.1 read when performing a read cycle, ce# and oe# must be asserted; we# and rp# must be deasserted. ce# is the device selection control; when active low, it enables the flash memory device. oe# is the data output control; when low, data is output on dq[15:0]. see figure 9, ?read operation waveform? on page 28 . 9.1.2 write a write cycle occurs when both ce# and we# are low; rp# and oe# are high. commands are issued to the command user interface (cui). the cui does not occupy an addressable memory location. address and data are latched on the rising edge of the we# or ce# pulse, whichever occurs first. see figure 10, ?write operations waveform? on page 32 . 9.1.3 output disable with oe# at a logic - high level (v ih ), the device outputs are disabled. dq[15:0] are placed in a high - impedance state. table 20. bus operations mode rp# ce# oe# we# dq[15:0] read v ih v il v il v ih d out write v ih v il v ih v il d in output disable v ih v il v ih v ih high-z standby v ih v ih x x high-z reset v il x x x high-z note: x = don?t care (v il or v ih )
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 40 order number: 290645, revision: 022 9.1.4 standby deselecting the device by bringing ce# to a logic - high level (v ih ) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. in standby, outputs are placed in a high-impedance state independent of oe#. if deselected during a program or erase operation, the device continues to consume active power until the program or erase operation is complete. 9.1.5 reset from read mode, rp# at v il for time t plph deselects the memory, places output drivers in a high - impedance state, and turns off all internal circuits. after return from reset, a time t phqv is required until the initial read-access outputs are valid. a delay (t phwl or t phel ) is required after return from reset before a write cycle can be initiated. after this wake - up interval, normal operation is restored. the cui resets to read-array mode, the status register is set to 0x80, and all blocks are locked. see figure 13, ?reset operations waveforms? on page 37 . if rp# is taken low for time t plph during a program or erase operation, the operation will be aborted; the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. the abort process goes through the following sequence: 1. when rp# goes low, the device shuts down the operation in progress, a process which takes time t plrh to complete. 2. after time t plrh , the part will either reset to read-array mode (if rp# is asserted during t plrh ) or enter reset mode (if rp# is deasserted after t plrh ). see figure 13, ?reset operations waveforms? on page 37 . in both cases, after returning from an aborted operation, the relevant time t phqv or t phwl /t phel must be observed before a read or write operation is initiated, as discussed in the previous paragraph. however, in this case, these delays are referenced to the end of t plrh rather than when rp# goes high. as with any automated device, it is important to assert rp# during a system reset. when the system comes out of reset, the processor reads from the flash memory. automated flash memories provide status information when read during program or block-erase operations. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. intel ? flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 41 10.0 modes of operation 10.1 read mode the flash memory has four read modes (read array, read identifier, read status, and cfi query) and two write modes (program and erase). three additional modes (erase suspend to program, erase suspend to read, and program suspend to read) are available only during suspended operations. table 22, ?command bus operations? on page 46 and table 23, ?command codes and descriptions? on page 47 summarize the commands used for these modes. appendix a, ?write state machine states? on page 54 is a comprehensive chart showing the state transitions. 10.1.1 read array when rp# transitions from v il (reset) to v ih , the device defaults to read-array mode and will respond to the read-control inputs (ce#, address inputs, and oe#) without any additional cui commands. when the device is in read array mode, four control signals control data output. ? we# must be logic high (v ih ) ? ce# must be logic low (v il ) ? oe# must be logic low (v il ) ? rp# must be logic high (v ih ) in addition, the address of the desired location must be applied to the address pins. if the device is not in read-array mode, as would be the case after a program or erase operation, the read array command (0xff) must be issued to the cui before array reads can occur. 10.1.2 read identifier the read-identifier mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. the device is switched to this mode by issuing the read identifier command (0x90). once in this mode, read cycles from addresses shown in table 21 retrieve the specified information. to return to read-array mode, issue the read array command (0xff).
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 42 order number: 290645, revision: 022 10.1.3 cfi query the cfi query mode outputs common flash interface (cfi) data after issuing the read query command (0x98). the cfi data structure contains information such as block size, density, command set, and electrical specifications. once in this mode, read cycles from addresses shown in appendix c, ?common flash interface,? retrieve the specified information. to return to read-array mode, issue the read array command (0xff). 10.1.4 read status register the status register indicates the status of de vice operations and the success/failure of that operation. the read status register (0x70) command causes subsequent reads to output data from the status register until another command is issued. to return to reading from the array, issue a read array (0xff) command. the status register bits are output on dq[7:0]. the upper byte, dq[15:8], outputs 0x00 when a read status register command is issued. table 21. device identification codes item address 1 data description base offset manufacturer id block 0x00 0x0089 device id block 0x01 0x88c0 8-mbit top boot device 0x88c1 8-mbit bottom boot device 0x88c2 16-mbit top boot device 0x88c3 16-mbit bottom boot device 0x88c4 32-mbit top boot device 0x88c5 32-mbit bottom boot device 0x88cc 64-mbit top boot device 0x88cd 64-mbit bottom boot device block lock status 2 block 0x02 dq0 = 0b0 block is unlocked dq0 = 0b1 block is locked block lock-down status 2 block 0x02 dq1 = 0b0 block is not locked-down dq1 = 0b1 block is locked down protection register lock status block 0x80 lock data protection register block 0x81 - 0x88 register data multiple reads required to read the entire 128-bit protection register. notes: 1.the address is constructed from a base address plus an offset. for example, to read the block lock status for block number 38 in a bottom boot device, set the address to 0x0f8000 plus the offset (0x02), i.e. 0x0f8002. then examine dq0 of the data to determine if the block is locked. 2.see section 11.2, ?reading block-lock status? on page 50 for valid lock status.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 43 the contents of the status register are latched on the falling edge of oe# or ce# (whichever occurs last) which prevents possible bus errors that might occur if status register contents change while being read. ce# or oe# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. when the wsm is active, sr[7] will indicate the status of the wsm; the remaining bits in the status register indicate whether the wsm was successful in performing the preferred operation see table 24, ?status register bit definition? on page 48 . 10.1.4.1 clear status register the wsm can set status register bits 1 through 7 and can clear bits 2, 6, and 7, but the wsm cannot clear status register bits 1, 3, 4 or 5. because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through the clear status register (0x50) command. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. clear the status register before beginning another command or sequence. the read array command must be issued before data can be read from the memory array. resetting the device also clears the status register. 10.2 program mode programming is executed using a two - write cycle sequence. the program setup command (0x40) is issued to the cui, followed by a second write that specifies the address and data to be programmed. the wsm will execute a sequence of internally timed events to program preferred bits of the addressed location, then verify the bits are sufficiently programmed. programming the memory results in specific bits within an address location being changed to a ?0.? if users attempt to program ?1?s, the memory cell contents do not change and no error occurs. the status register indicates programming status. while the program sequence executes, status bit 7 is ?0.? the status register can be polled by toggling either ce# or oe#. while programming, the only valid commands are read status register, program suspend, and program resume. when programming is complete, the program-status bits must be checked. if the programming operation was unsuccessful, sr[4] is set to indicate a program failure. if sr[3] is set, then v pp was not within acceptable limits, and the wsm did not execute the program command. if sr[1] is set, a program operation was attempted on a locked block and the operation was aborted. the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the cui to read-array mode. 10.2.1 12-volt production programming when v pp is between 1.65 v and 3.6 v, all program and erase current is drawn through the vcc pin. note: if v pp is driven by a logic signal, v ih min = 1.65 v. that is, v pp must remain above 1.65 v to perform in-system flash modifications.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 44 order number: 290645, revision: 022 when v pp is connected to a 12 v power supply, the device draws program and erase current directly from the vpp pin. this eliminates the need for an external switching transistor to control v pp . figure 16 on page 53 shows examples of how the flash power supplies can be configured for various usage models. the 12 v v pp mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. you cna apply 12 v to vpp during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. vpp may be connected to 12 v for a total of 80 hours maximum. stressing the device beyond these limits may cause permanent damage. 10.2.2 suspending and resuming program the program suspend command halts an in - progress program operation so that data can be read from other locations of memory. once the pr ogramming process starts, issuing the program suspend command to the cui requests that the wsm suspend the program sequence at predetermined points in the program algorithm. the device continues to output status register data after the program suspend command is issued. polling sr[7] and sr[2] will determine when the program operation has been suspended (both will be set to ?1?). the program-suspend latency is specified with t whrh1 /t ehrh1 . a read-array command can now be issued to the cui to read data from blocks other than that which is suspended. the only other valid commands while program is suspended are read status register, read identifier, cfi query, and program resume. after the program resume command is issued to the flash memory, the wsm will continue with the programming process and sr[2] and sr[7] will automatically be cleared. the device automatically outputs status register data when read (see figure 18, ?program suspend / resume flowchart? on page 57 ) after the program resume command is issued. v pp must remain at the same v pp level used for program while in program-suspend mode. rp# must also remain at v ih . 10.3 erase mode to erase a block, issue the erase set - up and erase confirm commands to the cui, along with an address identifying the block to be erased. this address is latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to ?1.? only one block can be erased at a time. the wsm will execute a sequence of internally timed events to program all bits within the block to ?0,? erase all bits within the block to ?1,? then verify that all bits within the block are sufficiently erased. while the erase executes, status bit 7 is a ?0.? when the status register indicates that erasure is complete, check the erase-status bit to verify that the erase operation was successful. if the erase operation was unsuccessful, sr[5] of the status register will be set to a ?1,? indicating an erase failure. if v pp is not within acceptable limits after the erase confirm command was issued, the wsm will not execute the erase sequence; instead, sr[5] of the status register is set to indicate an erase error, and sr[3] is set to a ?1? to identify that v pp supply voltage is not within acceptable limits. after an erase operation, clear the status register (0x50) before attempting the next operation. any cui instruction can follow after erasure is completed; however, to prevent inadvertent status- register reads, intel recommends that you place the flash in read-array mode after the erase is complete.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 45 10.3.1 suspending and resuming erase since an erase operation requires on the order of seconds to complete, an erase suspend command is provided to allow erase - sequence interruption to read data from?or program data to? another block in memory. once the erase sequence is started, issuing the erase suspend command to the cui suspends the erase sequence at a predetermined point in the erase algorithm. the status register indicates if/when the erase operation has been suspended. erase-suspend latency is specified by t whrh2 /t ehrh2 . a read array or program command can now be issued to the cui to read/program data from/to blocks other than that which is suspended. this nested program command can subsequently be suspended to read yet another location. the only valid commands while erase is suspended are read status register, read identifier, cfi query, program setup, program resume, erase resume, lock block, unlock block, and lock-down block. during erase-suspend mode, the device can be placed in a pseudo - standby mode by taking ce# to v ih , which reduces active current consumption. erase resume continues the erase sequence when ce# = v il . similar to the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 46 order number: 290645, revision: 022 bus operations are defined in table 20, ?bus operations? on page 39 . table 22. command bus operations command notes first bus cycle second bus cycle oper addr data oper addr data read array 1,3 write x 0xff read identifier 1,3 write x 0x90 read ia id cfi query 1,3 write x 0x98 read qa qd read status register 1,3 write x 0x70 read x srd clear status register 1,3 write x 0x50 program 2,3 write x 0x40/ 0x10 write pa pd block erase/confirm 1,3 write x 0x20 write ba d0h program/erase suspend 1,3 write x 0xb0 program/erase resume 1,3 write x 0xd0 lock block 1,3 write x 0x60 write ba 0x01 unlock block 1,3 write x 0x60 write ba 0xd0 lock-down block 1,3 write x 0x60 write ba 0x2f protection program 1,3 write x 0xc0 write pa pd x = "don?t care" pa = prog addr ba = block addr ia = identifier addr. qa = query addr. srd = status reg. data pd = prog data id = identifier data qd = query data notes: 1.following the read identifier or cfi query commands, read operations output device identification data or cfi query information, respectively. see section 10.1.2 and section 10.1.3 . 2.either 0x40 or 0x10 command is valid, but the intel standard is 0x40. 3.when writing commands, the upper data bus [dq8-dq15] should be either v il or v ih , to minimize current draw.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 47 table 23. command codes and descriptions code (hex) device mode command description ff read array this command places the device in read-array mode, which outputs array data on the data pins. 40 program set-up this is a two - cycle command. the first cycle prepares the cui for a program operation. the second cycle latches addresses and data information and initiates the wsm to execute the program algorithm. the flash outputs status register data when ce# or oe# is toggled. a read array command is required after programming to read array data. see section 10.2, ?program mode? on page 43 . 20 erase set-up this is a two - cycle command. it prepares the cui for the erase confirm command. if the next command is not an erase confirm command, then the cui will (a) set both sr.4 and sr.5 to ?1,? (b) place the device into the read-status register mode, and (c) wait for another command. see section 10.3, ?erase mode? on page 44 . d0 erase confirm program/erase resume unlock block if the previous command was an erase set-up command, then the cui will close the address and data latches and begin erasing the block indicated on the address pins. during program/erase, the device will respond only to the read status register, program suspend and erase suspend commands, and will output status register data when ce# or oe# is toggled. if a program or erase operation was previously suspended, this command will resume that operation. if the previous command was block unlock set-up, the cui will latch the address and unlock the block indicated on the address pins. if the block had been previously set to lock-down, this operation will have no effect. (see section 11.1 ) b0 program suspend erase suspend issuing this command will begin to suspend the currently executing program/erase operation. the status register will indicate when the operation has been successfully suspended by setting either the program-suspend sr[2] or erase-suspend sr[6] and the wsm status bit sr[7] to a ?1? (ready). the wsm will continue to idle in the suspend state, regardless of the state of all input- control pins except rp#, which will immediately shut down the wsm and the remainder of the chip if rp# is driven to v il . see sections 3.2.5.1 and 3.2.6.1. 70 read status register this command places the device into read-status register mode. reading the device will output the contents of the status register, regardless of the address presented to the device. the device automatically enters this mode after a program or erase operation has been initiated. see section 10.1.4, ?read status register? on page 42 . 50 clear status register the wsm can set the block-lock status sr[1], v pp status sr[3], program status sr[4], and erase- status sr[5] bits in the status register to ?1,? but it cannot clear them to ?0.? issuing this command clears those bits to ?0.? 90 read identifier this command puts the device into the read-identifier mode so that reading the device will output the manufacturer/device codes or block-lock status. see section 10.1.2, ?read identifier? on page 41 . 60 block lock, block unlock, block lock-down set-up this command prepares the cui for block-locking changes. if the next command is not block unlock, block lock, or block lock-down, then the cui will set both the program and erase-status register bits to indicate a command-sequence error. see section 11.0, ?security modes? on page 49 . 01 lock-block if the previous command was lock set-up, the cui will latch the address and lock the block indicated on the address pins. (see section 11.1 ) 2f lock-down if the previous command was a lock-down set-up command, the cui will latch the address and lock-down the block indicated on the address pins. (see section 11.1 ) 98 cfi query this command puts the device into the cfi-query mode so that reading the device will output common flash interface information. see section 10.1.3 and appendix c, ?common flash interface? . c0 protection program set-up this is a two-cycle command. the first cycle prepares the cui for a program operation to the protection register. the second cycle latches addresses and data information and initiates the wsm to execute the protection program algorithm to the protection register. the flash outputs status register data when ce# or oe# is toggled. a read array command is required after programming to read array data. see section 11.5 . 10 alt. prog set-up operates the same as program set - up command. (see 0x40/program set-up) 00 invalid/ reserved unassigned commands should not be used. intel reserves the right to redefine these codes for future functions. note: see appendix a, ?write state machine states? for mode transition information.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 48 order number: 290645, revision: 022 table 24. status register bit definition wsms ess es ps vpps pss bls r 76543210 notes: sr[7] write state machine status (wsms) 1 = ready 0=busy before checking program or erase- status bits, check the write state machine bit first to determine word program or block erase completion. sr[6] = erase - suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to ?1.? ess bit remains set to ?1? until an erase resume command is issued. sr[5] = erase status (es) 1 = error in block erase 0 = successful block erase when this bit is set to ?1,? wsm has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. sr[4] = program status (ps) 1 = error in programming 0 = successful programming when this bit is set to ?1,? wsm has attempted but failed to program a word/byte. sr[3] = v pp status (vpps) 1=v pp low detect, operation abort 0=v pp ok the v pp status bit does not provide continuous indication of v pp level. the wsm interrogates v pp level only after the program or erase command sequences have been entered and informs the system if v pp has not been switched on. the v pp is also checked before the operation is verified by the wsm. the v pp status bit is not guaranteed to report accurate feedback between v pplk and v pp1 min. sr[2] = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when program suspend is issued, wsm halts execution and sets both wsms and pss bits to ?1.? pss bit remains set to ?1? until a program resume command is issued. sr[1] = block lock status 1 = prog/erase attempted on a locked block; operation aborted. 0 = no operation to locked blocks if a program or erase operation is attempted to one of the locked blocks, this bit is set by the wsm. the operation specified is aborted and the device is returned to read status mode. sr[0] = reserved for future enhancements (r) this bit is reserved for future use and should be masked out when polling the status register. note: a command-sequence error is indicated when sr[4], sr[5], and sr[7] are set.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 49 11.0 security modes 11.1 flexible block locking the intel? advanced+ boot block flash memory (c3) device offers an instant, individual block- locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. this locking scheme offers two levels of protection. the first level allows software-only control of block locking (useful for data blocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). the following sections will discuss the operation of the locking system. the term ?state [abc]? will be used to specify locking states; for example, ?state [001],? where a = value of wp#, b = bit d1 of the block lock status register, and c = bit d0 of the block lock status register. figure 14, ?block locking state diagram? on page 49 displays all of the possible locking states. figure 14. block locking state diagram [x00] [x01] power-up/reset unlocked locked [011] [111] [110] locked- down 4,5 software locked [011] hardware locked 5 unlocked wp# hardware control notes: 1. [a,b,c] represents [wp#, d1, d0]. x = don?t care. 2. d1 indicates block lock-down status. d1 = ?0?, lock-down has not been issued to this block. d1 = ?1?, lock-down has been issued to this block. 3. d0 indicates block lock status. d0 = ?0?, block is unlocked. d0 = ?1?, block is locked. 4. locked-down = hardware + software locked. 5. [011] states should be tracked by system software to determine difference between hardware locked and locked-down states. software block lock (0x60/0x01) or software block unlock (0x60/0xd0) software block lock-down (0x60/0x2f) wp# hardware control
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 50 order number: 290645, revision: 022 11.1.1 locking operation the locking status of each block can be set to locked, unlocked, or lock-down, each of which will be described in the following sections. see figure 14, ?block locking state diagram? on page 49 and figure 21, ?locking operations flowchart? on page 60 . the following paragraph concisely summarizes the locking functionality. 11.1.1.1 locked state the default state of all blocks upon power-up or reset is locked (states [001] or [101]). locked blocks are fully protected from alteration. any program or erase operations attempted on a locked block will return an error on bit sr[1]. the state of a locked block can be changed to unlocked or lock down using the appropriate software commands. an unlocked block can be locked by writing the lock command sequence, 0x60 followed by 0x01. 11.1.1.2 unlocked state unlocked blocks (states [000], [100], [110]) can be programmed or erased. all unlocked blocks return to the locked state when the device is reset or powered down. the status of an unlocked block can be changed to locked or locked down using the appropriate software commands. a locked block can be unlocked by writing the unlock command sequence, 0x60 followed by 0xd0. 11.1.1.3 lock-down state blocks that are locked-down (state [011]) are protected from program and erase operations (just like locked blocks), but their protection status cannot be changed using software commands alone. a locked or unlocked block can be locked down by writing the lock-down command sequence, 0x60 followed by 0x2f. locked-down blocks revert to the locked state when the device is reset or powered down. the lock-down function depends on the wp# input pin. when wp# = 0, blocks in lock down [011] are protected from program, erase, and lock status changes. when wp# = 1, the lock-down function is disabled ([111]), and locked-down bl ocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. these blocks can then be relocked [111] and unlocked [110] as required while wp# remains high. when wp# goes low, blocks that were previously locked down return to the lock-down state [011], regardless of any changes made while wp# was high. device reset or power-down resets all blocks, including those in lock-down, to locked state. 11.2 reading block-lock status the lock status of each block can be read in read -identifier mode of the device by issuing the read- identifier command (0x90). subsequent reads at block address + 0x00002 will output the lock status of that block. the lock status is represented by dq0 and dq1: ? dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when entering lock down. ? dq1 indicates lock-down status and is set by the lock-down command. it cannot be cleared by software?only by device reset or power-down. see table 21, ?device identification codes? on page 42 for block-status information.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 51 11.3 locking operations during erase suspend changes to block-lock status can be performed during an erase-suspend by using the standard locking command sequences to unlock, lock, or lock down a block. this operation is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase operation, first issue the erase suspend command (0xb0), and then check the status register until it indicates that the erase operation has been suspended. next, write the preferred lock command sequence to a block and the lock status will be changed. after completing any preferred lock, read, or program operations, resume the erase operation with the erase resume command (0xd0). if a block is locked or locked down during a suspended erase of the same block, the locking status bits will be changed immediately. but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. refer to appendix a, ?write state machine states? on page 54 for detailed information on which commands are valid during erase suspend. 11.4 status register error checking using nested-locking or program-command seque nces during erase suspend can introduce ambiguity into status register results. since locking changes are performed using a two-cycle command sequence, for example, 0x60 followed by 0x01 to lock a block. following the block lock, block unlock, or block lock-down setup command (0x60) with an invalid command will produce a lock-command error (sr[4] and sr[5] will be set to 1) in the status register. if a lock-command error occurs during an erase suspend, sr[4] and sr[5] will be set to 1 and will remain at 1 after the erase is resumed. when erase is complete, any possible error during the erase cannot be detected by the status register because of the previous lock-command error. a similar situation happens if an error occurs during a program-operation error nested within an erase suspend. 11.5 128-bit protection register the c3 device architecture includes a 128-bit protection register than can be used to increase the security of a system design. for example, the num ber contained in the protection register can be used to ?match? the flash component with other system components, such as the cpu or asic, preventing device substitution. application note, ap-657 designing with the advanced+ boot block flash memory architecture, contains additional application information. the 128 bits of the protection register are divided into two 64-bit segments. one of the segments is programmed at the intel factory with a unique 64-bit number, which is unchangeable. the other segment is left blank for customer designs to program, as preferred. once the customer segment is programmed, it can be locked to prevent further programming.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 52 order number: 290645, revision: 022 11.5.1 reading the protection register the protection register is read in the read-identifier mode. the device is switched to this mode by issuing the read identifier command (0x90). once in this mode, read cycles from addresses shown in figure 15, ?protection register mapping ? retrieve the specified information. to return to read- array mode, issue the read array command (0xff). 11.5.2 programming the protection register the protection register bits are programmed us ing the two-cycle protection program command. the 64-bit number is programmed 16 bits at a time. first, issue the protection program setup command, 0xc0. the next write to the device will latch in address and data and program the specified location. the allowable addresses are listed in table 21, ?device identification codes? on page 42 . see figure 22, ?protection register programming flowchart? on page 61 . attempting to program to a previously locked protection register segment will result in a status register error (program error bit sr[4] and lock error bit sr[1] will be set to 1). note: do not attempt to address protection program commands outside the defined protection register address space; status register can be indeterminate. 11.5.3 locking the protection register the user-programmable segment of the protection register is lockable by programming bit 1 of the pr-lock location to 0. see figure 15, ?protection register mapping? on page 52 . bit 0 of this location is programmed to 0 at the intel factory to protect the unique device number. this bit is set using the protection program command to program 0xfffd to the pr-lock location. after these bits have been programmed, no further changes can be made to the values stored in the protection register. protection program commands to a locked section will result in a status register error (program error bit sr[4] and lock error bit sr[1] will be set to 1). protection register lockout state is not reversible. 11.6 v pp program and erase voltages the c3 device provides in-system programming and erase in the 1.65 v?3.6 v range. for fast production programming, 12 v programming can be used. see figure 16, ?example power supply configurations? on page 53 . figure 15. protection register mapping 0x88 0x85 64-bit segment (user-programmable) 0x84 0x81 0x80 pr lock register 0 64-bit segment (intel factory-programmed) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit protection register 0
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 53 11.6.1 program protection in addition to the flexible block locking, the v pp programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. when v pp is below or equal to v pplk , any program or erase operation will result in an error, prompting the corresponding status register bit (sr[3]) to be set. 0645_06 note: 1.a resistor can be used if the v cc supply can sink adequate current based on resistor value. see ap-657 designing with the advanced+ boot block flash memory architecture for details. figure 16. example power supply configurations v cc v pp 12 v fast programming absolute write protection with v pp v pplk system supply 12 v supply 10 k ? v cc v pp system supply 12 v supply low voltage and 12 v fast programming v cc v pp system supply prot# (logic signal) v cc v pp system supply low-voltage programming low-voltage programming absolute write protection via logic signal (note 1)
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 54 order number: 290645, revision: 022 appendix a write state machine states table 25 and table 26 show the write state machine command state transitions based on incoming commands. table 25. write state machine states command input (and next state) current state sr.7 data when read read array (ffh) program setup (10/ 40h) erase setup (20h) erase confirm (d0h) prog/ers suspend (b0h) prog/ers resume (d0) read status (70h) clear status (50h) read array ?1? array read array prog. setup ers. setup read array read sts. read array read status ?1? status read array prog. setup ers. setup read array read sts. read array read config. ?1? config read array prog. setup ers. setup read array read sts. read array read query ?1? cfi read array prog. setup ers. setup read array read sts. read array lock setup ?1? status lock command error lock (done) lock cmd. error lock (done) lock cmd. error lock cmd. error ?1? status read array prog. setup ers. setup read array read sts. read array lock oper. (done) ?1? status read array prog. setup ers. setup read array read sts. read array prot. prog. setup ?1? status protection register program prot. prog. (not done) ?0? status protection register program (not done) prot. prog. (done) ?1? status read array prog. setup ers. setup read array read sts. read array prog. setup ?1? status program program (not done) ?0? status program (not done) prog. sus. status program (not done) prog. susp. status ?1? status prog. sus. read array program suspend read array prog. (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array prog. susp. read array ?1? array prog. sus. read array program suspend read array prog. (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array prog. susp. read config ?1? config prog. sus. read array program suspend read array prog. (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array prog. susp. read query ?1? cfi prog. sus. read array program suspend read array prog. (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array program (done) ?1? status read array prog. setup ers. setup read array read status read array erase setup ?1? status erase command error erase (not done) erase cmd. error erase (not done) erase command error erase cmd. error ?1? status read array prog. setup ers. setup read array read status read array erase (not done) ?0? status erase (not done) erase sus. status erase (not done) ers. susp. status ?1? status erase sus. read array prog. setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array erase susp. array ?1? array erase sus. read array prog. setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array ers. susp. read config ?1? config erase sus. read array prog. setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array ers. susp. read query ?1? cfi erase sus. read array prog. setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array erase (done) ?1? status read array prog. setup ers. setup read array read sts. read array
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 55 table 26. write state machine states, continued command input (and next state) current state read config (90h) read query (98h) lock setup (60h) prot. prog. setup (c0h) lock confirm (01h) lock down confirm (2fh) unlock confirm (d0h) read array read config. read query lock setup prot. prog. setup read array read status read config. read query lock setup prot. prog. setup read array read config. read config. read query lock setup prot. prog. setup read array read query read config. read query lock setup prot. prog. setup read array lock setup locking command error lock operation (done) lock cmd. error read config. read query lock setup prot. prog. setup read array lock oper. (done) read config. read query lock setup prot. prog. setup read array prot. prog. setup protection register program prot. prog. (not done) protection register program (not done) prot. prog. (done) read config. read query lock setup prot. prog. setup read array prog. setup program program (not done) program (not done) prog. susp. status prog. susp. read config. prog. susp. read query program suspend read array program (not done) prog. susp. read array prog. susp. read config. prog. susp. read query program suspend read array program (not done) prog. susp. read config. prog. susp. read config. prog. susp. read query program suspend read array program (not done) prog. susp. read query. prog. susp. read config. prog. susp. read query program suspend read array program (not done) program (done) read config. read query lock setup prot. prog. setup read array erase setup erase command error erase (not done) erase cmd. error read config. read query lock setup prot. prog. setup read array erase (not done) erase (not done) erase susp. status ers. susp. read config. erase suspend read query lock setup erase suspend read array erase (not done) erase suspend array ers. susp. read config. erase suspend read query lock setup erase suspend read array erase (not done) eras sus. read config erase suspend read config. erase suspend read query lock setup erase suspend read array erase (not done) eras sus. read query erase suspend read config. erase suspend read query lock setup erase suspend read array erase (not done) ers.(done) read config. read query lock setup prot. prog. setup read array
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 56 order number: 290645, revision: 022 appendix b flow charts figure 17. word program flowchart pr ogram suspend loop start wr ite 0x40, wor d addr ess wr ite d ata, wor d addr ess read status register sr[7] = full status check (if desired) progr am complete suspend? 1 0 no yes word program procedure repeat for subsequent wor d pr ogr am oper ations. full status register check can be done after each pr ogr am, or after a sequence of pr ogram oper ations. wr ite 0xff after the last operation to set to the read arr ay state. comments bus operat ion command data = 0x40 addr = location to pr ogr am wr ite program setup data = data to pr ogram addr = location to pr ogr am wr ite data status register data: toggle ce# or oe# to update status register read none check sr[7] 1 = wsm ready 0 = wsm busy idle none (s etup) (confirm) full status check procedure read status register progr am successful sr[3] = sr[1] = 0 0 sr[4] = 0 1 1 1 v pp range error device pr otect err or progr am error sr[3] m ust be clear ed befor e the wr ite state machine will allow fur ther progr am attempts. if an er ror is detected, clear the status register befor e continuing operations - only the clear staus register com mand clear s the status register err or bits. idle idle bus operat ion none none command check sr[3]: 1 = v pp error check sr[4]: 1 = data pr ogr am err or comments idle none check sr[1]: 1 = block locked; operation abor ted
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 57 figure 18. program suspend / resume flowchart r ead status register sr[7] = sr[2] = read array data program completed done reading program resumed r ead ar r ay data 0 no 0 yes 1 1 program suspend / resume proce dure wr ite program resume data = 0xd0 addr = any address bus operation command comments wr ite program suspend data = 0xb0 addr = any address idle none check sr[7]: 1 = wsm r eady 0 = wsm busy idle none check sr[2]: 1 = pr ogr am suspended 0 = pr ogr am com pleted wr ite read array data = 0xff addr = any address read none read ar r ay data fr om bl ock other than the one being program med read none status register data toggle ce# or oe# to update status r egi ster addr = any address wr ite 0xff (read array) wr ite 0xd 0 any address (program resume) wr ite 0xff (read array) wr ite read status data = 0x70 addr = any address start wr ite 0xb0 any address (program suspend) write 0x70 any address (read status)
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 58 order number: 290645, revision: 022 figure 19. erase suspend / resume flowchart erase completed read array data 0 0 1 1 start read status r egister sr[7] = sr[6] = er ase resumed done r eading write write idle idle write erase suspend read ar r ay or pr ogr am none none pr ogr am resume data = 0xb0 addr = any address d ata = 0xff or 0x40 addr = any address check sr[7]: 1 = wsm r eady 0 = wsm busy check sr[6]: 1 = er ase suspended 0 = erase completed data = 0xd0 addr = any address bus operation command comments r ead none status register data. toggle c e# or oe# to update status register ; addr = any addr ess read or write none r ead ar r ay or pr ogr am data fr om /to block other than the one being erased erase suspend / resume procedure wr ite 0x70, any addr ess (read status) wr ite 0xb0, any addr ess (erase suspend) wr ite 0xd 0, any addr ess (e rase re sum e) wri te 0xff (read a rray) write read status data = 0x70 addr = any address read arr ay data wr i te 0xf f 0 (read array) 1
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 59 figure 20. block erase flowchart start full erase status check procedure r epeat for subsequent block er asur es. full status regi ster check can be done after each block er ase or after a sequence of block er asur es. wr ite 0xff after the last oper ation to enter r ead arr ay m ode. sr[1,3] must be cleared before the write state machine will allow further erase attem pts. only the cl ear status register com m and clear s sr[1, 3, 4, 5]. if an error is detected, clear the status register before attempting an erase retry or other error recovery. no suspend erase 1 0 0 0 1 1,1 1 1 0 yes suspend erase loop 0 wri te 0x20, bl ock addr ess wri te 0xd 0, bl ock addr ess read status r egister sr[7] = full erase status check (if desired) block erase complete read status r egister block erase successful sr[1] = block locked error block erase procedure bus operation command comments wr ite block erase setup data = 0x20 addr = block to be er ased ( ba) wr ite erase c onfir m data = 0xd0 addr = block to be er ased ( ba) r ead none status r egi ster data. toggle c e# or oe# to update status r egister data idle none c heck sr[7]: 1 = wsm r eady 0 = wsm busy bus operation command comments sr[3] = v pp range error sr[4,5] = command sequence er r or sr[5] = block erase error idle none c heck sr[3]: 1 = v pp range error idle none check sr[4,5]: both 1 = c om m and sequence er r or idle none c heck sr[5]: 1 = block erase err or idle none c heck sr[1]: 1 = attem pted er ase of l ocked bl ock; er ase abor ted. (b l ock e rase) (erase confirm)
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 60 order number: 290645, revision: 022 figure 21. locking operations flowchart no start wr ite 0x60, block address write 0x90 read bl ock lock status locking change? lock change complete write either 0x01/0xd 0/0x2f , block address wr ite 0xff any address yes wr ite wr ite wr ite (optional) read (optional) idle (optional) wr ite lock setup lock, unlock, or lock-d ow n confirm read device id block lock status none read array data = 0x60 addr = any address d ata = 0x01 (block lock) 0xd0 (block unlock) 0x2f (lock-down block) addr = bl ock to l ock/unlock/lock- dow n data = 0x90 addr = any address block lock status data addr = bl ock addr ess + offset 2 confirm locking change on d[1,0] . data = 0xff addr = any addr ess bus operation command comments locking operations procedure (lock confi rm) (read device id) (read array) o ptional (lock s etup)
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 61 figure 22. protection register programming flowchart full status check procedure pr ogr am pr otection register oper ation addresses m ust be within the protection register addr ess space. addr esses outside this space will r eturn an er ror . repeat for subsequent pr ogr amming oper ations. full status register check can be done after each pr ogr am, or after a sequence of program oper ations. wr ite 0xff after the last operation to set read ar ray state. sr[3] m ust be cleared befor e the write state machine will allow fur ther program attem pts. only the clear staus register comm and clear s sr[1, 3, 4]. if an er ror is detected, clear the status register before attem pting a pr ogram retr y or other err or recover y. 1 0 1 1 protection register programming procedure start write 0xc0, pr address write pr address & data read status register sr[7] = full status check (if desir ed) pr ogram complete read status register data pr ogram successful sr[3], sr[4] = v pp range er r or program er ror register locked; program aborted idle idle bus operation none none command check sr[1], sr[3], sr[4]: 0,1,1 = v pp range er r or check sr[1], sr[3], sr[4]: 0,0,1 = pr ogr amming err or comments wr ite wr ite idle program pr setup pr otection program none data = 0xc0 addr = fir st locati on to pr ogr am data = data to program addr = location to pr ogram check sr[7]: 1 = wsm ready 0 = wsm busy bus operation command comments read none status register data. toggle ce# or oe# to update status register data idle none check sr[1], sr[3], sr[4]: 1,0,1 = block locked; operation abor ted (program setup) (confirm data) 0 0 sr[3], sr[4] = 0 sr[3], sr[4] = 1
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 62 order number: 290645, revision: 022 appendix c common flash interface this appendix defines the data structure or ?database? returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software detects which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. c.1 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the device?s cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq0-dq7) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 0x10, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii ?q? and ?r,? appear on the low byte at word addresses 0x10 and 0x11. this cfi-compliant device outputs 0x00 data on upper bytes. the device outputs ascii ?q? in the low byte (dq0-dq7) and 0x00 in the high byte (dq8-dq15). at query addresses containing two or more bytes of information, the least-significant data byte is presented at the lower address, and the most-significant data byte is presented at the higher address. for tables in this appendix, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word-wide devices is always ?0x00,? the leading ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 0x00 on the upper byte in this mode. table 27. summary of query structure output as a function of device and mode device hex offset hex code ascii value device addresses 00010: 51 "q" 00011: 52 "r" 00012: 59 "y"
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 63 c.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or ?database.? table 29 summarizes the structure sub-sections and address locations. table 28. example of query structure output of x16 devices word addressing: offset hex code value a[x-0] dq[16:0] 0x00010 0051 "q" 0x00011 0052 "r" 0x00012 0059 "y" 0x00013 p_idlo prvendor 0x00014 p_idhi id # 0x00015 plo prvendor 0x00016 phi tbladr 0x00017 a_idlo altvendor 0x00018 a_idhi id # ... ... ... table 29. query structure offset sub-section name description 1 0x00000 manufacturer code 0x00001 device code 0x(ba+2) 2 block status register block-specific information 0x00004-0xf reserved reserved for vendor-specific information 0x00010 cfi query identification string command set id and vendor data offset 0x0001b system interface information device timing & voltage information 0x00027 device geometry definition flash device layout p 3 primary intel-specific extended query table vendor-defined additional information specific to the primary vendor algorithm notes: 1. refer to the query structure output section and offset 0x28 for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 0x08000 is block 1?s beginning location when the block size is 32k-word). 3. offset 15 defines ?p? which points to the primary intel-specific extended query table.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 64 order number: 290645, revision: 022 c.3 block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. see table 30 . block erase status (bsr[1]) allows system software to determine the success of the last block erase operation. bsr[1] can be used just after power-up to verify that the vcc supply was not accidentally removed during an erase operation. notes: 1. ba = block address beginning location (i.e., 0x08000 is block 1?s beginning location when the block size is 32k-word). table 30. block status register offset length description add. value 0x(ba+2) 1 1 block lock status register ba+2 --00 or --01 bsr[0] block lock status 0 = unlocked 1 = locked ba+2 (bit 0): 0 or 1 bsr[1] block lock-down status 0 = not locked down 1 = locked down ba+2 (bit 1): 0 or 1 bsr[7:2]: reserved for future use ba+2 (bit 2-7): 0
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 65 c.4 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). see table 31 . table 31. cfi identification offset length description add. hex code value 0x10 3 query-unique ascii string ?qry? 10: 11: 12: --51 --52 --59 ?q? ?r? ?y? 0x13 2 primary vendor command set and control interface id code 16-bit id code for vendor-specified algorithms 13: 14: --03 --00 0x15 2 extended query table primary algorithm address 15: 16: --35 --00 0x17 2 alternate vendor command set and control interface id code 0x0000 means no second vendor-specified algorithm exists 17: 18: --00 --00 0x19 2 secondary algorithm extended query table address 0x0000 means none exists 19: 1a: --00 --00
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 66 order number: 290645, revision: 022 table 32. system interface information c.5 device geometry definition table 33. device geometry definition offset length description add. hex code value 0x1b 1 v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1b: --27 2.7 v 0x1c 1 v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1c: --36 3.6 v 0x1d 1 v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1d: --b4 11.4 v 0x1e 1 v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1e: --c6 12.6 v 0x1f 1 ?n? such that typical single word program time-out =2 n s 1f: --05 32 s 0x20 1 ?n? such that typical max. buffer write time-out = 2 n s 20: --00 na 0x21 1 ?n? such that typical block erase time-out = 2 n ms 21: --0a 1 s 0x22 1 ?n? such that typical full chip erase time-out = 2 n ms 22: --00 na 0x23 1 ?n? such that maximum word program time-out = 2 n times typical 23: --04 512s 0x24 1 ?n? such that maximum buffer write time-out = 2 n times typical 24: --00 na 0x25 1 ?n? such that maximum block erase time-out = 2 n times typical 25: --03 8s 0x26 1 ?n? such that maximum chip erase time-out = 2 n times typical 26: --00 na offset length description add. hex code value 0x27 1 ?n? such that device size = 2 n in number of bytes 27 see table 34, ?device geometry details? on page 67 0x28 2 flash device interface: x8 async 28:00,29:00 x16 async 28:01,29:00 x8/x16 async 28:02,29:00 28: 29: --01 --00 x16 0x2a 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: 2b: --00 --00 0 0x2c 1 number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in ?bulk? 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) 2c: --02 2 0x2d 4 erase block region 1 information bits 0?15 = y, y+1 = number of identical-size erase blocks bits 16?31 = z, region erase block(s) size are z x 256 bytes 2d: 2e: 2f: 30: see table 34, ?device geometry details? on page 67 0x2d 14 erase block region 2 information bits 0?15 = y, y+1 = number of identical-size erase blocks bits 16?31 = z, region erase block(s) size are z x 256 bytes 31: 32: 33: 34: see table 34, ?device geometry details? on page 67
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 67 table 34. device geometry details address 16 mbit 32 mbit 64 mbit -b -t -b -t -b -t 0x27 --15 -15 --16 -16 --17 --17 0x28 --01 --01 --01 --01 --01 --01 0x29 --00 --00 --00 -00 -00 -00 0x2a --00 --00 --00 -00 -00 -00 0x2b --00 --00 --00 -00 -00 -00 0x2c --02 --02 --02 --02 --02 --02 0x2d --07 --1e --07 --3e --07 --7e 0x2e --00 --00 --00 -00 -00 -00 0x2f --20 --00 --20 -00 --20 --00 0x30 --00 --01 --00 --01 --00 --01 0x31 --1e --07 --3e --07 --7e --07 0x32 --00 --00 --00 -00 -00 -00 0x33 --00 --20 --00 --20 --00 --20 0x34 --01 --00 --01 --00 --01 --00
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 68 order number: 290645, revision: 022 c.6 intel-specific extended query table certain flash features and commands are optional as shown in table 35, ?primary-vendor specific extended query? on page 68 . the intel - specific extended query table specifies these features as well as other similar types of information. table 35. primary-vendor specific extended query offset 1 p = 0x15 length description (optional flash features and commands) address hex code value 0x(p+0) 0x(p+1) 0x(p+2) 3 primary extended query table unique ascii string ?pri? 35: 36: 37: --50 --52 --49 ?p? ?r? ?i? 0x(p+3) 1 major version number, ascii 38: --31 ?1? 0x(p+4) 1 minor version number, ascii 39: --30 ?0? 0x(p+5) 0x(p+6) 0x(p+7) 0x(p+8) 4 optional feature and command support (1=yes, 0=no) bits 9?31 are reserved; undefined bits are ?0.? if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. 3a: 3b: 3c: 3d: --66 --00 --00 --00 bit 0 chip erase supported bit 1 suspend erase supported bit 2 suspend program supported bit 3 legacy lock/unlock supported bit 4 queued erase supported bit 5 instant individual block locking supported bit 6 protection bits supported bit 7 page mode read supported bit 8 synchronous read supported bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 0 bit 4 = 0 bit 5 = 1 bit 6 = 1 bit 7 = 0 bit 8 = 0 no yes yes no no yes yes no no 0x(p+9) 1 supported functions after suspend: read array, status, query other supported operations are: bits 1?7 reserved; undefined bits are ?0? 3e: --01 bit 0 program supported after erase suspend bit 0 = 1 yes 0x(p+a) 0x(p+b) 2 block status register mask bits 2?15 are reserved; undefined bits are ?0? bit 0 block lock-bit status register active bit 1 block lock-down bit status active 3f: --03 40: --00 bit 0 = 1 yes bit 1 = 1 yes 0x(p+c) 1 v cc logic supply highest performance program/ erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts 41: --33 3.3 v 0x(p+d) 1 v pp optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts 42: --c0 12.0 v notes: 1. the variable p is a pointer which is defined at cfi offset 0x15.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 69 table 36. protection register information offset 1 p = 0x35 length description (optional flash features and commands) address hex code value 0x(p+e) 1 number of protection register fields in jedec id space. ?00h,? indicates that 256 protection bytes are available 43: --01 01 0x(p+f) 0x(p+10) (0xp+11) 4 44: 45: 46: --80 --00 --03 80h 00h 8 byte 0x(p+12) protection field 1: protection description this field describes user-available one time programmable (otp) protection register bytes. some are pre-programmed with device- unique serial numbers. others are user programmable. bits 0?15 point to the protection register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user- programmable. bits 0?7 = lock/bytes jedec-plane physical low address bits 8?15 = lock/bytes jedec -plane physical high address bits 16?23 = ?n? such that 2 n = factory pre-programmed bytes bits 24?31 = ?n? such that 2 n = user programmable bytes 47: --03 8 byte 0x(p+13) reserved for future use 48: notes: 1. the variable p is a pointer which is defined at cfi offset 0x15.
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 70 order number: 290645, revision: 022 appendix d additional information order number document/tool 297938 3 volt advanced+ boot block flash memory specification update 292216 ap-658 designing for upgrade to the advanced+ boot block flash memory 292215 ap-657 designing with the advanced+ boot block flash memory architecture contact your intel representative intel ? flash data integrator (intel ? fdi) software developer?s kit 297874 ifdi interactive: play with intel ? flash data integrator on your pc notes: 1.call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2.see the intel page at ?http://www.intel.com/design/flash? for technical documentation and tools.
intel? advanced+ boot block flash memory (c3) datasheet intel? advanced+ boot block flash memory (c3) january 2005 order number: 290645, revision: 022 71 appendix e ordering information figure 23. component ordering information package te = 48- lead tsop gt = 48- ball bga * csp ge = vf bga csp rc = easy bga pc = pb free easy bga ph = pb free vfbga js = pb free tsop product line designator for all intel ? flash products access speed (ns) (70, 80 , 90, 100 , 110 ) product family c3 = 3 volt advanced+ boot block v cc = 2.7 v?3.6 v v pp = 2.7 v?3.6 v or 11 .4 v?12.6 v device density 640 = x16 (64 mbit) 320 = x16 (32 mbit) 160 = x16 (16 mbit) 800 = x16 (8 mbit) t = top blocking b = bottom blocking lithography a = 0.25 m c = 0.18 m d = 0.13 m t e 2 8 f 3 2 0 c 3 t c 7 0
intel? advanced+ boot block flash memory (c3) january 2005 intel? advanced+ boot block flash memory (c3) datasheet 72 order number: 290645, revision: 022 table 37. product information ordering matrix valid combinations (all extended temperature) 48-lead tsop 48-ball bga* csp 48-ball vf bga easy bga extended 64 mbit te28f640c3tc80 te28f640c3bc80 ge28f640c3tc80 ge28f640c3bc80 rc28f640c3tc80 rc28f640c3bc80 extended 32 mbit te28f320c3td70 te28f320c3bd70 te28f320c3tc70 te28f320c3bc70 te28f320c3tc90 te28f320c3bc90 te28f320c3ta100 te28f320c3ba100 te28f320c3ta110 te28f320c3ba110 js28f320c3bd70 js28f320c3td70 js28f320c3bd90 js28f320c3td90 gt28f320c3ta100 gt28f320c3ba100 gt28f320c3ta110 gt28f320c3ba110 ge28f320c3td70 ge28f320c3bd70 ge28f320c3tc70 ge28f320c3bc70 ge28f320c3tc90 ge28f320c3bc90 ph28f320c3bd70 ph28f320c3td70 ph28f320c3bd90 ph28f320c3td90 rc28f320c3td70 rc28f320c3bd70 rc28f320c3td90 rc28f320c3bd90 rc28f320c3tc90 rc28f320c3bc90 rc28f320c3ta100 rc28f320c3ba100 rc28f320c3ta110 rc28f320c3ba110 pc28f320c3bd70 pc28f320c3td70 pc28f320c3bd90 pc28f320c3td90 extended 16 mbit te28f160c3td70 te28f160c3bd70 te28f160c3tc70 te28f160c3bc70 te28f160c3tc80 te28f160c3bc80 te28f160c3tc90 te28f160c3bc90 te28f160c3ta90 te28f160c3ba90 te28f160c3ta110 te28f160c3ba110 js28f160c3bd70 js28f160c3td70 gt28f160c3ta90 gt28f160c3ba90 gt28f160c3ta110 gt28f160c3ba110 ge28f160c3td70 ge28f160c3bd70 ge28f160c3tc70 ge28f160c3bc70 ge28f160c3tc80 ge28f160c3bc80 ge28f160c3tc90 ge28f160c3bc90 ph28f160c3bd70 ph28f160c3td70 rc28f160c3td70 rc28f160c3bd70 rc28f160c3tc70 rc28f160c3bc70 rc28f160c3tc80 rc28f160c3bc80 rc28f160c3tc90 rc28f160c3bc90 rc28f160c3ta90 rc28f160c3ba90 rc28f160c3ta110 rc28f160c3ba110 PC28F160C3bd70 PC28F160C3td70 extended 8 mbit te28f800c3td70 te28f800c3bd70 te28f800c3ta90 te28f800c3ba90 te28f800c3ta110 te28f800c3ba110 js28f800c3bd70 js28f800c3td70 ge28f800c3ta70 ge28f800c3ba70 ge28f800c3ta90 ge28f800c3ba90 rc28f800c3td70 rc28f800c3bd70 rc28f800c3ta90 rc28f800c3ba90 rc28f800c3ta110 rc28f800c3ba110 pc28f800c3bd70 pc28f800c3td70 note: the second line of the 48-ball bga package top side mark specifies assembly codes. for samples only, the first character signifies either ?e? for engineering samples or ?s? for silicon daisy chain samples. all other assembly codes without an ?e? or ?s? as the first character are production units.

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