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? freescale semiconductor, inc., 2008. all rights reserved. freescale semiconductor user?s guide the mpc8313e reference design board (rdb) is a system featuring the powerquicc? ii pro processor, which includes a built-in security accelerator. this low-cost, high-performance system solution consists of a printed circuit board (pcb) assembly plus a software board support package (bsp) distributed in a cd image. this bsp enables the fastest possible time-to-market for development or integration of applications including printer engines, broadband gateways, no-new-wires home adapters/access points, and home automation boxes. this document describes the hardware features of the board including specifications, block diagram, connectors, interfaces, and hardware straps. it also describes the board settings and physical connections needed to boot the mpc8313e rdb. finally, it considers the software shipped with the platform. when you finish reading this document, you should: ? be familiar with the board layout ? understand the default board configuration and your board configuration options ? know how to get started and boot the board ? know about the software and further documentation that supports the board document number: mpc8313erdbug rev. 4, 02/2009 contents 1. mpc8313e rdb hardware . . . . . . . . . . . . . . . . . . . . 2 2. board-level functions . . . . . . . . . . . . . . . . . . . . . . . . 7 3. connectors, jumpers, switches, and leds . . . . . . . 19 4. micro-jumper/resistor options for etsec1 . . . . . . 27 5. mpc8313e rdb board configuration . . . . . . . . . . 38 6. getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7. mpc8313e rdb software . . . . . . . . . . . . . . . . . . . . 46 8. frequently asked questions (faqs) . . . . . . . . . . . . 47 9. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 warning this is a class a product. in a domestic environment this product may cause radio interference, in which case the user may be required to take adequate measures. powerquicc? mpc8313e reference design board (rdb)
powerquicc? mpc8313e reference design board (rdb), rev. 4 2 freescale semiconductor mpc8313e rdb hardware use this manual in conjunction with the following documents: ? mpc8313e powerquicc? ii pro integrated communications processor family reference manual (mpc8313erm) ? mpc8313e powerquicc ii pro processor hardware specifications (mpc8313eec) ? ?hardware and layout design considerations for ddr memory interfaces? (an2582) note the normal function of the product may be disturbed by strong electromagnetic interference. if so, simply reset the product to resume normal operation by following the instructions in the manual. if normal function does not resume, use the product in another location. this equipment has been tested and found to comply with the limits for a class a digital device, pursuant to part 15 of the fcc rules. these limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. this equipment generates, uses, and can radiate radio frequency energy. if it is not installed and used in accordance with the instruction manual, it may cause harmful interference to radio communications. operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his or her own expense. 1 mpc8313e rdb hardware this section covers the features, block diagram, specifications, and mechanical data of the mpc8313e rdb. 1.1 features the board features are as follows: ? cpu: freescale mpc8313e running at 333/166 mhz; cpu/coherent system bus (csb) ? memory subsystem: ? 128 mbyte unbuffered ddr2 sdram discrete devices ? 8 mbyte flash single-chip memory ? 32 mbyte nand flash memory ? 256 kbit m24256 serial eeprom ? sd connector to interface with the sd memory card in spi mode ? interfaces: ? 10/100/1000 baset ethernet ports: ? etsec1, rgmii: five 10/100/1000 baset rj-45 interfaces using vitesse ? vsc7385 l2 switch, or selectable one 10/100/1000 baset rj-45 interface using marvell ? 88e1111 phy in revc board
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 3 mpc8313e rdb hardware ? etsec2, selectable rgmii or sgmii: one 10/100/1000 baset rj-45 interface using marvell 88e1111 phy ? usb 2.0 port: high-speed host/device ? usb interface: selectable on-chip phy or external ulpi phy interface by smsc usb3300 usb phy ? pci: 32-bit pci interface running at up to 66 mhz ? one 32-bit 3.3 v pci slot connected to pci bus ? one 32-bit 3.3 v minipci slot connected to pci bus ? dual uart ports: ? duart interface: supports two uarts up to 115200 bps for console display ? board connectors: ? lcd connectors by gpio ? atx power supply connector ? jtag/cop for debugging ? ieee std. 1588? signals for test and measurement ? real-time clock and thermal sensor on i 2 c bus ? programmable leds for debug use ? 6-layer pcb routing (4-layer signals, 2-layer power and ground)
powerquicc? mpc8313e reference design board (rdb), rev. 4 4 freescale semiconductor mpc8313e rdb hardware figure 1 shows the mpc8313e rdb block diagram. figure 1. mpc8313e rdb block diagram mpc8313e etsec1 vitesse l2 switch rgmii/ ulpi/ smsc usb phy ieee1588 etsec2 marvell phy rgmii/sgmii clock, pulse, etc. on-chip usb dual uart usb mini-ab usb mini-ab spi sd card 33/66 mhz 3.3 v 32-bit pci slot 3.3 v 32-bit minipci slot pci bus system clock and usb clock 128 mbyte ddr2 8 mbyte nor flash memory 32-bit ddr2 bus 32 mbyte nand flash memory leds/status buffers 16-bit local bus dac for ieee1588 clock (optional) i 2 c bus real-time clock thermal sensor gpio lcd connectors jtag/cop header jtag/cop power supply with low power mode te st points : selected by resistor options ---note--- eeprom marvell phy rgmii/sgmii
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 5 mpc8313e rdb hardware 1.2 specifications table 1 lists the specifications of the mpc8313e rdb. table 1. mpc8313e-rdb specifications characteristics specifications power requirements (without add-on card): typical maximum 12 v dc 0a 0 a 5.0 v dc1 ma1.5 a communication processor mpc8313e running at 266 mhz addressing: total address range flash memory (local bus) ddr2 sdram 4 gbyte (32 address lines) 8 mbyte with one chip-select 128 mbyte ddr2 sdram operating temperature 0 o c to 70 o c (room temperature) storage temperature ?25 o c to 85 o c relative humidity 5% to 90% (noncondensing) pcb dimensions: length width thickness 6693 mil (reva and revb) or 7692 mil (revc) 6693 mil 62 mil
powerquicc? mpc8313e reference design board (rdb), rev. 4 6 freescale semiconductor mpc8313e rdb hardware 1.3 mechanical data figure 2 shows the mpc8313e rdb revax and revb dimensions (in mil and [mm]). the board measures 170 mm 170 mm (6693 mil 6693 mil) for integration in a mini-itx chassis. figure 2. dimensions of the mpc8313e rdb (revax and revb)
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 7 board-level functions figure 3 shows the mpc8313e rdb rev c dimensions (in mil and [mm]). the board measures 195 mm 170 mm (7692 mil 6693 mil). figure 3. dimensions of the mpc8313e rdb (revc) 2 board-level functions the board-level functions are reset, external interr upts, clock distribution, ddr sdram controller, local bus controller, i 2 c interfaces, sd memory card interface, usb interface, etsec1 10/100/1000 baset interface, dual rs-232 ports, pci bus, and cop/jtag.
powerquicc? mpc8313e reference design board (rdb), rev. 4 8 freescale semiconductor board-level functions 2.1 reset and reset configurations the mpc8313e rdb reset module generates a single re set to the mpc8313e and other peripherals on the board. the reset unit provides power-on reset, hard reset, and soft reset signals in compliance with the mpc8313e hardware specification. figure 4 shows the reset circuitry. note the following: ? hard reset is generated either by the cop/jtag port or the mpc8313e. ? power-on reset is generated by the maxim max811 device. when mr is deasserted and 3.3 v is ready, the max811 internal timeout guarantees a minimum reset active time of 150 ms before poreset is deasserted. this circuitry guarantees a 150 ms poreset pulse width after 3.3 v reaches the right voltage level, which meets the specification of the poreset input of mpc8313e. ? cop/jtag port reset provides convenient hard-res et capability for a cop/jtag controller. the reset line is available at the cop/jtag port connector. the cop/jtag controller can directly generate the hard-reset signal by asserting this line low. ? push button reset interfaces using the mr signal with debounce capability to produce a manual master reset of the rdb. ? soft reset is generated by the cop/jtag port. assertion of sreset causes the mpc8313e to abort all current internal and external transactions and set most registers to their default values. figure 4. reset circuitry of the mpc8313e max811 3.3 v mr push button gnd hreset from cop sreset from cop trst from cop sreset to mpc8313e trst to mpc8313e poreset to mpc8313e nor flash l2 switch mpc8313e reset config logic marvell phy
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 9 board-level functions 2.2 external interrupts figure 5 shows the external interrupts to the mpc8313e. figure 5. mpc8313e interrupts the following are descriptions of the interrupt signals shown in figure 5 : ? all external interrupt signals are pulled up by 4.7 k resistors. ?irq0 is connected to sd card ?irq1 is connected to pci slot inta. ?irq2 is connected to and shared by the pci slot?s intb and the mini pci slot inta. ?irq3 is connected to the l2 switch as well as to an external usb phy (by an optional resistor). ?irq4 is connected to the marvell gbe phy as well as to rtc and lm75 (by an optional resistors). irq0 irq2 irq3 irq4 mpc8313e sd card irq1 pci slot (ad15) inta mini pci (ad14) inta and pci slot (ad15) intb l2 switch and ulpi external usb phy (optional) marvell phy, rtc (optional) and lm75 (optional)
powerquicc? mpc8313e reference design board (rdb), rev. 4 10 freescale semiconductor board-level functions 2.3 clock distribution figure 6 and table 2 show the clock distribution on the mpc8313e rdb. figure 6. mpc8313e-rdb clock scheme mpc8313e lclkx (nc) local bus pll ddr pll pci div 66.666 mhz osc clkin 33/66 mhz 33/66 mhz mini pci slot pci slot occr 2 pci_sync_out pci_sync_in system pll m66en 33/66 mhz cfg_clkin_div nc 48 mhz osc 25 mhz osc usb clkin l2 switch gbe phy gtx_clk125 sd_ref_clk 50 mhz osc/ 50 mhz vcxo ieee1588 tmr clk 0 1 2 ulpi usb gnd gnd 24 mhz crystal phy real-time gnd gnd 32.768 khz crystal clock ddr2 sdram clk mck mck# 133 mhz pll 125 mhz lv d s osc 125mhz
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 11 board-level functions 2.4 ddr2 sdram controller the mpc8313e processor uses ddr2 sdram as the system memory. the ddr2 interface uses the sstl2 driver/receiver and 1.8 v power. a vref 1.8 v/2 is needed for all sstl2 receivers in the ddr2 interface. for details on ddr2 timing design and termination, refer to the freescale application note entitled ?hardware and layout design considerations for ddr memory interfaces? (an2582). signal integrity test results show this design does not require terminating resistors (series resistor (r s ) and termination resistor (r t )) for the discrete ddr2 devices used. ddr2 supports on-die termination; the ddr2 chips and mpc8313e are connected directly. the interface is 1.8 v provided by an on-board table 2. clock distribution clock frequency module generated by description 66.666 mhz mpc8313e clkin 66.666 mhz oscillator the mpc8313e uses clkin to generate the pci_sync_out clock signal, which is fed back on the board through the pci_sync_in signal to the internal system pll. from the power-on reset configuration, the csb clock is generated by the internal pll and is fed to the e300 core pll for generating the e300 core clock. the cfg_clkin_div configuration input selects whether clkin or clkin/2 is driven on the pci_sync_out signal. the cfg_clkin_div is tied to the m66en input pin. 133 mhz ddr2 sdram mpc8313e the ddr memory controller is configured to use the 2:1 mode csb to ddr for the ddr interface (ddr266). the local bus clock uses 1:1 local to csb clock, which is configured by hard reset configuration or spmr register. 33/66 mhz pci 32-bit slot and minipci slot mpc8313e the pci module uses the pci_sync_in as its clock source. the trace length of the pci_sync_in to pci_sync_out signal is matched with all pci clocks on the rdb. 25 mhz l2 switch and gbe phy 25 mhz oscillator the 25 mhz oscillator provides the clock for the l2 switch and the gbe phy 125 mhz etsec clock gbe phy with pll (revc), or 125 mhz oscillators (revb), or gbe phy (revax) the gtx_clk125 and serdes (sgmii) clocks are provided by external oscillators (or by gbe phy in revax and revc boards). 48 mhz usb clock 48 mhz oscillator 48 mhz is provided for on-chip usb phy of mpc8313e 50 mhz ieee1588 clock (tmr_clk) 50 mhz oscillator/50 mhz vcxo 50 mhz is used by the ieee 1588 module. it can be an ordinary oscillator or vcxo controlled by spi dac. 24 mhz ulpi external usb phy 24 mhz crystal 24 mhz crystal is used by the ulpi external usb phy 32.768 khz real-time clock 32.768 khz crystal 32.768 khz crystal is used by the real-time clock
powerquicc? mpc8313e reference design board (rdb), rev. 4 12 freescale semiconductor board-level functions voltage regulator. vref, which is half the interface vo ltage, or 0.9 v, is provided by a voltage divider of 1.8 v for voltage tracking and low cost. the mpc8313e provides a pair of clock pins, which are connected and shared by the two ddr2 devices. figure 7 shows the ddr2 sdram controller connection. figure 7. ddr2 sdram connection 2.5 local bus controller the mpc8313e local bus controller has a 26-bit l ad[0?15] and la[16?25] address that consists of 16-bit data multiplex bus and control signals. the local bus speed is up to 133 mhz. to interface with the standard memory device, an address latch must provi de the address signals. the lale is used as the latching signal. to reduce loading of the high speed lo cal bus interface, a data buffer for all low-speed devices is attached to the memory controller. th e followings modules are connected to the local bus: ? 8 mbyte nor flash memory ? 32 mbyte nand flash memory ? led/status buffers 2.5.1 nor flash memory through the general-purpose chip-select machine (gpcm), the mpc8313e rdb provides 8 mbyte of flash memory using a chip-select signal. the flash memory is used with the 16-bit port size. figure 8 ddr2 device (512 mbit, 16-bit) mpc8313e ddr2 controller ddr2 device (512 mbit, 16-bit) mcs0 mck, mck , mcke mras , mcas , mwe mdm[0:3], mdqs[0:3] a[0:14], ba[0:2] mdq[0:31] odt vref 1.8 v reg vref
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 13 board-level functions shows the hardware connections for the flash memory. the starting address for the 8 mbyte flash memory is 0xfe00_0000 to 0xfe7f_ffff. figure 8. nor flash connection 2.5.2 nand flash memory the mpc8313e has native support for nand flash memory through its nand flash control machine (fcm). the mpc8313e rdb implements an 8-bit nand flash with 32 mbyte in size. figure 9 shows the nand flash connection. figure 9. nand flash connection mpc8313e elbc controller nor flash 16-bit nor_cs *note: nor_cs can be either cs0 or cs1 by dip switch option, default is cs0 latch buffer la[24:16] a[0:8] a[9:21] lba[15:3] lad[15:0] dq[0:15] lbd[15:0] we oe we0 gpl2 mpc8313e elbc controller nand flash 8-bit nand_cs *note: nand_cs can be either cs0 or cs1 by dip switch option; the default is cs1 cle ale we re r/b wp gpl0 gpl1 we0 gpl2 gpl4 gpl3 lad[0:7] io[7:0] *buffer lbd0-7
powerquicc? mpc8313e reference design board (rdb), rev. 4 14 freescale semiconductor board-level functions 2.5.3 led/status buffers the mpc8313e rdb has an 8-bit read/write buffer. the read buffer returns information on m66en, board revision, boot device (nor or nand), and sd card status. the write buffer controls eight leds on the board for status or debug indication. figure 10 shows the hardware connection of the buffers. figure 10. led/status buffers 2.6 i 2 c interfaces the mpc8313e has two i 2 c interfaces. on the mpc8313e rdb, i 2 c1 is used as master mode. it is connected to the following three devices as shown in figure 11 . ? serial eeprom m24256 at address 0x50. ? real-time clock ds1339u at address 0x68. ? thermal sensor lm75 at address 0x48. it may also be connected to the dac ad5301 at addr ess 0x0c, whose optional nature is represented in figure 11 by the dashed line. the connection of the i 2 c bus is shown in figure 11 . the m24256 serial eeprom can be used to store the reset configuration word of the mpc8313e, as well as to store the configuration registers? values and user program if the mpc8313e boot sequencer is enabled. by default, the eeprom is not used and the hard reset configuration words are loaded from local bus flash memory. for details about how to program mpc8313e elbc controller we0 gpl2 lad[0:7] buffer lcs3 lcx373 lcx245 8x leds write buffer read buffer sd_insert sd_protect rsvd0 boot0 rsvd1 m66en rev0 rev1 lbd[0:7] oe
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 15 board-level functions the reset configuration word value in i 2 c eeprom and the boot sequencer mode, refer to the mpc8313e reference manual. figure 11. i 2 c connection 2.7 sd memory card interface an sd memory card interface connects directly to th e spi bus of the mpc8313e. sd data mode and sdio mode are not supported. the spi mode is the only sd operating mode supported by this connection. hot insertion and removal is not supported. see figure 12 for the hardware connection. for revb boards, the sd card chip select signal is changed from gpio31(spisel ) to gpio13(la8) because when using spi as master mode, spisel cannot be set as gpio (which is supposed to be used for device select signal). in this case, another gpio pin should be used. gpio13 is implemented on this board as an example. i2c1-scl i 2 c eerom m24256 mpc8313e scl sda i2c1-sda i 2 c address = 0x50 i 2 c rtc ds1339u scl sda i 2 c address = 0x68 i 2 c sensor lm75 scl sda i 2 c address = 0x48 3.3 v i 2 c dac (optional) ad5301 scl sda i 2 c address = 0x0c
powerquicc? mpc8313e reference design board (rdb), rev. 4 16 freescale semiconductor board-level functions caution power down before inserting or removing the sd memory card. figure 12. sd memory card connection 2.8 usb interface mpc8313e supports a usb 2.0 high speed host/device interface through its on-chip usb phy or external ulpi usb phy. the mpc8313e rdb supports both options. by default, the on-chip usb phy is used. figure 13 shows the usb connections. figure 13. usb connections mpc8313e cs din dout sclk insert contact protect sd_cs spimosi spimiso spiclk sd_insert sd_contact sd_protect la8 (gpio13) spimosi spimiso spiclk sd memory card socket status read buffer local bus mpc8313e usb-dp usb-dm usb mini-ab on-chip usb phy ulpi external usb phy interface usb3300 usb phy usb vbus power supply usb mini-ab usb-vbus control control **ulpi irq3 **note: because ulpi is multiplexed with etsec1 rgmii, by default on-chip phy is used. a change of resistor option is needed to use the external usb phy interface. or
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 17 board-level functions 2.9 etsec1 10/100/1000 baset interface etesc1 is set to operate in rgmii mode. it connects to a vsc7385 5-port l2 switch, as shown in figure 14 . figure 14. rgmii interface connection for l2 switch 2.10 etsec2 10/100/1000 baset interface etesc2 can be set to operate in rgmii mode (default) or sgmii mode. figure 15 shows the hardware connection for etsec. figure 15. etsec2 connection vsc7385 mpc8313e rgmii etsec1 local bus lcs2#, gpcm 8bit data rj-45 ports l2 switch mpc8313e rgmii etsec2 88e1111 gbe phy sgmii rj-45 port note: by default, rgmii is used and sgmii is optional mdc, mdio mdio phy address = 4
powerquicc? mpc8313e reference design board (rdb), rev. 4 18 freescale semiconductor board-level functions 2.11 dual rs-232 ports dual rs-232 ports are supported on the rdb. figure 16 illustrates the serial port connection using a max3232 3.3 v rs-232 driver to interface with a 9-pin d type female connector. this serial connection runs at up to 115.2 kbps. figure 16. rs-232 debug ports connection 2.12 pci bus the 32-bit pci interface connects to a 32-bit 3.3 v pci slot and a minipci slot (see figure 17 ). figure 17. pci bus connection mpc8313e uart1 rxd rts txd cts uart2 rxd rts txd cts max3232 txd rxd cts rx tx tx do di di rts female db-9 rs-232 serial port rx do 3 7 8 2 max3232 txd rxd cts rx tx tx do di di rts female db-9 rs-232 serial port rx do 3 7 8 2 mpc8313e 32bit pci pci-ad[0:31] pci-cbe[0:3] pci-req0 pci-gnt0 pci-ctrl 32bit 3.3 v pci slot 32-bit 3.3 v minipci slot pci-req1 pci-gnt1 [ad14] [ad15]
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 19 connectors, jumpers, switches, and leds 2.13 cop/jtag port the common on-chip processor (cop) is part of the mpc8313e jtag module and is implemented as a set of additional instructions and logic. this port can connect to a dedicated emulator for extensive system debugging. several third-party emulators in the mark et can connect to the host computer through the ethernet port, usb port, parallel port, rs-232, and so on. a typical setup using a usb port emulator is shown in figure 18 . figure 18. connecting mpc8313e-rdb to a usb emulator the 16-pin generic header connector carries the cop/ jtag signals and the additional signals for system debugging. the pinout of this connector is shown in figure 19 . figure 19. mpc8313e rdb cop connector 3 connectors, jumpers, switches, and leds table 3 summarizes the connectors, jumpers, switches, and leds on the mpc8313e rdb and provides the number of the section/page on which each is discussed. the rest of this section discusses each of these in the order of its appearance in the table. table 3. connectors, jumpers, switches, and leds reference description section/page connectors p1 14-pin cop/jtag connector 3.1/page 21 pc mpc8313e rdb p1 usb emulator usb port cop port tdi pull-up tck tms sreset hreset ckstp_out gnd trst pull-up ckstp_in nc nc nc gnd 1 tdo
powerquicc? mpc8313e reference design board (rdb), rev. 4 20 freescale semiconductor connectors, jumpers, switches, and leds p2 3.3 v pci slot [idsel - ad15] 3.2/page 21 p3 minipci slot [idsel - ad14] 3.3/page 22 p4 usb mini-ab connector (on-chip phy) 3.4/page 22 p5 rj-45 lan connectors enet4 (top), enet5 (bottom). see figure 23 3.5/page 23 p6 rj-45 lan connectors enet2 (top), enet3 (bottom). see figure 23 p7 rj-45 lan connectors enet0 (top), enet1 (bottom). see figure 23 p8 usb mini-ab connector (external ulpi usb phy) 3.4/page 22 p9 atx type power supply connector. the board can be powered by an atx power supply or the power supply bundled with the mini-itx case. ? p10 ieee 1588 connector (optional) 3.9/page 25 p11 dual uart connector. uart1 (top), uart2 (bottom) 3.6/page 24 u44 sd memory card socket 3.7/page 24 bt1 rtc battery holder, cr2032 type. the real-time clock on the rdb requires a battery when the board is powered o ff. when placing or replacing the battery, take care to ensure that the polarity is correct. ? j20 connector for chassis connection (power on, power led, reset) ? j21 lcd connector 3.8/page 24 j22 lcd connector j23 lcd backlight connector. a 2-pin header (j23) is provided for lcd backlight power. pin1 is 5 v and pin 2 is gnd. ? j24 mcu programming connector. j24 is used for mcu programming on the rdb. it is reserved. ? jumpers j19 open (default)?power on controlled by switch; close?power is always on ? switches s1 system reset button. resets the mpc8313e rdb. (poreset ). press once on the push button reset switch on the rdb to cause a power-on reset (poreset ) to the board. ? s2 power on button. press once to power on/off. ? s3 dip switch. selects the reset configuration source (rst_cfg_src) for the mpc8313e. 3.10/page 26 s4 dip switch. board revision indicator and boot device selector. 3.11/page 26 leds d6 enet5 link 10 ? d7 enet5 link 100 ? d8 enet5 duplex ? d9 enet5 rx ? d12 usb vbus ? d10 on-chip usb phy ctl0 ? table 3. connectors, jumpers, switches, and leds (continued) reference description section/page
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 21 connectors, jumpers, switches, and leds 3.1 cop connector (p1) the cop connector allows the user to connect a cop/jtag-based debugger to the mpc8313e rdb for debugging. table 4 lists the pin assignments of the cop connector. 3.2 pci slot (p2) the mpc8313e rdb has one 32-bit 3.3-v pci expansion slot (p2) for an expansion card. the slot connects ad15 for its device select signal. only the 3.3-v pci card is supported. turn off power during d11 on-chip usb phy ctl1 ? d16 12-v indicator ? d15 5-v indicator ? d14 3.3-v indicator ? d17 2.5-v indicator ? d13 5-v standby indicator ? d3 programmable led0 (red) 3.12/page 27 d5 programmable led1 (yellow) d2 programmable led2 (green) d1 programmable led3 (green) d22 programmable led4 (green) d21 programmable led5 (green) d20 programmable led6 (green) d4 programmable led7/lcd_en (green) table 4. cop connector pin assignments pin signal pin signal 1 tdo 2 gnd 3 tdi 4 trst 5qreq 6 vdd_sense 7 tck 8 ckstp_in 9tms 10 nc 11 sreset 12 nc 13 hreset 14 nc 15 ckstp_out 16 gnd table 3. connectors, jumpers, switches, and leds (continued) reference description section/page
powerquicc? mpc8313e reference design board (rdb), rev. 4 22 freescale semiconductor connectors, jumpers, switches, and leds insertion and removal of the pci card. as figure 20 shows, 3.3-v pci cards can be identified by the key position on the pci card. figure 20. 3.3 v key on a typical 3.3 v pci card 3.3 minipci connector (p3) there is a minipci connector (p3) on the rdb. the sl ot connects to ad14 for its device select signal. figure 21 shows how to install a minipci card. figure 21. installation of minipci card 3.4 usb connectors (p4, p8) there are two usb connectors on the mpc8313e rd b. one connects to the on-chip phy of the mpc8313e, and the other connects to the external ulpi usb phy. either can be enabled at a time. the pci slot 5 v key match 3.3 v key here front panel at x p ow e r connector m i n i p c i c a r d 1 . i n s e r t 2. press down
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 23 connectors, jumpers, switches, and leds selection between the two requires modification of micro -jumpers/resistor options as discussed later. by default, the on-chip phy usb is used. figure 22 shows the usb connectors in front panel. figure 22. usb connectors 3.5 ethernet connectors (p5, p6, p7) the mpc8313e rdb has six ethernet ports (rj-45). the first five ports (g0?g4) are supported by etsec1 (l2 switch), and the last port (g5) is supported by etsec2 (gbe phy). figure 23 shows the g0?g5 mapping viewing from the front panel. figure 23. ethernet connectors usb leds: ctl1 ctl0 vbus for external ulpi usb phy for on-chip phy g0 g1 g2 g3 g4 g5 usb mini-ab usb type a rx duplex link100 link10 g5 leds link1000 tx a b a b a b a b a b a: link/activity 1000 b: link/activity 10/100 g0-g4 leds:
powerquicc? mpc8313e reference design board (rdb), rev. 4 24 freescale semiconductor connectors, jumpers, switches, and leds 3.6 rs-232 uart connector (p11) serial interfaces are available at connector p11. it is a double deck rs-232 female connector. the upper port is uart1 and the lower port is uart2. by default, uart1 is used. figure 24 shows the rs-232 uart connector front view. . figure 24. rs-232 uart connectors 3.7 sd memory card socket (u44) an sd card socket (u44) for sd memory card installation is located next to the uart connector of the board. figure 25 shows how to install a compact flash card. figure 25. installation of sd card 3.8 lcd connectors (j21, j22) two headers (j21, j22) are provided for lcd connections. they use the mpc8313e gpio interface. both headers carry the same set of gpio signal pins, but they are different physically. j21 is single row of 1 14, and j22 is double row of 2 7. table 5 shows the mapping. table 5. lcd connector pin assignment pin number description 1gnd 25v 3 5 v to ?5 v variable 4gpio2 5gpio3 6gpio1 uart1 uart2 sd memory 1gb card
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 25 connectors, jumpers, switches, and leds 3.9 ieee 1588 connector (optional) a header (p10) is provided for ieee 1588 signals connection. it is double row of 2 8 header connector. the pinout of this connector is shown in figure 26 . figure 26. ieee 1588 connector (optional) 7 pull-down 8 pull-down 9 pull-down 10 pull-down 11 gpio7 12 gpio6 13 gpio5 14 gpio4 table 5. lcd connector pin assignment (continued) pin number description tsec_tmr_pp1 tsec_tmr_pp2 tsec_tmr_pp3 gnd gnd gnd tsec_tmr_gclk tsec_tmr_alarm1 tsec_tmr_alarm2 tsec_tmr_trig1 tsec_tmr_trig2 tsec_tmr_trig2 gnd tsec_tmr_clk 1 3.3 v by tsec1 phy) 3.3 v (optional if not used by tsec1 phy) (optional if not used
powerquicc? mpc8313e reference design board (rdb), rev. 4 26 freescale semiconductor connectors, jumpers, switches, and leds 3.10 dip switch s3 dip switch s3 selects the reset configuration source (rst_cfg_src) for the mpc8313e. figure 27 shows the factory default configuration of s3. figure 27. dip switch s3 check the mpc8313e reference manual for the meaning of the cfg_rst_src combination. by default, the dip switch is set to all on, meaning cfg_rst_src[0..3] = 0000. in this case, the hardware reset configuration is loaded from local bus nor flash memory. 3.11 dip switch s4 dip switch s4 on the rdb is shown in figure 28 , with the factory default configuration. figure 28. dip switch s4 rsvd is reserved. when software options are implemented, their values can be read from a buffer on the board. cfg_boot_ecc_dis switch is off by default to disable booting with ecc by driving high to 1 2 3 4 on cfg_rst_src0 0 1 cfg_rst_src1 cfg_rst_src2 cfg_rst_src3 1 2 3 4 on 0 1 rsvd rev1 boot1 (nand) cfg_boot_ecc_dis
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 27 micro-jumper/resistor options for etsec1 the signal lb_por_cfg_boot_ecc_dis (tsec1_mdc) during power on reset (revb and revc only. revax is a reserved switch (rsvd0)). rev1 represents bit 1 of the revision number. together with rev0 (implemented by resistor option; the default is 0), rev[0..1] shows the revision number, which is 01 by default. the values can be read from a buffer on the rdb. boot1 selects the boot device on the rdb. by default, boot1 is set, so chip-select 0 (cs0 ) is connected to the nor flash. cs1 is connected to the nand flash memory. if boot1 is cleared, cs0 is connected to nand flash memory, and cs1 is connected to nor flash memory. 3.12 rdb programmable leds eight programmable leds give status indication and debug information. figure 29 shows the diagram. figure 29. programmable leds an 8-bit write register on the rdb turns the leds on and off. the leds are arranged so that the most significant bit represents led0 and least significant b it represents led7; that is, led[0..7]. a write of 0x00 turns on all leds, and 0xff turns off all leds. 4 micro-jumper/resistor options for etsec1 the etsec1 rgmii, ulpi usb, and ieee 1588 signals are multiplexed on the mpc8313e. the mpc8313e rdb supports switching among the three interfaces using micro-jumpers (reva boards) or resistor options (reva1 or later boards). note for ieee 1588 support, use the same setting as for the etsec1 rgmii. in this case, a 50 mhz clock would be provided for the ieee 1588 tmr_clk pin. led0 led1 led2 (red) (yellow) (green) led3 (green) led4 (green) led5 (green) led6 (green) led7/lcd_en (green)
powerquicc? mpc8313e reference design board (rdb), rev. 4 28 freescale semiconductor micro-jumper/resistor options for etsec1 4.1 for reva boards figure 30 shows the micro-jumper locations. figure 30. reva micro-jumper locations by default the reva boards are shipped with the following settings: setup 1: ? etsec1, rgmii ? etsec2, rgmii the corresponding micro-jumper settings are shown in table 6 . table 6. default micro-jumper settings for reva jumper setting jumper setting jumper setting jumper setting j13 1-2 j7 1-2 j5 open j18 2-3 j12 1-2 j9 1-2 j1 open j16 1-2 j6 1-2 j2 open j15 1-2 j8 1-2 j17 1-2 j3 1-2 j14 1-2 j4 1-2 j11 open j10 1-2
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 29 micro-jumper/resistor options for etsec1 there are alternative settings for reva boards: setup 2: ? etsec1, usb dr with external ulpi usb phy (usb3300) ? etsec2, sgmii (remove r87, c275; connect 125 mhz clock from r181 to sgmii sclk) the corresponding micro-jumper settings are shown in table 7 . setup 3: ? etsec1, usb dr with external ulpi usb phy (usb3300) ? etsec2, rgmii the corresponding micro-jumper settings are shown in table 8 . table 7. alternative micro-jumper settings for reva (setup 2) jumper setting jumper setting jumper setting jumper setting j13 open j7 2-3 j5 2-3 j18 1-2 j12 open j9 2-3 j1 2-3 j16 open j6 2-3 j2 2-3 j15 open j8 2-3 j17 open j3 2-3 j14 2-3 j4 2-3 j11 2-3 j10 2-3 table 8. alternative micro-jumper settings for reva (setup 3) jumper setting jumper setting jumper setting jumper setting j13 open j7 2-3 j5 2-3 j18 1-2 j12 open j9 2-3 j1 2-3 j16 open j6 2-3 j2 2-3 j15 open j8 2-3 j17 open j3 2-3 j14 2-3 j4 2-3 j11 2-3 j10 2-3
powerquicc? mpc8313e reference design board (rdb), rev. 4 30 freescale semiconductor micro-jumper/resistor options for etsec1 setup 4 ? etsec1, rgmii ? etsec2, sgmii (remove r87, c275; connect 125 mhz clock from r181 to sgmii sclk) the corresponding micro-jumper settings are shown in table 9 . because the etsec1 ethernet switch phy on the rdb supports only rgmii, the etsec1 sgmii is not supported. the micro-jumper settings listed only ma tter for the etsec1 pin connections. they have nothing to do with switching between etsec2 rgmii and sgmii. the settings of etsec2 sgmii are provided as a reference. table 9. alternative micro-jumper settings for reva (setup 4) jumper setting jumper setting jumper setting jumper setting j13 1-2 j7 1-2 j5 open j18 2-3 j12 1-2 j9 1-2 j1 open j16 1-2 j6 1-2 j2 open j15 1-2 j8 1-2 j17 1-2 j3 1-2 j14 1-2 j4 1-2 j11 open j10 1-2
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 31 micro-jumper/resistor options for etsec1 4.2 reva1 to reva4 boards for reva1 or later boards, the micro-jumpers are replaced by resistor options for easier modification. figure 31 shows the resistor locations. table 10 shows the default configuration. figure 31. locations of resistor options on reva1 or later boards setup 1: ? etsec1, rgmii ? etsec2, rgmii table 10. default resistor options for reva1 to reva4 resistor setting resistor setting resistor setting resistor setting r258 short r267 open r276 short r285 open r259 open r268 short r277 open r286 short r260 short r269 open r278 short r287 open r261 open r270 short r279 open r288 short r262 short r271 open r280 short r289 open r263 open r272 short r281 open r290 short r264 short r273 open r282 short r291 open
powerquicc? mpc8313e reference design board (rdb), rev. 4 32 freescale semiconductor micro-jumper/resistor options for etsec1 figure 32 shows the graphical representation for setup 1. figure 32. default resistor options for reva1 table 11 shows the alternative configuration. setup 2: ? etsec1, usb dr with external ulpi usb phy (usb3300) ? etsec2, sgmii r265 open r274 short r283 open r293 short r266 short r275 open r284 short r292 open table 11. setup 2 resistor options for reva1 resistor setting resistor setting resistor setting resistor setting r258 open r267 short r276 open r285 short r259 short r268 open r277 short r286 open r260 open r269 short r278 open r287 short r261 short r270 open r279 short r288 open r262 open r271 short r280 open r289 short r263 short r272 open r281 short r290 open r264 open r273 short r282 open r291 short r265 short r274 open r283 short r293 open r266 open r275 short r284 open r292 short table 10. default resistor options for reva1 to reva4 (continued) resistor setting resistor setting resistor setting resistor setting
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 33 micro-jumper/resistor options for etsec1 figure 33 shows the graphical representation for setup 2. figure 33. setup 2 resistor options for reva1 table 12 shows the alternative configuration. setup 3: ? etsec1, usb dr with external ulpi usb phy (usb3300) ? etsec2, rgmii table 12. setup 3 resistor options for reva1 resistor setting resistor setting resistor setting resistor setting r258 open r267 short r276 open r285 short r259 short r268 open r277 short r286 open r260 open r269 short r278 open r287 short r261 short r270 open r279 short r288 open r262 open r271 short r280 open r289 short r263 short r272 open r281 short r290 open r264 open r273 short r282 open r291 short r265 short r274 open r283 short r293 open r266 open r275 short r284 open r292 short
powerquicc? mpc8313e reference design board (rdb), rev. 4 34 freescale semiconductor micro-jumper/resistor options for etsec1 figure 34 shows the graphical representation for setup 3. figure 34. setup 3 resistor options for reva1 table 13 shows the alternative configuration. setup 4: ? etsec1, rgmii ? etsec2, sgmii table 13. setup 4 resistor options for reva1 resistor setting resistor setting resistor setting resistor setting r258 short r267 open r276 short r285 open r259 open r268 short r277 open r286 short r260 short r269 open r278 short r287 open r261 open r270 short r279 open r288 short r262 short r271 open r280 short r289 open r263 open r272 short r281 open r290 short r264 short r273 open r282 short r291 open r265 open r274 short r283 open r293 short r266 short r275 open r284 short r292 open
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 35 micro-jumper/resistor options for etsec1 figure 35 shows the graphical representation for setup 4. figure 35. setup 4 resistor options for reva1 because the etsec1 ethernet switch phy on the rdb supports only rgmii, the etsec1 sgmii is not supported on the rdb. the resistor options listed only matter for the etsec1 pin connections. they have nothing to do with switching between etsec2 rgmii and sgmii. they are listed for reference. the switch between etsec2 rgmii and sgmii does not require hardware modification on the rdb. 4.3 revb boards for revb boards, three more resistor options (r311?r313) are added to route three ieee 1588 signals to the ieee 1588 connector. all other resistor options are the same as on the reva1 to reva4 boards. table 14 shows how to populate the resistors if these three optional signals are used. 4.4 revc boards for revc boards, 22 more resistor options (r311?r313) are added to route etsec2 rgmii signals either to l2 switch or marvell 88e1111 phy. all other resistor options are the same as on the revb boards. table 14. resistor options for revb using three optional ieee 1588 signals signal resistor setting resistor setting resistor setting tsec_tmr_trig2/tsec1_rx_er/ulpi1_dir r311 short r266 open r267 open tsec_tmr_alarm1/tsec1_rx_er/ulpi1_clk r312 short r280 open r281 open tsec_tmr_pp3/tsec1_rx_er/ulpi1_stp r313 short r284 open r285 open
powerquicc? mpc8313e reference design board (rdb), rev. 4 36 freescale semiconductor micro-jumper/resistor options for etsec1 table 15 shows how to populate the resistors if routing etsec2 rgmii signals to l2 switch. setup 1: etsec1, rgmii signals to l2 switch figure 36 shows the graphical representation for setup 1. figure 36. setup 2 resistor options for revc table 15. setup 1 resistor options for revc resistor setting resistor setting resistor setting resistor setting resistor setting r118 short r346 open r336 short r370 short r360 short r342 open r123 short r337 open r352 short r361 open r119 short r347 open r338 short r353 open r362 short r343 open r330 short r339 open r354 short r363 open r120 short r331 open r340 short r355 open r365 short r344 open r332 short r341 open r356 short r364 open r121 short r333 open r345 open r357 open r366 short r345 open r334 short r350 short r358 short r367 open r122 short r335 open r346 open r359 open - -
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 37 micro-jumper/resistor options for etsec1 table 16 shows the alternative configuration. setup 2: ? etsec1, rgmii signals to phy figure 37 shows the graphical representation for setup 2. figure 37. setup 2 resistor options for revc table 17 shows the alternative configuration. setup 3: ? etsec1, sgmii signals to phy table 16. setup 2 resistor options for revc resistor setting resistor setting resistor setting resistor setting resistor setting r118 open r346 open r336 short r370 short r360 short r342 short r123 short r337 open r352 short r361 open r119 open r347 short r338 open r353 short r362 open r343 short r330 open r339 short r354 open r363 short r120 open r331 short r340 open r355 short r365 open r344 short r332 open r341 short r356 open r364 short r121 open r333 short r345 short r357 short r366 open r345 short r334 open r350 open r358 open r367 short r122 open r335 short r346 short r359 short - - table 17. setup 3 resistor options for revc resistor setting resistor setting resistor setting resistor setting resistor setting r118 open r346 open r336 short r370 short r360 short r342 short r123 short r337 open r352 short r361 open
powerquicc? mpc8313e reference design board (rdb), rev. 4 38 freescale semiconductor mpc8313e rdb board configuration figure 38 shows the graphical representation for setup 3. figure 38. setup 2 resistor options for revc 5 mpc8313e rdb board configuration this section describes the opera tional frequency and c onfiguration options of the mpc8313e rdb. 5.1 pci operating frequency an m66en input pin determines the frequency of the pci interface. on the mpc8313e rdb, the m66en signal level is determined by the pci agent card connected to the minipci or pci slot. if a 33 mhz-only card is inserted, the m66en signal is driven to 0 by the pci agent card according to the pci specification. however, it is pulled to 1 if it can perform at 66 mhz. by default, the mpc8313e rdb runs its pci interfaces at 66 mhz unless a 33-mhz pci card is inserted. 5.2 reset configuration word the reset configuration word (rcw) controls the clock ratios and other basic device functions such as pci host or agent mode, boot location, and endian mode. th e reset configuration word is divided into reset r119 open r347 short r338 open r353 short r362 open r343 short r330 open r339 short r354 open r363 short r120 open r331 short r340 open r355 short r365 open r344 short r332 open r341 short r356 open r364 short r121 open r333 short r345 short r357 short r366 open r345 short r334 open r350 open r358 open r367 short r122 open r335 short r346 short r359 short - - table 17. setup 3 resistor options for revc (continued) resistor setting resistor setting resistor setting resistor setting resistor setting
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 39 mpc8313e rdb board configuration configuration word lower (rcwl) and reset configur ation word higher (rcwh) and is loaded from the local bus during the power-on or hard reset flow. the default rcw low bit setting is 0x6204_0000. the default rcw high bit setting is 0xa060_7800. the rcw is located at the lowest 64 bytes of the boot flash memory, which is 0xfe00_0000 if the default memory map is used. table 18 shows the default rcw in the flash memory. the rcw definitions are shown in figure 39 and figure 40 . table 18. default rcw in flash memory address fe000000: 62626262 62626262 04040404 04040404 fe000010: 00000000 00000000 00000000 00000000 fe000020: a0a0a0a0 a0a0a0a0 60606060 60606060 fe000030: 78787878 78787878 00000000 00000000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field lbcm ddrcm ? spmf ? corepll 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? figure 39. reset configuration word low (rcwl) bit settings 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pcihost ? pciabr ? coredis bms bootseq swen romloc rlext ? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tsec1m tsec2m ? tle lale ? figure 40. reset configuration word high (rcwh) bit settings table 19. rcwl bit descriptions bits name meaning description 0 lbcm local bus clock mode local bus controller clock: csb_clk 0: default ratio 1:1 1 ratio 2:1 1 ddrcm ddr sdram clock mode ddr controller clock: csb_clk 0 ratio 1:1 1: default ratio 2:1 2?3 ? reserved must be set to 10
powerquicc? mpc8313e reference design board (rdb), rev. 4 40 freescale semiconductor mpc8313e rdb board configuration 4?7 spmf[0?3] system pll multiplication factor 0000 reserved 0001 reserved 0010 (default) 2:1 0011 3:1 0100 4:1 0101 5:1 4?7 spmf[0?3] system pll multiplication factor 0110 6:1 0111-1111 reserved 8 ? reserved must be cleared. 9?15 corepll [0?6] value coreclk: csb_clk vco divider nn 0000 0 pll bypassed pll bypassed 00 0001 0 1:1 2 01 0001 0 1:1 4 10 0001 0 1:1 8 00 0001 1 1.5:1 2 01 0001 1 1.5:1 4 10 0001 1 1.5:1 8 00 0010 0 (default) 2:1 2 9?15 corepll [0?6] 01 0010 0 2:1 4 10 0010 0 2:1 8 00 0010 1 2.5:1 2 01 0010 1 2.5:1 4 10 0010 1 2.5:1 8 00 0011 0 3:1 2 01 0011 0 3:1 4 10 0011 0 3:1 8 16?31 ? reserved. must be cleared. table 19. rcwl bit descriptions (continued) bits name meaning description
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 41 mpc8313e rdb board configuration table 20. reset configuration word high (rcwh) bit descriptions bits name meaning description 0 pcihost pci host mode 0 pci agent 1: default pci host 1 reserved ? must be cleared 2 pciarb pci1 arbiter 0 pci arbiter disabled 1: default pci arbiter enabled 3 reserved ? must be cleared 4 coredis core disable mode 0: default e300 enabled 1 e300 disabled 5 bms boot memory space 0: default 0x0000_0000?0x007f_ffff 1 0xff80_0000?0xffff_ffff 6?7 bootseq boot sequencer configuration 00: default boot sequencer is disabled 01 boot sequencer load configuration from i 2 c 10 boot sequencer load configuration from eeprom 11 reserved 8 swen software watchdog enable 0: default disabled 1 enabled 9?11 romloc boot rom interface location 000 ddr2 sdram 001 pci 010,011, 100 reserved 101 local bus gpcm, 8 bits 110: default local bus gpcm, 16 bits 111 reserved 12?13 rlext boot rom location extension 00: default legacy mode 01 nand flash mode 10,11 reserved 14-15 reserved ? must be cleared 16-18 tsec1m tsec1 mode 000 mii mode 001 rmii mode 011:default rgmii mode 101 rtbi mode 110 sgmii mode 010,100,111 reserved
powerquicc? mpc8313e reference design board (rdb), rev. 4 42 freescale semiconductor mpc8313e rdb board configuration 5.3 power supply the mpc8313e rdb requires a power supply from the atx power connector. the atx supply connector directly provides 12-v, 5-v, and 3.3-v voltages. core voltage, ddr2 voltage, rgmii voltage, and phy-specific voltages are provided by either switchi ng or linear regulated depending on the voltage drop and current consumption requirement. mpc8313e power-down mode is supported. a regulator that can be shut down is implemented for this purpose. the mpc8313e does not require the core supply voltage and io supply voltages to be applied in any particular order. however, during the power ramp up, before the power supplies are stable, there may be an interval when the io pins are actively driven. after the power is stable, as long as poreset is asserted, most io pins are three-stated. to minimize the time that io pins are actively driven, apply core voltage before io voltage and assert poreset before the power supplies fully ramp up. table 21 shows the power supply table. 19-21 tsec2m tsec2 mode 000 mii mode 001 rmii mode 011:default rgmii mode 101 rtbi mode 110 sgmii mode 010,100,111 reserved 22-27 reserved ? must be cleared 28 tle true little endian 0: default big-endian mode 1 true little endian mode 29 lale local bus ale signal timing 0: default normal lale timing 1 lale is negated 1/2 lbc_controller_clk earlier. 30-31 reserved ? must be cleared table 21. power supply usage summary voltage usage budget solution 1 v shutdownable vdd, avdd1 <1 a mic1510etb+ regulator (3 a) with tracking 1 v vddc <10 a mic1953eub+ switching 1.2 v vsc7385, 88e1111 1.75 a + 0.4 a mic37302 ldo (3 a) 1.8 v ddr2 0.5 a + ddr chip x2pcs mic37302 ldo (3 a) 2.5 v rgmii 0.2 a + 0.2 a + 0.2 a mic39100-2.5ws (1 a) 3.3 v general io variable direct from atx power table 20. reset configuration word high (rcwh) bit descriptions (continued) bits name meaning description
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 43 getting started 5.4 chip-select assignments and memory map table 22 shows an example memory map on the mpc8313e rdb for u-boot in nor flash memory. 6 getting started this section describes how to boot the mpc8313e rdb. the on-board flash memory is preloaded with a flash image from the factory. before powering up the board, verify that all the on-board dip switches and jumpers are set to the factory defaults according to the settings listed in section 6.1, ?board jumper settings,? and make all external connections as described in section 6.2, ?external cable connections.? caution avoid touching areas of integrated circ uitry and connectors; static discharge can damage circuits. warning only the 3.3-v pci card is supported. turn off power during insertion and removal of a pci card. 5 v switching power, pci cards 0.5?1 a direct from atx power 12 v none nil direct from atx power table 22. example memory map, local access window, and chip-select assignments address range target interface chip-select line device name port size (bits) 0x0000_0000?0x07ff_ffff ddr2 mcs0# ddr sdram (128 mbyte) 32 0x8000_0000?0x9fff_ffff pci nil pci memory space (512 mbyte) 32 0xe000_0000?0xe00f_ffff internal bus nil immr (1 mbyte) ? 0xe200_0000?0xe20f_ffff pci nil pci i/o space (1 mbyte) 32 0xe280_0000?0xe280_7fff nand controller lcs1# nand flash window (32kbyte) 8 0xf000_0000?0xf001_ffff local bus lcs2# vsc7385 (128kbyte) 8 0xfa00_0000?0xfa00_7fff local bus lcs3# read/write buffer (32kbyte) 8 0xfe00_0000?0xfe7f_ffff local bus lcs0# boot flash (8 mbyte) 16 table 21. power supply usage summary voltage usage budget solution
powerquicc? mpc8313e reference design board (rdb), rev. 4 44 freescale semiconductor getting started 6.1 board jumper settings figure 41 shows the top view of the mpc8313e rdb with pin 1 marked for each reference. there are two dip switches (s3, s4) and one jumper (j19). their default settings are listed in table 23 . figure 41. mpc8313e-rdb top view table 23. default dip switch and jumper setting reference default setting s3 0000 (all on) s4 1111 (all off) j19 open (no jumper) pin 1 p8 d12 p1 d6 cop connector s2 s1 j20 d16 p11 j19 s4 j23 j22 j24 j21 u44 s3 1234 on 12 3 4 on d3 d22 d5 d2 d1 d21 d20 d4 mpc8313e p3 p2 p5 p6 p7 d15 d14 d17 d13 d7 d8 d9 d10 d11 p4 pci slot [idsel-ad15] minipci slot [idsel-ad14] cfg_rst_src0 cfg_rst_src1 cfg_rst_src2 cfg_rst_src3 rsvd cfg_boot_ecc_dis rev1 boot1# (nand) vbus ctl0 ctl1 lcd connector lcd backlight lcd connector mcu connector power on button, reset button programmable led0-7 micro-jumper/resistor option area for rgmii/ulpi/ieee1588 selection mpc8313e-rdb s/n: ieee 1588 connector (optional) p10 and l2 switch/phy selection
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 45 getting started 6.2 external cable connections do not turn on power until all cables are connected a nd the serial port is configured as described in section 6.3, ?serial port configuration (pc).? connect the serial port of the mpc8313e rdb system and the personal computer using an rs-232 cable as shown in figure 42 . figure 42. external connections 6.3 serial port configuration (pc) before powering up the mpc8313e rdb, configure the serial port of the attached computer with the following values: ? data rate: 115200 bps ? number of data bits: 8 ? parity: none ? number of stop bits: 1 ? flow control: hardware/none 6.4 power up an atx-type power connector (p9) should be used to supply necessary dc power to the mpc8313e rdb. it can be provided by an atx-type power supply or from a mini-itx case. warning turn off the main power for the atx power supply/mini-itx case before the power connector is attached. pc g0 g1 g2 g3 g4 g5 a b a b a b a b a b cat-5 cable to one of the ports (lower- right-most is etsec2, other five are etsec1) straight-through 9-conductor serial cable, m-f (upper port for uart1 default; lower port for uart2)
powerquicc? mpc8313e reference design board (rdb), rev. 4 46 freescale semiconductor mpc8313e rdb software power up the power supply. a few seconds after power up, the u-boot prompt => should be received by the serial terminal program as shown here: u-boot 1.x.x (fsl development) (date - time) mpc83xx clock configuration: coherent system bus: xxx mhz core: yyy mhz local bus controller: xxx mhz local bus: yy mhz ddr: xxx mhz ? hit any key to stop autoboot: 0 => note the normal function of the product may be disturbed by strong electromagnetic interference. if so, simply reset the product to resume normal operation by following the instructions in the manual. if normal function does not resume, use the product in another location. 7 mpc8313e rdb software a board support package (bsp) is pre-installed on the mpc8313e rdb. this bsp consists of a bootloader (u-boot), a generic powerpc linux-based system, a nd an associated file system. u-boot, the linux kernel, and the file system reside in the on-board flash memory. at power up, the linux system runs on the mpc8313e rdb. the mpc8313e rdb bsp generation takes advantage of a tool called the linux target image builder (ltib). ltib is a suite of tools that leverages existing open source configuration scripts and source code packages and bundles them into a single bsp-generati on package. the source code packages include boot loaders and linux kernel sources as well as many user-space source code packages to build a complete bsp. ltib also provides compiler packages required to build the bsp. freescale developers use ltib to create bsps for a multitude of freescale development targets. ltib leverages as many bsp elements as possible for all freescale-supported targets, and it offers the flexibility to customize components that require platform-specific modifications. the mpc8313e rdb bsp release package contains a file named mpc8313e rdb-.iso . this file is an iso image that can be burned to a cd-rom or mounted directly from your hard disk. note that is the release creation date. the ltib installation script that installs all necessary packages on a host linux pc and allows you to modify the bsp and packages within the bsp is in the /ltib-mpc8313e-rdb subdirectory within the iso image. this iso image contains a file called readme.txt that describes how to genera te and install the bsp on the mpc8313e rdb hardware platform. readme.txt contains the latest information for each bsp release. the iso image also contains release notes.txt , which describes changes to the current bsp version versus earlier releases. to rebuild the bsp package or to add application software, carefully follow the instructions in readme.txt . this file contains details on how to build , run, and install the bsp. it guides the
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 47 frequently asked questions (faqs) user to achieve a successful re-installation of the bsp on the mpc8313e rdb. this iso image contains the following documents as well: ? mpc8313erdbug.pdf . this user's guide document in pdf format. ? mpc8313e-rdb_schematic.pdf . the platform schematic in pdf format. ? sec2swug.pdf . user's guide for the driver software of the security engine. this document details the driver software interface to boost the throughput pe rformance of security applications such as ipsec. ? ltibfaq.pdf . frequently asked questions for ltib, whic h is a useful document describing how to use ltib to build the iso image. for more information on the mpc8313e rdb, visit the freescale website listed on the back cover of this document. to run demonstrations or to acquire details of freescale third-party applications for this mpc8313e rdb, contact your local freescale sales office. 8 frequently asked questions (faqs) here are some commonly asked questions and their respective answers. 8.1 what are the differences among rdb revisions? there are five revisions of the rdb, which are reva, reva1, reva2, reva3, reva4, revb and revc. table 24 lists and describes these revisions. table 24. mpc8313e-rbd revisions revision description reva there are two major issues on the reva board: ? on-chip phy usb signals (dp, dm) are swapped. to use the usb, use a usb cable that swaps the signals (the cable is attached in the reva package). ? nand flash memory cannot be used as a boot device. reva1 fixes both major issues on the reva board. the boot-from-nand on the reva1 rdb has been verified. however, on the current bsp preloaded on reva1 rdb, nand flash memory is empty, so it is also not bootable. booting from nand flash memory will be supported in a future release of the bsp. software for reva and reva1 differs only in the or1[bctld] register setting for nand flash memory. that is, reva or1[bctld] is 1; while reva1 or1[bctld] is 0. reva2 a minor update from reva1 for mass production. it updates the silkscreen and adds a 12-v fan connector (j25) and resistor loading for atx power. software can be shared without modification between reva1 and reva2. reva3 fixes the pmc register issue mentioned in section 8.5, ?power management control (pmc) registers cannot be accessed? ? because of a processor erratum, a 166 mhz csb frequency should be used. for this reason, some reva3 and all later boards have 33 mhz instead of 66 mhz as the clock input (check your board u15 oscillator marking). the core/csb/ddr frequency setting is 333/166/333 mhz. however, there are two drawbacks: ? pci bus can run at up to only 33 mhz ? pci/mini-pci card can run at 66 mhz (has its m66en pulled up) and should be used. even the pci bus on the rdb runs at only 33 mhz. otherwise, the pci frequency is further divided and it becomes 16.6 mhz.
powerquicc? mpc8313e reference design board (rdb), rev. 4 48 freescale semiconductor frequently asked questions (faqs) 8.2 what should i do if the flash (nor flash) image on the rdb is accidentally erased? you should set the rdb to use a hardcoded reset configuration and reprogram the flash memory by debugger (for example, codewarrior debugger + usbtap). to use a hardcoded reset configuration, set dip switch s3 as off-on-off-off (1011). on the other hand, if there is a reset configuration in nand flash or the i 2 c eeprom, you may want to use either one as a hard reset configuration source. alternatively, some reva3 a nd all later boards have the i 2 c eeprom bootloader programmed. it can be used to reprogram the nor flash memory without a debugger. the procedure is as follows: 1. power off the board and set dip switch s3 as on-off-on-on (0100). 2. connect the board to kermit (a uart terminal program; the other terminal program does not work at this mode). kermit can be downloaded from http://kermit.wwarthen.com/download.htm. 3. set the baud rate in kermit as 38400 bps (for a 66 mhz clock-in rdb) or 19200 bps (for a 33 mhz clock-in rdb). 4. power on the board and you should see the following in kermit: hello and welcome to i2c bootloader ## ready for binary (kermit) download 5. go to kermit send and select the u-boot image bina ry to be written into flash memory. 6. wait for the file transfer and flash programming until you see success in the kermit window. 7. power off the board and set dip switch s3 back to on-on-on-on (0000). 8. power on the board and you should see a running u-boot. reva4 fixes the second drawback point of reva3. revb ? added gtx_clk125 sourced from external 125 mhz oscillator. ? added an optional ieee 1588 connector (p10). ? added three more resistor options (r311?r313) to route 3 ieee 1588 signals that only available in etsec1 to the ieee 1588 connector. ? changed s4 to support lb_por_cfg_boot_ecc_dis. ? changed sd chip select signal from spisel (gpio31) to gpio13. revc ? added a marvell 88e1111 phy. phy address assigned to 0x3. use same irq3# as l2 switch. ? added resistor option for rgmii signals route to either to l2 switch or marvell 88e1111 phy. ? added sgmii support for etsec1 if using the added marvell 88e1111 phy. (sgmii for etsec2 already supported.) ? added pll cy23ep05sxc-1 u86 to phy gerneated 125 mhz clock. ? changed default tsec1_gtx_clk125 clock source to pll cy23ep05sx-1 instead of external 125 mhz oscillator. ? changed u36 1a linear regulator mic39100-2.5ws to 3a mic37302wr for higher 2.5v power consumption by additional phy. ? changed default dac to 16-bit spi controlled max5203beub+ (u47). table 24. mpc8313e-rbd revisions revision description
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 49 revision history 8.3 what is the hardware setting for boot from nand flash? set dip switch s4 as off-off-off-on (1110) and set dip switch s3 as on-on-on-off (0001). note that there is no boot image on nand flash memory with the default shipment. 8.4 some atx power supplies do not work with the rdb? some atx power supplies may need a large 5-v loading to stabilize the 3.3-v output; otherwise, you may observe the 3.3 v lowered to around 2.9 v?3 v. the consequence can be a periodic reset by the on-board voltage monitoring circuit. for a workaround, you may take one of the following actions: ? add a 5-v loading to the power supply, fo r example, attach a hard disk drive. ? change to another atx power supply that does not require a large 5-v loading. ? use the power supply provided with the rdb package. starting from revision reva2, a resistor loading for 5 v is added. it should work better with the atx power supply that requires large 5-v loading. if there is still a problem, simply apply one of the workarounds presented here. 8.5 power management control (pmc) registers cannot be accessed? the pmc registers range from immr + 0x0b00 to immr + 0x0bff. when this area is accessed in u-boot, the rdb hangs up. it appears that the pmc block is related to the jtag interface; trst must not be pulled down for normal operation of the pmc block. possible workarounds are as follows: ? attach a debugger to drive trst high during normal operation. ? remove the pull-down resistor (r37) for trst. although this tested on some rdbs without any problem, it violates the hardware specification. if it does not work on your rdb, use another workaround. ? this problem is fixed in reva3 9 revision history table 25 provides a revision history for this document. table 25. document revision history rev. number date substantive change(s) 0 2/2007 initial public release. 1 4/2007 replaced a faulty table of contents and restructured sections of the document for clarity. 2 4/2007 added information to section 8, frequently asked questions (faqs)
powerquicc? mpc8313e reference design board (rdb), rev. 4 50 freescale semiconductor revision history 3 3/2008 ? added gtx_clk125 sourced from external 125 mhz oscillator. ? added an optional ieee 1588 connector (p10). ? added three more resistor options (r311?r313) to route three ieee 1588 signals that are only available in etsec1 to the ieee 1588 connector. ? changed s4 to support lb_por_cfg_boot_ecc_dis. ? changed sd chip select signal from spisel(gpio31) to gpio13. 4 8/2008 ? added a marvell 88e1111 phy. phy address assigned to 0x3. use same irq3# as l2 switch. ? added resistor option for rgmii signals route to either to l2 switch or marvell 88e1111 phy. ? added sgmii support for etsec1 if using the added marvell 88e1111 phy. (sgmii for etsec2 already supported.) ? added pll cy23ep05sxc-1 u86 to phy gerneated 125 mhz clock. ? changed default tsec1_gtx_clk125 clock source to pll cy23ep05sx-1 instead of external 125 mhz oscillator. ? changed u36 1a linear regulator mic39100-2.5ws to 3a mic37302wr for higher 2.5v power consumption by additional phy. ? changed default dac to 16-bit spi controlled max5203beub+ (u47). table 25. document revision history (continued) rev. number date substantive change(s)
powerquicc? mpc8313e reference design board (rdb), rev. 4 freescale semiconductor 51 revision history this page intentionally left blank
document number: mpc8313erdbug rev. 4 02/2009 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 +1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. the powerpc name is a trademark of ibm corp. and is used under license. ieee 1588 are registered trademarks of the institute of electrical and electronics engineers, inc. (ieee). this product is not endorsed or approved by the ieee. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2008. all rights reserved.

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