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integrated silicon solution, inc. ? 1-800-379-4774 1 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 32,768/65,536-bit spi serial electrically erasable prom features ? 2.1 mhz clock rate low power cmos ? active current less than 3.0 ma (5.5v) ? standby current less than 10 a (5.5v) low-voltage operation ? is25c64-3 & is25c32-3 (vcc = 2.5v to 5.5v) ? is25c64-2 & is25c32-2 (vcc = 1.8v to 5.5v) block write protection ? protect 1/4, 1/2, or entire array 32 byte page write mode serial peripheral interface (spi) compatible ? supports spi modes 0 (0,0) and 3 (1,1) self timed write cycles (5 ms typical) high-reliability ? endurance: 1 million cycles per byte ? data retention: 100 years ? esd protection >4000v industrial temperature available 8-pin pdip or soic, and 14-pin tssop packages preliminary information november 2001 the is25c64-2 is a 1.8v (1.8v-5.5v) 64k-bit (8192x8) electrically erasable prom, is25c64-3 is a 2.5v (2.5v- 5.5v) 64k bit (8192x8) electrically erasable prom, is25c32-2 is a 1.8v (1.8v-5.5v) 32k-bit (4096x8) electri- cally erasable prom, is25c32-3 is a 2.5v (2.5v-5.5v) 32k-bit (4096x8) electrically erasable prom. the is25cxx (is25c64-2, is25c64-3, is25c32-2 and is25c32-3) family is a low-cost and low voltage/low power spi serial eeprom. it is fabricated using issi's ad- vanced cmos eeprom technology and provides a low power and low voltage operation for low power industrial and commercial application. the is25cxx family is available in 8 pin pdip, 8 pin soic, and 14 pin tssop packages. the is25cxx is enabled through the chip select pin ( cs ) and accessed via a 3-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all programming cycles are completely self-timed, and no separate erase cycle is required before write. block write protection is enabled by programming the status register with one of four configurations of write protection. separate program enable and program disable instructions are provided for additional data protection. hardware data protection is provided via the wp pin to protect against inadvertent write attempts to the status register. the hold pin can suspend communications without re-initializing the serial sequence. description product offering overview part no voltage speed standby icc read icc write icc temperature is25c64-2 1.8v-5.5v 500 khz < 5 a 1 ma 3 ma c,i is25c64-3 2.5v-5.5v 2.1mhz < 10 a 1 ma 3 ma c,i is25c32-2 1.8v-5.5v 500 khz < 5 a 1 ma 3 ma c,i is25c32-3 2.5v-5.5v 2.1mhz < 10 a 1 ma 3 ma c,i
2 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? pin configuration 8-pin dip and soic 14-pin tssop pin descriptions cs chip select sck serial data clock si serial data input so serial data output gnd ground v cc power wp write protect hold suspends serial input nc no connect pin descriptions serial clock (sck) - this pin is used to synchronize the communication between the microcontroller and the is25c64, is25c32. op-codes, byte addresses, or data present on the si pin and latched on the rising edge of the sck. data on the so pin is updated on the falling edge of the sck for spi modes (0,0 & 1,1). serial data input (si) - the si pin is used to input all op- codes, byte addresses, and data to be written to the device. input data is latched on the rising edge of the serial clock for spi modes (0,0 & 1,1). serial data output (so) - the so pin is used to transfer data out of the device. during a read cycle, data is shifted out on the falling edge of the serial clock for spi modes (0,0 & 1,1). chip select ( ): when the cs pin is low, the device is enabled. when the cs pin is high the device is disabled. cs high takes the so output pin to high impedance and forces the devices into a standby mode (unless an internal write operation is underway). the devices draws zero current in the standby mode. a high-to-low transition on cs is required prior to any sequence being initiated. a low-to-high transition on cs after a valid write sequence is what initiates an internal write cycle. 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 14 13 12 11 10 9 8 1 2 3 4 5 6 7 cs so nc nc nc wp gnd vcc hold nc nc nc sck si
integrated silicon solution, inc. ? 1-800-379-4774 3 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? pin descriptions continued: write protect ( ) - the wp pin will allow normal read/ write operations when held high. when wp is tied low and the wpen bit in the status register is set to "1", all write operations to the status register are inhibited. wp going low while cs is still low will interrupt a write to the status register. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit is set to 0. figure 10 illustrates the wp timing sequence during a write opera- tion. hold ( ): the hold pin is used to pause transmis- sion to the device while in the middle of a serial sequence without having to retransmit entire sequence at a later time. to pause, hold must be brought low while sck is low. the so pin is in a high impedance state during the time the part is paused, and transition on the si pins will be ignored. to resume communication, hold is brought high, while sck is low. ( hold should be held high any time this function is not being used.) hold may be tied high directly to vcc or tied to vcc through a resistor. the hold timing diagram illustrates hold timing sequence. serial interface description master: this device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the device always operates as a slave. msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code that defines the operations to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the device, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reinitialize the serial communications. block diagram status register 8192 x 8/4096 x 8 memory array hold cs wp clock so output buffer sck si data register mode decode logic gnd vcc address decoder
4 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? functional descriptions the is25c32/64 utilizes an 8-bit instruction register. the list of instructions and their operation codes are contained in table 1. all instructions, addresses, and data are transferred with the msb first and start with a high-to low cs transition. write enable (wren): this device will power-up in the write disable state when vcc is applied. all program- ming instructions must therefore be preceded by a write enable instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instruction is indepen- dent of the status of the wp pin. read status register (rdsr): the read status register instruction provides access to the status register. the ready/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. table 1. instruction set instruction name format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array write 0000 x010 write data to memory array table 2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 wpen x x x bp1 bp0 wen rdy table 3. read status register bit definition bit definition bit 0 ( rdy ) bit 0 = 0 ( rdy ) indicates the device is ready. bit 0 = 1 indicates the write cycle is in progress. bit 1(wen) bit 1 = 0 indicates the device is not write enabled. bit 1 = 1 indicates the device is write enabled. bit 2 (bpo) see table 4 bit 3 (bp1) see table 4 bits 4 - 6 are 0s when the device is not an internal write cycle. bits 7 (wpen) see table 5. bits 0-7 are 1s during an internal write cycle. table 4. status register format status register bits array addresses protected level bp1 bp0 is25c32 is25c64 0 0 0 none none 1(1/4) 0 1 0c00 1800 -0fff -1fff 2(1/2) 1 0 0800 1000 -0fff -1fff 3(all) 1 1 0000 0000 -0fff -1fff write status register (wrsr): the wrsr in- struction allows the user to select one of four levels of protection. the device is divided into four array seg- ments. one quarter (1/4), one half (1/2) or all of the memory segments can be protected. any of the data within any selected segment will therefore be read only. the block write protection levels and corresponding status register control bits are shown in table 4. the three bits, bp, bp1 and wpen are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. wren, twc, rdsr).
integrated silicon solution, inc. ? 1-800-379-4774 5 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? the wrsr instruction also allows the user to enable or disable the write protect ( wp ) pin through the use of the write protect enable (wpen) bit. hardware write protec- tion is enabled when the wp pin is low and the wpen bit is '"1". hardware write protection is disabled when either the wp pin is high or the wpen bit is "0". when the device is hardware write protected, writes to the status register, including the block protect bits and the wpen bit, and the block-protected sections in the memory array are dis- abled. writes are only allowed to sections of the memory which are not block-protected. note: when the wpen bit is hardware write protected, it cannot be changed back to "0", as long as the pin is held low. read sequence (read) : reading the device via the so (serial output) pin requires the following sequence. after the cs line is pulled low to select a device, the read op-code is transmitted via the si line followed by the byte address to be read (a15-a0, refer to table 6). upon completion, any data on the si line will be ignored. the data (d7-d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data comes out. the read sequence can be continued since the byte address is automati- cally incremented and data will continue to be shifted out. when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. write sequence (read): in order to program the device, two sperate instructions must be executed. first, the device must be write enabled via the write enable (wren) instruction. then a write (write) instruction may be executed. also the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. during an internal write cycle, all commands will be ignored except the rdsr instruction. a write instruction requires the following sequence. after the cs line is pulled low to select the device, the write op-code is transmitted via the si line followed by the byte address (a15-a0) and the data (d7-d0) to be programmed (refer to table 6). programming will start after the cs pin is brought high. (the low to high transition of the cs pin must occur during the sck low- time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device can be deter- mined by initiating a read status register (rdsr) instruction. if bit 0 = 1, the write cycle is still in progress. if bit 0 = 0 , the write cycle has ended. only the read status register instruction is enabled during the write programming cycle. the device is capable of the 32-byte page write operation. after each byte of data is received, the five low order address bits are internally incremented by one; the high order bits of the address will remain constant. if more than 32 bytes of data are transmit- ted, the address counter will roll over the previously written data will be overwritten. the device is auto- matically returned to the write disable state at the completion of a write cycle. note: if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs falling edge is required to re-initiate the serial communi- cation. table 5. wpen operation protected unprotected protected wpen wen blocks blocks register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable table 6. address key name is25c32 is25c64 a n a 11- a 0 a 12- a 0 don't a 15- a 12 a 15- a 13 care bits
6 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? absolute maximum ratings (1) symbol parameter value unit v s supply voltage -0.5 to +6.25 v v p voltage on any pin ?1.0v to + 7.0v v t bias temperature under bias ?40 to +85 c t stg storage temperature ?65 to +150 c i out output current 5 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range (is25c64-2 and is25c32-2) range ambient temperature v cc commercial 0c to +70c 1.8v to 5.5v industrial ?40c to +85c 1.8v to 5.5v capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters and not 100% tested. 2. test conditions: t a = 25c, f = 1 mhz, vcc = 5.0v. operating range (is25c64-3 and is25c32-3) range ambient temperature v cc commercial 0c to +70c 2.5v to 5.5v industrial ?40c to +85c 2.5v to 5.5v
integrated silicon solution, inc. ? 1-800-379-4774 7 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? dc electrical characteristics symbol parameter test conditions min. max. unit v ol 1 output low voltage v cc = 1.8v, i ol = 0.15 ma ? 0.2 v v ol 2 output low voltage v cc = 2.5v, i ol = 1.0 ma ? 0.4 v v o h1 output high voltage v cc = 1.8v, i o h = -100ua v cc - 0.2 ? v v o h2 output high voltage v cc = 2.5v, i o h = -1ma v cc - 0.8 ? v v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage ?1.0 v cc x 0.3 v i li input leakage current v in = v cc max. -3.0 3 a i lo output leakage current -3.0 3 a power supply characteristics symbol parameter test conditions min. max. unit i cc 1 vcc operating current read at 500 khz (vcc=5v) ? 1.0 ma i cc 2 vcc operating current write at 500 khz (vcc=5v) ? 3.0 ma i sb 1 standby current vcc = 1.8v ? 5 a i sb 2 standby current vcc = 5.5v, v in = v cc or gnd ? 10 a
8 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? ac characteristics applicable over recommended operating range from t a = -40 c to +85 c, v cc = as specified, cl = 1 ttl gate and 100 pf (unless otherwise noted). 1.8v 2.5v symbol parameter min max min max units f sck sck clock frequency 0 0.5 0 2.1 mhz t ri input rise time ? 2 ? 2 s t fi input fall time ? 2 ? 2 s t wh sck high time 800 ? 200 ? ns t wl sck low time 800 ? 200 ? ns t cs cs high time 1000 ? 250 ? ns t css cs setup time 1000 ? 250 ? ns t csh cs hold time 1000 ? 250 ? ns t su data in setup time 100 ? 50 ? ns t h data in hold time 100 ? 50 ? ns t hd hold setup time 400 ? 100 ? ns t cd hold time 400 ? 300 ? ns t v output valid 0 800 0 200 ns t ho output hold time 0 ? 0 ? ns t lz hold to output low z 0 200 0 200 ns t hz hold to output high z ? 200 ? 200 ns t dis output disable time ? 1000 ? 250 ns t wc write cycle time ? 20 ? 10 ms endurance (1) 5.0v, 25c, page mode 1m ? 1m ? write cycles
integrated silicon solution, inc. ? 1-800-379-4774 9 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? timing diagrams wrdi timing wren timing synchronous data timing cs sk d in d out v ih v il v ih v il v ih v il v oh v ol valid in high-z high-z t css t wh t wl t h t su t cs t csh t v t ho t dis high-z wren op-code cs sk d in d out high-z wrdi op-code cs sk d in d out
10 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? read timing wrsr timing rdst timing cs sk din dout instruction 76 54321 0 data o u t cs sk din dout instruction 76 54321 0 data i n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sk din dout instruction byte address 76 54321 0 data out
integrated silicon solution, inc. ? 1-800-379-4774 11 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? timing write timing 76 54321 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sk din dout instruction byte address data in cs sck hold d out t cd t hd t hz t lz t hd t cd
12 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 06/25/02 is25c32-2/3 is25c64-2/3 issi ? ordering information commercial range: 0c to +70c voltage frequency range part number package 500 khz 1.8v is25c32-2p 300-mil plastic dip to 5.5v is25c32-2g small outline (jedec std) is25c32-2z 14-pin tssop 500 khz 1.8v is25c64-2p 300-mil plastic dip to 5.5v is25c64-2g small outline (jedec std) is25c64-2z 14-pin tssop 2.1 mhz 2.5v is25c32-3p 300-mil plastic dip to 5.5v is25c32-3g small outline (jedec std) is25c32-3z 14-pin tssop 2.1 mhz 2.5v is25c64-3p 300-mil plastic dip to 5.5v IS25C64-3G small outline (jedec std) is25c64-3z 14-pin tssop ordering information industrial range: ?40c to +85c voltage frequency range part number package 500 khz 1.8v is25c32-2pi 300-mil plastic dip to 5.5v is25c32-2gi small outline (jedec std) is25c32-2zi 14-pin tssop 500 khz 1.8v is25c64-2pi 300-mil plastic dip to 5.5v is25c64-2gi small outline (jedec std) is25c64-2zi 14-pin tssop 2.1 mhz 2.5v is25c32-3pi 300-mil plastic dip to 5.5v is25c32-3gi small outline (jedec std) is25c32-3zi 14-pin tssop 2.1 mhz 2.5v is25c64-3pi 300-mil plastic dip to 5.5v IS25C64-3Gi small outline (jedec std) is25c64-3zi 14-pin tssop issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com

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