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publication# 080153 rev : e amendment: / 0 issue date: october 1999 am79574 subscriber line interface circuit distinctive characteristics programmable constant resistance feed line-feed characteristics independent of battery variations programmable loop-detect threshold on-chip switching regulator for low-power dissipation pin for external ground-key noise filter capacitor available ground-key detect option available two-wire impedance set by single external impedance polarity reversal feature tip open state for ground-start lines test relay driver optional on-hook transmission block diagram vtx rd rdc c1 c2 c3 c4 e1 e0 input decoder and control two-wire interface switching regulator test relay driver ring relay driver ringout testout gkfil a (tip) hpa hpb da db l bgnd chs chclk agnd 16855c-001 signal transmission power-feed controller off-hook detector ground-key detector ring-trip detector det notes: 1. am79574?e0 and e1 inputs; ring and test relay drivers sourced internally to bgnd. 2. output amplifier current gain (k 1 ) = 1000. rsn b(ring) vreg vbat qbat vcc vee
2 am79574 data sheet ordering information standard products legerity standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. am79574 temperature range package type device name/description valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on legerity?s standard military?grade products. jc j = 32-pin plastic leaded chip carrier (pl 032) c = commercial (0 c to 70 c)* performance grade blank = standard specification ?1 = performance grading ?2 = performance grading note: * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ?40 c to +85 c is guaranteed by characterization and periodic sampling of production units. am79574 subscriber line interface circuit valid combinations am79574 ?1 ?2 jc
slic products 3 connection diagram top view 1 notes: 1. pin 1 is marked for orientation. 2. tp is a thermal conduction pin tied to substrate (qbat). vcc bgnd a(tip) tp 43 2 323130 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 qbat rd hpb vtx vee 26 27 28 29 l c4 tp agnd testout hpa chs chclk e1 vbat da dgnd rdc c1 c3 det e0 c2 ringout db vreg b(ring) rsn
4 am79574 data sheet pin descriptions pin names type description agnd gnd analog (quiet) ground a(tip) output output of a(tip) power amplifier bgnd gnd battery (power) ground b(ring) output output of b(ring) power amplifier c3?c1 input decoder. ttl compatible. c3 is msb and c1 is lsb. c4 input test relay driver command. ttl compatible. logic low enables the driver. chclk input chopper clock. input to switching regulator (ttl compatible). freq = 256 khz (nominal). chs input chopper stabilization. connection for external stabilization components. da input ring-trip negative. negative input to ring-trip comparator. db input ring-trip positive. positive input to ring-trip comparator. det output detector. logic low indicates that the selected detector is tripped. logic inputs c3?c1, e1, and e0 select the detector. open-collector with a built-in 15 k ? pull-up resistor. dgnd gnd digital ground e0 input a logic high enables det . a logic low disables det . e1 input e1 = high connects the ground-key detector to det , and e1 = low connects the off-hook or ring-trip detector to det . hpa capacitor high-pass filter capacitor. a(tip) side of high-pass filter capacitor. hpb capacitor high-pass filter capacitor. b(ring) side of high-pass filter capacitor. l output switching regulator power transistor. connection point for filter inductor and anode of catch diode. has up to 60 v of pulse waveform on it and must be isolated from sensitive circuits. keep the diode connections short because of the high currents and high di/dt. qbat battery filtered battery supply for the signal processing circuits. rd resistor detector resistor. threshold modification and filter point for the off-hook detector. rdc resistor dc feed resistor. connection point for the dc feed current programming network, which also connects to the receiver summing node (rsn). v rdc is negative for normal polarity and positive for reverse polarity. ringout output ring relay driver. sourcing from bgnd with internal diode to qbat. rsn input the metallic current (ac and dc) between a(tip) and b(ring) = 1000 x the current into this pin. the networks that program receive gain, two-wire impedance, and feed resistance all connect to this node. this node is extremely sensitive. route the 256 khz chopper clock and switch lines away from the rsn node. testout output test relay driver. source from bgnd with internal diode to qbat. tp thermal thermal pin. connection for heat dissipation. internally connected to substrate (qbat). leave as open circuit or connected to qbat. in both cases, the tp pins can connect to an area of copper on the board to enhance heat dissipation. vbat battery battery supply. connected through an external protection diode. vcc power +5 v power supply. vee power ?5 v power supply. vreg input regulated voltage. provides negative power supply for power amplifiers, connection point for inductor, filter capacitor, and chopper stabilization. vtx output transmit audio. unity gain version of the a(tip) and b(ring) metallic voltage. vtx also sources the two-wire input impedance programming network.
slic products 5 absolute maximum ratings storage temperature ......................... ? 55 c to +150 c v cc with respect to agnd/dgnd...... ? 0.4 v to +7.0 v v ee with respect to agnd/dgnd ...... +0.4 v to ? 7.0 v v bat with respect to agnd/dgnd ..... +0.4 v to ? 70 v note: rise time of v bat (dv/dt) must be limited to 27 v/ s or less when q bat bypass = 0.33 f. bgnd with respect to agnd/dgnd.. +1.0 v to ? 3.0 v a(tip) or b(ring) to bgnd: continuous..................................... ? 70 v to +1.0 v 10 ms (f = 0.1 hz) .......................... ? 70 v to +5.0 v 1 s (f = 0.1 hz) .............................. ? 90 v to +10 v 250 ns (f = 0.1 hz) ........................ ? 120 v to +15 v current from a(tip) or b(ring) ....................... 150 ma voltage on ringout ........bgnd to 70 v above q bat voltage on testout ........bgnd to 70 v above q bat current through relay drivers .............................60 ma voltage on ring-trip inputs (da and db) ......................................... v bat to 0 v current into ring-trip inputs .................................. 10 ma peak current into regulator switch (l pin) ..............................................150 ma switcher transient peak off voltage on l pin ............................................+1.0 v c4 ? c1, e1, chclk to agnd/dgnd ....................... ? 0.4 v to v cc + 0.4 v maximum power dissipation, (see note) ...... t a = 70 c in 32-pin plcc package..............................1.74 w note: thermal limiting circuitry on-chip will shut down the circuit at a junction temperature of about 165 c. the device should never be exposed to this temperature. operation above 145 c junction temperature may degrade device reliability. see the slic packaging considerations for more information. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature ............................. 0 c to +70 c* v cc ..................................................... 4.75 v to 5.25 v v ee .................................................. ? 4.75 v to ? 5.25 v v bat ...................................................... ? 40 v to ? 58 v agnd/dgnd.......................................................... 0 v bgnd with respect to agnd/dgnd ........................ ? 100 mv to +100 mv load resistance on vtx to ground............. 10 k ? min operating ranges define those limits between which the functionality of the device is guaranteed. * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ? 40 c to +85 c is guaranteed by characterization and periodic sampling of production units.
6 am79574 data sheet electrical characteristics notes: * p.g. = performance grade ? 2 grade performance parameters are equivalent to ? 1 performance parameters except where indicated. description test conditions (see note 1) min typ max unit note analog (v tx ) output impedance 3 ? 4 analog (v tx ) output offset 0 c to 70 c ? 1* ? 40 c to +85 c ? 1 ? 35 ? 30 ? 40 ? 35 +35 +30 +40 +35 mv ? ? ? 4 4 analog (rsn) input impedance 1 20 ? 4 longitudinal impedance at a or b 300 hz to 3.4 khz 35 overload level z 2win = 600 to 900 ? 4-wire 2-wire ? 3.1 +3.1 vpk 2 transmission performance, 2-wire impedance 2-wire return loss (see test circuit d) 300 hz to 500 hz 500 hz to 2.5 khz 2500 hz to 3.4 khz 26 26 20 db 4, 11 longitudinal balance (2-wire and 4-wire, see test circuit c) r l = 600 ? longitudinal to metallic l-t, l-4 300 hz to 3.4 khz 300 hz to 3.4 khz ? 1* 48 52 db longitudinal to metallic l-t, l-4 200 hz to 1 khz normal polarity 0 c to +70 c ? 2* normal polarity ? 40 c to +85 c ? 2 reverse polarity ? 2 63 58 54 ? 4 ? 1 khz to 3.4 khz normal polarity 0 c to +70 c ? 2* normal polarity ? 40 c to +85 c ? 2 reverse polarity ? 2 58 54 54 ? 4 ? longitudinal signal generation 4-l 300 hz to 800 hz 300 hz to 800 hz ? 1* 40 42 longitudinal current capability per wire active state oht state 25 18 marms 4 insertion loss (2- to 4-wire and 4- to 2-wire, see test circuits a and b) gain accuracy 0 dbm, 1 khz, 0 c to +70 c 0 dbm, 1 khz, ? 40 c to +85 c 0 dbm, 1 khz, 0 c to +70 c ? 1* 0 dbm, 1 khz, ? 40 c to +85 c ? 1 ? 0.15 ? 0.20 ? 0.1 ? 0.15 +0.15 +0.20 +0.1 +0.15 db ? 4 ? 4 variation with frequency 300 hz to 3.4 khz relative to 1 khz 0 c to +70 c ? 40 c to +85 c ? 0.1 ? 0.15 +0.1 +0.15 ? 4 gain tracking +7 dbm to ? 55 dbm 0 c to +70 c ? 40 c to +85 c ? 0.1 ? 0.15 +0.1 +0.15 ? 4
slic products 7 electrical characteristics (continued) description test conditions (see note 1) min typ max unit note balance return signal (4- to 4-wire, see test circuit b) gain accuracy 0 dbm, 1 khz, 0 c to +70 c 0 dbm, 1 khz, ? 40 c to +85 c 0 dbm, 1 khz, 0 c to +70 c ? 1* 0 dbm, 1 khz, ? 40 c to +85 c ? 1 ? 0.15 ? 0.20 ? 0.1 ? 0.15 +0.15 +0.20 +0.1 +0.15 db ? 4 ? 4 variation with frequency 300 hz to 3.4 khz relative to 1 khz 0 c to +70 c ? 40 c to +85 c ? 0.1 ? 0.15 +0.1 +0.15 ? 4 gain tracking +7 dbm to ? 55 dbm 0 c to +70 c ? 40 c to +85 c ? 0.1 ? 0.15 +0.1 +0.15 ? 4 group delay f = 1 khz 5.3 s 4 total harmonic distortion (2- to 4-wire or 4- to 2-wire, see test circuits a and b) total harmonic distortion 0 dbm, 300 hz to 3.4 khz +9 dbm, 300 hz to 3.4 khz ? 64 ? 55 ? 50 ? 40 db idle channel noise c-message weighted noise 2-wire, 0 c to +70 c 2-wire, 0 c to +70 c ? 1* 2-wire, ? 40 c to +85 c +7 +7 +7 +15 +12 +15 dbrnc ? ? 4 4-wire, 0 c to +70 c 4-wire, 0 c to +70 c ? 1* 4-wire, ? 40 c to +85 c +7 +7 +7 +15 +12 +15 ? ? 4 psophometric weighted noise 2-wire, 0 c to +70 c 2-wire, 0 c to +70 c ? 1* 2-wire, ? 40 c to +85 c ? 83 ? 83 ? 83 ? 75 ? 78 ? 75 dbmp 7 ? 4, 7 4-wire, 0 c to +70 c 4-wire, 0 c to +70 c ? 1* 4-wire, ? 40 c to +85 c ? 83 ? 83 ? 83 ? 75 ? 78 ? 75 7 ? 4, 7 single frequency out-of-band noise (see test circuit e) metallic 4 khz to 9 khz 9 khz to 1 mhz 256 khz and harmonics ? 76 ? 76 ? 57 dbm 4, 5, 9 4, 5, 9 4, 5 longitudinal 1 khz to 15 khz above 15 khz 256 khz and harmonics ? 70 ? 85 ? 57 4, 5, 9 4, 5, 9 4, 5 line characteristics (see figure 1) bat = ?48 v, r l = 600 ? and 900 ? , r feed = 800 ? apparent battery voltage active state 47 50 53 v loop current accuracy active state ? 7.5 +7.5 % loop current ? tip open r l = 600 ? 1.0 ma loop current ? open circuit r l = 0 ? 1.0 loop current limit accuracy oht state active state ? 20 +20 % 10 fault current limit, i l lim (i ax + i bx ) a and b shorted to gnd 130 ma
8 am79574 data sheet electrical characteristics (continued) description test conditions (see note 1) min typ max unit note power dissipation, bat = ? 48 v, normal polarity on-hook open circuit state ? 1* 35 35 120 80 mw on-hook oht state ? 1* 135 135 250 200 on-hook active state ? 1* 200 200 400 300 off-hook oht state r l = 600 ? 500 750 off-hook active state r l = 600 ? 650 1000 supply currents v cc on-hook supply current open circuit state oht state active state 3.0 6.0 8.0 4.5 10.0 13.0 ma v ee on-hook supply current open circuit state oht state active state 1.0 2.3 3.0 2.3 3.7 6.0 v bat on-hook supply current open circuit state oht state active state 0.4 3.2 4.5 1.0 5.5 7.0 power supply rejection ratio (v ripple = 50 mvrms) v cc 50 hz to 3.4 khz ? 1* 25 30 45 45 db 6, 7 3.4 khz to 50 khz ? 1* 22 25 35 40 v ee 50 hz to 3.4 khz ? 1* 20 25 40 40 3.4 khz to 50 khz ? 1* 10 10 25 25 v bat 50 hz to 3.4 khz ? 1* 27 30 45 45 3.4 khz to 50 khz ? 1* 20 25 40 40 off-hook detector current threshold accuracy i det = 365/r d nominal ? 20 +20 % ground-key detector thresholds, active state, bat = ? 48 v (see test circuit f) ground-key resistance threshold b(ring) to gnd 2.0 5.0 10.0 k ? ground-key current threshold b(ring) to gnd 9 ma 8 midpoint to gnd 9 ring-trip detector input bias current ? 5 ? 0.05 a offset voltage source resistance 0 ? to 2 m ? ? 50 0 +50 mv 12 logic inputs (c4 ? c1, e0, e1, and chclk) input high voltage 2.0 v input low voltage 0.8 input high current all inputs except e1 ? 75 40 a input high current input e1 ? 75 45 input low current ? 0.4 ma
slic products 9 electrical characteristics (continued) relay driver schematics switching characteristics note: e1 is internally connected to a logical 0. description test conditions (see note 1) min typ max unit note logic output (det ) output low voltage i out = 0.8 ma 0.4 v output high voltage i out = ? 0.1 ma 2.4 relay driver outputs (ringout, testout) on voltage 50 ma source bgnd ? 2 bgnd ? .95 v off leakage 0.5 100 a clamp voltage 50 ma sink q bat ? 2 v symbol parameter test conditions temperature range min typ max unit note *tgkde e1 low to det high (e0 = 1) e1 low to det low (e0 = 1) ground-key detect state r l open, r g connected (see figure h) 0 c to +70 c ? 40 c to +85 c 0 c to +70 c ? 40 c to +85 c 3.8 4.0 1.1 1.6 s 4 tgkdd e0 high to det low (e1 = 0) 0 c to +70 c ? 40 c to +85 c 1.1 1.6 tgkd0 e0 low to det high (e1 = 0) 0 c to +70 c ? 40 c to +85 c 3.8 4.0 *tshde e1 high to det low (e0 = 1) e1 high to det high (e0 = 1) switchhook detect state r l = 600 ? , r g open (see figure g) 0 c to +70 c ? 40 c to +85 c 0 c to +70 c ? 40 c to +85 c 1.2 1.7 3.8 4.0 *tshdd e0 high to det low (e1 = 1) 0 c to +70 c ? 40 c to +85 c 1.1 1.6 *tshd0 e0 low to det high (e1 = 1) 0 c to +70 c ? 40 c to +85 c 3.8 4.0 ringout q bat bgnd testout q bat bgnd
10 am79574 data sheet switching waveforms notes: 1. unless otherwise noted, test conditions are bat = ? 48 v, v cc = +5 v, v ee = ? 5 v, r l = 600 ? , c hp = 0.22 f, r dc1 = r dc2 = 20 k ? , c dc = 0.1 f, r d = 51.1 k ? , no fuse resistors, two-wire ac output impedance, programming impedance (z t ) = 600 k ? resistive, receive input summing impedance (z rx ) = 300 k ? resistive. (see table 2 for component formulas.) 2. overload level is defined when thd = 1%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes that the two-wire ac load impedance matches the impedance programmed by z t . 4. not tested in production. this parameter is guaranteed by characterization or correlation to other tests. 5. these tests are performed with a longitudinal impedance of 90 ? and metallic impedance of 300 ? for frequencies below 12 khz and 135 ? for frequencies greater than 12 khz. these tests are extremely sensitive to circuit board layout. 6. this parameter is tested at 1 khz in production. performance at other frequencies is guaranteed by characterization. 7. when the slic is in the anti-sat 2 operating region, this parameter is degraded. the exact degradation depends on system design. the anti-sat 2 region occurs at high loop resistances when ? v bat ? ? ? v ax ? v bx ? is less than 14 v. 8. midpoint is defined as the connection point between two 300 ? series resistors connected between a(tip) and b(ring). 9. fundamental and harmonics from 256 khz switch-regulator chopper are not included. 10. calculate loop-current limit using the following equations: e1 to det* e0 to det e1* e0 det tshdd tshd0 tgkdd tgkd0 notes: * e1 is internally connected to a logical 0. 1. all delays measured at 1.4 v level. det * e1* tgkde tshde tgkde tshde in oht state: in active state: i limit 0.5 v apparent r feed -------------------------------------- = i limit 0.8 v apparent r feed -------------------------------------- =
slic products 11 11. assumes the following z t network: 12. tested with 0 ? source impedance. 2 m ? is specified for system design purposes only. 13. group delay can be considerably reduced by using a z t network such as that shown in note 11 above. the network reduces the group delay to less than 2 s. the effect of group delay on linecard performance may be compensated for by using qslac ? or dslac ? devices. note: * a logic low on e0 disables the det output into the open collector state. table 1. slic decoding det output state c3 c2 c1 two-wire status e0 = 1* e1 = 0 e0 = 1* e1 = 1 0 0 0 0 open circuit ring trip ring trip 1 0 0 1 ringing ring trip ring trip 2 0 1 0 active loop detector ground key 3 0 1 1 on-hook tx (oht) loop detector ground key 4 1 0 0 tip open loop detector ? 5 1 0 1 reserved loop detector ? 6 1 1 0 active polarity reversal loop detector ground key 7 1 1 1 oht polarity reversal loop detector ground key table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired 2-wire ac input impedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rx is connected from vrx to the rsn pin, z t is defined above, and g 42l is the desired receive gain. r dc1 , r dc2 , and c dc form the network connected to the rdc pin. r dc1 and r dc2 are approximately equal. r d and c d form the network connected from rd to ? 5 v and i t is the threshold current between on hook and off hook. vtx rsn 300 k ? 300 k ? 30 pf z t 1000 z 2win 2r f ? () = z rx z l g 42l ----------- 1000 z t ? z t 1000 z l 2r f + () + ---------------------------------------------------- ? = r dc1 r dc2 50 r feed 2r f ? () = + c dc 1.5 ms r dc1 r dc2 + r dc1 r dc2 ? ------------------------------- - ? = r d 365 i t -------- - c d 0.5 ms r d ------------------ = , =
12 am79574 data sheet dc feed characteristics 3 5 2 1 6 7 a. v a ? v b (v ab ) voltage vs. loop current (typical) notes: 1. constant-resistance feed region: 2. anti-sat ? 1 turn-on: 3. anti-sat ? 2 turn-on: 4. open circuit voltage: 5. anti-sat ? 1 region: 6. anti-sat ? 2 region: 7. current limit: active state, oht state, v ab 50 i l r dc 50 --------- - ? = v ab 31.8 v = v ab 1.077 v bat 12.538 ? = v ab 0.377 v bat 20.48 , + = v bat 50.2 v < v ab 39.39 v = v bat 50.2 v v ab 39.39 i l r dc 118.3 ------------- ? = v ab 0.377 v bat 20.48 i l r dc 200 --------- - ? + = i l 0.8 2500 r dc ----------- - = i l 0.5 2500 r dc ----------- - = v bat = ? 47.3 v r dc = 40 k ? 4 active state oht state
slic products 13 dc feed characteristics (continued) v bat = ? 47.3 v r dc = 40 k ? b. loop current vs. load resistance (typical) i l r dc1 feed resistance programmed by r dc1 and r dc2 c. feed programming a rsn rdc slic a b r l r dc2 c dc b figure 1. dc feed characteristics
14 am79574 data sheet test circuits vtx rsn agnd r t r rx v l v ab v ab r l rsn agnd vtx v rx r rx i l2-4 = ? 20 log (v tx / v ab ) a. two- to four-wire insertion loss i l4-2 = ? 20 log (v ab / v rx ) b. four- to two-wire insertion loss and balance return signal vtx rsn agnd r t r rx v rx s2 open, s1 closed: l-t long. bal. = 20 log (v ab / v l ) l-4 long. bal. = 20 log (v tx / v l ) brs = 20 log (v tx / v rx ) slic slic slic slic r l 2 b(ring) a (tip) b (ring) a(tip) v l s1 b (ring) a (tip) s2 1/ c << r l c s2 closed, s1 open: 4-l long. sig. gen. = 20 log (v l /v rx ) c. longitudinal balance r r v m z in 900 ? v s r t r rx b (ring) a (tip) rsn agnd vtx d. two-wire return loss test circuit note: z d is the desired impedance (e.g., the characteristic impedance of the line). r l = ? 20 log (2 v m / v s ) r t idc r l 2 v l r l 2 r l 2
slic products 15 test circuits (continued) 1/ c << 90 ? e. single-frequency noise slic b(ring) a(tip) 68 ? 68 ? 56 ? c c idc s m r l r l r e s e a(tip) b(ring) current feed or ground key f. ground-key detection v cc 6.2 k ? 15 pf e0 a(tip) b(ring) g. loop-detector switching r l = 600 ? e1 h. ground-key switching r g = 2 k ? det a(tip) b(ring)
slic products 16 physical dimensions pl032 revision summary revision b to revision c minor changes were made to the data sheet style and format to conform to legerity standards. revision c to revision d in the pin description table, inserted/changed tp pin description to: ? thermal pin. connection for heat dissipa- tion. internally connected to substrate (qbat). leave as open circuit or connected to qbat. in both cases, the tp pins can connect to an area of copper on the board to enhance heat dissipation. ? minor changes were made to the data sheet style and format to conform to legerity standards. revision d to revision e the physical dimensions (pl032) were added to the physical dimensions section. deleted the ceramic dip and plastic dip parts (am79571 and am79573) and references to them. updated the pin description table to correct inconsistencies. .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530
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