1 ? fn8186.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyright intersil americas inc. 2005, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. X93254 dual digitally controlled potentiometers (xdcps?) the intersil X93254 is a dual digitally controlled potentiometer (xdcp). the device consists of two resistor arrays, wiper switches, a control section, and nonvolatile memory. the wiper positions are controlled by individual up/down interfaces. a potentiometer is implemented by a resistor array composed of 31 resistive elements and a wiper switching network. the position of each wip er element is controlled by a set of independent cs , u/d , and inc inputs. the position of the wiper can be stored in nonvolatile memory and then be recalled upon during a subsequent power-up operation. each potentiometer is connected as a two-terminal variable resistor and can be used in a wide variety of applications including: ? bias and gain control ? lcd contrast adjustment pinout X93254 (14 ld tssop) top view features ? dual solid-state potentiometers ? independent up/down interfaces ? 32 wiper tap points per potentiometer - wiper position stored in nonvolatile memory and recalled on power-up ? 31 resistive elements per potentiometer - temperature compensated - maximum resistance tolerance of 30% - terminal voltage, 0 to v cc ? low power cmos -v cc = 3v 10% - active current, 250a max - standby current, 1a max ? high reliability - endurance 200,000 data changes per bit - register data retention, 100 years ?r total value = 50k ? 14 ld tssop package v cc cs 1 inc 2 u/d 2 r h2 v ss 1 2 3 4 8 7 6 5 r l1 dnc* *do not connect. cs 2 inc 1 u/d 1 r h1 r l2 dnc* 14 13 12 11 9 10 ordering information part number part marking v cc limits (v) r total (k ) temp range (c) package pkg dwg. # X93254uv141-3 x9325 4uve 3 10% 50 -40 to +85 14 ld tssop m14.173 data sheet february 4, 2008
2 fn8186.1 february 4, 2008 block diagram control and memory up/down (u/d 1 ) increment (inc 1 ) device select (cs 1 ) v cc (supply voltage) v ss (ground) r h1 r l1 30k r h2 r l2 control and memory up/down (u/d 2 ) increment (inc 2 ) device select (cs 2 ) 30k pin descriptions tssop symbol description 1 dnc do not connect 2r l1 low terminal 1 3cs 1 chip select 1 4inc 2 increment 2 5u/d 2 up/down 2 6r h2 high terminal 2 7v ss ground 8 dnc do not connect 9r l2 low terminal 2 10 cs 2 chip select 2 11 v cc supply voltage 12 inc 1 increment 1 13 u/d 1 up/down 1 14 r h1 high terminal 1 X93254
3 fn8186.1 february 4, 2008 absolute maximum rati ngs thermal information voltage on cs , inc , u/d , r h , r l and v cc with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +6.5v maximum resistor current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ma recommended operating conditions temperature range industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3v 10% (note 6) temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . +300c maximum reflow temperature (40s) . . . . . . . . . . . . . . . . . . . . +240c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (v h(n) (actual) - v h(n) (expected)) = 1 ml maximum. n = 1 .. 29 only 2. relative linearity is a measure of the error in step size between taps = v h(n+1) - [v h(n) + ml] = 0.5 ml, n = 1 .. 29 only. 3. 1 ml = minimum increment = r tot /31. 4. typical values are for t a = +25c and nominal supply voltage. 5. limits established by characteri zation and are not production tested. 6. when performing multiple write operations, v cc must not decrease by more than 150mv from its initial value. 7. parts are 100% tested at +25c. over-temperature limi ts established by characterization and are not production tested. potentiometer specifications over recommended operating condi tions, unless otherwise stated. symbol parameter test conditions/notes min (note 7) typ (note 4) max (note 7) unit r tot end-to-end resistance 37.5 50 62.5 k v r r h , r l terminal voltages 0 v cc v power rating r total = 50k 1m (note 5) noise ref: 1khz -120 dbv (note 5) r w wiper resistance (note 5) 1000 i w wiper current (note 5) 0.6 ma resolution 3% absolute linearity (note 1) v h(n)(actual) - v h(n)(expected) 1 mi (note 3) relative linearity (note 2) v h(n+1) - [v h(n)+mi 0.5 mi (note 3) r total temperature coefficient (note 5) 35 ppm/c c h /c l /c w potentiometer capacitances see ?circuit #2 spice macro model? on page 4 10/10/25 pf (note 5) X93254
4 fn8186.1 february 4, 2008 . test circuit #1 circuit #2 spice macro model dc operating specifications over recommended operating condi tions unless otherwise stated. symbol parameter test conditions/notes min (note 7) typ (note 4) max (note 7) unit i cc1 v cc active current (increment) per dcp cs = v il , u/d = v il or v ih and inc = 0.4v @ max. t cy 50 250 a i cc2 v cc active current (store) (eeprom store) per dcp cs = v ih , u/d = v il or v ih and inc =v ih @ max. t wr 600 a i sb standby supply current cs = v cc - 0.3v, u/d and inc = v ss or v cc - 0.3v 1a i li cs 1 or cs 2 v in = v cc 1 a i li cs 1 or cs 2 v cc = 3v, cs = 0 60 100 150 a i li inc 1 , inc 2 , u/d 1 , u/d 2 input leakage current v in = v ss to v cc )1a v ih cs 1 , cs 2 , inc 1 , inc 2 , u/d 1 , u/d 2 input high voltage v cc x 0.7 v cc + 0.5 v v il cs 1 , cs 2 , inc 1 , inc 2 , u/d 1 , u/d 2 input high voltage -0.5 v cc x 0.1 v c in cs 1 , cs 2 , inc 1 , inc 2 , u/d 1 , u/d 2 input capacitance v cc = 3v, v in = v ss , t a = +25c, f = 1mhz (note 5) 10 pf endurance and data retention parameter min unit minimum endurance 200,000 data changes per bit data retention 100 years v l test point v h /r h ac conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input reference levels 1.5v c h c l 10pf 10pf r h r total c w 25pf r l ac operating specifications over recommended operating conditi ons, unless otherwise stated. cs , inc , u/d , r h and r l are used to refer to either cs 1 or cs 2 , etc. symbol parameter min (note 7) typ (note 4) max (note 7) unit t cl cs to inc setup 100 ns t ld inc high to u/d change 100 ns t di u/d to inc setup 100 ns t ll inc low period 1 s t lh inc high period 1 s t lc inc inactive to cs inactive 1 s t cph cs deselect time (no store) 250 ns t cph cs deselect time (store) 10 ms X93254
5 fn8186.1 february 4, 2008 ac timing power-up and power-down requirements there are no restrictions on the power-up or power-down conditions of v cc and the voltages applied to the potentiometer pins provided that v cc is always more positive than or equal to v h and v l , i.e., v cc v h, v l . the v cc ramp rate specification is always in effect. pin descriptions in the text, cs , inc , u/d , r h and r l are used to refer to either cs 1 or cs 2 , etc. note: these signals can be applied independently or at the same time. r h and r l the r h and r l pins of the X93254 ar e equivalent to the fixed terminals of a mechanical potentiometer. the minimum voltage is v ss and the maximum is v cc . the terminology of r h and r l references the relative position of the terminal in relation to wiper movement direction selected by the u/d input per potentiometer. up/down (u/d ) the u/d input controls the direction of a single potentiometer?s wiper movement and whether the counter is incremented or decremented. increment (inc ) the inc input is negative-edge triggered. toggling inc will move the wiper and either increment or decrement the corresponding potentiometer?s counter in the direction indicated by the logic level on the corresponding potentiometer?s u/d input. chip select (cs ) a potentiometer is selected when the corresponding cs input is low. its current counter value is stored in nonvolatile memory when the corresponding cs is returned high while the corresponding inc input is also high. after the store operation is complete, the affected potentiometer will be placed in the low power standby mode until the potentiometer is selected once again. principles of operation there are multiple sections for each potentiometer in the X93254: an input control, a co unter and decode section; the nonvolatile memory; and a resistor array. each input control section operates just like an up /down counter. the output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. under the proper conditions, th e contents of the counter can be stored in nonvolatile memory and retained for future use. each resistor array is compri sed of 31 individual resistors t cyc inc cycle time 2 s t r , t f (note 5) inc input rise and fall time 500 s t r v cc (note 5) v cc power-up rate 1 50 v/ms t wr store cycle 510ms ac operating specifications over recommended operating conditi ons, unless otherwise stated. cs , inc , u/d , r h and r l are used to refer to either cs 1 or cs 2 , etc. (continued) symbol parameter min (note 7) typ (note 4) max (note 7) unit cs inc u/d t ci t il t ih t cyc t id t di t ic t cph t f t r 10% 90% 90% (store) note: cs , inc , u/d , r h and r l are used to refer to either cs 1 or cs 2 , etc. X93254
6 fn8186.1 february 4, 2008 connected in series. at either end of the array and between each resistor is an electronic switch that transfers the connection at that point to the wiper. each wiper, when at either fi xed terminal, acts like its mechanical equivalent and does not move beyond the last position. that is, the counte r does not wrap around when clocked to either extreme. if the wiper is moved several positions, multiple taps are connected to the wiper for t iw (inc to v w change). the 2-terminal resistance value for the device can temporarily change by a significant amount if the wiper is moved several positions. when the device is powered-do wn, the last wiper position stored will be maintained in the nonvolatile memory for each potentiometer. when power is restored, the contents of the memory are recalled and each wiper is set to the value last stored. instructions and programming the inc , u/d and cs inputs control the movement of the wiper along the resistor array. with cs set low the potentiometer is selected and enabled to respond to the u/d and inc inputs. high to low transitions on inc will increment or decrement (depend ing on the state of the u/d input) a 5-bit counter. the out put of this counter is decoded to select one of thirty two wiper positions along the resistive array. the value of the counter is stored in nonvolatile memory whenever each cs transitions high while the inc input is also high. in order to avoid an accidental store during power-up, each cs must go high with v cc during initial power-up. when left open, each cs pin is internally pulled up to v cc by an internal 30k resistor. the system may select the X93254, move any wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. after the wiper movement is performed as previously descr ibed and once the new position is reached, the system must keep inc low while taking cs high. the new wiper position will be maintained until changed by the system or until a power-up/down cycle recalled the previously stored dat a. in order to recall the stored position of the wiper on power-up, the cs pin must be held high. this procedure allo ws the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. the adjustments might be based on user preference, system parameter changes due to temperature drift, or other system trim requirements. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move each wiper up and down until the proper trim is attained. symbol table applications information electronic digitally controlled (xdcp) potentiometers provide three powerful application advantages: 1. the variability and reliability of a solid-state potentiometer 2. the flexibility of computer-based digital controls 3. the retentivity of nonvolatil e memory used for the storage of multiple potentiometer settings or data mode selection cs inc u/d mode l h wiper up l l wiper down h x store wiper position h x x standby current l x no store, return to standby l h wiper up (not recommended) l l wiper down (not recommended) waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance X93254
7 fn8186.1 february 4, 2008 . low voltage high impedance instrumentation amplifier micro-power lcd contrast control single supply variable gain amplifier v r two terminal variable resistor. variable current i + ? u1a 10k 50k ? + u1c gain = 50k 10k 1 + 50k r total ) ( u1 = lt1467 v out 50k ? + u1b 10k 50k 50k 1 /2 X93254 (r total ) 10k + 10k ? v in 3.3v + ? u1a 100k 300k ? + u1b 1 + 100k 50k + r total ) ( u1 = lmc6042 v out = -3.88 ?12v 100k 1 /2 X93254 (r total ) 240k 3.3v 100k 3.3v 50k v out = -2.75v to -11.6v gain = r total 10k + ? u1 20k 3.3v 20k 3.3v v out u1 = lmc6042 10k v in 1 /2 X93254 (r total ) X93254
8 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8186.1 february 4, 2008 X93254 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06
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