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cy62157e mobl ? 8-mbit (512 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05695 rev. *h revised may 30, 2011 8-mbit (512 k 16) static ram features very high speed: 45 ns ? industrial: ?40 c to +85 c ? automotive-e: ?40 c to +125 c wide voltage range: 4.5 v?5.5 v ultra low standby power ? typical standby current: 2 ? a ? maximum standby current: 8 ? a (industrial) ultra low active power ? typical active current: 1.8 ma at f = 1 mhz ultra low standby power easy memory expansion with ce 1 , ce 2 and oe features automatic power down when deselected cmos for optimum speed and power available in pb-free 44-pin tsop ii and 48-ball vfbga package functional description the cy62157e is a high performance cmos static ram organized as 512k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. place the device into standby mode when deselemobl ? cted ( ce 1 high or ce 2 low or both bhe and ble are high). the input or output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: deselected ( ce 1 high or ce 2 low) outputs are disabled ( oe high) both byte high enable and byte low enable are disabled ( bhe, ble high) write operation is active ( ce 1 low, ce 2 high and we low) to write to the device, take chip enable ( ce 1 low and ce 2 high) and write enable ( we) inputs low. if byte low enable ( ble) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 18 ). if byte high enable ( bhe) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable ( ce 1 low and ce 2 high) and output enable ( oe) low while forcing the write enable ( we) high. if byte low enable ( ble) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable ( bhe) is low, then data from memory appears on i/o 8 to i/o 15 . see truth table on page 12 for a complete description of read and write modes. logic block diagram 512k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 10 a 18 ce 2 ce 1 power down circuit bhe ble ce 2 ce 1 [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 2 of 18 contents product portfolio ..............................................................3 pin configuration .............................................................3 maximum ratings .............................................................4 operating range ...............................................................4 electrical characteristics .................................................4 capacitance ......................................................................5 thermal resistance ..........................................................5 ac test loads and waveforms .......................................5 data retention characteristics .......................................6 data retention waveform ................................................6 switching characteristics ................................................7 switching waveforms ......................................................8 read cycle no. 1 (address transition controlled) .....8 read cycle no. 2 ( oe controlled) ..............................8 write cycle no. 1 (we controlled) ..............................9 write cycle no. 2 (ce1 or ce2 controlled) ..............10 write cycle no. 3 (we controlled, oe low) ............11 write cycle no. 4 (bhe/ble controlled, oe low) ......................................11 truth table ......................................................................12 ordering information ......................................................13 ordering code definitions .........................................13 package diagrams ..........................................................14 acronyms ........................................................................16 document conventions .................................................16 units of measure .......................................................16 document history page .................................................17 sales, solutions, and legal information ......................18 worldwide sales and design support .......................18 products ....................................................................18 psoc solutions .........................................................18 [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 3 of 18 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( ? a) f = 1 mhz f = f max min typ [1] max typ [1] max typ [1] max typ [1] max cy62157ell industrial 4.5 5.0 5.5 45 1.8 3 18 25 2 8 cy62157ell automotive 4.5 5.0 5.5 55 1.8 4 18 35 2 30 pin configuration [2, 3] we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc a 18 nc 3 2 6 5 4 1 d e b a c f g h 48-ball vfbga a 16 nc vcc top view 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 44-pin tsop ii top view a 6 a 7 a 3 a 2 a 1 a 0 a 17 a 4 a 9 a 10 a 11 a 12 a 15 a 16 oe bhe ble ce we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss 10 a 18 a 14 a 8 a 13 notes 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 2. nc pins are not connected on the die. 3. the 44-pin tsop ii package has only one chip enable ( ce) pin. [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 4 of 18 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ............................. ?65 c to + 150 c ambient temperature with power applied ........................................ ?55 c to + 125 c supply voltage to ground potential .........................................................?0.5 v to 6.0 v dc voltage applied to outputs in high z state [4, 5] .........................................?0.5 v to 6.0 v dc input voltage [4, 5] ..................................... ?0.5 v to 6.0 v output current into outputs (low) ............................20 ma static discharge voltage ........................................> 2001 v (mil-std-883, method 3015) latch up current ....................................................> 200 ma operating range device range ambient temperature v cc [6] cy62157ell industrial ?40 c to +85 c 4.5 v to 5.5 v automotive ?40 c to +125 c electrical characteristics over the operating range parameter description test conditions 45 ns (industrial) 55 ns (automotive) unit min typ [7] max min typ [7] max v oh output high voltage i oh = ?1 ma 2.4 ? ? 2.4 ? ? v v ol output low voltage i ol = 2.1 ma ? ? 0.4 ? ? 0.4 v v ih input high voltage v cc = 4.5 v to 5.5 v 2.2 ? v cc + 0.5 2.2 ? v cc + 0.5 v v il input low voltage v cc = 4.5 v to 5.5 v ?0.5 ? 0.8 ?0.5 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ?4 ? +4 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ?4 ? +4 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ? 18 25 ? 18 35 ma f = 1 mhz ? 1.8 3 ? 1.8 4 i sb1 [8] automatic ce power down current ? cmos inputs ce 1 > v cc ?? 0.2 v or ce 2 < 0.2 v or ( bhe and ble) > v cc ? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 ( oe and we), v cc = v cc(max) ?28?230 ? a i sb2 [8] automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or ( bhe and ble) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?28?230 ? a notes 4. v il(min) = ?2.0 v for pulse durations less than 20 ns for i < 30 ma. 5. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 8. chip enables ( ce 1 and ce 2 ) and byte enables ( bhe and ble) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 5 of 18 capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [9] description test conditions 44-pin tsop ii 48-ball vfbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 77 72 c/w ? jc thermal resistance (junction to case) 13 8.86 c/w ac test loads and waveforms figure 1. ac test loads and waveforms 3 v v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 parameters values unit r1 1800 ? r2 990 ? r th 639 ? v th 1.77 v note 9. tested initially and after any design or process changes that may affect these parameters. [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 6 of 18 data retention characteristics over the operating range parameter description conditions min typ [10] max unit v dr v cc for data retention 2 ? ? v i ccdr [11] data retention current v cc = 2 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or ( bhe and ble) > v cc ? 0.2 v , v in > v cc ? 0.2 v or v in < 0.2 v industrial ? ? 8 ? a automotive ? ? 30 t cdr [12] chip deselect to data retention time 0??ns t r [13] operation recovery time cy62157ell-45 45 ? ? ns cy62157ell-55 55 ? ? data retention waveform figure 2. data retention waveform [14] v cc(min) t cdr v dr > 2 v data retention mode t r v cc(min) ce 1 or v cc bhe. ble ce 2 or notes 10. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 11. chip enables ( ce 1 and ce 2 ) and byte enables ( bhe and ble) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 12. tested initially and after any design or process changes that may affect these parameters. 13. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 14. bhe. ble is the and of both bhe and ble. deselect the chip by either disabling chip enable signals or by disabling both bhe and ble. [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 7 of 18 switching characteristics over the operating range parameter [15, 16] description 45 ns (industrial) 55 ns (automotive) unit min max min max read cycle t rc read cycle time 45 ? 55 ? ns t aa address to data valid ?45?55 ns t oha data hold from address change 10 ? 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 45 ? 55 ns t doe oe low to data valid ? 22 ? 25 ns t lzoe oe low to low z [17] 5 ? 5 ? ns t hzoe oe high to high z [17, 18] ? 18 ? 20 ns t lzce ce 1 low and ce 2 high to low z [17] 10 ? 10 ? ns t hzce ce 1 high and ce 2 low to high z [17, 18] ? 18 ? 20 ns t pu ce 1 low and ce 2 high to power up 0 ? 0 ? ns t pd ce 1 high and ce 2 low to power down ? 45 ? 55 ns t dbe ble/ bhe low to data valid ? 45 ? 55 ns t lzbe ble/ bhe low to low z [17] 10 ? 10 ? ns t hzbe ble/ bhe high to high z [17, 18] ? 18 ? 20 ns write cycle [19] t wc write cycle time 45 ? 55 ? ns t sce ce 1 low and ce 2 high to write end 35 ? 40 ? ns t aw address setup to write end 35 ? 40 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0?0? ns t pwe we pulse width 35 ? 40 ? ns t bw ble/ bhe low to write end 35 ? 40 ? ns t sd data setup to write end 25 ? 25 ? ns t hd data hold from write end 0?0? ns t hzwe we low to high z [17, 18] ? 18 ? 20 ns t lzwe we high to low z [17] 10 ? 10 ? ns notes 15. test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing ref erence levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ac test loads and waveforms on page 5 . 16. ac timing parameters are subject to byte enable signals ( bhe or ble) not switching when chip is disabled. see application note an13842 for further clarification. 17. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 18. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 19. the internal write time of the memory is defined by the overlap of we, ce 1 = v il , bhe, ble, or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the signal that terminates the write. [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 8 of 18 switching waveforms read cycle no. 1 (address transition controlled) [20, 21] read cycle no. 2 ( oe controlled) [21, 22] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe/ ble data out v cc supply current high i cc i sb impedance notes 20. the device is continuously selected. oe, ce 1 = v il , bhe, ble or both = v il , and ce 2 = v ih . 21. we is high for read cycle. 22. address valid before or similar to ce 1 , bhe, ble transition low and ce 2 transition high. [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 9 of 18 write cycle no. 1 ( we controlled) [23, 24, 25] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 26 ce 1 address ce 2 we data i/o oe bhe/ ble notes 23. the internal write time of the memory is defined by the overlap of we, ce 1 = v il , bhe, ble, or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenc ed to the edge of the signal that terminates the write. 24. data i/o is high impedance if oe = v ih . 25. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 26. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 10 of 18 write cycle no. 2 ( ce 1 or ce 2 controlled) [27, 28, 29] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 30 ce 1 address ce 2 we data i/o oe bhe/ ble notes 27. the internal write time of the memory is defined by the overlap of we, ce 1 = v il , bhe, ble, or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenc ed to the edge of the signal that terminates the write. 28. data i/o is high impedance if oe = v ih . 29. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 30. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 11 of 18 write cycle no. 3 ( we controlled, oe low) [31] write cycle no. 4 ( bhe/ ble controlled, oe low) [31] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 32 ce 1 address ce 2 we data i/o bhe / ble t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 32 ce 1 address ce 2 we data i/o bhe / ble notes 31. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 32. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 12 of 18 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power h x [33] x x x x high z deselect/power down standby (i sb ) x [33] l x x x x high z deselect/power down standby (i sb ) x [33] x [33] x x h h high z deselect/power down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) read active (i cc ) l h h l l h high z (i/o 0 ?i/o 7 ); data out (i/o 8 ?i/o 15 ) read active (i cc ) l h h h l h high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) write active (i cc ) l h l x l h high z (i/o 0 ?i/o 7 ); data in (i/o 8 ?i/o 15 ) write active (i cc ) note 33. the ?x? (don?t care) state for the chip enables in the truth table refer to the logic state (either high or low). intermedia te voltage levels on these pins is not permitted. [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 13 of 18 ordering information speed (ns) ordering code package diagram package type operating range 45 CY62157ELL-45ZSXI 51-85087 44-pin thin small outline package type ii (pb-free) industrial 55 cy62157ell-55zsxe 51-85087 44-pin thin small outline package type ii (pb-free) automotive cy62157ell-55bvxe 51-85150 48-ball very fine-pitch ball grid array (pb-free) contact your local cypress sales representative for availability of these parts. ordering code definitions temperature range: x = i or e i = industrial; e = automotive-e pb-free package type: xx = zs or bv zs = 44-pin tsop ii bv = 48-ball vfbga speed grade: xx = 45 ns or 55 ns low power e = process technology 90 nm buswidth = 16 density = 8-mbit family code: mobl sram family company id: cy = cypress cy xx xx 621 5 7 e ll x - x [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 14 of 18 package diagrams figure 3. 48-ball vfbga (6 8 1 mm) bv48/bz48, 51-85150 51-85150 *f [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 15 of 18 figure 4. 44-pin tsop z44-ii, 51-85087 package diagrams (continued) 51-85087 *c [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 16 of 18 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable ram random access memory sram static random access memory ttl transistor-transistor logic tsop thin small outline package vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celcius mhz mega hertz a micro amperes s micro seconds ma milli amperes mm milli meter ns nano seconds ? ohms % percent pf pico farad v volts w watts [+] feedback
cy62157e mobl ? document #: 38-05695 rev. *h page 17 of 18 document history page document title: cy62157e mobl ? , 8-mbit (512 k 16) static ram document number: 38-05695 rev. ecn no. issue date orig. of change description of change ** 291273 see ecn pci new data sheet *a 457689 see ecn nxr added automotive product removed industrial product removed 35 ns and 45 ns speed bins removed ?l? bin updated ac test loads table corrected t r in data retention characteristics from 100 ? s to t rc ns updated the ordering information and replaced the package name column with package diagram *b 467033 see ecn nxr added industrial product (final information) removed 48 ball vfbga package and its relevant information changed the i cc(typ) value of automotive from 2 ma to 1.8 ma for f = 1mhz changed the i sb2(typ) value of automotive from 5 ? a to 1.8 ? a modified footnote #4 to include current limit updated the ordering information table *c 569114 see ecn vkn added 48 ball vfbga package updated logic block diagram added footnote #3 updated the ordering information table *d 925501 see ecn vkn added footnote #9 related to i sb2 and i ccdr added footnote #14 related ac timing parameters *e 1045801 see ecn vkn converted automotive specs from preliminary to final *f 2934396 06/03/10 vkn added footnote #23 related to chip enable updated package diagrams updated template. *g 3110053 12/14/2010 pras changed table footnotes to footnotes. added ordering code definitions. *h 3269641 05/30/2011 rame removed the note ?for best practice recommendations, please refer to the cypress application note an1064, sram system guidelines.? and its reference in functional description . updated electrical characteristics . updated data retention characteristics . added acronyms and units of measure . updated in new template. [+] feedback
document #: 38-05695 rev. *h revised may 30, 2011 page 18 of 18 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all products and company names me ntioned in this document may be the trademarks of their respective holders. cy62157e mobl ? ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.com/go/automotive clocks & buffers cypress.com/go/clocks interface cypress.com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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