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a s dsp microcomputer information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringeme nts of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. rev. a sharc and the sharc logo are registered trademarks of analog devices, inc. adsp-21161n summary high performance 32-bit dsp?applications in audio, medical, military, wi reless communications, graphics, imaging, motor-control, and telephony super harvard architecture?four independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead i/o code compatible with all other sharc family dsps single-instruction-multiple-data (simd) computational architecture?two 32-bit ieee floating-point computation units, each with a multiplier, alu, shifter, and register file serial ports offer i 2 s support via 8 programmable and simultaneous receive or transmit pins, which support up to 16 transmit or 16 receive channels of audio integrated peripherals?int egrated i/o processor, 1m bit on-chip dual-ported sram, sdram controller, glueless multiprocessing features, and i/o ports (serial, link, external bus, spi, and jtag) adsp-21161n supports 32-bit fixed, 32-bit float, and 40-bit floating-point formats key features 100 mhz (10 ns) core instruction rate single-cycle instruction execution, including simd operations in both computational units 600 mflops peak and 400 mflops sustained performance 225-ball 17 mm 17 mm mbga package functional block diagram alu mult data register file (pey) 16 40-bit barrel shifter barrel shifter alu data register file (pex) 16 40-bit timer instruction cache 32 48-bit dag1 8 4 32 program sequencer 32 pm address bus dm address bus 32 bus connect (px) pm data bus dm data bus 64 64 core processor spi ports (1) serial ports (4) link ports (2) dma controller 5 16 20 4 iop registers (memory mapped) control, status, & data buffers i/o processor two independent dual-ported blocks addr data data data addr addr data addr processor port i/o port b l o c k 0 b l o c k 1 dual-ported sram host port addr bus mux multiprocessor interface data bus mux 32 24 external port 6 12 8 jtag test and emulation gpio flags sdram controller ioa 18 iod 64 dag2 8 4 32 mult one technology way, p.o.box 9106, norwood, ma 02062-9106, u.s.a. tel:781/329-4700 www.analog.com fax:781/326-8703 ? 2003 analog devices, inc. all rights reserved.
adsp-21161n ?2? rev. a key features (continued) 1 m bit on-chip dual-ported sram (0.5 m bit block 0, 0.5 m bit block 1) for independent access by core processor and dma 200 million fixed-point macs sustained performance dual data address generators (dags) with modulo and bit-reverse addressing zero-overhead looping with single-cycle loop setup, providing efficient program sequencing ieee 1149.1 jtag standard test access port and on-chip emulation single instruction multiple data (simd) architecture provides: two computational processing elements concurrent execution?each processing element executes the same instruction, but operates on different data code compatibility?at assembly level, uses the same instruction set as other sharc dsps parallelism in buses and computational units enables: single-cycle execution (with or without simd) of: a multiply operation, an alu operation, a dual memory read or write, and an instruction fetch transfers between memory and core at up to four 32-bit floating- or fixed- point words per cycle, sustained 1.6 gbytes/s bandwidth accelerated fft butterfly computation through a multiply with add and subtract dma controller supports: 14 zero-overhead dma channels for transfers between adsp-21161n internal memory and external memory, external peripherals, host processor, serial ports, link ports, or serial peripheral interface (spi- compatible) 64-bit background dma transf ers at core clock speed, in parallel with full-speed processor execution 800 m bytes/s transfer rate over iop bus host processor interface to 8-, 16-, and 32-bit microprocessors; the host can directly read/write adsp-21161n iop registers 32-bit (or up to 48-bit) wide synchronous external port provides: glueless connecti on to asynchronous, sbsram and sdram external memories memory interface supports programmable wait state generation and wait mode for off-chip memory up to 50 mhz operation for non-sdram accesses 1:2, 1:3, 1:4, 1:6, 1:8 cloc k into core clock frequency multiply ratios 24-bit address, 32-bit data bus. 16 additional data lines via multiplexed link port data pins allow complete 48-bit wide da ta bus for single-cycle external instruction execution direct reads and writes of iop registers from host or other 21161n dsps 62.7 mega-word address range for off-chip sram and sbsram memories 32-48, 16-48, 8-48 execut ion packing for executing instruction directly from 32 -bit, 16-bit, or 8-bit wide external memories 32-48, 16-48, 8-48, 32-32/6 4, 16-32/64, 8-32/64, data packing for dma transfers directly from 32-bit, 16-bit, or 8-bit wide external memories to and from internal 32-, 48-, or 64-bit internal memory can be configured to have 48-bit wide external data bus, if link ports are not used. the link port data lines are multiplexed with the data lines d0 to d15 and are enabled through control bits in syscon sdram controller for glueless interface to low cost external memory zero wait state, 100 mhz operation for most accesses extended external memory banks (64 m words) for sdram accesses page sizes up to 2048 words an sdram controller supports sdram in any and all memory banks support for interface to run at core clock and half the core clock frequency support for 16 m bits, 64 m bits, 128 m bits, and 256 m bits with sdram data bus configurations of
?3? rev. a adsp-21161n table of contents general description . . . . . . . . . . . . . . . . . . . . 3 adsp-21161n family core architecture . . . . . . . . . 5 simd computational engine . . . . . . . . . . . . . . . . 5 independent, parallel computat ion units . . . . . . . 5 data register file . . . . . . . . . . . . . . . . . . . . . . . . . 5 single-cycle fetch of instruction and four operands . . . . . . . . . . . . . . . . . . . . . . . . . . 5 instruction cache . . . . . . . . . . . . . . . . . . . . . . . . . 5 data address generators with hardware circular buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 flexible instruction set . . . . . . . . . . . . . . . . . . . . . 5 adsp-21161n memory and i/o interface features . 5 dual-ported on-chip memory . . . . . . . . . . . . . . . 5 off-chip memory and peripherals interface . . . . . 6 sdram interface . . . . . . . . . . . . . . . . . . . . . . . . . 6 target board jtag emulator connector . . . . . . . 7 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . 7 multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 link ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 serial peripheral (compatible) interface . . . . . . . . 9 host processor interface . . . . . . . . . . . . . . . . . . . . 9 general-purpose i/o ports . . . . . . . . . . . . . . . . . . . 9 program booting . . . . . . . . . . . . . . . . . . . . . . . . . . 9 phase-locked loop and crystal double enable . . 9 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9 designing an emulator-compatible dsp board (target) . . . . . . . . . . . . . . . . . . . . . 10 additional information . . . . . . . . . . . . . . . . . . . . . . 11 pin function descriptions . . . . . . . . . . . . . 12 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 18 absolute maximum ratings . . . . . . . . . . 19 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . 19 timing specifications . . . . . . . . . . . . . . . . 20 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . 21 power-up sequencing ? silicon revision 0.3, 1.0, 1.1 . . . . . . . . . . . . . . . . . . . . 22 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 memory read ? bus master . . . . . . . . . . . . . . . . 27 memory write ? bus master . . . . . . . . . . . . . . . . 28 synchronous read/write ? bus master . . . . . . . . 29 synchronous read/write ? bus slave . . . . . . . . . . 30 host bus request . . . . . . . . . . . . . . . . . . . . . . . . 31 asynchronous read/write ? host to adsp-21161n . . . . . . . . . . . . . . . . . . 33 three-state timing ? bus master, bus slave . . . . 35 dma handshake . . . . . . . . . . . . . . . . . . . . . . . . 37 sdram interface ? bus master . . . . . . . . . . . . . 39 link ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 spi interface specifications . . . . . . . . . . . . . . . . . 47 jtag test access port and emulation . . . . . . . . 50 output drive currents . . . . . . . . . . . . . . . . . . . . . . 51 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 output enable time . . . . . . . . . . . . . . . . . . . . . . 51 output disable time . . . . . . . . . . . . . . . . . . . . . 51 example system hold time ca lculation . . . . . . . 51 capacitive loading . . . . . . . . . . . . . . . . . . . . . . . 52 environmental conditions . . . . . . . . . . . . . . . . . . . 52 thermal characteristics . . . . . . . . . . . . . . . . . . . 52 225-ball metric mbga pin configurations . . . . . . . . . . . . . . . . . . 53 outline dimensions . . . . . . . . . . . . . . . . . . . . 55 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . 55 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 general description the adsp-21161n sharc dsp is the first low cost derivative of the adsp-21160 featuring analog devices super harvard architecture. easing portabilit y, the adsp-21161n is source code compatible with the adsp-21160 and with first generation adsp-2106x sharcs in sisd (single instruction, single data) mode. like other sharc dsps, the adsp-21161n is a 32-bit processor that is optimized for high performance dsp applications. the adsp-21161n includes a 100 mhz core, a dual-ported on-chip sram, an integrated i/o processor with multiprocessing support, and multiple internal buses to eliminate i/o bottlenecks. as was first offered in the adsp-21160, the adsp-21161n offers a single-instruction-multi ple-data (simd) architecture. using two computational unit s (adsp-2106x sharcs have one), the adsp-21161n can double cycle performance versus the adsp-2106x on a ra nge of dsp algorithms. fabricated in a state of the art, high speed, low power cmos process, the adsp-21161n has a 10 ns instruction cycle time. with its simd computational hardware running at 100 mhz, the adsp-21161n can perform 600 million math operations per second. table 1 shows performance benchmarks for the adsp-21161n. table 1. benchmarks (at 100 mhz) benchmark algorithm speed (at 100 mhz) 1024 point complex fft (radix 4, with reversal) 171 s fir filter (per tap) 1 5 ns iir filter (per biquad) 1 40 ns 1 1 specified in sisd mode. using simd, the same benchmark applies for two sets of computations. for example, two sets of biquad operations can be performed in the same amount of time as the sisd mode benchmark. matrix multiply (pipelined) [3 1 0 1 () 0 1 0 1 00
adsp-21161n ?4? rev. a the adsp-21161n continues sharc?s industry-leading standards of integration for dsps , combining a high performance 32-bit dsp core with integrated, on-chip system features. these features include a 1 m bit dual ported sram memory, host processor interface, i/o processor that supports 14 dma channels, four serial ports, tw o link ports, sdram controller, spi interface, external parallel bus, and glueless multiprocessing. the block diagram of the adsp-21161n on page 1 illustrates the following architectural features: ? ? (1 2) ? ? 2 ? ? (1 ) ? ? : ? ? 2111 ? ? ? ? ? ? ? 12 1 . . figure 1. system diagram dma device (optional) data clkout dmar2-1 dmag2-1 addr data host processor interface (optional) 3 12 clock clkin xtal irq2-0 2 clk_cfg1-0 eboot lboot flag11-0 timexp clkdbl reset jtag 7 sbts adsp-21161n bms link devices (2 max) (optional) lxclk lxack lxdat7-0 sclk0 d0b d0a fs0 serial device (optional) cs boot eprom (optional) addr memory and peripherals (optional) oe data cs rd ras ack br6-1 rpba id2-0 pa hbg hbr sdwe ms3-0 wr data47-16 data addr cs ack we addr23-0 d a t a c o n t r o l a d d r e s s brst sdram (optional) sclk1 d1b d1a fs1 serial device (optional) sclk2 d2b d2a fs2 serial device (optional) sclk3 d3b d3a fs3 serial device (optional) spiclk miso mosi spids spi compatible device (host or slave) (optional) data cas ras dqm we addr cs a10 cke clk dqm cas redy sdcke sda10 sdclk1-0 rstout
?5? rev. a adsp-21161n adsp-21161n family core architecture the adsp-21161n includes the fo llowing architectural features of the adsp-2116x family core. the adsp-21161n is code compatible at the assembly level with the adsp-21160, adsp- 21060, adsp-21061, adsp-21062, and adsp-21065l. simd computational engine the adsp-21161n contains two computational processing elements that operate as a single instruction multiple data (simd) engine. the processing elements are referred to as pex and pey, and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both pro- cessing elements, but each processing element operates on different data. this architecture is efficient at executing math intensive dsp algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the processing elements. because of this requirement, entering simd mode also doubles the bandwidth between memory and th e processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. simd is supported only for internal memory accesses and is not supported for off-chip accesses. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform single-cycle instructions. the three units with in each processing element are arranged in parallel, maximizi ng computational throughput. single multifunction instructio ns execute parallel alu and mul- tiplier operations. in simd mode, the parallel alu and multiplier operations occur in bo th processing elements. these computation units support ieee 32-bit single-precision floating- point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats. data register file a general-purpose data register fi le is contained in each process- ing element. the register files transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-register (16 primary, 16 secondary) register files, combined with the adsp-2116x enhanced harvard architecture, allow unconstrained data flow between computa- tion units and internal memory. the registers in pex are referred to as r0 ? r15 and in pey as s0 ? s15. single-cycle fetch of instruction and four operands the adsp-21161n features an enhanced harvard architecture in which the data memory (dm) bus transfers data and the program memory (pm) bus transfers both instructions and data (see figure 1 on page 4 ). with the adsp-21161n?s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and an instruct ion (from the cache), all in a single cycle. instruction cache the adsp-21161n includes an on-chip instruction cache that enables three-bus operation for fe tching an instruction and four data values. the cache is select ive?only the instructions whose fetches conflict with pm bus data accesses are cached. this cache enables full-speed execution of co re, looped operations such as digital filter multiply-accumulate s, and fft butterfly processing. data address generators with hardware circular buffers the adsp-21161n?s two data address generators (dags) are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allow efficient programming of delay lines and other data struct ures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of the adsp-21161n contain suffi- cient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). the dags automati- cally handle address pointer wrap-around, reduce overhead, increase performance, and simplify implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word accommodates a variety of parallel operations, for concise programming. for example, the adsp- 21161n can conditionally execute a multiply, an add, and a subtract in both processing elem ents, while branching, all in a single instruction. adsp-21161n memory and i/o interface features the adsp-21161n adds the following architectural features to the adsp-2116x family core: dual-ported on-chip memory the adsp-21161n contains one megabit of on-chip sram, organized as two blocks of 0.5 m bits. each block can be config- ured for different combinations of code and data storage. each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o processor. the dual- ported memory in combination with three separate on-chip buses allow two data transfers from the core and one from the i/o processor, in a single cycle. on the adsp-21161n, the memory can be configured as a maximu m of 32k words of 32-bit data, 64k words of 16-bit data, 21k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to one megabit. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction. while each memory block can st ore combinations of code and data, accesses are most efficient wh en one block stores data using the dm bus for transfers, and the other block stores instructions and data using the pm bus for transfers. using the dm bus and
adsp-21161n ?6? rev. a pm bus, with one dedicated to each memory block, assures single-cycle execution with two da ta transfers. in this case, the instruction must be available in the cache. off-chip memory and peripherals interface the adsp-21161n?s external port provides the processor?s interface to off-chip memory an d peripherals. the 62.7-m word off-chip address space (254.7-m wo rd if all sdram) is included in the adsp-21161n?s unified ad dress space. the separate on- chip buses?for pm addresses, pm data, dm addresses, dm data, i/o addresses, and i/o data?are multiplexed at the external port to create an external system bus with a single 24-bit address bus and a single 32-bit data bus. every access to external memory is based on an address that fetches a 32-bit word. when fetching an instruction from external memory, two 32-bit data locations are being accessed for packed instructions. unused link port lines can also be used as additional data lines data15 ? data0, allowing single-cycle execution of instructions from external memory, at up to 100 mhz. figure 3 on page 7 shows the alignment of various accesses to external memory. the external port supports asynchronous, synchronous, and syn- chronous burst accesses. synchronous burst sram can be interfaced gluelessly. the adsp-21161n also can interface glue- lessly to sdram. addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. the adsp-21161n provides programmable memory wait states and external memory acknowledge controls to allow interfacing to memory and peripherals with variable access, hold, and disable time requirements. sdram interface the sdram interface enables the adsp-21161n to transfer data to and from synchronous dram (sdram) at the core clock frequency or at one-half the core clock frequency. the figure 2. memory map 0x000a 0000 - 0x000a 7fff (blk 1) 0x0002 8000 - 0x0002 9fff (blk 1) 0x0005 0000 - 0x0005 3fff (blk 1) 0x0010 0000 - 0x0011 ffff 0x0004 0000 - 0x0004 3fff (blk 0) 0x0008 0000 - 0x0008 7fff (blk 0) 0x0012 0000 - 0x0013 ffff 0x0014 0000 - 0x0015 ffff 0x0016 0000 - 0x0017 ffff 0x001a 0000 - 0x001b ffff 0x0000 0000 - 0x0001 ffff 0x0002 0000 - 0x0002 1fff (blk 0) 0x0020 0000 bank 1 ms0 bank 2 ms1 bank 3 ms2 ms3 iop registers long word addressing short word addressing normal word addressing address bank 0 0x03ff ffff (sdram) 0x00ff ffff (non-sdram) 0x0400 0000 0x07ff ffff (sdram) 0x04ff ffff (non-sdram) 0x0800 0000 0x0bff ffff (sdram) 0x08ff ffff (non-sdram) 0x0c00 0000 0x0fff ffff (sdram) 0x0cff ffff (non-sdram) note: bank sizes are fixed 0x0018 0000 - 0x0019 ffff internal memory space multiprocessor memory space address iop registers of adsp-21161n with id = 001 iop registers of adsp-21161n with id = 010 iop registers of adsp-21161n with id = 011 iop registers of adsp-21161n with id = 100 iop registers of adsp-21161n with id = 101 iop registers of adsp-21161n with id = 110 reserved 0 x 001c 0000 0 x 001f ffff external memory space
?7? rev. a adsp-21161n synchronous approach, coupled wi th the core clock frequency, supports data transfer at a high throughput?up to 400 m bytes/s for 32-bit transfers and 600 m bytes/s for 48-bit transfers. the sdram interface provides a glueless interface with standard sdrams?16 mb, 64 mb, 128 mb, and 256 mb? and includes options to support additional buffers between the adsp-21161n and sdram. the sdram interface is extremely flexible and provid es capability for connecting sdrams to any one of the adsp-21161n?s four external memory banks, with up to all four banks mapped to sdram. systems with several sdram devices connected in parallel may require buffering to meet overall system timing requirements. the adsp-21161n supports pipe lining of the address and control signals to enable such buffering between itself and multiple sdram devices. target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test access port of the adsp-21161n processor to monitor and contro l the target board processor during emulation. analog devices dsp tools product line of jtag emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. the processor?s jtag interface ensures that the emulator will not affect target system loading or timing. for complete information on sharc analog devices dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware user?s guide. for detailed infor- mation on the interfacing of analog devices jtag emulators with analog devices dsp products with jtag emulation ports, please refer to engineer to engineer note ee-68: analog devices jtag emulation technical reference . both of these documents can be found on the analog devices website: http://www.analog.com/dsp/tech_docs.html dma controller the adsp-21161n?s on-chip dma controller enables zero- overhead data transfers without processor intervention. the dma controller operates independently and invisibly to the processor core, allowing dma oper ations to occur while the core is simultaneously executing its program instructions. dma transfers can occur between the adsp-21161n?s internal memory and external memory, external peripherals, or a host processor. dma transfers can also occur between the adsp- 21161n?s internal memory and its serial ports, link ports, or the spi-compatible (serial peripheral interface) port. external bus packing and unpacking of 32-, 48-, or 64-bit words in internal memory is performed during dma transfers from either 8-, 16-, or 32-bit wide external memory. fourteen channels of dma are available on the adsp-21161n?two are shared between the spi interface and the link ports, eight via the serial ports, and four via the processor?s external port (for host processor, other adsp-21161ns, memory, or i/o transfers). programs can be downloaded to the adsp-21161n using dma transfers. asyn- chronous off-chip peripherals can control two dma channels using dma request/grant lines ( dmar2C1 , dmag2C1 o dma dma , dma dma multiprocessing the adsp-21161n offers powerful features tailored to multiprocessing dsp systems. th e external port and link ports provide integrated gluele ss multiprocessing support. the external port supports a unified address space (see figure 2 on page 6 ) that enables direct inte rprocessor accesses of each adsp-21161n?s internal memory-mapped (i/o processor) reg- isters. all other internal memory can be indirectly accessed via dma transfers initiated via the programming of the iop dma parameter and control registers. distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six adsp- 21161ns and a host processor. master processor change over incurs only one cycle of overhead. bus arbitration is selectable as either fixed or rotating priority. bus lock enables indivisible read-modify-write sequences for semaphores. a vector interrupt is provided for interprocessor commands. maximum throughput for interprocessor data transfer is 400 m bytes/s over the external port. two link ports provide a second method of multiprocessing com- munications. each link port can support communications to another adsp-21161n. the adsp-21161n, running at 100 mhz, has a maximum throughput for interprocessor com- munications over the links of 200 m bytes/s. the link ports and cluster multiprocessing can be used concurrently or independently. link ports the adsp-21161n features two 8-bit link ports that provide additional i/o capabilities. with the capability of running at 100 mhz, each link port can support 100 m bytes/s. link port i/o is especially useful for po int-to-point interprocessor commu- nication in multiprocessing syst ems. the link ports can operate independently and simultaneously, with a maximum data throughput of 200 m bytes/s. link port data is packed into 48- or 32-bit words and can be dir ectly read by the core processor figure 3. external data alignment options da t a 1 5?0 15 8 7 0 l1data7?0 dat a15-8 l0data7?0 da ta7?0 16-bit packed dma data 16-bit packed instruc- tion execution float or fixed, d31?d0, 32-bit pa cked 32-bit pa cked instruc- tion extra da ta lines data15?0 ar e only accessible if link port s are disabled. enab le these additional data l inks by select- ing ipac k 1 ? 0 = 0 1in s ys c o n. 48-bit instruct ion fetch (no packing) 47 4 0 39 32 3 1 24 2 3 16 data4 7?1 6 8-bit packed dma d ata 8-bit packed inst ruct ion execution prom bo o t note:
adsp-21161n ?8? rev. a or dma-transferred to on-chip memory. each link port has its own double-buffered input and output registers. clock/acknowl- edge handshaking controls link port transfers. transfers are programmable as either transmit or receive. serial ports the adsp-21161n features four synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. each serial port is made up of two data lines, a clock and fram e sync. the data lines can be programmed to either transmit or receive. figure 4. shared memory multiprocessing system ack oe addr data cs we global memory and peripherals (optional) c o n t r o l adsp-21161n #1 addr23-0 control adsp-21161n #3 id2-0 reset clkin 3 adsp-21161n #4 clock addr data sdram (optional) cs addr data boot eprom (optional) id2-0 reset clkin c o n t r o l a d d r e s s d a t a c o n t r o l a d d r e s s d a t a control adsp-21161n #2 id2-0 reset clkin 2 1 addr data host processor interface (optional) we ras cas dqm clk a10 cke cs data47-16 sdwe ras cas dqm sdclk1-0 sda10 sdcke br6-2 rd ms3-0 sbts cs ack br1 redy hbg hbr wr bms addr23-0 reset data47-16 addr23-0 data47-16
?9? rev. a adsp-21161n the serial ports operate at up to half the clock rate of the core, providing each with a maximum data rate of 50 m bit/s. the serial data pins are programmable as either a transmitter or receiver, providing greater flexibility for serial communications. serial port data can be automatically transferred to and from on-chip memory via a dedicated dma. each of the serial ports features a time division multiplex (tdm) multichannel mode, where two serial ports are tdm transmitters and two serial ports are tdm receivers (sport0 rx paired with sport2 tx, sport1 rx paired with sport3 tx ). each of the serial ports also support the i 2 s protocol (an industry standard interface commonly used by audio codecs, adcs and dacs), with two data pins, allowing four i 2 s channels (using two i 2 s stereo devices) per serial port, with a maximum of up to 16 i 2 s channels. the serial ports permit little-endi an or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. for i 2 s mode, data-word lengths are selectable between 8 bits and 32 bits. serial ports offer selectable synchronization and transmit modes as well as optional -law or a-law companding. serial port clocks and frame syncs can be internally or externally generated. serial peripheral (compatible) interface serial peripheral interface (spi) is an industry standard synchro- nous serial link, enabling th e adsp-21161n spi-compatible port to communicate with other spi-compatible devices. spi is a 4-wire interface consisting of two data pins, one device select pin, and one clock pin. it is a full-duplex synchronous serial interface, supporting both master and slave modes. the spi port can operate in a multimaster environment by interfacing with up to four other spi-compatible devices, either acting as a master or slave device. the adsp-21161n spi-compatible peripheral implementation also features programmable baud rate and clock phase/polarities. the adsp-21161 n spi-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. host processor interface the adsp-21161n host interface enables easy connection to standard 8-bit, 16-bit, or 32-bit microprocessor buses with little additional hardware required. the host interface is accessed through the adsp-21161n?s external port. four channels of dma are available for the host interface; code and data transfers are accomplished with low software overhead. the host processor requests the adsp-21161n?s external bus with the host bus request ( hbr , hbg , cs t iop adsp21161, dma dma dma x general-purpose i/o ports the adsp-21161n also contains 12 programmable, general purpose i/o pins that can function as either input or output. as output, these pins can signal pe ripheral devices; as input, these pins can provide the test for conditional branching. program booting the internal memory of the adsp-21161n can be booted at system power-up from either an 8-bit eprom, a host processor, the spi interface, or through one of the link ports. selection of the boot source is controlled by the boot memory select ( bms , eboot eprom b, l/h b lboot , 16, 32 phase-locked loop and crystal double enable the adsp-21161n uses an on-chip phase-locked loop (pll) to generate the internal clock for the core. the clk_cfg1 ? 0 pins are used to select ratios of 2:1, 3:1, and 4:1. in addition to the pll ratios, the clkdbl t 1 2 ) clkdbl pll x w clkcg1 0 clkdbl , 21, 31, 41, 61, 1 clki s 10 p 20 power supplies the adsp-21161n has separate power supply connections for the analog (av dd /agnd), internal (v ddint ), and external (v ddext ) power supplies. the internal and analog supplies must meet the 1.8 v requirement. the external supply must meet the 3.3 v requirement. all external supply pins must be connected to the same supply. note that the analog supply (av dd ) powers the adsp-21161n?s clock generator pll. to produce a stable clock, provide an external circuit to filter the power input to the av dd pin. place the filter as close as possible to the pin. for an example circuit, see figure 5 . to prevent noise coupling, use a wide trace for the analog ground (agnd) signal and install a decoupling capacitor as close as possible to the pin. development tools the adsp-21161n is supported with a complete set of software and hardware development tools, including analog devices emulators and visualdsp++ 1 development environment. the same emulator hardware that supports other adsp-21xxx dsps, also fully emulates the adsp-21161n. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/lib rary builder), a linker, a loader, figure 5. analog power (av dd ) filter circuit 1 visualdsp++ is a registered tra demark of analog devices, inc. 10
adsp-21161n ?10? rev. a a cycle-accurate instruction-level simulator, a c/c++ compiler, and a c/c++ run-time library that includes dsp and mathemat- ical functions. two key points for these tools are: ? 2111 ++ ++ 2111 . ++ . ? 210 210 2111. ++ ++ : ? ++ ( ) ? ? ? ? ? ? ? ++ . 21 ++ . : ? . ? . 11.1 2111 . . . 21 . 21 . . designing an emulator-compatible dsp board (target) the analog devices dsp tools family of emulators are tools that every dsp developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. the emulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the dsp must be halted to send data and commands, but once an operation has been completed by the emulator, the ds p system is set running at full speed with no impact on system timing. to use these emulators, the targ et?s design must include the interface between an analog devices jtag dsp and the emulation header on a custom dsp target board. target board header the emulator interface to an analog devices jtag dsp is a 14-pin header, as shown in figure 6 . the customer must supply this header on the target board in order to communicate with the emulator. the interface consists of a standard dual row 0.025" square post header, set on 0.1" 0.1 0.25. . . ( ) . 0.15 0.10 . . trst , emu t tag btms, btck, btdi, btrst w , btms, btck, btrst , btdi t tag dsp r tag figure 6. jtag target board connector for jtag equipped analog devices dsp (jumpers in place) top view 13 14 11 12 910 78 56 34 12 gnd tms tck tdi tdo gnd key (no pin) btms btck btdi gnd btrst trst emu
?11? rev. a adsp-21161n jtag emulator pod connector figure 8 details the dimensions of the jtag pod connector at the 14-pin target end. figure 9 displays the keep-out area for a target board header. the keep-out area enables the pod connector to properly seat onto the target board header. this board area should contain no components (chi ps, resistors, capacitors, etc.). the dimensions are referenced to the center of the 0.025" square post pin. design-for-emulation circuit information for details on target board desi gn issues including mechanical layout, single processor connectio ns, multiprocessor scan chains, signal buffering, signal terminat ion, and emulator pod logic, see the ee-68: analog devices j tag emulation technical reference on the analog devices website ( www.analog.com )?use site search on ?ee-68?. this document is updated regularly to keep pace with improvements to emulator support. additional information this data sheet provides a general overview of the adsp-21161n architecture and functionality. for detailed information on the adsp-2116x family core architecture and instruction set, refer to the adsp-21161 sharc dsp hardware reference and the adsp-21160 sharc dsp instruction set reference . figure 7. jtag target board connector with no local boundary scan top view 13 14 11 12 910 9 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd figure 8. jtag pod connector dimensions figure 9. jtag pod co nnector keep-out area 0.64" 0.88" 0.24" 0.10" 0.1 5"
adsp-21161n ?12? rev. a pin function descriptions adsp-21161n pin definitions are listed below. inputs identified as synchronous (s) must meet timing requirements with respect to clkin (or with respect to tck for tms, tdi). inputs identified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst t ddet gd, x ? 20 0 (: 2111 20 00.) ? pa , ack, rd , wr , dmarx , dmagx , id20 00x t adsp 21161 dsp id20 00x ? 0 ( 0) (: 2111 sharc dsp hardware reference. ) ? emu , tms, trst , tdi t t t t 2 a a, g g, i i, o o, p p s, s s, a/d a d, o/d o d, t ts sbts adsp21161 u sharc , adsp21161 50 ? . . . 2. 2 0 . 2111 . 2111 ( ). 2111 . 20 . 2111 2 000. 1 . 2111 . . 1 . 2111 2 000. : data15 ? 8 pins (multiplexed with l1dat7 ? 0) can also be used to extend the data bus if the link ports are disabled and will not be used. in addition, data7 ? 0 pins (multiplexed with l0dat7 ? 0) can also be used to extend the data bus if the link ports are not used. this enables execution of 48-bit instructions from external sb sram (system clock speed-external port), sram (system clock speed-external port) and sdram (cor e clock or one-half the core clock speed). the ipackx instruction packing mode bits in syscon should be set correctly (ipack1 ? 0=0x1) to enable this full instruction width/no-packing mode of operation. ms3C0 i/o/t m s l t x m x 16 m sdram 64 m sdram t ms3C0 i , ms3C0 i , ms3C0 , clki ack i , msx sharc t 24 25 26 2 ms3C0 rd i/o/t m r s rd adsp21161 x iop adsp21161 ex , adsp21161, rd adsp21161 iop i , rd rd 20 ? 2 000.
?13? rev. a adsp-21161n wr i/o/t m w l s wr adsp21161 x iop adsp 21161 ex wr adsp21161 iop i , wr wr 20 ? 2 000. . 2111 . . . 2111 () . . ( rd wr brst a dsp brst t adsp21161 id2 000x ack i/o/s m a ex ack x ack i/o , , x t adsp21161 ack iop ack 20 ? 2 000. sbts i/s s b ts ex sbts x , , , i adsp21161 x sbts , sbts sbts / adsp21161 cas i/o/t sdram c a s i ras , msx , sdwe , sdclkx, sda10, sdram ras i/o/t sdram r a s i cas , msx , sdwe , sdclkx, sda10, sdram sdwe i/o/t sdram w e i cas , ras , msx , sdclkx, sda10, sdram dqm o/t sdram d m i , dqm sdram sdclk0 i/o/s/t sdram c o 0 c sdram sdclk1 o/s/t sdram c o 1 a sdram sdram , , e sdclk1 sdclkx sdcke i/o/t sdram c e e clk , sdram sda10 o/t sdram a10 p e sdram sdram t dsp a10 sdram irq2C0 i/a i r l t clki lag11 0 i/o/a p e a , a , x timep o t ex a tcout hbr i/a h b r m adsp 21161 x w hbr , adsp 21161 hbg t , adsp21161 , , , hbr adsp21161 br6C1 t 2 p d p t
adsp-21161n ?14? rev. a hbg i/o h b g a hbr , x hbg adsp21161 hbr i , hbg adsp21161 a hbr , hbg , hbg 1 ck 1 clki t , hbg 20 ? 50 ? . cs i/a c s a adsp21161 red o o/d h b a t adsp21161 red iop cs hbr dmar1 i/a dma r 1 dma c 11 a x dma dmar1 20 ? 2 000. dmar2 i/a dma r 2 dma c 12 a x dma dmar2 20 ? 2 000. dmag1 o/t dma g 1 dma c 11 a ad sp21161 dma x d dmag1 20 ? 2 000. dmag2 o/t dma g 2 dma c 12 a adsp21161 dma x d dmag2 20 ? 2 000. br6C1 i/o/s m b r u adsp21161 a adsp21161 brx id2 0 i x adsp21161, brx brx bmstr o b m o i , adsp21161 x t adsp21161 bmstr i id 000, t id2 0i m id d br6 br1 adsp21161 id 001 br1 , id010 br2 , u id000 id001 t rpba i/s r p b a s w rpba , w rpba , x t adsp 21161 i rpba , clki adsp21161 pa i/o/t p a a pa adsp21161 dma x pa adsp 21161 i , pa pa 20 ? 2 000. ( 0 1 2 ). . . . ( 0 1 2 ). . . . ( 0 1 2 ). . . 2. ()
?15? rev. a adsp-21161n fsx i/o transmit or receive frame sync (serial ports 0, 1, 2, 3). the frame sync pulse initiates shifting of serial data. this signal is either generated internally or externally. it can be active high or low or an early or a late frame sync, in reference to the shifting of serial data. spiclk i/o serial peripheral interface clock signal . driven by the master, th is signal controls the rate at which data is transferred. the master may transmit data at a variety of baud rates. spiclk cycles once for each bit transmitted. spiclk is a gated clock that is active during data transfers, only for the length of the tr ansferred word. slave devices ignore the serial clock if the slave select input is driven inac tive (high). spiclk is used to shift out and shift in the data driven on the miso and mosi lines. the data is always shifted out on one clock edge of the clock and samp led on the opposite edge of the clock. clock polarity and clock phase relative to data are programmable into the spictl control register and define the transfer format. spiclk has a 50 k ? . spids i s p i s d s a t , i spids , i , , lag3 0 , ddet adsp21161 adsp 21161 spi , adsp21161 lag3 0 spids adsp21161 spi mosi i/o / spi m o s i adsp21161 , mosi , i adsp21161 , mosi , i adsp21161 spi , mosi mosi mosi miso i/o / spi m i s o i adsp21161 , miso , i adsp21161 , miso , i adsp21161 spi , miso miso miso miso / opd spictl only one slave is allowed to transmit data at any given time. lxdat7 ? 0 [data15 ? 0] i/o [i/o/t] link port data (link ports 0 ? 1). for silicon revisions 1.2 and higher, each lxdat pin has a keeper latch that is enabled when used as a data pin; or a 20 k ? . 0. 1.0 1.1 50 ? . : l1dat7 ? 0 are multiplexed with the data15 ? 8 pins l0dat7 ? 0 are multiplexed with the data7 ? 0 pins. if link ports are disabled and are not used, these pins can be used as additional data lines for executing instructions at up to the full clock rate from external memory. see data47 ? 16 for more information. lxclk i/o link port clock (link ports 0 ? 1). each lxclk pin has an internal pull-down 50 k ? . ( 0 1). 50 ? . . bms t lboot i l b , bms t t 2 p d p t
adsp-21161n ?16? rev. a bms i/o/t b m s s eboot lboot t 4 t h prom , dma 10 epb0 l spi , dma t eprom bms clki i l c i u tal cl ki adsp21161 i adsp21161 x c clki tal c x clki tal adsp21161 x x t adsp21161 x clki t clki clkcg1 0 clki , , tal o c o t 2 u clki adsp 21161 x s clki clkcg10 i c/clki r c adsp21161 2 1 0 . clkdbl 6 ( clkdbl clkdbl i c d m e t 2 1 2 . . 25 . clkdbl tal 50 mh pll t 2 ( reset clkdbl gd, ddet 1 . 25 100 50 00 10 clkdbl 0 t x t 100 mh clki x tal t 3 p 1 a 1 125 mh 100 mh 25 mh clkout x s 10 p 20 when using an external crys tal, the maximum crystal frequency cannot exceed 25 mhz. for all other external clock sources, the maximum clkin frequency is 50 mhz. clkout o/t local clock out . clkout is 1 2 1 2 . clkdbl t adsp21161 hbg a dsp clkout t adsp21161 id2 000x i clkdbl , clkout2 clkdbl , clkout1 : clkout is only controlled by the clkdbl pin and operates at either 1 clkin or 2 clkin. do not use clkout in multiproces sing systems. use clkin instead. reset i/a p r r adsp21161 x t reset t 2 p d p t
?17? rev. a adsp-21161n boot modes rstout 1 o r o w rstout , i 400 reset pll tck i t c ta g p tag tms i/s t m s tag u tms 20 ? . () . . 20 ? . () . . trst i/a t r tag r trst adsp21161 trst 20 ? . emu o o/d e s m adsp 21161 a d dsp t tag emu 50 ? . . +1. (1 ). . +. . (1 ). . +1. ( ). . . . . (2 ). . . (5 2 ). 1 rstout x 12 2 c 12, rstout t 3 c r r clkdbl clkc clkc cclk clkclk :1 11 0 :1 1 :1 00 0 :1 1:2 00 1 :1 1:2 01 0 :1 1:2 2. () . bms bm mc bms eprom 0 0 1 i h p 0 1 0 i s b spi 0 1 1 i l p 0 0 0 i b p x x 1 1 x i r
adsp-21161n ?18? rev. a specifications recommended operating conditions parameter c grade k grade test conditions min max min max unit v ddint internal (core) supply voltage 1.71 1.89 1.71 1.89 v av dd analog (pll) supply voltage 1.71 1.89 1.71 1.89 v v ddext external (i/o) supply voltage 3.13 3.47 3.13 3.47 v v ih high level input voltage 1 1 applies to input and bidirectio nal pins: data47?16, addr23?0, ms3C0 , rd , wr , ack, sbts , irq2C0 , lag110, hbg , hbr , cs , dmar1 , dmar2 , br6C1 , id20, rpba, pa , brst, sx, dxa, dxb, sclkx, ras , cas , sdwe , sdclk0, lxdat0, lxclk, lxack, spiclk, mosi, miso, spids , eboot, lboot, bms , sdcke, clkcgx, clkdbl , clki, reset , trst, tck, tms, tdi ddet x 20 ddet 05 20 ddet 05 il l l i 1 ddet 05 0 05 0 t case c o t 2 2 s t c p 52 40 105 0 5 . 1 1 : 1 20 ms3C0 , rd , wr , ack, dqm, lag110, hbg , red, dmag1 , dmag2, br6C1 , bmstr, pa , brst, sx, dxa, dxb, sclkx, ras , cas , sdwe , sda10, lxdat0, lxclk, lxack, spiclk, mosi, miso, bms , sdclkx, sdcke, emu , tal, tdo, clkout, timep, rstout ddet , i oh 20 a 2 2 s o d c p 51 24 ol l l o 1 ddet , i ol 40 a 2 04 i ih h l i c 3, 4 3 a data416, addr230, ms3C0 , sbts , irq2C0 , lag110, hbg , hbr , cs , br6C1 , id20, rpba, brst, sx, dxa, dxb, sclkx, ras , cas , sdwe , sdclk0, lxdat0, lxclk, lxack, spiclk, mosi, miso, spids , eboot, lboot, bms , sdcke, clkcgx, clkdbl , tck, reset , clki 4 a 20 ? : rd , wr , ack, dmar1 , dmar2 , pa , trst , tms, tdi ddet x, i ddet x 10 a i il l l i c 3 ddet x, i 0 10 a i ihc clki h l i c 5 5 a clki ddet x, i ddet x 35 a i ilc clki l l i c 5 ddet x, i 0 35 a i ikh k h l c 6 6 a addr 230, data40, ms3C0 , brst, clkout ddet x, i 20 250 100 a i ikl k l l c 6 ddet x, i 0 50 200 a i ikhod k h o c 6, , c c, ddet x 300 a i iklod k l o c 6, , ddet x 300 a i ilpu l l i c pu 4 ddet x, i 0 350 a i oh ts l c , 10, 11 ddet x, i ddet x 10 a i ol ts l c , 12, 13 ddet x, i 0 10 a i olpu1 ts l c pu1 10 ddet x, i 0 500 a i olpu2 ts l c pu2 11 ddet x, i 0 350 a i ohpd1 ts l c pd1 12 ddet x, i ddet x 350 a i ohpd2 ts l c pd2 13 ddet x, i ddet x 500 a i ddipeak s c i 14, 15 cclk 100 , ddit x 00 a i ddihigh s c i 15, 16 cclk 100 , ddit x 650 a i ddilow s c i 15, 1 cclk 100 , ddit x 500 a i ddidle s c i 15, 1 cclk 100 , ddit x 400 a ai dd s c a 1 a dd x 10 a c i i c 20, 21 i 1 mh, t case 25c, i 1 4 s
?19? rev. a adsp-21161n absolute maximum ratings esd sensitivity 9 applies to three-statable pins: data47?16, addr23?0, ms3C0 , clkout, lag110, red, hbg , bms , br6C1 , ras , cas , sdwe , dqm, sdclkx, sdcke, sda10, brst 10 a 20 ? : rd , wr , dmag1 , dmag2 , pa 11 a 50 ? : . emu , miso, mosi 12 a 50 ? : 0 ( 1.2) . 2 . 1.2 . 1 20 ? : 0 ( 1.2 ). 1 . . 21. 15 . 1 . 21. 1 . 21. 1 2111 . 21. 1 . 20 . 21 . () ( ) 1 . . 0. +2.2 1 . . . () ( ) 1 . . . . 0. +2.2 () ( ) 1 . . 0. +. 1 . . . . . . . . . . . . . . . . 0.5 + 0.5 1 . . . . . . . . . 0.5 + 0.5 1 . . . . . . . . . . . . . . . . . . . . . . . . . .200 1 . . . . . . . . . . .5 +150 ( ) . 000 . 2111 . .
adsp-21161n ?20? rev. a timing specifications the adsp-21161n?s internal clock switches at higher frequen- cies than the system input clock (clkin). to generate the internal clock, the dsp uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the dsp?s internal clock (the clock source for the external port logic and i/o pads). the adsp-21161n?s internal clock (a multiple of clkin) provides the clock signal for timing internal memory, processor core, link ports, serial ports, and external port (as required for read/write strobes in asynchronous access mode). during reset, program the ratio between the dsp?s internal clock frequency and external (clkin) clock fr equency with the clk_cfg1?0 and clkdbl e x , c r r t 3 p 1 t , , dix lxclkd clki 10 cclki 21, 31, 41, 61, 1 x i clkoutclki 11 21 t 5 clkout cclk c g o t r d 1 c clki i c 1/ ck clkout ex p s c 1/ ckop plliclk pll i c 1/ plli cclk c c 1/ cclk ck clki c p 1/clki cclk p c c p 1/cclk lclk l p c p cclk ( ) ( ) ( ) 1 : (1 2 1: ) ( ) (1:1 1:2 ) ( ) figure 10. core clock and system clock relationship to clkin clock doubler clkdbl clkout clkcg0 clki crstal oscillator 20mh tal quart crstal 2mh ma core io processor spi
?21? rev. a adsp-21161n use the exact timing information gi ven. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect sta- tistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 40 on page 51 under test conditions for voltage reference levels. switching characteristics specify how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching charac- teristics describe what the processor will do in a given circum- stance. use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. power dissipation total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers. internal power dissipation depends on the instruction execution sequence and the data operands in volved. using the current spec- ifications (i ddinpeak , i ddinhigh , i ddinlow , i ddidle ) from the electrical characteristics on page 18 and the current-versus- operation information in table 6 , the programmer can estimate the adsp-21161n?s internal power supply (v ddint ) input current for a specific applicatio n, according to the following formula: the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: ? ( o ) ? ( f ) ? ( c ) ? ( v dd ) and is calculated by: the load capacitance should include the processor package capacitance (c in ). the switching frequenc y includes driving the load high and then back low. at a maximum rate of 1/t ck , address and data pins can drive high and low, while writing to a sdram memory. example: estimate p ext with the following assumptions: ? (2 ) ? 1 ? 1 50 ? 50 ? 100 ? ? p ext equation is calculated for each class of pins that can drive, as shown in table 7 . a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: where: p ext is from table 7 . p int is i ddint 1.8 v, using the calculation i ddint listed in power dissipation on page 21 . p pll is ai dd 1.8 v, using the value for ai dd listed in the electrical characteristics on page 18 . % peak i ddinpeak % high i ddinhigh % low i ddinlow + % idle i ddidle i ddint -------------------------------------------------- table 6. operation types versus input current operation peak activity 1 (i ddinpeak ) high activity 1 (i ddinhigh ) low activity 1 (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache intern al memory internal memory core memory access 2 2 per t ck cycle (dm ) 1 ( ) 1 2 1 2 1 ( 2) 1 ( 2) 1 ( ) . 2 2:1 . ( ) 20 . p ext oc v dd 2 f = p total p ext p int p pll ++ =
adsp-21161n ?22? rev. a note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. power-up sequencing ? silicon revision 0.3, 1.0, 1.1 the timing requirements for dsp startup for silicon revision 0.3, 1.0, or 1.1 are given in table 8 . table 7. external power calculations (3.3 v device) pin type number of pins % switching c f v dd 2 = p ext address 11 20 24.7 pf 50 mhz 10.9 v = 0.030 w msx 4 0 24 /a 10 0000 w sdwe 1 0 24 /a 10 0000 w d 32 50 14 50 mh 10 012 w sdclk0 1 100 24 100 mh 10 002 w p ext = 0.185 w table 8. power-up sequencing for revis ions 0.3, 1.0, and 1.1 (dsp startup) parameter min max unit timing requirements t rstvdd reset l b ddit / ddet 0 ddramp ddit / ddet r r 1 0000 / iddedd ddit b ddet 50 200 clkdd clki a ddit / ddet 0 200 ddrst ddit / ddet b reset d 2 100 clkrst clki b reset d 3 100 pllrst pll c s b reset d 20 1 t 0 / 2 ddit 0 1 36 ddet 0 33 2 t 0 ddit ddet t ddit ddet 1 33 reset 3 t 100 clki r a 25 x tal x 100 pll clki figure 11. power-up sequen cing for revisions 0.3, 1. 0, and 1.1 (dsp startup) reset clkdbl clkcg-0 clki rstdd ddet ddit clkrst ddramp iddedd ddramp pllrst clkdd ddrst
?23? rev. a adsp-21161n power-up sequencing ? silicon revision 1.2 the timing requirements for dsp startup for silicon with revision 1.2 are given in table 9 . rstout x adsp21161 03, 10, 11 t b15 d dsp, i/o esd t esd , a d s t s 1 33 13 i adsp21161 33 i s esd t pu s r 12 dsp s p m mx u timing requirements t rstvdd reset l b ddit / ddet 0 iddedd ddit b ddet 50 200 clkdd clki a ddit / ddet 1 0 200 clkrst clki b reset d 2 10 pllrst pll c s b reset d 3 20 wrst s reset l p 4 4 ck switching requirements t corerst dsp core reset deasserted after reset 400 ck 3, 5 1 ddit / ddet 1 33 2 a clki , r a 25 x tal x 3 b clki 4 a s 4 clki reset i/o 5 t 400 srst t 11 i , clki , 401 x figure 12. power-up sequencing for revisi on 1.2 (dsp startup) reset rstout clkdbl clkcg-0 clki rstdd ddet ddit pllrst clkrst clkdd iddedd corerst
adsp-21161n ?24? rev. a protection circuitry. with this technique, if the 1.8 v rail rises ahead of the 3.3 v rail, the scho ttky diode pulls the 3.3 v rail along with the 1.8 v rail. clock input in systems that use multiprocessing or sbsram, clkdbl x clki d clkout sbsram u x clkdbl clkout clki clkout clock signals the adsp-21161n can use an external clock or a crystal. see clkin pin description. the programmer can configure the adsp-21161n to use its internal clock generator by connecting the necessary components to clkin and xtal. figure 15 shows the component connections used for a crystal operating in fundamental mode. figure 13. dual voltage schottky diode 3.3v i/o voltage regulator 1.8v core voltage regulator v ddext v ddint adsp-21161n dc input source table 10. clock input parameter 100 mhz unit min max timing requirements t ck clkin period 1 20 238 ns t ckl clkin width low 1 7.5 119 ns t ckh clkin width high 1 7.5 119 ns t ckrf clkin rise/fall (0.4 v?2.0 v) 3 ns t cclk cclk period 10 30 ns switching characteristics t dckoo clkout delay after clkin 0 2 ns t ckop clkout period t ckop ?1 t ckop +1 ns t ckwh clkout width high t ckop /2?2 t ckop /2+2 ns t ckwl clkout width low t ckop /2?2 t ckop /2+2 ns 1 clkin is dependent on the config uration of the clkcfgx and clkdbl cclk figure 14. clock input clkin t ckh t ck t ckl clkout t dckoo 1 t ckop 1 t ckwl 1 t ckwh 1 clkout notes: 1. when clkdbl is disabled a speciicatio to clki applies to the risig edge ol 2 whe clkdbl is eabled a speciicatio to clki applies to the risig or allig edge dckoo 2 ckop 2 dckoo 2 ckwh 2 ckwl 2 figure 15. 100 mhz operation (fundamental mode crystal) clkin xtal c2 27pf c1 27pf x1 suggested components for 100mhz operation: ecliptek ec2sm-25.000m (surface mount package) ecliptek ec-25.000m (through-hole package) c1 = 27pf c2 = 27pf note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. this 25mhz crystal generates a 100mhz cclk and a 50mhz ep clock with clkdbl eabled ad a 2 pll multipl ratio
?25? rev. a adsp-21161n reset interrupts table 11. reset parameter min max unit timing requirements t wrst reset p l 1 4 ck srst reset s b clki h 2 5 1 a 2 o adsp21161 clki pc adsp21161 x , figure 16. reset reset clki wrst srst t2 i p m mx u timing requirements t sir irq2C0 s b clki 1 6 hir irq2C0 h a clki 1 0 ipw irq2C0 p 2 2 ckop 1 o irqx 2 a sir hir figure 17. interrupts clkin t ipw t sir t hir irq2C0
adsp-21161n ?26? rev. a timer flags table 13. timer parameter min max unit switching characteristic t dtex clkin to timexp 1 7 ns figure 18. timer clkin timexp t dtex t dtex table 14. flags parameter min max unit timing requirement t sfi flag11?0 in setup before clkin 1 4ns t hfi flag11?0 in hold after clkin 1 1ns t dwrfi flag11?0 in delay after rd / wr l 1 12 hiwr lag110 i h a rd / wr d 1 0 switching characteristics t dfo flag11?0 out delay after clkin 9 ns t hfo flag11?0 out hold after clkin 1 ns t dfoe clkin to flag11?0 out enable 1 ns t dfod clkin to flag11?0 out disable 5 ns 1 flag inputs meeting these setup and hold times for instruction cycle n will affect conditional instructions in instruction cycl e n+2. figure 19. flags clkin flag11?0 out flag output clkin flag input flag11?0 in t dfo t hfo t dfo t dfod t dfoe t sfi t hfi t hfiwr t dwrfi rd wr
?27? rev. a adsp-21161n memory read ? bus master use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to clkin. these specification s apply when the adsp-21161n is the bus master accessing external memory space in asynchro- nous access mode. table 15. memory read ? bus master parameter min max unit timing requirements t dad address, selects de lay to data valid 1, 2 t ckop ?0.25t cclk ?11+w ns t drld rd l d 1 05 ckop 11w hda d h a, s 3 0 sds d s rd h hdrh d h rd h 3 1 daak ack d a, s 2, 4 ckop 05 cclk 12w dsak ack d rd l 4 ckop 05 cclk 11w sakc ack s clki 4 05 cclk 3 hakc ack h a clki 1 switching characteristics t drha address selects hold after rd h 025 cclk 1h darl a s rd l 2 025 cclk 3 rw rd p ckop 05 cclk 1w rwr rd h wr , rd , dmagx l 05 cclk 1hi w wait ckop hi ckop , wait hi 0 h ckop wait h 0 1 d d/s u dad , drld , sds 2 t ms x, bms 3 d h u hda hdrh s ex s h t c p 51 4 ack d/s u daak , dsak , sakc ack l ack h figure 20. memory read ? bus master ack data t darl t rw t dad t daak t hdrh t hda t rwr t drld t drha t dsak t sds t sakc t hakc clkin address msx bms rd wr dmag
adsp-21161n ?28? rev. a memory write ? bus master use these specifications for as ynchronous interfacing to memories (and memory-mapped peripherals) without reference to clkin. these specification s apply when the adsp-21161n is the bus master accessing external memory space in asynchro- nous access mode. table 16. memory write ? bus master parameter min max unit timing requirements t daak ack delay from address, selects 1, 2 t ckop ?0.5t cclk ?12+w ns t dsak ack delay from wr l 1 ckop 05 cclk 11w sakc ack s clki 1 05 cclk 3 hakc ack h a clki 1 1 switching characteristics t dawh address, selects to wr d 2 ckop 025 cclk 3w dawl a, s wr l 2 025 cclk 3 ww wr p ckop 05 cclk 1w ddwh d s b wr h ckop 025 cclk 135w dwha a h a wr d 025 cclk 1h dwhd d h a wr d 025 cclk 1h datrwh d d a wr d 3 025 cclk 2h 025 cclk 25h wwr wr h wr , rd , dmagx l 05 cclk 125hi ddwr d d b wr rd l 025 cclk 3i wde wr l d e 025 cclk 1 w wait ckop h ckop , wait h 0 hi ckop , wait hi 0 i ckop , wait i 0 1 ack d/s u daak dsak sakc ack l ack h 2 t msx , bms 3 s ex s h t c p 51 figure 21. memory write ? bus master t datrwh ack data t dawl t ww t daak t wwr t wde t ddwr t dwha t dawh t dsak t ddwh t dwhd t sakc t hakc clkin address msx bms wr rd dmag
?29? rev. a adsp-21161n synchronous read/write ? bus master use these specifications for interfacing to external memory systems that require clkin, relative to timing or for accessing a slave adsp-21161n (in multipro cessor memory space). when accessing a slave adsp-21161n, these switching characteristics must meet the slave's timing requirements for synchronous read/writes (see synchronous read/write ? bus slave on page 30 ). the slave adsp-21161n must also meet these (bus master) timing requirements for data and acknowledge setup and hold times. table 17. synchronous read/write ? bus master parameter min max unit timing requirements t ssdati data setup before clkin 5.5 ns t hsdati data hold after clkin 1 ns t sackc ack setup before clkin 0.5t cclk +3 ns t hackc ack hold after clkin 1 ns switching characteristics t daddo address, msx , bms , brst, d a clki 10 haddo a, msx , bms , brst, h a clki 15 drdo rd h d a clki 025 cclk 1 025 cclk dwro wr h d a clki 025 cclk 1 025 cclk drwl rd / wr l d a clki 025 cclk 1 025 cclk ddato d d a clki 125 hdato d h a clki 15 figure 22. synchronous read/write ? bus master clkin ack (in) data (out) data (in) write cycle read cycle t drwl t hsdati t ssdati t drdo t dwro t hdato t ddato t drwl t sackc t hackc t haddo t daddo address msx brst rd wr
adsp-21161n ?30? rev. a synchronous read/write ? bus slave use these specifications for ad sp-21161n bus master accesses of a slave?s iop registers in multiprocessor memory space. the bus master must meet these (bus slave) timing requirements. table 18. synchronous read/write ? bus slave parameter min max unit timing requirements t saddi address, brst setup before clkin 5 ns t haddi address, brst hold after clkin 1 ns t srwi rd / wr s b clki 5 hrwi rd / wr h a clki 1 ssdati d s b clki 55 hsdati d h a clki 1 switching characteristics t ddato data delay after clkin 12.5 ns t hdato data hold after clkin 1.5 ns t dackc ack delay after clkin 10 ns t hacko ack hold after clkin 1.5 ns figure 23. synchronous read/write ? bus slave clkin address ack data (out) write access data (in) read access t saddi t haddi t dackc t hacko t hrwi t srwi t ddato t hdato t srwi t hrwi t hsdati t ssdati rd wr
?31? rev. a adsp-21161n host bus request use these specifications for asynchro nous host bus requests of an adsp-21161n ( hbr , hbg t 1 h b r p m mx u timing requirements t hbgrcsv hbg l rd / wr / cs 1 shbri hbr s b clki 1 6 hhbri hbr h a clki 1 1 shbgi hbg s b clki 6 hhbgi hbg h a clki 1 switching characteristics t dhbgo hbg d a clki hhbgo hbg h a clki 15 drdcs red o/d a/d l cs hbr l 2 10 trdhg red o/d d red a/d h hbg 2 ckop 14 ardtr red a/d d cs hbr h 2 11 1 o 2 o/d , a/d figure 24. host bus request re d y (o/d) re d y (a/d) o/d = open drain, a/d = active drive t drdycs t hbgrcsv t trdyhg t ardytr t sh b gi t hhbgi clkin (ou t ) hb g hhbri sh b r i hhbgo dhbg o hb r i hb g hb r cs ou t hb g rd wr cs
adsp-21161n ?32? rev. a multiprocessor bus request use these specifications for pass ing of bus mastership between multiprocessing adsp-21161ns ( brx t 20 m b r p m mx u timing requirements t sbri brx , s b clki h hbri brx , h a clki h 05 spai pa s b clki h hpai pa h a clki h 1 srpbai rpba s b clki h 6 hrpbai rpba h a clki h 2 switching characteristics t dbro brx d a clki h hbro brx h a clki h 10 dpaso pa d a clki h, s trpas pa d a clki h, s 15 dpamo pa d a clki h, m 025 cclk patr pa d b clki h, m 025 cclk 5 figure 25. multipro cessor bus request t hbri rp ba o/d = op en drai n t hr p b ai t srpbai t sbri clkin pa out s la e dbro hbro dp a so trpas pa out master dpamo patr pa i od hpai spai brx out br x i
?33? rev. a adsp-21161n asynchronous read/write ? host to adsp-21161n use these specifications for asynch ronous host processor accesses of an adsp-21161n, after the host has asserted cs hbr a hbg adsp21161, rd wr adsp21161 iop hbr hbg a dsp hbr , hbg dsp dsp host internal memory access is not supported. table 21. read cycle parameter min max unit timing requirements t sadrdl address setup and cs l b rd l 0 hadrdh a h cs h l a rd 2 wrwh rd / wr h w 35 drdhrd rd h d a red o/d d 0 drdhrd rd h d a red a/d d 0 switching characteristics t sdatrdy data valid before redy disable from low 2 ns t drdyrdl redy (o/d) or (a/d) low delay after rd l 10 rdprd red o/d a/d l p r 15 cclk hdarwh d d a rd h 26 t 22 w c p m mx u timing requirements t scswrl cs l s b wr l 0 hcswrh cs l h a wr h 0 sadwrh a s b wr h 6 hadwrh a h a wr h 2 wwrl wr l w cclk +1 rd / wr h w 35 dwrhrd wr h d a red o/d a/d d 0 sdatwh d s b wr h 5 hdatwh d h a wr h 4 switching characteristics t drdywrl redy (o/d) or (a/d) low delay after wr / cs l 1 11 rdpwr red o/d a/d l p w 1 12 1 o io
adsp-21161n ?34? rev. a figure 26. asynchro nous read/write ? host to adsp-21161n redy (o/d) read cycle data (out) red y (a /d ) o/d = open drain, a/d = active drive redy (o/d) wr ite c y cle da t a ( in ) address redy (a/d) t drdyrdl t hdarwh t r dyprd t drdhrdy t sdatrdy t sda twh t hdatwh t drdywrl t hadw rh t rdypw r t dwrhrdy t sadwrh t sc s wrl t hcswrh t hadrdh t wrwh t wwrl t wrwh t sadrdl rd cs wr address cs
?35? rev. a adsp-21161n three-state timing ? bus master, bus slave these specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to clkin and the sbts t btc htc sbts d , dsp sbts , hbr , mms a dsp hbr , hbg dsp dsp t 23 ts t b m, b s p m mx u timing requirements t stsck sbts s b clki 6 htsck sbts h a clki 2 switching characteristics t miena address/select enable after clkin high 1.5 9 ns t miens strobes enable after clkin high 1 ? 1.5 + hbg e a clki 15 mitra a/s d a clki h 05 ckop 20 0.5 15 0.25 ? 1 0.25 ? 12.5 hbg d a clki 2 05 ckop 20 0.5 + 15 1.5 10 1.5 1.5 0.2 5 2 0.5 + 0.5 + +5 ?5 hbg l 4 15 ckop 6 15 ckop 2 strhbg rd / wr / dmagx d b hbg l 4 ckop 0.25 ? + 0.25 + bms d b hbg l 4 05 ckop 4 05 ckop 2 mehbg m i e a hbg h 4 ckop 5 ckop 5 1 s rd , wr , dmagx 2 w 05, 10, 15 12, 13, 14, 3 i , / 4 m i a, rd , wr , msx , dmagx , bms eprom bms eprom
adsp-21161n ?36? rev. a figure 27. three-state timi ng ? bus master, bus slave clkin ack memory interface clkout t cdctr data memory interface t mitra, t mitrs, t mitrhg t htsck t cdcen t miena, t miens, t mienhg clkin t atrhbg, t strhbg, t btrhbg t stsck t daten t acken t dattr t acktr t menhbg sbts hbg memor iterace address rd wr msx dmagx bms i eprom mode
?37? rev. a adsp-21161n dma handshake these specifications describe th e three dma handshake modes. in all three modes dmar , dmag x x , addr230, rd , wr , ms3C0 , ack, dmag p m , addr230, rd , wr , ms3C0 , ack dmag p m , m rb m, m wb m, s r/wb m addr23 0, rd , wr , ms3C0 , data4 16, ack t 24 dma h p m mx u timing requirements t sdrc dmarx s b clki 1 35 wdr dmarx w l 2 cclk 45 sdatdgl d s a dmagx l 3 ckop 05 cclk hdatidg d h a dmagx h 2 datdrh d a dmarx h 3 ckop 3 dmarll dmarx l e l e 4 ckop dmarh dmarx w h 2 cclk 45 switching characteristics t ddgl dmagx l d a clki 025 cclk 1 025 cclk wdgh dmagx h w 05 cclk 1hi wdgl dmagx l w ckop 05 cclk 1 hdgc dmagx h d a clki ckop 025 cclk 10 ckop 025 cclk datdgh d b dmagx h 5 ckop 025 cclk ckop 025 cclk 5 datrdgh d d a dmagx h 6 025 cclk 3 025 cclk 4 dgwrl wrx l b dmagx l 15 2 dgwrh dmagx l b wrx h ckop 05 cclk 2w dgwrr wrx h b dmagx h 15 2 dgrdl rdx l b dmagx l 15 2 drdgh rdx l b dmagx h ckop 05 cclk 2w dgrdr rdx h b dmagx h 15 2 dgwr dmagx h wrx , rdx l 05 cclk 2hi dadgh a/s dmagx h 15 ddgha a/s h a dmagx h 1 w wait . ( 0). 1 . 2 dmarx/dmagx wdr dmarh cclk 45 cclk 452 345 mh t 3 sdatdgl dmarx o, dmarx , datdrh dmarx 4 u dmarll dmarx clki o, wdr dmarh 5 datdgh dmarx i dmarx , datdgh ckop 025 cclk ckop x 6 s ex s h t c p 51 t
adsp-21161n ?38? rev. a figure 28. dma handshake clkin t sdrc data data t wdr t sdrc t dmarh t dmarll t hdgc t wdgh t ddgl t vdatdgh t datdrh t datrdgh t hdatidg t dgwrl t dgwrh t dgwrr t dgrdl t drdgh t dgrdr t sdatdgl (external device to external memory) (external memory to external device) transfers between adsp-21161n internal memory and external device transfers between external device and external memory 1 (external handshake mode) t ddgha address msx dadgh wdgl rom eteral drie to adsp-2 rom adsp-2x to eteral drie dgwr dmarx dmagx wr rd memor read bus master memor write bus master or schroous readwrite bus master timig speciicatios or addr230 rd wr ms3-0 ad ack also appl here
?39? rev. a adsp-21161n sdram interface ? bus master use these specifications for adsp-21161n bus master accesses of sdram: sdram interface ? bus slave these timing requirements allow a bus slave to sample the bus master?s sdram command and detect when a refresh occurs: table 25. sdram interface ? bus master parameter min max unit timing requirements t sdsdk data setup before sdclk 2.0 ns t hdsdk data hold after sdclk 2.3 ns switching characteristics t dsdk1 first sdclk rise delay after clkin 1, 2 0.75t cclk + 1.5 0.75t cclk + 8.0 ns t sdk sdclk period t cclk 2 0.25 +2.5 2.0 0.5 + 2.0 5 0.5 0.5 1.5 0.5 + .0 2 5 0 1 ? 0.25 ? 5 ? 0.25 ? 0. +.2 1 1 1 . 2 . msx , dqm, ras , cas , sda10, sdwe 4 sdram c sdram clk , 5 dsp sdram sdram t 26 sdram i b s p m mx u timing requirements t ssdkc1 first sdclk rise after clkout 1, 2, 3 sdck ? 0.5 ? 0.5 ? 0.25 + 2.0 2 1 1 1 1 . 2 1 2 . . ras , cas , sdwe
adsp-21161n ?40? rev. a figure 29. sdram interface clkin sdclk data(in) data(out) cmnd 1 addr (out) cmnd 1 (out) addr (out) clkout sdclk (in) cmnd 2 (in) t sdk t dsdk1 t sdkh t sdkl t sdsdk t hdsdk t dcadsdk t sdensdk t sdtrsdk t hcadsdk t dcadsdk t hcadsdk t sdcen t sdctr t sdatr t sdaen t ssdkc1 t scsdk t hcsdk clkin t sdsdken t sdsdktr sdclk 1 command = sdcke, msx ras cas sdwe dqm ad sda0 2 commad sdcke ras cas ad sdwe
?41? rev. a adsp-21161n link ports calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between ldata and lclk. setup skew is the maximum delay that can be introduced in ldata relative to lclk, (setup skew = t lclktwh min? t dldch ? t sldcl ). hold skew is the maximum delay that can be introduced in lclk relative to ldata, (hold skew = t lclktwl min ? t hldch ? t hldcl ). calculations made directly from speed specifications will result in unrealistically smal l skew times because they include multiple tester guardbands. th e setup and hold skew times shown below are calculated to include only one tester guardband. adsp-21161n setup skew = 1.5 ns max adsp-21161n hold skew = 1.5 ns max note that there is a two-cycle effect latency between the link port enable instruction and the dsp enabling the link port. table 27. link ports ? receive parameter min max unit timing requirements t sldcl data setup before lclk low 1 ns t hldcl data hold after lclk low 3.5 ns t lclkiw lclk period t lclk ns t lclkrwl lclk width low 4.0 ns t lclkrwh lclk width high 4.0 ns switching characteristics t dlalc lack low delay after lclk high 1 812ns 1 lack goes low with t dlalc relative to rise of lclk after first nibble, but does not go low if the receiver's link buffer is not about to fill. figure 30. link ports?receive lclk ldat7-0 lack (out) receive in t sldcl t hldcl t dlalc t lclkrwl t lclkiw t lc lkrwh
adsp-21161n ?42? rev. a table 28. link ports ? transmit parameter min max unit timing requirements t slach lack setup before lclk high 8 ns t hlach lack hold after lclk high ?2 ns switching characteristics t dldch data delay after lclk high 3 ns t hldch data hold after lclk high 0 ns t lclktwl lclk width low 0.5t lclk ?1.0 0.5t lclk +1.0 ns t lclktwh lclk width high 0.5t lclk ?1.0 0.5t lclk +1.0 ns t dlaclk lclk low delay after lack high 0.5t lclk +3 3t lclk +11 ns figure 31. link ports?transmit lclk ldat7-0 lack (in) the t slach requirement applies to the rising edge of lclk only for the first nibble transmitted. transmit last nibble/byte transmitted first nibble/byte transmitted lclk inactive (high) out t dldch t hldch t lclktwh t lclktwl t slach t hlach t dlaclk
?43? rev. a adsp-21161n serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. table 29. serial ports ? external clock parameter min max unit timing requirements t sfse transmit/receive fs setup before transmit/receive sclk 1 3.5 ns t hfse transmit/receive fs hold after transmit/receive sclk 1 4ns t sdre receive data setup before receive sclk 1 1.5 ns t hdre receive data hold after receive sclk 1 4ns t sclkw sclkx width 7 ns t sclk sclkx period 2t cclk ns 1 referenced to sample edge. table 30. serial ports ? internal clock parameter min max unit timing requirements t sfsi fs setup time before sclk (transmit/receive mode) 1 8ns t hfsi fs hold after sclk (transmit/receive mode) 1 0.5t cclk +1 ns t sdri receive data setup before sclk 1 4ns t hdri receive data hold after sclk 1 3ns 1 referenced to sample edge. table 31. serial ports ? external clock parameter min max unit switching characteristics t dfse fs delay after sclk (internally generated fs) 1, 2, 3 13 ns t hofse fs hold after sclk (internally generated fs) 1, 2 , 3 3ns t ddte transmit data delay after sclk 1, 2 16 ns t hdte transmit data hold after sclk 1, 2 0ns 1 referenced to drive edge. 2 sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. 3 sclk/fs configured as a receive clock/frame sy nc with the ddir bit = 0 in spctlx register. table 32. serial ports ? internal clock parameter min max unit switching characteristics t dfsi fs delay after sclk (internally generated fs) 1, 2, 3 4.5 ns t hofsi fs hold after sclk (internally generated fs) 1, 2, 3 ?1.5 ns t ddti transmit data delay after sclk 1, 2 7.5 ns t hdti transmit data hold after sclk 1, 2 0ns t sclkiw sclk width 2 0.5t sclk ?2.5 0.5t sclk +2 ns 1 referenced to drive edge. 2 sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. 3 sclk/fs configured as a receive clock/frame sy nc with the ddir bit = 0 in spctlx register.
adsp-21161n ?44? rev. a table 33. serial ports ? enable and three-state parameter min max unit switching characteristics t ddten data enable from ex ternal transmit sclk 1, 2 4ns t ddtte data disable from external transmit sclk 1 10 ns t ddtin data enable from internal transmit sclk 1 0ns t ddtti data disable from internal transmit sclk 1 3ns 1 referenced to drive edge. 2 sclk/fs configured as a transmit clock/frame sy nc with the ddir bit = 1 in spctlx register. table 34. serial ports ? external late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external transmit fs or external receive fs with mce = 1, mfd = 0 1 13 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 1 0.5 ns 1 mce = 1, transmit fs enable and transmit fs valid follow t ddtlfse and t ddtenfs .
?45? rev. a adsp-21161n figure 32. serial ports drive edge sclk (int) drive edge sclk drive edge drive edge sclk sclk (ext) t ddtte t ddten t ddtti t ddtin d x a/d x b d x a/d x b sclk fs drive edge sample edge data receive? internal clock data receive? external clock sclk fs drive edge sample edge note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t sdri t hdri t sfsi t hfsi t dfsi t hofsi t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse d x a/d x b d x a/d x b t ddti sclk fs drive edge sample edge data transmit ? internal clock t sfsi t hfsi t dfsi t hofsi t sclkiw d x a/d x b t hdti note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t ddte sclk fs drive edge sample edge data transmit ? external clock t sfse t hfse t dfse t hofse t sclkw d x a/d x b t hdte
adsp-21161n ?46? rev. a figure 33. serial ports ? external late frame sync drive sample drive sclk fs d x a/d x b drive sample drive late external transmit fs e x ternal receive fs with mce = 1, mfd = 0 1st bit 2nd bit sclk fs 1st bit 2nd bit t hofse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t hofse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i d x a/d x b
?47? rev. a adsp-21161n spi interface specifications table 35. spi interface protocol ? master switching and timing parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input set-up time) 0.5t cclk +10 ns t hspidm spiclk last sampling edge to data input not valid 0.5t cclk +1 ns t spitdm sequential transfer delay 2t cclk ns switching characteristics t spiclkm serial clock cycle 8 t cclk ns t spichm serial clock high period 4t cclk ?4 ns t spiclm serial clock low period 4t cclk ?4 ns t ddspidm spiclk edge to data out valid (data out delay time) 3 ns t hdspidm spiclk edge to data out not valid (data out hold time) 0 ns t sdscim_0 flag3?0 (spi device select) low to first spiclk edge for cphase = 0 5t cclk ns t sdscim_1 flag3?0 (spi device select) low to first spiclk edge for cphase = 1 3t cclk ns t hdsm last spiclk edge to flag3?0 high t cclk ?3 ns table 36. spi interface protocol ? slave switching and timing parameter min max unit timing requirements t spiclks serial clock cycle 8t cclk ns t spichs serial clock high period 4t cclk ?4 ns t spicls serial clock low period 4t cclk ?4 ns t sdsco spids a spiclk e cphase 0 35 cclk cphase 1 15 cclk hds l spiclk e spids a cphase 0 0 sspids d i spiclk e d i s t 0 hspids spiclk l s e d i cclk 1 sdppw spids d p cphase 0 cclk switching characteristics t dsoe spids a d o a 2 05 cclk 55 dsdhi spids d d h i 15 05 cclk 55 ddspids spiclk e d o d o d t 05 cclk 3 hdspids 1 spiclk e d o d o h t 025 cclk 3 hdlsbs 1 spiclk e l b o d o h t lsb 05 spiclk 45 cclk dso 2 spids a d o cphase 0 15 cclk 1 w cphase 0 1, hdlsbs 2 a spids
adsp-21161n ?48? rev. a figure 34. spi interface protocol ? master switching and timing t sspidm t hspidm t hdspidm lsb msb t hsspidm t ddspidm mosi (output) miso (input) flag3-0 (output) spiclk (cp = 0) (output) spiclk (cp = 1) (output) t spichm t spiclm t spiclm t spiclkm t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cphase = 1 cphase = 0 msb valid t sdscim t sspidm lsb valid
?49? rev. a adsp-21161n figure 35. spi interface protocol ? slave switching and timing t hspids t ddspids t dsdhi lsb msb msb valid t hspids t dsoe t ddspids t hdspids miso (output) mosi (input) t sspids spids iput spiclk cp 0 iput spiclk cp iput sdsco spichs spicls spicls spiclks hds spichs sspids hspids dsdhi lsb alid msb msb alid dsoe ddspids miso output mosi iput sspids lsb alid lsb cphase cphase 0 sdppw dso hdlsbs
adsp-21161n ?50? rev. a jtag test access port and emulation table 37. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck low 1 2ns t hsys system inputs hold after tck low 1 15 ns t trstw trst p 4 ck switching characteristics t dtdo tdo delay from tck low 13 ns t dsys system outputs delay after tck low 2 30 ns 1 system inputs = da ta47?16, addr23?0, rd , wr , ack, rpba, spids , eboot, lboot, dmar2C1 , clkcg10, clkdbl , cs , hbr , sbts , id20, irq2C0 , reset , bms , miso, mosi, spiclk, dxa, dxb, sclk x, sx, lxdat0, lxclk, lxack, sdwe , hbg , ras , cas , sdclk0, sdcke, brst, br6C1 , pa , ms3C0 , lag110 2 s o bms , miso, mosi, spiclk, dxa, dxb, sclkx, sx, lxdat0, lxclk, lxack, data416, sdwe , ack, hbg , ras , cas , sdclk10, sdcke, brst, rd , wr , br6C1 , pa , ms3C0 , addr230, lag110, dmag2C1 , dqm, red, clkout, sda10, timep, emu , bmstr, rstout figure 36. jtag test access port and emulation tck tms tdi tdo system inputs system outputs t stap t tck t htap t dtdo t ssys t hsys t dsys
?51? rev. a adsp-21161n output drive currents figure 37 shows typical i-v characteri stics for the output drivers of the adsp-21161n. the curves represent the current drive capability of the output drivers as a function of output voltage. test conditions the dsp is tested for output en able, disable, and hold time. output enable time output pins are considered to be enabled when they have made a transition from a high impedanc e state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 38 ). if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. output disable time output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? . : . ? . ? 0.5 . example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? 2111 . ? 0. . ( ) ( ). (.. ). figure 37. typical drive currents sweep (v ddext ) voltage ? v 60 ?10 ?40 03.5 0.5 1.0 1.5 2.0 2.5 3.0 50 0 ?20 ?30 30 10 40 20 ?50 ?60 l o a d ( v d d e x t ) c u r r e n t ? m a v ddext = 3.47v, ?40c v ddext =3.3v,+25c v ddext = 3.13v, +105c v ddext = 3.13v, +105c v ddext = 3.47v, ?40c v ddext =3.3v,+25c 80 ?80 t decay c l ? v () i l -------------------- - = figure 38. output enable/disable figure 39. 31eq uivalent device loading for ac measurements (includes all fixtures) figure 40. voltage re ference levels for ac measurements (except ou tput enable/disable) reference signal t dis output starts driving v oh (measured) ?
adsp-21161n ?52? rev. a capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 39 on page 51 ). figure 41 shows graphically how output delays an d holds vary with load capaci- tance. (note that this graph or de rating does not apply to output disable delays; see output disable time on page 51 .) the graphs of figure 41 , figure 42 , and figure 43 may not be linear outside the ranges shown for typical outp ut delay vs. load capacitance and typical output rise time (20% ? 80%, v = min) vs. load capacitance. environmental conditions the thermal characteristics in which the dsp is operating influence performance. thermal characteristics the adsp-21161n is packaged in a 225-ball mini ball grid array (mbga). the adsp-21161n is specified for a case tem- perature ( t case ) . to e n s u r e t h at t h e t case data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. use the center block of ground pins (mbga balls: f6-10, g6-10, h6-10, j6-10, k6-10) to provide thermal pathways to the printed circuit board?s ground plane. a heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive. where: ? t case = case temperature (measured on top surface of package) ? pd = power dissipation in w (this value depends upon the specific application; a me thod for calculating pd is shown under power dissipation). ? ca = value from table 38 . ? jb = 8.0c/w figure 41. typical output delay or hold vs. load capacitance (at max case temperature) figure 42. typical output rise/fall time (20% ? 80%, v ddext = max) figure 43. typical output rise/fall time (20% ? 80%, v ddext = min) load capacitance ? pf 2 5 ?5 0210 30 60 90 120 150 180 20 15 10 5 nominal y = 0.0835x - 2.42 o u t p u t d e l a y o r h o l d ? n s load capacitance ? pf 16.0 8.0 0 0 200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 fall time rise time y = 0.0743x + 1.5613 r i s e a n d f a l l t i m e s ? n s ( 0 . 6 9 4 v t o 2 . 7 7 v , 2 0 % t o 8 0 % ) y = 0.0414x + 2.0128 load capacitance ? pf 16.0 8.0 0 0200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 fall time rise time y = 0.0773x + 1.4399 r i s e a n d f a l l t i m e s ? n s ( 0 . 6 9 4 v t o 2 . 7 7 v , 2 0 % t o 8 0 % ) y = 0.0417x + 1.8674 table 38. airflow over package versus ca airflow (linear ft./min.) 0 200 400 ca (c/w) 1 1 jc = 6.8c/w. 17.9 15.2 13.7 t case t amb pd ca () + =
?53? rev. a adsp-21161n 225-ball metric mbga pin configurations table 39. 225-ball metric mbga pin assignments pin name pbga pin number pin name pbga pin number pin name pbga pin number pin name pbga pin number nc a01 trst b01 tms c01 tdo d01 bmstr a02 tdi b02 emu c02 tck d02 bms a03 rpba b03 gd c03 lag11 d03 spids a04 mosi b04 spiclk c04 miso d04 eboot a05 s0 b05 d0b c05 sclk0 d05 lboot a06 sclk1 b06 d1a c06 d1b d06 sclk2 a0 d2b b0 d2a c0 s1 d0 d3b a0 d3a b0 s2 c0 ddit d0 l0dat4 a0 l0dat b0 s3 c0 sclk3 d0 l0ack a10 l0clk b10 l0dat6 c10 l0dat5 d10 l0dat2 a11 l0dat1 b11 l1dat c11 l0dat3 d11 l1dat6 a12 l1dat4 b12 l1dat3 c12 l1dat5 d12 l1clk a13 l1ack b13 l1dat1 c13 data42 d13 l1dat2 a14 l1dat0 b14 data45 c14 data46 d14 c a15 rstout 1 b15 data4 c15 data44 d15 lag10 e01 lag5 01 lag1 g01 lag0 h01 reset e02 lag 02 lag2 g02 irq0 h02 lag e03 lag 03 lag4 g03 ddit h03 d0a e04 lag6 04 lag3 g04 irq1 h04 ddet e05 ddit 05 ddet g05 ddit h05 ddit e06 gd 06 gd g06 gd h06 ddet e0 gd 0 gd g0 gd h0 ddit e0 gd 0 gd g0 gd h0 ddet e0 gd 0 gd g0 gd h0 ddit e10 gd 10 gd g10 gd h10 ddet e11 ddit 11 ddet g11 ddit h11 l0dat0 e12 data3 12 data34 g12 data2 h12 data3 e13 data40 13 data35 g13 data2 h13 data43 e14 data3 14 data33 g14 data30 h14 data41 e15 data36 15 data32 g15 data31 h15 irq2 01 timep k01 addr1 l01 addr16 m01 id1 02 addr22 k02 addr1 l02 addr12 m02 id2 03 addr20 k03 addr21 l03 addr1 m03 id0 04 addr23 k04 addr2 l04 addr6 m04 ddet 05 ddit k05 ddet l05 addr0 m05 gd 06 gd k06 ddit l06 ms1 m06 gd 0 gd k0 ddet l0 br6 m0 gd 0 gd k0 ddit l0 ddet m0 gd 0 gd k0 ddet l0 wr m0 gd 10 gd k10 ddit l10 sda10 m10 ddet 11 ddit k11 ddet l11 ras m11 data26 12 data22 k12 cas l12 ack m12 data24 13 data1 k13 data20 l13 data1 m13 data25 14 data21 k14 data16 l14 dmag2 m14 data2 15 data23 k15 data1 l15 dmag1 m15
adsp-21161n ?54? rev. a addr14 n01 addr13 p01 nc r01 addr15 n02 addr9 p02 addr11 r02 addr10 n03 addr8 p03 addr7 r03 addr5 n04 addr4 p04 addr3 r04 addr1 n05 ms2 p05 ms3 r05 ms0 06 sbts p06 pa r06 br5 0 br4 p0 br3 r0 br2 0 br1 p0 rd r0 brst 0 sdclk1 p0 clkout r0 sdcke 10 sdclk0 p10 hbr r10 cs 11 red p11 hbg r11 clkcg1 12 clki p12 clkdbl r12 clkcg0 13 dqm p13 tal r13 a d d 1 4 ag d p 1 4 sdwe r14 dmar1 15 dmar2 p15 c r15 1 rstout x 12 l 03, 10, 11 figure 44. 225-ball metric mbga pin assignments (bottom view, summary) table 39. 225-ball metric mbga pin assignments (continued) pin name pbga pin number pin name pbga pin number pin name pbga pin number pin name pbga pin number vddint vddext gnd * agnd avdd signal * use the center block of ground pins to provide thermal pathways to your printed circuit board ground plane key: 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 r p n m l k j h g f e d c b a
?55? rev. a adsp-21161n outline dimensions the adsp-21161n comes in a 17 mm 1 225 15 . 225 (225) 1 1 225 (). 2111100 0 +5 100 1 1. . 2111100 0 +105 100 1 1. . 1.5 ( 1) 1.00 15 1 1 12 11 10 5 2 1 1.1 ( 1) 0.20 0.0 0.0 0.50 ( ) 0.0 1 1.00 1. 0 0 1.00 ( ) 1.00 : 1. 122 . 2. 0.25 . . 0.10 .
adsp-21161n ?56? rev. a revision history location page 5/03?changed from rev. 0 to rev. a changes to: key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 simd computational engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 off-chip memory and peripherals interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 phase-locked loop and crys tal double enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 design-for-emulation circuit information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 memory read ? bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 memory write ? bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 synchronous read/write ? bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 host busrequest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 asynchronous read/write ? host to adsp-21161n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 three-state timing ? bus master, bus slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
?57? rev. a adsp-21161n changes to: table 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 changes to formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . global location page
?58?
?59?
?60? c02935?0?5/03(a)

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