SI4732CY vishay siliconix new product document number: 71926 s-03778?rev. c, 21-apr-03 www.vishay.com 1 n-channel synchronous mosfets with break-before-make features 0- to 30-v operation under-voltage lockout shoot through resistant fast switching times so-16 package driver impedance?3 30-v mosfets high side: 0.028 v dd = 4.5 v low side: 0.008 v dd = 4.5 v switching frequency: 250 khz to 1 mhz description the SI4732CY n-channel synchronous mosfet with break-before-make (bbm) is a high speed driver designed to operate in high frequency dc-dc switch-mode power supplies. it?s purpose is to simplify the use of n-channel mosfets in high frequency buck regulators. this device is designed to be used with any single output pwm ic or asic to produce a highly efficient, low cost, synchronous rectifier converter. the little foot plus drivers si4732dy is packaged in vishay-siliconix?s high-performance so-16 package. functional block diagram boot d 1 s 1 d 2 v dd clk undervoltage lockout gnd q 2 q 1 - + v dd sync en v ref level shift s 2 order number: SI4732CY (without tape and reel) SI4732CY-t1 (with tape and reel)
SI4732CY vishay siliconix new product www.vishay.com 2 document number: 71926 s-03778?rev. c, 21-apr-03 absolute maximum ratings (t a = 25 c unless otherwise noted) parameter symbol steady state unit logic supply v dd 7 logic inputs v in - 0.7 to v dd + 0.3 v drain voltage v d1 30 v bootstrap voltage v boot v s1 + 7 t a = 25 c i d1 5.3 continuous drain current (t j = 150 c) a t a = 70 c i d1 4.25 a continuous drain current (t j = 150 c) a t a = 25 c i d2 11 a t a = 70 c i d2 8.85 maximum power dissipation a p d 1.2 w operating junction and storage temperature range driver t j t - 65 to 125 c operating junction and storage temperature range mosfets t j , t stg - 65 to 150 c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol steady state unit drain voltage v d1 0 to 30 logic supply v dd 4.5 to 5.5 v input logic high voltage v ih 0.6 x v dd to v dd v input logic low voltage v il - 0.3 to 0.3 x v dd bootstrap capacitor c boot 100 n to 1 f ambient t emperature t a - 40 to 85 c thermal resistance ratings parameter symbol typical maximum unit high-side junction-to-ambient a r thja1 85 105 low-side junction-to-ambient a st d st t r thja2 68 85 c/w high-side junction-to-foot (drain) b steady state r thjf1 26 33 c/w low-side junction-to-foot (drain) b r thjf2 16 20 notes a. surface mounted on 1? x1? fr4 board, 0.062? thick, 2-oz copper double sided. b. junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is i ntended for use in conjunction with the thermal impedance of the pc board pads to ambient (r thja = r thjf + r thpcb-a ). it can also be used to estimate chip temperature if power dissipation and the lead temperature of a heat carrying (drain) lead is known.
SI4732CY vishay siliconix new product document number: 71926 s-03778?rev. c, 21-apr-03 www.vishay.com 3 specifications test conditions unless specified limits parameter symbol t a = 25 c 4.5 v < v dd <5.5 v, 4.5 v < v d1 <30 v min typ a max unit power supplies logic voltage v dd 4.5 5.5 v logic current (static) i dd(en) v dd = 4.5 v, v clk, sync = 4.5 v 280 500 a logic current (static) i dd(dis) v dd = 4.5 v, v clk, sync = 0 v 220 500 a logic current (dynamic) i dd1(dyn) v dd = 5 v, f clk = 250 khz 20 ma logic current (dynamic) i dd2(dyn) v dd = 5 v, f clk = 1 mhz 70 ma logic input logic input voltage?high (v clk, sync ) v high v dd = 4 5 v 2.7 2.3 v logic input voltage?low (v clk, sync ) v low v dd = 4 . 5 v -0.3 2.25 0.8 v protection break-before-make reference v bbm v dd = 5.5 v 2.4 under-voltage lockout v uvlo v dd = 4 5 v 3.75 4 4.25 v under-voltage lockout hysteresis v h v dd = 4.5 v 0.4 mosfets drain-source voltage v ds i d = 250 a 30 v drain source on state resistance a r ds(on)1 v dd = 4.5 v, i d = 10 a q1 23 28 m c q2 5.5 8 m diode forward voltage a v sd1 i s = 2 a v gs = 0 v q1 0.7 1.1 v diode forward voltage a v sd2 i s = 2 a, v gs = 0 v q2 0.7 1.1 v dynamic b driver clk to s1/d2 off delay t d(off) 34 60 driver clk to s1/d2 fall time t f f s = 1 mhz, i d = 10 a 2.8 10 driver clk to s1/d2 on delay t d(on) f s = 1 mhz , i d = 10 a v in = 12 v, v out = 1.6 v 81 150 ns driver clk to s1/d2 rise time t r 18.4 40 ns source-drain reverse recovery time?q 2 t rr i f 2.7 a, di/dt = 100 a/ s 50 80 notes a. pulse test: pulse width 300 ms, duty cycle 2%. b. typical values are for design aid only, not guaranteed nor subject to production testing.
SI4732CY vishay siliconix new product www.vishay.com 4 document number: 71926 s-03778?rev. c, 21-apr-03 timing diagrams 10% 10% 50% 90% 90% 50% 50% clk s 1 /d 2 clk s 1 /d 2 t f t r t d(off) t d(on) 50% switching test set?up 20 v mosfet drive circuitry with break-before-make c boot d 1 s 1 d 2 s 2 c boot s 1 /d 2 l c l + r l v out gnd gnd clk v dd signal input c c sync en gnd 5 v g 1 g 2
13 so-16 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 top view d1 s 1 d1 s 1 gnd c boot clk v dd sync en s2 s2 d2 d2 d2 s2 d2 SI4732CY vishay siliconix new product document number: 71926 s-03778?rev. c, 21-apr-03 www.vishay.com 5 pin configuration truth table sync en clk q 1 q 2 h h on off h l off on l h on off l l off off pin description pin symbol description 1, 2 d 1 high-side mosfet drain 3 gnd signal ground 4 clk input logic signal 5 sync en synchronous enable 6, 7, 8 s 2 low-side mosfet source 9, 10, 11, 12 d 2 low-side mosfet drain 13 v dd logic supply; decoupling to gnd (with a dap is strongly recommended) 14 c boot bootstrap capacitor for upper mosfet 15, 16 s 1 high-side mosfet source application circuit gnd 5 v 0 v to 30 v mosfet drive circuitry with break-before-make c boot d 1 s 1 d 2 s 2 c boot l c l + gnd gnd clk v dd q 1 q 2 dc-dc controller power up sequence: 1 ensure v dd is within spec before allowing. 2 clk to be set high. power down sequence: 1 ensure clk is low before turning. 2 turn v dd off. sync en v ou t
SI4732CY vishay siliconix new product www.vishay.com 6 document number: 71926 s-03778?rev. c, 21-apr-03 device operation the vishay siliconix mosfet plus driver product is optimized for dc-dc conversion in all aspects?driver design through mosfet optimization. the integrated packaged allows the pcb designer to ignore the mosfet driving current loops and focus on one board layout aspect?output current loop. it also allows for simplicity when adding additional phases to a system. the mosfet driver is designed to eliminate any shoot-through currents in the output mosfet stage by integrating a break-before-make circuit topology. when the low-side mosfet is to be turned on, there is an internal reference voltage, v bbm , that the s 1 node needs to be below before the low-side mosfet is turned on. when the high-side mosfet is to be turned on, there is an optimized delay time (based on the mosfet pair used) that will ensure that the low-side is turned off, and minimize the body diode conduction. in addition, the low impedance mosfet drivers are optimized with the mosfet gate impedance to help ensure an ?off? state gate voltage during any shoot-through conditions when the high-side mosfet is turned on. the mosfets are designed to meet a specific set of conditions to provide the best performance possible. these requirements are as follows. 1. the size of the mosfet is selected to provide a good compromise between power dissipation and size. 2. the high-side mosfet is designed to minimize the r ds(on) -q g figure-of-merit and to have a low r g for short switching times. 3. the low-side mosfet is designed to have the optimum r ds(on) , low r g for short switching times, and low q gd /q gs ratio to eliminate shoot-through conditions. switch timing the SI4732CY has a built-in delay time that is optimized for the mosfet pair. when the clk signal goes low, the high-side driver will turn off, and the output will start to ramp down, t f . after a total delay, t d(off) , the low-side driver turns on to provide the synchronous rectification. when the clk goes high, the low-side driver turns off; as the body diode starts to conduct, the high-side mosfet turns on after a total delay, t d(on) . the output then ramps up, t r . typical characteristics (25 c unless noted) representative safe operating curve the following guidelines are meant to allow the designer the quickest and simplest method to working with the vishay siliconix mosfet plus driver products. 1. the SI4732CY has a limited maximum output current capability, depending on the frequency, duty cycle and ambient temperature. the following graph shows the limitation operating frequency (khz) 0 3 6 9 12 0 200 400 600 800 1000 1200 i out (a) v in = 20 v v out = 1.6 v t a = 25 c i out vs. operating frequency t a = 80 c typical performance 2. the following chart shows experimental results based on a specific set of operating conditions. operating frequency (khz) 0 1 2 3 4 5 6 0 250 500 750 1000 1250 power dissipation (w) v in = 20 v v out = 1.6 v v dd = 5 v i out = 12 a i out = 8 a power dissipation vs. frequency
SI4732CY vishay siliconix new product document number: 71926 s-03778?rev. c, 21-apr-03 www.vishay.com 7 typical characteristics (25 c unless noted) i out (a) power dissipation vs. i out 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 036912 power dissipation (w) v in = 20 v v out = 1.6 v v dd = 5 v 300 khz 700 khz 3. the dissipation of the heat generated by the mosfet plus driver product is highly dependent on the board thermal impedance and the r thjf of the so-16 package. when all of these factors are put together, a set of efficiency curves are developed as shown. this experimental result is based on a spreading copper area on the board of one and a half square inches. 76 78 80 82 84 86 88 90 92 4 6 8 10 12 14 i o (a) efficiency comparison efficiency (%) v in = 20 v inductor of 0.82 h, 5050ez 500 khz 1000 khz 300 khz 700 khz board design guidelines the performance characteristics shown above was done using a board that follows a suggested layout of the device and surrounding components. the basic design rules are as follows. 1. minimize the distance of the v dd capacitor to the v dd pins and ground. 2. place the output inductor close to the s 1 and d 2 pads. using a large copper area around these pads help improve the thermal performance. adding thermal vias to help dissipate the heat also improves performance. 3. use a large copper area for the d 1 and s 2 pads. again, using thermal vias in this area will help the thermal performance.
SI4732CY vishay siliconix new product www.vishay.com 8 document number: 71926 s-03778?rev. c, 21-apr-03 board layout bottom layer bottom layer overlay i nternal plane 1 internal plane 2 top layer overlay top layer
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