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1 S2062 dual serial backplane device october 13, 2000 / revision c S2062 ? dual serial backplane device device specification figure 1. typical dual gigabit ethernet application features ? broad operating rate range (0.77 - 1.3 ghz) - 1062 mhz (fibre channel) - 1250 mhz (gigabit ethernet) line rates - 1/2 rate operation ? dual transmitter with phase-locked loop (pll) clock synthesis from low speed reference ? dual receiver pll provides clock and data recovery ? internally series terminated ttl outputs ? on-chip 8b/10b line encoding and decoding for two separate parallel 8-bit channels ? 2x8 bit parallel ttl interface ? low-jitter serial pecl interface ? local loopback ? interfaces with coax, twinax, or fiber optics ? single +3.3v supply, 1.37 w power dissipation ? compact 21mm x 21mm 156 tbga package applications ? ethernet backbones ? workstation ? frame buffer ? switched networks ? data broadcast environments ? proprietary extended backplanes general description the S2062 facilitates high-speed serial transmission of data in a variety of applications including gigabit ethernet, fibre channel, serial backplanes, and pro- prietary point to point links. the chip provides two separate transceivers which can be operated indi- vidually for a data capacity of >2 gbps. each bi-directional channel provides 8b/10b coding/ decoding, parallel to serial and serial to parallel con- version, clock generation/recovery, and framing. the on-chip transmit pll synthesizes the high-speed clock from a low-speed reference. the on-chip dual receive pll is used for clock recovery and data re- timing on the two independent data inputs. the transmitter and receiver each support differential pecl-compatible i/o for copper or fiber optic com- ponent interfaces with excellent signal integrity. lo- cal loopback mode allows for system diagnostics. the chip requires a 3.3v power supply and dissi- pates 1.37 watts. figure 1 shows the S2062 and s2068 in a gigabit ethernet application. figure 2 combines the S2062 with a crosspoint switch to demonstrate a serial backplane application. figure 3 is the input/ output diagram. figures 4 and 5 show the transmit and receive block diagrams, respectively. mac (asic) S2062 dual gigabit ethernet interface mac to serial backplane s2068 ge interface serial bp driver (asic)
2 dual serial backplane device S2062 october 13, 2000 / revision c figure 2. typical backplane application mac (asic) S2062 atm fibre channel ethernet etc. mac (asic) crosspoint switch s2016 s2025 mac (asic) S2062 atm fibre channel ethernet etc. mac (asic) mac (asic) S2062 atm fibre channel ethernet etc. mac (asic) mac (asic) S2062 atm fibre channel ethernet etc. mac (asic) backplane signal group
3 S2062 dual serial backplane device october 13, 2000 / revision c figure 3. S2062 input/output diagram refclk rate reset tclko txap/n txbp/n rxbp/n rxap/n dina[0:7] sofa, kgena 10 dinb[0:7] sofb, kgenb 10 tclka tclkb 10 rca p/n 10 rcb p/n douta[0:7] eofa, kflaga doutb[0:7] eofb, kflagb clksel erra errb lpen cmode tmode testmode1 testmode
4 dual serial backplane device S2062 october 13, 2000 / revision c figure 4. transmitter block diagram 8b/10b encode 8 10 sofa kgena dina[0:7] 8 shift reg 8b/10b encode 8 10 sofb kgenb dinb[0:7] 8 shift reg din pll 10x/20x refclk clksel rate refclk tclko fifo (input) fifo (input) txap txan txabp txbp txbn txbbp tclkb tclka 0 1 0 1 tmode
5 S2062 dual serial backplane device october 13, 2000 / revision c figure 5. receiver block diagram dout cru serial- parallel eofa kflaga erra douta[0:7] rxap rxan q fifo (output) lpen dout cru serial- parallel eofb kflagb errb doutb[0:7] rxbp rxbn txbbp txabp refclk 8b/10b decode framing data stretching timing 8 8 rcap/n 2 rcbp/n 2 cmode rate fifo (output) 8 8 10 10 8b/10b decode framing data stretching timing tmode
6 dual serial backplane device S2062 october 13, 2000 / revision c transmitter description the transmitter section of the S2062 contains a single pll which is used to generate the serial rate transmit clock for all transmitters. two channels are provided with a variety of options regarding input clocking and loopback. the transmitters can operate in the range of 0.77 ghz to 1.3 ghz, 10 or 20 times the reference clock frequency. data input the S2062 has been designed to simplify the paral- lel interface data transfer and provides the utmost in flexibility regarding clocking of parallel data. prior, or less sophisticated, implementations of this function have either forced the user to synchronize transmit data to the reference clock or to provide the output clock as a reference to the pll, resulting in in- creased jitter at the serial interface. the S2062 in- corporates a unique fifo structure on both the parallel inputs and the parallel outputs which en- ables the user to provide a clean reference source for the pll and to accept a separate external clock which is used exclusively to reliably clock data into the device. data is input to each channel of the S2062 nominally as a 10 bit wide word. this consists of eight data bits of user data, kgen, and sof. an input fifo and a clock input, tclkx, are provided for each channel of the S2062. the S2062 can be configured to use ei- ther the tclkx (tclk mode) input or the refclk input (refclk mode). in tclk or refclk mode, each byte of data is clocked into its fifo with the tclkx provided with each byte. table 1 provides a summary of the input modes for the S2062. operation in the tclk mode makes it easier for users to meet the relatively narrow setup and hold time window required by the parallel 10-bit interface. the tclk signal is used to clock the data into an internal holding register and the S2062 synchronizes its internal data flow to insure stable operation. how- ever, regardless of the clock mode, refclk is al- ways the vco reference clock. this facilitates the provision of a clean reference clock resulting in mini- mum jitter on the serial output. the tclk must be frequency locked to refclk, but may have an arbi- trary but fixed phase relationship. adjustment of in- ternal timing of the S2062 is performed during reset. once synchronized, the S2062 can tolerate up to 3ns of phase drift between tclk and refclk. figure 6 demonstrates the flexibility afforded by the S2062. a low jitter reference is provided directly to the S2062 at either 1/10 or 1/20 the serial data rate. this insures minimum jitter in the synthesized clock used for serial data transmission. a system clock output at the parallel word rate, tclko, is derived from the pll and provided to the upstream circuit as a system clock. the frequency of this output is con- stant at the parallel word rate, 1/10 the serial data rate, regardless of whether the reference is provided at 1/10 or 1/20 the serial data rate. this clock can be buffered as required without concern about added delay. there is no phase requirement between tclko and tclkx, which is provided back to the S2062, other than that they remain within 3ns of the phase relationship established at reset. the S2062 also supports the traditional refclk (tbc) clocking found in fibre channel and gigabit ethernet applications and is illustrated in figure 7. half rate operation the S2062 supports full and 1/2 rate operation for all modes of operation. when rate is low, the S2062 serial data rate equals the vco frequency. when rate is high, the vco is divided by 2 before being provided to the chip. thus the S2062 can support fibre channel and serial backplane functions at both full and 1/2 the vco rate. 8b/10b coding the S2062 provides 8b/10b line coding for each channel. the 8b/10b transmission code includes se- rial encoding and decoding rules, special characters, and error control. information is encoded, 8 bits at a time, into a 10 bit transmission character. the char- acters defined by this code ensure that enough tran- sitions are present in the serial bit stream to make clock recovery possible at the receiver. the encod- ing also greatly increases the likelihood of detecting any single or multiple errors that might occur during the transmission and reception of data 1 . the 8b/10b transmission code includes d-charac- ters, used for data transmission, and k-characters, used for control or protocol functions. each d-char- acter and k-character has a positive and a negative parity version. the parity of each codeword is se- lected by the encoder to control the running disparity of the data stream. k-character generation is con- trolled individually for each channel using the kgenx input. when kgen is asserted, the data on the parallel input is mapped into the corresponding control character. the parity of the k-character is selected to minimize running disparity in the serial data stream. table 3 lists the k characters sup- ported by the S2062 and identifies the mapping of the din[7:0] bits to each character.
7 S2062 dual serial backplane device october 13, 2000 / revision c figure 6. din data clocking with tclk a special input, sof, is provided for each channel to simplify the generation of the k28.5 character. when sof is asserted, the k28.5 character is generated regardless of the data on the parallel input. the k28.5 character can be of either positive or negative parity, depending on the current running disparity. table 4 shows the mapping of the 8b/10b characters repre- sentation. data is transmitted bit a or din[0] first. in addition to data and k characters, the S2062 can also generate a unique sync sequence consisting of 16 consecutive k28.5 characters. this event is initi- ated by the simultaneous assertion of kgenx and sofx for one clock period. the sofx and kgenx inputs should be held low until the sync sequence has completed. the sync sequence may start with either a positive or negative parity k28.5. (depending on the current running disparity.) the parity of the second and third k28.5 are inverse with respect to a valid 8b/ refclk S2062 vco/10 or vco/20 tclkx dinx[0:7] ref oscillator mac asic tclko pll 1 1. a.x. widner and p.a. franaszek, "a byte-oriented dc bal- anced (0,4) 8b/10b transmission code," ibm research report rc9391, may 1982. x f o sx n e g kt u p t u o n i d 2 6 0 2 s 00 a t a d l e l l a r a p d e d o c n e 01 e l b a t y b d e n i f e d s a r e t c a r a h c k ] 0 : 7 [ n i d d n a 3 10 r e t c a r a h c 5 . 8 2 k 11 , r e t c a r a h c d r o w 6 1 l a i c e p s r o - + - + - + - + - + - + - - + + + - + - + - + - + - + - + + - - 10b sequence. parity of the remaining k28.5 alter- nate in accordance with the 8b/10b coding standard. thus, the parity of the k28.5 pattern consists of + + - - + - + - + - + - + - + - or - - + + - + - + - + - + - + - +. table 2 shows the transmitter control signals. frequency synthesizer (pll) the S2062 synthesizes a serial transmit clock from the reference signal. upon startup, the S2062 will obtain phase and frequency lock within 2500 bit times after the start of receiving reference clock in- puts. reliable locking of the transmit pll is assured, but a lock-detect output is not provided. table 2. transmitter control signals note that internal synchronization of fifos is performed upon de-assertion of reset. e d o m tn o i t a r e p o 0 o t d e s u k l c f e r . e d o m k l c f e r l l a r o f s o f i f o t n i a t a d k c o l c . s l e n n a h c 1 k c o l c o t d e s u x c b t . e d o m c b t . s l e n n a h c l l a r o f s o f i f o t n i a t a d table 1. input modes figure 7. din clocking with refclk refclk S2062 tclkx dinx[0:7] ref oscillator mac asic tclko pll vc0/10
8 dual serial backplane device S2062 october 13, 2000 / revision c table 3. k character generation (sofx = 0) k r e t c a r a h c ] 0 : 7 [ n i dn e g k + d r t n e r r u c- d r t n e r r u c s t n e m m o c j h g f i e d c b aj h g f i e d c b a 0 . 8 2 k 1 . 8 2 k 2 . 8 2 k 3 . 8 2 k 4 . 8 2 k 5 . 8 2 k 6 . 8 2 k 7 . 8 2 k 7 . 3 2 k 7 . 7 2 k 7 . 9 2 k 7 . 0 3 k 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 r e t c a r a h c c n y s table 4. data to 8b/10b alphabetic representation e t y b a t a d ] 9 : 0 [ t u o d r o ] 9 : 0 [ n i d 0123456789 n o i t a t n e s e r p e r c i r e m u n a h p l a b 0 1 / b 8 abcdei fghj table 5. operating rates e t a rl e s k l c k l c f e r y c n e u q e r f t u p t u o l a i r e s e t a r o k l c t y c n e u q e r f 00 0 1 / r d sz h g 3 . 1 C 7 7 . 00 1 / r d s 01 0 2 / r d sz h g 3 . 1 C 7 7 . 00 1 / r d s 10 0 1 / r d sz h g 5 6 . 0 - 9 3 . 00 1 / r d s 11 0 2 / r d sz h g 5 6 . 0 - 9 3 . 00 1 / r d s reference clock input the reference clock input must be supplied with a low-jitter clock source. all reference clocks in a sys- tem must be within 200 ppm of each other to insure that the clock recovery units can lock to the serial data. the frequency of the reference clock must be either 1/10 the serial data rate, clksel = 0, or 1/20 the serial data rate, clksel=1. in both cases the fre- quency of the parallel word rate output, tclko, is constant at 1/10 the serial data rate. see table 5. serial data outputs the S2062 provides lvpecl level serial outputs. each high speed output should be provided with a resistor to vss (gnd) near the device. a value of 4.5 k w provides optimal performance with minimum impact on power dissipation. the resistance may be as low as 450 w , but this will dissipate additional power with no sub- stantive performance improvement. outputs are de- signed to perform optimally when ac-coupled. transmit fifo initialization the transmit fifo must be initialized after stable delivery of data and tclk to the parallel interface, and before entering the normal operational state of the circuit. fifo initialization is performed upon the de-assertion of the reset signal. tclko will oper- ate normally regardless of the state of reset. note: sdr = serial data rate.
9 S2062 dual serial backplane device october 13, 2000 / revision c k c o l t n e r r u c e t a t se t a t s e t a t s e t a t se t a t s y c n e u q e r f l l p ) k l c f e r . s v () k l c f e r . s v ( ) k l c f e r . s v ( ) k l c f e r . s v () k l c f e r . s v ( e t a t s k c o l w e n d e k c o l m p p 8 8 4 d e k c o l n u d e k c o l n u m p p 4 4 2 d e k c o l n u table 6. lock to reference frequency criteria receiver description each receiver channel is designed to implement a serial backplane receiver function through the physi- cal layer. a block diagram showing the basic func- tion is provided in figure 5. whenever a signal is present, the receiver attempts to recover the serial clock from the received data stream. after acquiring bit synchronization, the S2062 searches the serial bit stream for the occur- rence of a k28.5 character on which to perform word synchronization. once synchronization on both bit and word boundaries is achieved, the receiver pro- vides the decoded data on its parallel outputs. data input a differential input receiver is provided for each channel of the S2062. each channel has a loopback mode in which the serial data from the transmitter replaces external serial data. the loopback function for both channels is controlled by the loopback en- able signal, lpen. the high speed serial inputs to the S2062 are inter- nally biased to vdd-1.3v. all that is required exter- nally are ac-coupling and line-to-line differential termination. clock recovery function clock recovery is performed on the input data stream for each channel of the S2062. the receiver pll has been optimized for the anticipated needs of serial backplane systems. a simple state machine in the clock recovery macro decides whether to acquire lock from the serial data input or from the reference clock. the decision is based upon the frequency and run length of the serial data inputs. if at any time the frequency or run length checks are violated, the state machine forces the vco to lock to the refer- ence clock. this allows the vco to maintain the cor- rect frequency in the absence of data. the lock to reference frequency criteria insure that the S2062 will respond to variations in the serial data input frequency (compared to the reference frequency). the new lock state is dependent upon the current lock state, as shown in table 6. the run-length criteria insure that the S2062 will respond appropriately and quickly to a loss of signal. the run- length checker flags a condition of consecutive ones or zeros across 12 parallel words. thus 119 or less con- secutive ones or zeros does not cause signal loss, 129 or more causes signal loss, and 120 - 128 may or may not, depending on how the data aligns across byte boundaries. if both the off-frequency detect circuitry test and the run- length test are satisfied, the cru will attempt to lock to the incoming data. when lock is achieved, lock-det is asserted on the err, eof, and kflag status lines. it is possible for the run length test to be satisfied due to noise on the inputs, even if no signal is present. in this case the lock detect status may periodically assert as the vco frequency approaches that of the refclk. in any transfer of pll control from the serial data to the reference clock, the rcxp/n outputs remain phase con- tinuous and glitch free, assuring the integrity of down- stream clocking. when operating in tclk mode, both pll lock status are indicated by a 1-0-1 on the err, eof, and kflag outputs, respectively. reference clock input a single reference clock, which serves both transmitter and receiver, must be provided from a low jitter clock source. the frequency of the received data stream (di- vided-by-10 or -20) must be within 200 ppm of the refer- ence clock to insure reliable locking of the receiver pll. serial-to-parallel conversion once bit synchronization has been attained by the S2062 cru, the S2062 must synchronize to the 10 bit word boundary. word synchronization in the S2062 is accomplished by detecting and aligning to the 8b/10b k28.5 codeword. the S2062 will detect and byte-align to either polarity of the k28.5. each channel of the S2062 will detect and align to a k28.5 anywhere in the data stream. for tclk or refclk mode operation, the presence of a k28.5 is indicated for each channel by the assertion of the eofx signal. table 7 details the function of the eof, kflag, and err pins in status reporting. as indicated in table 7, a 1-0-1 on the err, eof, and kflag signals on any channel is indicative of cru lock failure.
10 dual serial backplane device S2062 october 13, 2000 / revision c r r ef o eg a l f kn o i t p i r c s e dk n a r 00 0 r e t c a r a h c a t a d d i l a v a t a h t s e t a c i d n i . r e t c a r a h c l a m r o n . d e t c e t e d n e e b s a h 5 00 1 r e t c a r a h c k a t a h t s e t a c i d n i . ) 5 . 8 2 k t o n ( r e t c a r a h c k . d e t c e t e d n e e b s a h 5 . 8 2 k n a h t r e h t o 5 01 0 . d e s u t o n 01 1 f o r e t c a r a h c 5 . 8 2 k a t a h t s e t a c i d n i . - 5 . 8 2 k r o + 5 . 8 2 k . d e t c e t e d n e e b s a h y t i r a p y r a r t i b r a 3 10 0 t o n d r o w a t a h t s e t a c i d n i . n o i t a l o i v d r o w e d o c s a h g n i p p a m x . x k r o x . x d d i l a v y n a o t g n i d n o p s e r r o c . d e v i e c e r n e e b 2 10 1 t i b u r c f o s s o l s e t a c i d n i , e d o m k l c t e h t n i n o i t a r e p o . k c o l 1 11 0 s a h r o r r e y t i r a p s i d g n i n n u r a t a h t s e t a c i d n i . r o r r e y t i r a p . d e v r e s b o n e e b 4 11 1 . d e s u t o n table 7. error and status reporting
11 S2062 dual serial backplane device october 13, 2000 / revision c e d o me d o m cq e r f n / p x c r e d o m k c o l c f l a h00 2 / o c v e d o m k c o l c l l u f10 1 / o c v table 8. output clock mode 8b/10b decoding after serial to parallel conversion, the S2062 pro- vides 8b/10b decoding of the data. the received 10- bit codeword is decoded to recover the original 8-bit data. the decoder also checks for errors and flags, either invalid codeword errors or running disparity errors by assertion of the errx signal. error type is determined by examining the eof output in accor- dance with table 7. when more than one reportable condition occurs simultaneously, reporting is in ac- cordance with the rank assigned by table 7. data output data is output on the dout[0:7] outputs. k-characters are flagged using the kflag signal. the eof (with kflag) is used to indicate the reception of a valid k28.5 character. invalid codewords and decoding er- rors are indicated on the err output. kflag, eof, and err are buffered with the data in the fifo to insure that all outputs are synchronized at the S2062 outputs. errors are reported independently for each channel in tclk or refclk mode operation. the S2062 ttl outputs are optimized to drive 65 w line impedances. internal source matching provides good performance on unterminated lines of reason- able length. parallel output clock rate two output clock modes are supported, as shown in table 8. when cmode is high, a complementary ttl clock at the data rate is provided on the rcxp/n outputs. data should be clocked on the rising edge of rcxp. when cmode is low, a complementary ttl clock at 1/2 the data rate is provided. data should be latched on the rising edge of rcxp and the rising edge of rcxn. in fibre channel and gigabit ethernet applications, multiple consecutive k28.5 characters cannot be generated. however, for serial backplane applica- tions this can occur. the S2062 must be able to operate properly when multiple k28.5 characters are received. after the first k28.5 is detected and aligned, the rcxp/n clock will operate without glitches or loss of cycles. figure 8. S2062 diagnostic loopback operation output disabled cru csu other operating modes operating frequency range the S2062 is designed to operate at serial baud rates of 0.77 ghz to 1.3 ghz (616 mbps to 1040 mbps user data rate). the part is specified at fibre channel (1062 mhz) and gigabit ethernet (1.25 ghz) serial baud rates, but will operate satisfactorily at any rate in this range. loopback mode when loopback mode is enabled, the serial data from the transmitter is provided to the serial input of the receiver, as shown in figure 8. this provides the ability to perform system diagnostics and off-line testing of the interface to verify the integrity of the serial channel before enabling the transmission me- dium. loopback mode can be simultaneously en- abled for both channels using the loopback-enable input, lpen. note that the high speed outputs are disabled during loopback operation. test modes the reset pin is used to initialize the transmit fifos and must be asserted (low) prior to entering the normal operational state (see section transmit fifo initialization).
12 dual serial backplane device S2062 october 13, 2000 / revision c table 10. transmitter output signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a x t n a x t . f f i d l c e p v l o6 1 d 5 1 e . a l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h p b x t n b x t . f f i d l c e p v l o5 1 g 6 1 g . b l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h o k l c tl t to 4 1 kd e d i v o r p s i k c o l c s i h t . e t a r a t a d l e l l a r a p e h t t a k c o l c t u p t u o l t t . y r t i u c r i c m a e r t s - p u y b e s u r o f e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 a n i d 6 a n i d 5 a n i d 4 a n i d 3 a n i d 2 a n i d 1 a n i d 0 a n i d l t ti 2 1 p 4 1 t 2 1 r 1 1 p 3 1 t 1 1 r 2 1 t 0 1 p s i s u b s i h t n o a t a d l e l l a r a p . a l e n n a h c r o f a t a d t i m s n a r t . k l c f e r r o a k l c t f o e g d e g n i s i r e h t n o n i d e k c o l c a f o sl t ti 5 1 tf o r e t c a r a h c 5 . 8 2 k e h t s e s u a c h g i h a f o s . a e m a r f f o t r a t s . s t u p t u o a l e n n a h c n o d e t t i m s n a r t e b o t y t i r a p e t a i r p o r p p a a n e g kl t ti 3 1 rn o a t a d e h t s e s u a c h g i h a n e g k . n o i t a r e n e g r e t c a r a h c - k . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ a n i d a k l c tl t ti 0 1 rs i l a n g i s s i h t , h g i h s i e d o m t n e h w . a k c o l c a t a d t i m s n a r t e h t o t n i a f o s d n a , a n e g k , ] 7 : 0 [ a n i d n o a t a d k c o l c o t d e s u . d e r o n g i s i a k l c t , w o l s i e d o m t n e h w . 2 6 0 2 s 7 b n i d 6 b n i d 5 b n i d 4 b n i d 3 b n i d 2 b n i d 1 b n i d 0 b n i d l t ti 6 1 m 5 1 m 4 1 m 6 1 n 5 1 n 4 1 n 6 1 p 5 1 p d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . b l e n n a h c r o f a t a d t i m s n a r t . k l c f e r r o b k l c t f o e g d e g n i s i r e h t n o n i b f o sl t ti 5 1 lf o r e t c a r a h c 5 . 8 2 k e h t s e s u a c h g i h b f o s . b e m a r f f o t r a t s . s t u p t u o b l e n n a h c n o d e t t i m s n a r t e b o t y t i r a p e t a i r p o r p p a b n e g kl t ti 4 1 ln o a t a d e h t s e s u a c h g i h b n e g k . n o i t a r e n e g r e t c a r a h c - k . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ b n i d b k l c tl t ti 6 1 rs i l a n g i s s i h t , h g i h s i e d o m t n e h w . b k c o l c a t a d t i m s n a r t e h t o t n i b f o s d n a , b n e g k , ] 7 : 0 [ b n i d n o a t a d k c o l c o t d e s u . d e r o n g i s i b k l c t , w o l s i e d o m t n e h w . 2 6 0 2 s table 9. transmitter input pin assignment and descriptions
13 S2062 dual serial backplane device october 13, 2000 / revision c table 11. mode control signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d e d o m t s e tl t ti3 d. n o i t a r e p o l a m r o n r o f w o l p e e k . l o r t n o c e d o m t s e t 1 e d o m t s e tl t ti 6 1 l. n o i t a r e p o l a m r o n r o f w o l p e e k . l o r t n o c e d o m t s e t e d o m tl t ti 3 1 ad e s u s i k l c f e r , w o l s i e d o m t n e h w . l o r t n o c e d o m t i m s n a r t . 2 6 0 2 s e h t o t n i x n e g k d n a , x f o s , ] 7 : 0 [ x n i d n o a t a d k c o l c o t e h t o t n i a t a d k c o l c o t d e s u s i x k l c t , h g i h s i e d o m t n e h w . 2 6 0 2 s l e s k l cl t ti 1 1 be h t r o f l l p e h t s e r u g i f n o c l a n g i s s i h t . t u p n i t c e l e s k l c f e r e h t , 0 = l e s k l c n e h w . y c n e u q e r f k l c f e r e t a i r p o r p p a n e h w . e t a r d r o w l e l l a r a p e h t l a u q e d l u o h s y c n e u q e r f k l c f e r l e l l a r a p e h t 2 / 1 e b d l u o h s y c n e u q e r f k l c f e r e h t , 1 = l e s k l c . e t a r a t a d k l c f e rl t ti 5 1 jy c n e u q e r f d n a o c v t i m s n a r t e h t r o f d e s u s i k c o l c e c n e r e f e r . a t a d l a i r e s r e v i e c e r e h t m o r f d e r e v o c e r k c o l c e h t r o f k c e h c t e s e rl t ti 5 1 bs i l l p r e v i e c e r e h t . t e s e r n i d l e h s i 2 6 0 2 s e h t , w o l n e h w e h t n o d e z i l a i t i n i e r a s o f i f e h t . k l c f e r e h t o t k c o l o t d e c r o f s e t a r e p o 2 6 0 2 s e h t , h g i h n e h w . t e s e r f o e g d e g n i s i r . y l l a m r o n e t a rl t ti 1 1 cl a u q e e t a r t u p t u o l a i r e s e h t h t i w s e t a r e p o 2 6 0 2 s e h t , w o l n e h w e h t h t i w s e t a r e p o 2 6 0 2 s e h t , h g i h n e h w . y c n e u q e r f o c v e h t o t . s n o i t c n u f l l a r o f 2 y b d e d i v i d y l l a n r e t n i o c v note: all ttl inputs except refclk have internal pull-up networks.
14 dual serial backplane device S2062 october 13, 2000 / revision c table 12. receiver output pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 a t u o d 6 a t u o d 5 a t u o d 4 a t u o d 3 a t u o d 2 a t u o d 1 a t u o d 0 a t u o d l t to2 l 1 l 2 k 1 k 3 j 1 j 3 h 2 h s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r a l e n n a h c n o d i l a v d n a e d o m k c o l c l l u f n i p a c r f o e g d e g n i s i r e h t n o d i l a v . e d o m k c o l c f l a h n i n a c r d n a p a c r h t o b f o e g d e g n i s i r e h t a f o el t to1 gt u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e a l e n n a h c n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t s e t a c i d n i . ] 7 : 0 [ a t u o d s t u p t u o a t a d l e l l a r a p e h t a g a l f kl t to2 ga t a h t s e t a c i d n i a g a l f k n i h g i h a . g a l f r e t c a r a h c - k a l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ a t u o d e c a f r e t n i l e l l a r a p . d e v i e c e r s a w r e t c a r a h c a r r el t to2 je h t s e i f i n g i s a r r e n o h g i h a . r o r r e e v i e c e r a l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d p a c r n a c r l t to1 m 3 l , a f o e , ] 7 : 0 [ a t u o d , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r n e h w p a c r f o e g d e g n i s i r e h t n o d i l a v e r a a r r e d n a , a g a l f k p a c r h t o b f o e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i . e d o m k c o l c f l a h n i n a c r d n a 7 b t u o d 6 b t u o d 5 b t u o d 4 b t u o d 3 b t u o d 2 b t u o d 1 b t u o d 0 b t u o d l t to8 p 5 t 6 r 6 p 5 r 3 t 5 p 3 r s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r b l e n n a h c n o d i l a v d n a e d o m k c o l c l l u f n i p b c r f o e g d e g n i s i r e h t n o d i l a v . e d o m k c o l c f l a h n i n b c r d n a p b c r h t o b f o e g d e g n i s i r e h t b f o el t to2 pt u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e b l e n n a h c n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t s e t a c i d n i . ] 7 : 0 [ b t u o d s t u p t u o a t a d l e l l a r a p e h t b g a l f kl t to1 ra t a h t s e t a c i d n i b g a l f k n i h g i h a . g a l f r e t c a r a h c - k b l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ b t u o d e c a f r e t n i l e l l a r a p . d e v i e c e r s a w r e t c a r a h c b r r el t to4 pe h t s e i f i n g i s b r r e n o h g i h a . r o r r e e v i e c e r b l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d p b c r n b c r l t to7 r 7 p , b f o e , ] 7 : 0 [ b t u o d , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r n e h w p b c r f o e g d e g n i s i r e h t n o d i l a v e r a b r r e d n a , b g a l f k p b c r h t o b f o e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i . e d o m k c o l c f l a h n i n b c r d n a
15 S2062 dual serial backplane device october 13, 2000 / revision c table 15. power and ground signals table 13. receiver input pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a x r n a x r . f f i d l c e p v l i5 b 4 a s i p a x r . a l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d o t d e s a i b y l l a n r e t n i . e v i t a g e n e h t s i n a x r , t u p n i e v i t i s o p e h t . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v p b x r n b x r . f f i d l c e p v l i0 1 b 1 1 a s i p b x r . b l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d o t d e s a i b y l l a n r e t n i . e v i t a g e n e h t s i n b x r , t u p n i e v i t i s o p e h t . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v table 14. receiver control signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d n e p ll t ti 4 1 cd e e p s h g i h e h t s i e c r u o s t u p n i , w o l n e h w . e l b a n e k c a b p o o l r o f t u p t u o l a i r e s e h t , h g i h n e h w . l e n n a h c h c a e r o f t u p n i l a i r e s . t u p n i s t i o t k c a b d e p o o l s i l e n n a h c h c a e e d o m cl t ti2 cs k c o l c t u p t u o l e l l a r a p e h t , w o l n e h w . l o r t n o c e d o m k c o l c e h t , h g i h n e h w . e t a r a t a d e h t 2 / 1 o t l a u q e s i e t a r ) n / p x c r ( . e t a r a t a d e h t o t l a u q e s i e t a r ) n / p x c r ( s k c o l c t u p t u o l e l l a r a p note: all ttl inputs except refclk have internal pull-up networks. e m a n n i p. y t q# n i pn o i t p i r c s e d a d d v3 5 c , 3 1 b , 8 b. e s i o n w o l ) d d v ( r e w o p g o l a n a a s s v3 3 1 c , 4 b , 8 a. ) s s v ( d n u o r g g o l a n a d d v3 6 c , 2 1 b , 0 1 a. ) d d v ( y r t i u c r i c d e e p s h g i h r o f r e w o p s s v b u s s s v 8, 4 1 a , 2 1 a , 7 a , 5 a , 3 a 2 1 c , 0 1 c , 8 c . ) s s v ( y r t i u c r i c d e e p s h g i h r o f d n u o r g
16 dual serial backplane device S2062 october 13, 2000 / revision c e m a n n i p. y t q# n i pn o i t p i r c s e d r w p l c e p2 6 1 j , 4 1 g. ) d d v ( r e w o p l c e p d n g l c e p3 6 1 f , 5 1 d , 6 1 c. ) s s v ( d n u o r g l c e p r w p g i d5 1 n , 6 1 k , 2 d , 1 c , 2 b. ) d d v ( r e w o p y r t i u c r i c e r o c d n g g i d8 , 4 1 j , 3 e , 2 e , 1 d , 3 c 1 t , 1 p , 5 1 k . ) s s v ( d n u o r g y r t i u c r i c e r o c r w p l t t9 , 3 n , 2 m , 1 h , 3 g , 1 f 7 t , 8 r , 4 r , 9 p . ) d d v ( o / i l t t r o f r e w o p d n g l t t1 1, 3 m , 3 k , 3 f , 2 f , 1 e , 8 t , 4 t , 2 t , 3 p , 2 n 1 1 t . ) s s v ( o / i l t t r o f d n u o r g r w p3 9 b , 6 1 a , 2 a. r e w o p d n g0 1, 6 b , 3 b , 1 b , 9 a , 6 a , 5 1 h , 5 1 f , 6 1 e , 9 c 6 1 h . d n u o r g 1 p a c 2 p a c 25 1 a 4 1 b . r o t i c a p a c r e t l i f p o o l l a n r e t x e r o f s n i p c n0 2, 7 c , 4 c , 6 1 b , 7 b , 1 a , 4 1 f , 4 1 e , 4 1 d , 5 1 c , 2 r , 4 1 p , 3 1 p , 4 1 h 5 1 r , 4 1 r , 9 r 6 1 t , 0 1 t , 9 t , 6 t . t c e n n o c t o n o d . s n i p t s e t s a d e s u . d e t c e n n o c t o n table 15. power and ground signals (continued)
17 S2062 dual serial backplane device october 13, 2000 / revision c figure 9. S2062 pinout (bottom view) a b c d e f g h j k l m n p r t 1 c nd n gr w p g i dd n g g i dd n g l t tr w p l t ta f o er w p l t t2 a t u o d4 a t u o d6 a t u o dp a c rr w p g i dd n g g i db g a l f kd n g g i d 2 r w pr w p g i de d o m cr w p g i dd n g g i dd n g l t ta g a l f k0 a t u o da r r e5 a t u o d7 a t u o dr w p l t td n g l t tb f o ec nd n g l t t 3 b u s s s vd n gd n g g i d t s e t e d o m d n g g i dd n g l t tr w p l t t1 a t u o d3 a t u o dd n g l t tn a c rd n g l t tr w p l t td n g l t t0 b t u o d2 b t u o d 4 n a x ra s s vc n b r r er w p l t td n g l t t 5 s s vp a x ra d d v 1 b t u o d3 b t u o d6 b t u o d 6 d n gd n gd d v 4 b t u o d5 b t u o dc n 7 b u s s s vc nc n n b c rp b c rr w p l t t 8 a s s va d d vb u s s s v 7 b t u o dr w p l t td n g l t t 9 d n gr w pd n g r w p l t tc nc n 0 1 d d vp b x rs s v 0 a n i da k l c tc n 1 1 n b x rl e s k l ce t a r 4 a n i d2 a n i dd n g l t t 2 1 b u s s s vd d vb u s s s v 7 a n i d5 a n i d1 a n i d 3 1 e d o m ta d d va s s v c na n e g k3 a n i d 4 1 s s v2 p a cn e p lc nc nc n l c e p r w p c nd n g g i do k l c tb n e g k5 b n i d2 b n i dc nc n6 a n i d 5 1 1 p a ct e s e rc n l c e p d n g n a x td n gp b x td n gk l c f e rd n g g i db f o s6 b n i d3 b n i d0 b n i dc na f o s 6 1 r w pc nd n g l c e pp a x td n g l c e p d n g n b x td n g l c e p r w p r w p g i d t s e t 1 e d o m 7 b n i d4 b n i d1 b n i db k l c tc n note: nc used as test pins. do not connect.
18 dual serial backplane device S2062 october 13, 2000 / revision c figure 10. S2062 pinout (top view) t r p n m l k j h g f e d c b a d n g g i db g a l f kd n g g i dr w p g i dp a c r6 a t u o d4 a t u o d2 a t u o dr w p l t ta f o er w p l t td n g l t td n g g i dr w p g i dd n gc n 1 d n g l t tc nb f o ed n g l t tr w p l t t7 a t u o d5 a t u o da r r e0 a t u o da g a l f kd n g l t td n g g i dr w p g i de d o m cr w p g i dr w p 2 2 b t u o d0 b t u o dd n g l t tr w p l t td n g l t tn a c rd n g l t t3 a t u o d1 a t u o dr w p l t td n g l t td n g g i d t s e t e d o m d n g g i dd n gb u s s s v 3 d n g l t tr w p l t tb r r e c na s s vn a x r 4 6 b t u o d3 b t u o d1 b t u o d a d d vp a x rs s v 5 c n5 b t u o d4 b t u o d d d vd n gd n g 6 r w p l t tp b c rn b c r c nc nb u s s s v 7 d n g l t tr w p l t t7 b t u o d b u s s s va d d va s s v 8 c nc nr w p l t t d n gr w pd n g 9 c na k l c t0 a n i d s s vp b x rd d v 0 1 d n g l t t2 a n i d4 a n i d e t a rl e s k l cn b x r 1 1 1 a n i d5 a n i d7 a n i d b u s s s vd d vb u s s s v 2 1 3 a n i da n e g kc n a s s va d d ve d o m t 3 1 6 a n i dc nc n2 b n i d5 b n i db n e g ko k l c td n g g i dc n l c e p r w p c nc nc nn e p l2 p a cs s v 4 1 a f o sc n0 b n i d3 b n i d6 b n i db f o sd n g g i dk l c f e rd n gp b x td n gn a x t l c e p d n g c nt e s e r1 p a c 5 1 c nb k l c t1 b n i d4 b n i d7 b n i d t s e t 1 e d o m r w p g i d l c e p r w p d n gn b x t l c e p d n g d n gp a x td n g l c e pc nr w p 6 1 note: nc used as test pins. do not connect.
19 S2062 dual serial backplane device october 13, 2000 / revision c figure 11. compact 21mm x 21mm 156 tbga package device S2062 19.8?c/w q ja 3.5?c/w q jc thermal management
20 dual serial backplane device S2062 october 13, 2000 / revision c tclkx dinx[0:7], sofx, kgenx t 1 t 2 serial data out figure 13. transmitter timing (tclk mode, tmode = 1) table 17. S2062 transmitter timing (tclk mode, tmode = 1) 1. all ac measurements are made from the reference voltage levels of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 1 k l c t . t . r . w p u t e s a t a d0 . 1-s n. 1 e t o n e e s t 2 k l c t . t . r . w d l o h a t a d5 . 0-s n x k l c t n e e w t e b t f i r d e s a h p k l c f e r d n a 3 -3 +s n figure 12. transmitter timing (refclk mode, tmode = 0) table 16. S2062 transmitter timing (refclk mode, tmode = 0) 1. all ac measurements are made from the reference voltage level of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). refclk dinx[0:7], sofx, kgenx t 1 t 2 serial data out s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 1 k l c f e r . t . r . w p u t e s a t a d5 . 0-s n. 1 e t o n e e s t 2 k l c f e r . t . r . w d l o h a t a d3 . 1-s n
21 S2062 dual serial backplane device october 13, 2000 / revision c figure 15. receiver timing (half clock mode, cmode = 0) figure 14. receiver timing (full clock mode, cmode = 1) rcxn doutx[0:7], eofx, kflagx, errx serial data in t 3 t 4 rcxp rcxn doutx[0:7], eofx, kflagx, errx serial data in rcxp t 5 t 6 t 7 t 5 t 6 s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 3 n / p x c r . t . r . w p u t e s a t a d 5 7 . 2 5 . 3 s n s p b g 5 2 . 1 t a s p b g 2 6 0 . 1 t a 1 t 4 n / p x c r . t . r . w d l o h a t a d0 . 2s n t 5 n / p x c r . t . r . w p u t e s a t a d 5 . 2 5 . 3 s n s p b g 5 2 . 1 t a s p b g 2 6 0 . 1 t a 1 t 6 n / p x c r . t . r . w d l o h a t a d0 . 2s n t 7 n x c r o t e s i r p x c r m o r f e m i t e s i r 8 . 7 3 . 9 2 8 . 8 4 . 0 1 s n s n s p b g 5 2 . 1 t a s p b g 2 6 0 . 1 t a 1 t p r t , p f s e m i t l l a f d n a e s i r p x c r0 . 3s n. 8 1 e r u g i f e e s t n r t , n f s e m i t l l a f d n a e s i r n x c r0 . 3s n. 8 1 e r u g i f e e s t r d t , f d s e m i t l l a f d n a e s i r x t u o d0 . 3s n. 7 1 e r u g i f e e s e l c y c y t u de l c y c y t u d n / p x c r0 40 6% table 18. S2062 receiver timing (full and half clock mode) 1. measurements made from the reference voltage levels of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v).
22 dual serial backplane device S2062 october 13, 2000 / revision c note: measurements are made at 1.4v level of clocks. table 19. S2062 transmitter (tclko timing) figure 16. tclko timing s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 8 k l c f e r . t . r . w o k l c t25 . 7s n e l c y c y t u d o k l c t% 0 4% 0 6% refclk t 8 tclko
23 S2062 dual serial backplane device october 13, 2000 / revision c r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t e s a c5 5 -5 2 1c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j5 5 -0 5 1c ? e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? d n g o t t c e p s e r h t i w d d v n o e g a t l o v5 . 0 -0 . 7 +v n i p t u p n i l t t y n a n o e g a t l o v5 . 0 -7 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o v0d d vv t n e r r u c k n i s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l c e p d e e p s h g i h0 3a m o / i l t t , e g a t l o v e g r a h c s i d c i t a t s0 0 0 2v o / i l c e p , e g a t l o v e g r a h c s i d c i t a t s0 0 5 1v r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a00 7c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j0 3 1c ? o t t c e p s e r h t i w n i p r e w o p y n a n o e g a t l o v s s v / d n g 3 1 . 33 . 37 4 . 3v n i p t u p n i l t t n o e g a t l o v07 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o v d d v v 2 - d d vv s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t fe c n a r e l o t y c n e u q e r f0 0 1 -0 0 1 +m p p d t 2 - 1 y r t e m m y s0 40 6% . t p % 0 5 t a e l c y c y t u d t r c r t , f c r e m i t l l a f d n a e s i r k l c f e r2s n. % 0 8 - % 0 2 r e t t i j0 8s p n i a t n i a m o t , k a e p - o t - k a e p 3 . g n i n e p o e y e % 7 7 table 20. absolute maximum ratings table 21. recommended operating conditions table 22. reference clock requirements
24 dual serial backplane device S2062 october 13, 2000 / revision c s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v h o ) l t t ( e g a t l o v h g i h t u p t u o4 . 28 . 2d d vv i n i m = d d v h o a m 4 - = v l o ) l t t ( e g a t l o v w o l t u p t u od n g5 2 0 .5 . 0v i n i m = d d v l o a m 4 = v h i ) l t t ( e g a t l o v h g i h t u p n i0 . 2v v l i ) l t t ( e g a t l o v w o l t u p n id n g8 . 0v i h i ) l t t ( t n e r r u c h g i h t u p n i0 4a v n i x a m = d d v , v 4 . 2 = i l i ) l t t ( t n e r r u c w o l t u p n i0 0 6a v n i x a m = d d v , v 8 . 0 = d d it n e r r u c y l p p u s5 1 43 3 5a m. n r e t t a p 0 1 0 1 p d n o i t a p i s s i d r e w o p7 3 . 14 8 . 1w . n r e t t a p 0 1 0 1 v f f i d g n i w s e g a t l o v t u p n i l a i t n e r e f f i d . n i m s t u p n i l c e p l a i t n e r e f f i d r o f 0 0 10 0 2 2v m. 0 2 e r u g i f e e s d v t u o e g a t l o v t u p t u o l a i r e s l a i t n e r e f f i d g n i w s 0 0 5 10 0 9 10 0 2 2v m k 5 . 4 h t i w d e l p u o c c a w 0 0 1 d n a n w o d l l u p w e e s . n o i t a n i m r e t l a i t n e r e f f i d . 9 1 e r u g i f c n i e c n a t i c a p a c t u p n i3f p table 25. dc characteristics s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c r e t t i j l a t o tr e t t i j l a t o t t u p t u o a t a d l a i r e s2 9 1s p. k a e p - o t - k a e p t j d r e t t i j c i t s i n i m r e t e d t u p t u o a t a d l a i r e s0 8s p. k a e p - o t - k a e p t r s t , f s e m i t l l a f d n a e s i r t u p t u o a t a d l a i r e s0 0 3s pk 5 . 4 . % 0 8 - % 0 2 w . d n u o r g o t s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c t k c o l ) y c n e u q e r f ( e m i t k c o l n o i t i s i u q c a y c n e u q e r f ) s p b g 5 2 . 1 ( ) k c o l f o s s o l ( 5 7 1s e l p m a s n r e t t a p e l d i b 0 1 / b 8 . p u t r a t s e c i v e d m o r f , s i s a b t k c o l ) e s a h p ( e s a h p ( e m i t k c o l n o i t i s i u q c a e s a h p ) s p b g 5 2 . 1 ( ) y t i u n i t n o c s i d 0 5 1s n e e s ( e y e a t a d t u p n i % 0 9 . ) 2 2 e r u g i f 0 8 1s n. e y e a t a d t u p n i % 0 7 t j d e c n a r e l o t r e t t i j t u p n i c i t s i n i m r e t e d0 7 3s p r e t t i j t u p n i e c n a r e l o t e c n a r e l o t r e t t i j l a t o t t u p n i a t a d l a i r e s9 9 5s p y b d e i f i c e p s s a , k a e p - o t - k a e p . z 3 . 2 0 8 e e e i r r s r , f s e m i t l l a f d n a e s i r t u p n i a t a d l a i r e s0 5 3s p. % 0 8 - % 0 2 table 23. serial data timing, transmit outputs table 24. serial data timing, receive inputs
25 S2062 dual serial backplane device october 13, 2000 / revision c output load the S2062 serial outputs require a resistive load to set the output current. the recommended resistor value is 4.5 k w to ground. this value can be varied to adjust drive current, signal voltage swing, and power usage on the board. acquisition time with the input eye diagram shown in figure 22, the S2062 will recover data with a 1e-9 ber within the time specified by t lock in table 24 after an instan- taneous phase shift of the incoming data. figure 20. high speed differential inputs figure 17. serial input/output rise and fall time figure 21. receiver input eye diagram jitter mask figure 18. ttl input/output rise and fall time figure 19. serial output load figure 22. acquisition time eye diagram t r t f 80% 20% 50% 80% 20% 50% t r t f +2.0v +0.8v +2.0v +0.8v 4.5 k 4.5 k 0.01 f 0.01 f vcc -1.3v 100 0.01 f 0.01 f vcc - 1.3 v bit time amplitude 24% 1.3 normalized amplitude normalized time 1.0 0.0 0.2 0.3 0.5 0.7 0.8 0.1 0.6 0.4 0.3 0.7 0.9 1.0 0.0
26 dual serial backplane device S2062 october 13, 2000 / revision c figure 23. loop filter capacitor connections cap1 270 22 nf cap2 270 S2062
27 S2062 dual serial backplane device october 13, 2000 / revision c ordering information x xxxx x prefix device package x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i C s2 6 0 2a g b t 6 5 1 C b t amcc is a registered trademark of applied micro circuits corporation. copyright ? 2000 applied micro circuits corporation d57/r249 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1

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