h anb it HDD16M64D8W url : www.hbe.co.kr 1 hanbit electronics co.,ltd. rev 2.0 (november.2002) general description the hanbit HDD16M64D8W is 16m bit x 64 double data rate sdram high density memory modules. the hanbit HDD16M64D8W consists of eight cmos 16m x 8 bit with 4banks double data rate sdrams in 66pin tsop - ii(400mil) packages mounted on a 184pin glass - epoxy substrate. four 0.1uf decoupling capacitors are mounted on the printed circuit board in parallel for each ddr sdram. the HDD16M64D8W is dual in - line memory modules and intended for mounting into 184pin edge connector sockets. synchronou s design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges of dqs. range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high b andwidth, high performance memory system applications. features ? p art identification HDD16M64D8W C 10a : 1 00 mhz (cl= 2 ) HDD16M64D8W C 13a : 1 33 mhz (cl= 2 ) HDD16M64D8W C 13b : 1 33 mhz (cl= 2.5 ) ? power supply : v dd : 2.5v 0.2v, v ddq : 2.5v 0.2v ? double - data - rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? differential clock inputs(ck and ck) ? dll aligns dq and dqs transition with ck transition ? programmable read latency 2, 2.5 (clock) ? programmable burst length (2, 4, 8) ? programmable burst type (sequential & interleave) ? edge aligned data output, center aligned data input ? auto & self refresh, 7.8us refresh interval(8k/64ms refresh) ? serial presence detect with eeprom ? pcb : height 1250 mi l, double sided component ddr sdram module 128mbyte (16mx64bit), based on16mx8,4banks, 4k ref., dimm, part no . h dd16m64d8w
h anb it HDD16M64D8W url : www.hbe.co.kr 2 hanbit electronics co.,ltd. rev 2.0 (november.2002) pin assignment p1 p2 pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 vref 35 dq25 69 dq43 103 nc 138 /ck0 172 vddq 2 dq1 36 dqs3 70 vdd 104 vddq 139 vss 173 nc 3 vss 37 a4 71 */cs2 105 dq12 140 *dm8 174 dq60 4 dq1 38 vdd 72 dq48 106 dq13 141 a10 175 dq61 5 dqs0 39 dq26 73 dq49 107 dm1 142 *cb6 176 vss 6 dq2 40 dq27 74 vss 108 vdd 143 vddq 177 dm7 7 vdd 41 a2 75 /ck2 109 dq14 144 *cb7 178 dq62 8 dq3 42 vss 76 ck2 110 dq15 145 vss 17 9 dq63 9 nc 43 a1 77 vddq 111 dm1 146 dq36 180 vddq 10 nc 44 *cb0 78 dqs6 112 vddq 147 dq37 181 sa0 11 vss 45 *cb1 79 dq50 113 *ba2 148 vdd 182 sa1 12 dq8 46 vdd 80 dq51 114 dq20 149 dm4 183 sa2 13 dq9 47 *dqs8 81 vss 115 *a12 150 dq38 184 vddspd 14 dqs1 48 a0 82 vddid 116 vss 151 dq39 15 vddq 49 *cb2 83 dq56 117 dq21 152 vss 16 ck1 50 vss 84 dq57 118 a11 153 dq44 17 /ck1 51 *cb3 85 vdd 119 dm2 154 /ras 18 vss 52 ba1 86 dqs7 120 vdd 155 dq45 19 dq10 53 dq32 87 dq58 121 dq22 156 vddq 20 dq11 54 vddq 88 dq59 122 a8 157 /cs0 21 cke0 55 dq33 89 vss 123 dq23 158 */cs1 22 vddq 56 dqs4 90 nc 124 vss 159 dm5 23 dq16 57 dq34 91 sda 125 a6 160 vss 24 dq17 58 vss 92 scl 126 dq28 161 dq46 25 dqs2 59 ba0 93 vss 127 dq29 162 dq47 26 vss 60 dq35 94 dq4 128 vddq 163 */cs3 27 a9 61 dq40 95 dq5 129 dm3 164 vddq 28 dq18 62 vddq 96 vddq 131 a3 165 dq52 29 a7 63 /we 97 dm0 132 vss 166 dq53 30 vddq 64 dq41 98 dq6 133 dq31 167 *a13 31 dq19 65 /cas 99 dq7 134 *cb4 168 vdd 3 2 a5 66 vss 100 vss 135 *cb5 169 dm6 33 dq24 67 dqs5 101 nc 136 vddq 170 dq54 34 vss 68 dq42 102 nc 137 ck0 171 dq55 * these pins should be nc in the system which does not support spd pin pin description pin pin description a0~a12 address input vdd power supply(2.5v) ba0~ba1 bank select address vddq power supply for dqs(2.5v) dq0~dq63 data input/output vref power supply for reference cb0~cb7 check bit(data input/output) vddspd serial eeprom power supply(3.3) dqs0~dqs7 data strobe input/output vss ground dm0~dm7 data - in mask sa0~sa2 address in eeprom ck0~ck2,/ck0~/ck2 clock input sda serial data i/o cke0 clock enable input scl serial clock /cs0 chip select input /we write enable /ras row address strobe vddid vdd indentification flag
h anb it HDD16M64D8W url : www.hbe.co.kr 3 hanbit electronics co.,ltd. rev 2.0 (november.2002) /cas column address strobe nc no connection f unctional block diag ram
h anb it HDD16M64D8W url : www.hbe.co.kr 4 hanbit electronics co.,ltd. rev 2.0 (november.2002) absolute maximum rat ings parameter symbol rating unte voltage on any pin relative to vss v in , v out - 0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd - 1.0 ~ 3.6 v voltage on v ddq supply relative to vss v ddq - 0.5 ~ 3.6 v storage temperature t stg - 55 ~ +150 c power dissipation p d 8.0 w short circuit current i os 50 ma notes: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation shoul d be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. power & dc operating con ditions ( recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) ) parameter symbol min max unit note supply voltage v dd 2.3 2.7 v i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref v ddq /2 - 50mv v ddq /2+50mv v 1 i/o termination voltage (system) v tt v ref C 0.04 v ref + 0.04 v 2 input high voltage v ih (dc) v ref + 0.15 v ref + 0.3 v 4 input low voltage v il (dc) - 0.3 v ref - 0.15 v 4 input voltage level, ck and /ck inputs v in (dc) - 0.3 v ddq + 0.3 v input differential voltage , ck and /ck inputs v id (dc) 0.3 v ddq + 0.6 v 3 input crossing po int voltage, ck and ck inputs v ix (dc) 1.15 1.35 v 5 input leakage current i l i - 2 2 ua out put leakage current i oz - 5 5 ua out put high current (v out = 1.95v) i oh - 16.8 ma out put low current (v out = 0.35v) i o l 16.8 ma output high current(half strengh driver) i oh - 9 ma output high current(half strengh driver) i ol 9 ma notes 1. includes 25mv margin for dc offset on v ref , and a combined total of 50mv margin for all ac noise and dc offset on v ref , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v ref , both of which may result in v ref noise. v ref should be de - coupled with an inductance of 3nh. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc le vel of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck. 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specifications are relative to a v ref envelop that has been bandwidth limited to 200mhz. 5. the value of v ix is expected to equal 0.5* v ddq of the transmitting device and must track variations in the dc level of the same. 6. these charactericteristic s obey the sstl - 2 class ii standards.
h anb it HDD16M64D8W url : www.hbe.co.kr 5 hanbit electronics co.,ltd. rev 2.0 (november.2002) ddr sdram idd spec t able symbol b3(ddr333@cl=2.5) a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit note i d d0 840 760 760 ma idd1 1040 960 960 ma idd2p 28 24 24 ma idd2f 200 176 176 ma idd2q 144 120 120 ma idd3p 280 280 280 ma idd3n 440 440 440 ma idd4r 1280 1136 1136 ma idd4w 1216 1040 1040 ma idd5 1480 1480 1480 ma normal 16 16 16 ma idd6 low power 8 8 8 ma optional idd7a 2640 2400 2400 ma * module idd was calculated on the basis of component id d and can be differently measured according to dq loading cap. ac operating condition s parameter/ condition s tmbol min max unit note input high (logic 1) voltage, dq, dqs and dm s ignals v ih (ac) v ref + 0.31 3 input low (logic 0) voltage, dq, dqs an d dm signals. v il (ac) v ref - 0.31 v 3 input differential voltage, ck and ck inputs v id (ac) 0.7 v ddq +0.6 v 1 input crossing point voltage, ck and ck inputs v ix (ac) 0.5*v ddq - 0.2 0.5*v ddq +0.2 v 2 note 1. v id is the magnitude of the difference betwee n the input level on ck and the input on ck. 2. the value of v ix is expected to equal 0.5* v ddq of the transmitting device and must track variations in the dc level of the same. 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specificatims are refation to a v ref envelope that has been bandwidth limited 20mhz. ac operating test conditions parameter value unit note input reference voltage for clock 0. 5 * v ddq v input signal maximum peak swing 1.5 v input signal minimum slew rate 0.5 v/ns input levels( v i h / v i l ) v re f +0.31/ v re f - 0.31 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load c ondition see load circuit v
h anb it HDD16M64D8W url : www.hbe.co.kr 6 hanbit electronics co.,ltd. rev 2.0 (november.2002) input/output capacitance ( v dd = 2.5v , v ddq = 2.5v , t a = 2 5 c, f = 1mhz ) description symbol min max units input c apacitance( a0 ~ a1 2, b a0 ~ b a1 ,ras,cas, we ) c in1 49 57 pf input c apacitance(ck e 0) c in2 42 50 p f input c apacitance( c s 0) c in3 42 50 pf input c apacitance( cl k 0, cl k 1 ,cl k 2 ) c in4 22 25 pf data & dqs input/output c apacitance(d q 0~d q6 3) c out1 6 8 pf input c apacitance(d m 0~d m 8) c in5 6 8 pf ac timming parameter s & specifications (these ac charicteri s tics were tested on the component) ddr200 ddr266a ddr266b - 10a - 13a - 13b parameter symbol min max min max min max unit note row cycle time t rc 70 65 65 ns 1 refresh row cycle time t rfc 80 75 75 ns 1,2 row active time t ras 48 120k 45 120k 45 120k ns 1,2 / ras to / cas delay t rcd 20 20 20 ns 3 row precharge time t rp 20 20 20 ns 3 row active to row active delay t rrd 15 15 15 ns 3 write recovery time t wr 2 2 2 t ck 3 last data in to read command t cdlr 1 1 1 t ck 2 col. addres s to col. address delay t ccd 1 1 1 t ck cl=2.0 10 12 7.5 12 10 12 ns clock cycle time cl=2.5 t ck 12 7.5 12 7.5 12 ns
h anb it HDD16M64D8W url : www.hbe.co.kr 7 hanbit electronics co.,ltd. rev 2.0 (november.2002) clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs - out access time from ck/ck t dqsck - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns output data access time from ck/ck t ac - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns data strobe edge to ouput data edge t dqsq - +0.6 - +0.5 - +0.5 ns read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck data out high impedence time from ck - /ck t hzq - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns 2 ck to valid dqs - in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs - in setup time t wpres 0 0 0 ns 3 dqs - in hold time t wpreh 0.25 0.25 0.25 t ck dqs - in falling edge to ck rising - setup time t d ss 0.2 0.2 0.2 t ck dqs - in falling edge to ck rising hold time t dsh 0.2 0.2 0.2 t ck dqs - in high level width t dqsh 0.35 0.35 0.35 t ck dqs - in low level wi dth t dqsl 0.35 0.35 0.35 t ck dqs - in cycle time t dsc 0.9 1.1 0.9 1.1 0.9 1.1 t ck address and control input setup time t is 1.1 0.9 0.9 ns address and control input hold time t ih 1.1 0.9 0.9 ns mode register set cycle time t mrd 16 15 15 ns dq & dm setup time to dqs t ds 0.6 0.5 0.5 ns dq & dm hold time to dqs t dh 0.6 0.5 0.5 ns dq & dm input pulse width t dipw 2 1.75 1.75 ns power down exit time t pdex 10 10 10 ns exit self refresh to write command t xsw 116 95 ns ex it self refresh to bank active command t xs a 80 75 75 ns exit self refresh to read command t xs r 200 200 200 cycle refresh interval time t ref 15.6 15.6 15.6 us 1 output dqs valid window t q h 0.35 0.35 0.35 t ck dqs write postamble time t w pst 0.25 0.25 0.25 t ck 4 notes : 1. maximum burst refresh cycle : 8 2. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progr ess on the bus. if a previous write was in progress, dqs could be high at this time, depending on t dqss . 3. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (b us turnaround) will degrade accordingly. 4. a write command can be applied with t rcd satisfied after this command. 5. for registered dimms, t cl and t ch are 3 45% of the period including both the half period jitter ( t jit (hp) ) of the pll and the half jitter due to crosstalk ( t ji t (crosstalk) ) on the dimm. 6. input setup/hold slew rate derating input setup/hold slew rate t is t ih (v/ns) (ps) (ps) 0.5 0 0 0 .4 +50 +50 0.3 +100 +100
h anb it HDD16M64D8W url : www.hbe.co.kr 8 hanbit electronics co.,ltd. rev 2.0 (november.2002) this derating table is used to increase t d s / t dh in the case where the input slew rate is below 0.5v/ns. input setup/hold slew rate based on the lesser of ac - ac slew rate and dc - dc slew rate. 7. i/o setup/hold slew rate derating input setup/hold slew rate t is t ih (v/ns) (ps) (ps) 0.5 0 0 0.4 + 75 + 75 0.3 + 150 + 150 this derating table is used to increase t d s / t dh in the case where the i/o slew rate is below 0.5v/ns. i/o setup/hold slew rate based on the lesser of ac - ac slew rate and dc - dc slew rate. 8. i/o setup/hold plateau derating i/o input level t ds t dh (mv) (ps) (ps) 280 +50 +50 this derating table is used to increase t d s / t dh in the case where the input level is flat below v ref 310mv for a duration of up to 2ns. 9. i/o delta rise/fall rat e(1/slew - rate) derating delta rise/fall rate t ds t dh (ns/v) (ps) (ps) 0 0 0 0.25 +50 +50 0.5 +100 +100 this derating table is used to increase t d s / t dh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calated as 1/sl ewrate1 - 1/slewrate2. for example, if slew rate 1 = 5v/ns and slew rate 2 =.4v/ns then the delta rise/fall rate = - 0/5ns/v. input s/h slew rate based on larger of ac - ac delta rise/fall rate and dc - dc delta rise/fall rate. 10. this parameter is fir system sim ulation purpose. it is guranteed by design. 11. for each of the terms, if not already an integer, round to the next highest integer. t ck is actual to the system clock cycle time. command truth table (v=valid, x=do n t care, h=logic hig h, l=logic low) command cke n - 1 cke n /cs /ras /cas /we dm ba 0,1 a10/ ap a11 a9~a0 note register extended mrs h x l l l l x op code 1,2 register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh s elf refresh exit l h h x x x x x 3 bank active & r ow a ddr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge e able h x l h l h x v h column address (a0 ~ a 9 ) 4 auto precharge disable h l 4 w rite & column address auto precharge en able h x l h l l x v h column address (a0 ~ a 9 ) 4,6 burst stop h x l h h l x x 7 bank selection v l precharge all banks h x l l h l x x h x 5 h x x x entry h l l v v v x clock suspend or activ e power down exit l h x x x x x x h x x x precharge power down mode entry h l l h h h x x
h anb it HDD16M64D8W url : www.hbe.co.kr 9 hanbit electronics co.,ltd. rev 2.0 (november.2002) h x x x exit l h l v v v x dm h x v x 8 h x x x 9 no operation command h x l h h h x x 9 note : 1. op code : operand code. a0 ~ a12 & b a0 ~ b a1 : program keys. (@emrs/mrs) 2. emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. b a0 ~ b a1 : bank select addresses. if both b a0 and b a1 are "low" at read, write, row active and prec harge, bank a is selected. if b a0 is "high" and b a1 is "low" at read, write, row active and precharge, bank b is selected. if b a0 is "low" and b a1 is "high" at read, write, row active and precharge, bank c is selected. if both b a0 and b a1 are "high" at rea d, write, row active and precharge, bank d is selected. 5. if a 10/ap is "high" at row precharge, b a0 and b a1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/writ e command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data - in ar e masked at the both edges (write dm latency is 0). 9. this combination is not defined for any function, which means "no operation(nop)" in ddr sdram. package dimensions unit : mm front C side 3 2 . 7 4 1 0 . 2 0
h anb it HDD16M64D8W url : www.hbe.co.kr 10 hanbit electronics co.,ltd. rev 2.0 (november.2002) rear - side o r dering information part number density org. package ref. vcc mode max.frq HDD16M64D8W - 10a 128mbyte 16m x 64 184pin dimm 4k 2.5v ddr 100mhz/cl2 HDD16M64D8W - 13a 128mbyte 16m x 64 184pin dimm 4k 2.5v ddr 133mhz/cl2 HDD16M64D8W - 13b 128mbyte 16m x 64 184pin dimm 4k 2.5v ddr 133mhz/cl2.5 3 2 . 7 4 1 0 . 2 0
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