xpressarray-ii - feature sheet xpressarray-ii - feature sheet ami semiconductor xpressarray ? -ii 0.15 m structured asic product description ? next-generation 0.15m structured asic platform for high- performance 1.5v asics and fpga-to-asic conversions ? nre and production cost savings ? significant time-to-market advantages ? drop-in replacement for cost-reducing xilinx? virtex?-ii and virtex-ii pro and altera? apex-ii and stratix designs ? 511k to 4.8m asic gates ? 210mhz system, 500mhz local clock speeds ? low power consumption 0.055w/mhz/gate @ 1.575v ? 258kbits to 4.8mbits of block ram memory ? 18kbit initializable dual-port ram blocks at speeds up to 330mhz ? up to 6.1mbits of memory when 50 percent of the logic sites are used for distributed memory ? initializable distributed memory at speeds up to 210mhz ? flexible i/o technology, any i/o standard assigned to any i/o pin ? configurable signal, core and i/o power supply pin locations ? supports lvttl, lvcmos, pci33, pci66, pci-x 133, pci-x 2.0, gtl/+, hstl class 1, 2, 3, and 4, sstl2 class 1 and 2, lvpecl (input), and lvds i/o standards ? 1.5v, 1.8v, 2.5v, and 3.3v capable i/o ? true 3.3v tolerance with no external resistor necessary ? digital controlled impedance (dci) ? built-in dual data rate (ddr) support ? lvds data rates to 1gbps ? up to 1360 user i/os ? comprehensive clock management circuitry ? up to eight delay-locked loops (dlls) and eight phase-locked loops (plls) ? variety of package options ? integrated high-fault coverage scan-test, memory bist and jtag key features targeted at medium-density, high-speed, 1.5v asic applications and high-density fpga-to-asic conversions, the xpressarray-ii (xpa-ii) 0.15m structured asic is an innovative next-generation technology platform that reduces time-to-market for system-on-chip (soc) applications while delivering significant nre and unit cost savings. xpa-ii offers a true drop-in replacement for xilinx virtex-ii and virtex-ii pro and altera apex-ii and stratix fpgas, making it the industry's lowest cost asic conversion solution. the result is a simplified route to cost reductions for oems looking to combine the flexibility of fpga prototyping with a path to asics for final production. operating with system clock speeds up to 210mhz for 18x18 soft multipliers and local clocks up to 500mhz and available in a variety of package options, xpa-ii 0.15m devices deliver high-performance, low power asic solutions with densities to 4.8m asic gates. configurable memory ranges from 258kbits to 4.8mbits, which increases up to 6.1mbits of memory with the addition of distributed configurable memory, assuming 50 percent of the logic sites are used for memory. flexible i/o technology includes support for a comprehensive array of common standards and compatibility with 1.5v, 1.8v, 2.5v, and 3.3v i/o
xpressarray-ii - feature sheet xpressarray-ii - feature sheet ami semiconductor www.amis.com devices sold by amis are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. am is makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent inf ringement. amis makes no warranty of merchantability or fitness for any purposes. amis reserves the right to discontinue production and change specifications and p rices at any time and without notice. ami semiconductor's products are intended for use in commercial applications. applications requiring extended temperature range, u nusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by amis for such applications. copyright ?2006 ami semiconductor, inc. m-20623-003 ko technology xpa-ii technology is ideal for medium density asic applications requiring high performance and low power, with 1.5v operation. xpa-ii devices are fabricated using a hybrid technology that integrates an established 0.15m front-end process with a proven amis metal finishing technology, which is used to produce a customized back-end. the 0.15m processing steps are common to multiple applications, reducing costs by allowing existing tooling to be utilized. at the same time, tooling and manufacturing costs are significantly lower for the metal finishing process than for traditional 0.15m cell-based processes. the result is that xpa-ii delivers reduced cycle times and significant reductions in terms of both nre and unit cost through manufacturing utilizing structured asic technology. there are nine bases in the amis xpa-ii family. these bases offer between 511k and 4.8m gates and up to 4.8mbits of block ram. ram may be configured as single or dual port with asymmetrical port widths. the architecture also supports ram initialization. flexible i/o technology includes fully configurable core and i/o power supply pads and support for one of the industry's widest ranges of i/o standards including lvttl, lvcmos, pci33, pci66, pci-x 133, pci-x 2.0, gtl/+, hstl class 1, 2, 3, and 4, sstl2 class 1 and 2, lvpecl input, and lvds. comprehensive clock management circuitry features up to eight all digital dlls and a maximum of eight plls. compared to equivalent fpgas operating at the same voltage levels, xpa-ii devices offer higher densities, better performance and lower power consumption. low power consumption further contributes to cost savings as lower cost plastic packaging can be used in many cases. xpa-ii products are designed for pin-for-pin replacement of xilinx and altera fpgas and offer integration of multiple fpgas into one asic. package options include a wide range of flip chip bgas in 1.00mm and 1.27mm pitches. schemes. i/os support dci on-chip termination. ddr support for high-speed memory interface is built-in. high fault coverage is provided through integrated scan-test, memory bist and jtag support. for fpga conversions, rapid access to xpressarray (xpa) technology can be achieved via ami semiconductor's netrans? fpga-to-asic design flow. alternatively, the availability of xpa synthesis libraries for leading commercial synthesizers allows conversion of fpga designs to asics by simply re-targeting from an fpga library to an xpa library. for a data sheet with complete technical specifications, please visit ami semiconductor's technical resources at www.amis.com. (1) usable 2rw ram bits (2) usable 2-nand equivalent logic gates product description continued no distributed ram 50% distributed ram xpa-ii base user i/os dlls plls 18k memory blocks memory bits (k) 1 logic gates (k) 2 memory bits (k) 1 logic gates (k) 2 x2p360 360 2 4 14 258 511 389 256 x2p560 560 4 4 40 737 912 972 456 x2p640 640 4 4 48 884 1219 1198 609 X2P720 720 4 4 57 1056 1589 1459 725 x2p846 846 4 4 101 1862 1854 2338 927 x2p880 880 4 4 101 1862 2127 2408 1063 x2p1040 1040 4 4 145 2673 2889 3414 1445 x2p1200 1200 8 8 189 3484 4085 4532 2042 x2p1360 1360 8 8 264 4866 4868 6116 2434
|
