1 white microelectronics ? phoenix, az ? (602) 437-1520 3 sram dualithics 2x512kx8 dualithic? sram advanced* ws1m8v-xcx features n access times 17, 20, 25, 35, 45, 55ns n evolutionary, corner power/ground pinout n packaging: ? 32 pin, hermetic ceramic dip (package 300) n organized as two banks of 512kx8 n commercial, industrial and military temperature ranges n 3.3v power supply n low power cmos n ttl compatible inputs and outputs n output enable internally tied to gnd. * this data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice. october 1998 note: 1. cs 1 and cs 2 are used to select the lower and upper 512kx8 of the device. cs 1 and cs 2 must not be enabled at the same time. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd v cc a15 a17 we a13 a8 a9 a11 cs2 a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 pin configuration for ws1m8v-xcx 32 dip top view block diagram 512k x 8 512k x 8 a 0-18 we cs 1 cs 2 i/o 0-7 (1) (1) a 0-18 address inputs i/o 0-7 data input/output cs 1-2 chip selects we write enable v cc +3.3v power supply gnd ground pin description
2 white microelectronics ? phoenix, az ? (602) 437-1520 3 sram dualithics ws1m8v-xcx truth table absolute maximum ratings parameter symbol min max unit operating temperature t a -55 +125 c storage temperature t stg -65 +150 c signal voltage relative to gnd v g -0.5 +4.6 v junction temperature t j 150 c supply voltage v cc -0.5 5.5 v cs we mode data i/o power h x standby high z standby l h read data out active l l write data in active note: oe is internally tied to gnd. recommended operating conditions parameter symbol condition max unit input capacitance c in v in = 0v, f = 1.0mhz 28 pf output capicitance c out v out = 0v, f = 1.0mhz 28 pf this parameter is guaranteed by design but not tested. parameter symbol min max unit supply voltage v cc 3.0 3.6 v input high voltage v ih 2.2 v cc + 0.3 v input low voltage v il -0.3 +0.8 v operating temp. (mil.) t a -55 +125 c capacitance (t a = +25 c) dc characteristics (v cc = 3.3v, gnd = 0v, t a = -55 c to +125 c) parameter sym conditions units min max input leakage current i li v cc = 3.6, v in = gnd to v cc 10 m a output leakage current i lo 1 cs = v ih , v out = gnd to v cc 10 m a operating supply current i cc 1 cs = v il , f = 5mhz, vcc = 3.6 160 ma standby current i sb 1 cs = v ih , f = 5mhz, vcc = 3.6 30 ma output low voltage v ol i ol = 8.0ma 0.4 v output high voltage v oh i oh = -4.0ma 2.4 v note: dc test conditions: v ih = v cc -0.3v , v il = 0.3v 1. oe is internally tied to gnd.
3 white microelectronics ? phoenix, az ? (602) 437-1520 3 sram dualithics ws1m8v-xcx i current source d.u.t. c = 50 pf eff i ol v 1.5v (bipolar supply) z current source oh notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z 0 = 75 w . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. ac test circuit ac test conditions parameter typ unit input pulse levels v il = 0, v ih = 2.5 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v ac characteristics (v cc = 3.3v, gnd = 0v, t a = -55 c to +125 c) parameter symbol -17 -20 -25 -35 -45 -55 units read cycle min max min max min max min max min max min max read cycle time t rc 17 20 25 35 45 55 ns address access time t aa 17 20 25 35 45 55 ns output hold from address change t oh 000 000ns chip select access time t acs 17 20 25 35 45 55 ns chip select to output in low z t clz 1 222 444ns chip disable to output in high z t chz 1 9 1012152020ns 1. this parameter is guaranteed by design but not tested. 2. oe is internally tied to gnd. ac characteristics (v cc = 3.3v, gnd = 0v, t a = -55 c to +125 c) parameter symbol -17 -20 -25 -35 -45 -55 units write cycle min max min max min max min max min max min max write cycle time t wc 17 20 25 35 45 55 ns chip select to end of write t cw 14 14 15 25 35 50 ns address valid to end of write t aw 14 14 15 25 35 50 ns data valid to end of write t dw 91010202525ns write pulse width t wp 14 14 15 25 35 40 ns address setup time t as 0000 0 0ns address hold time t ah 0000 5 5ns output active from end of write t ow 1 2344 5 5ns write enable to output in high z t whz 1 9 9 10 15 15 25 ns data hold time t dh 0000 0 0ns 1. this parameter is guaranteed by design but not tested.
4 white microelectronics ? phoenix, az ? (602) 437-1520 3 sram dualithics ws1m8v-xcx ws32k32-xhx timing waveform - read cycle write cycle - cs controlled write cycle - we controlled address data i/o write cycle 1, we controlled t aw t cw t ah t wp t dw t whz t as t ow t dh t wc data valid cs we address data i/o write cycle 2, cs controlled t aw t as t cw t ah t wp t dh t dw t wc cs we data valid address data i/o read cycle 2 (we = v ih ) t aa t acs t clz t rc data valid high impedance cs t chz address data i/o read cycle 1 (cs = v il , we = v ih ) t aa t oh t rc data valid previous data valid note: oe is internally tied to gnd.
5 white microelectronics ? phoenix, az ? (602) 437-1520 3 sram dualithics ws1m8v-xcx package 300: 32 pin, ceramic dip, single cavity side brazed 2.5 (0.100) typ 1.27 (0.050) 0.1 (0.005) 0.46 (0.018) 0.05 (0.002) 0.84 (0.033) 0.4 (0.014) 3.2 (0.125) min 15.04 (0.592) 0.3 (0.012) 0.25 (0.010) 0.05 (0.002) 15.25 (0.600) 0.25 (0.010) 42.4 (1.670) 0.4 (0.016) 4.34 (0.171) 0.79 (0.031) pin 1 identifier all linear dimensions are millimeters and parenthetically in inches ordering information lead finish: blank = gold plated leads a = solder dip leads device grade: m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c package: c = ceramic 0.600" dip (package 300) access time (ns) low voltage supply 3.3v 10% organization, two banks of 512k x 8 sram white microelectronics w s 1m8 v - xxx c x x
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