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this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 1.1 / may. 2005 1 184pin unbuffered ddr sdram dimms based on 512mb b ver. features address table organization ranks sdrams # of drams # of row/bank/column address refresh method 256mb 32m x 64 1 32mb x 16 4 13(a0~a12)/2(ba0,ba1)/10(a0~a9) 8k / 64ms 512mb 64m x 64 1 64mb x 8 8 13(a0~a12)/2(ba0,ba1)/11(a0~a9,a11) 8k / 64ms 512mb 64m x 72 1 64mb x 8 9 13(a0~a12)/2(ba0,ba1)/11(a0~a9,a11) 8k / 64ms 1gb 128m x 64 2 128mb x 8 16 13(a0~a12)/2(ba0,ba1)/11(a0~a9,a11) 8k / 64ms 1gb 128m x 72 2 128mb x 8 18 13(a0~a12)/2(ba0,ba1)/11(a0~a9,a11) 8k / 64ms performance range note: 1. 2.6v 0.1v vdd and vddq power supply for ddr400 and 2.5v 0.2v for ddr333 and below part-number suffix -d43 1 -j -h unit speed bin ddr400b ddr333 ddr266b - cl - trcd- trp 3-3-3 2.5-3-3 2.5-3-3 ck max clock frequency cl=3 200 - - mhz cl=2.5 166 166 133 mhz cl=2 133 133 133 mhz this hynix unbuffered dual in-line memory module (dimm) series consists of 512mb b ver. ddr sdrams in 400mil tsop ii packages on a 184pin glass-epoxy substrate. this hynix 512mb b ver. based unbuffered dimm series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. it is suitable for easy interchange and addition. ? jedec standard 184-pin du al in-line memory module (dimm) ? two ranks 128m x 72, 128m x 64 and one rank 64m x 72, 64m x 64, 32m x 64 organization ?2.6v 0.1v vdd and vddq power supply for ddr400, 2.5v 0.2v for ddr333 and below ? all inputs and outputs ar e compatible with sstl_2 interface ? fully differential clock operations (ck & /ck) with 133/166/200mhz ? dll aligns dq and dqs transition with ck transition ? programmable cas latency: ddr266(2, 2.5 clock), ddr333(2.5 clock), ddr400(3 clock) ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? edge-aligned dqs with data outs and center-aligned dqs with data inputs ? auto refresh and self refresh supported ? 8192 refresh cycles / 64ms ? serial presence detect (spd) with eeprom ? built with 512mb ddr sdrams in 400 mil tsop ii packages ? lead-free product listed for each configuration (rohs compliant)
rev. 1.1 / may. 2005 2 1 184pin unbufferd ddr sdram dimms ordering information note: 1. the ?lead-free? products contain lead less than 0.1% by weight and satisfy rohs - please contact hynix for product availabili ty. * these products are built with hy5du124( 8,16)22bt[p], the hyni x ddr sdram component. part number density organization # of drams material dimm dimension ecc support hymd532646b6-h 256mb 32mb x 16 4 normal 133.35 x 31.75 x 3.18 [mm 3 ] none hymd532646bp6-h 256mb 32mb x 16 4 lead-free 1 none hymd532646b6j-d43/j 256mb 32mb x 16 4 normal none hymd532646bp6j-d43/j 256mb 32mb x 16 4 lead-free 1 none hymd564646b8-h 512mb 64mb x 8 8 normal none hymd564646bp8-h 512mb 64mb x 8 8 lead-free 1 none hymd564646b8j-d43/j 512mb 64mb x 8 8 normal none hymd564646bp8j-d43/j 512mb 64mb x 8 8 lead-free 1 none hymd564726b8-h 512mb 64mb x 8 9 normal ecc hymd564726bp8-h 512mb 64mb x 8 9 lead-free 1 ecc hymd564726b8j-d43/j 512mb 64mb x 8 9 normal ecc hymd564726bp8j-d43/j 512mb 64mb x 8 9 lead-free 1 ecc hymd512646b8-h 1gb 128mb x 8 16 normal 133.35 x 31.75 x 4 [mm 3 ] none hymd512646bp8-h 1gb 128mb x 8 16 lead-free 1 none hymd512646b8j-d43/j 1gb 128mb x 8 16 normal none hymd512646bp8j-d43/j 1gb 128mb x 8 16 lead-free 1 none hymd512726b8-h 1gb 128mb x 8 18 normal ecc hymd512726bp8-h 1gb 128mb x 8 18 lead-free 1 ecc hymd512726b8j-d43/j 1gb 128mb x 8 18 normal ecc hymd512726bp8j-d43/j 1gb 128mb x 8 18 lead-free 1 ecc
rev. 1.1 / may. 2005 3 1 184pin unbufferd ddr sdram dimms pin description pin assignment note: 1. pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are reserved for x72 variants of this module and are not used on the x64 ve rsions. 2. pins 111, 158 are not used for single rank module. 3. pin 167 is ?nc? for 256mb, 512mb and 1gb or ?a13? for 2gb module. 4. pins 9, 10, 71, 82, 90, 101, 102, 103, 113, 163, 167, 173 are not used on this module. pin pin description pin pin description ck0~2, /ck0~2 differential clock inpu ts vdd power supply for core and i/o /cs0, /cs1 chip select inputs vddq power supply for dqs cke0, cke1 clock enab le inputs vss ground /ras, /cas, /we commend sets inputs vref input/output reference a0 ~ a13 address inputs vddspd power supply for spd a10/ap address input/autoprecharge v ddid vdd, vddq level detection ba0, ba1 bank address sa0~sa2 spd address inputs dq0~dq63 data inputs/outputs scl spd clock input cb0~cb7 data check bits sda spd data input/output dqs0~dqs8 data strobes du do not use dm0~8 data-in masks nc no connect test reserved for test equipment use pin name pin name pin name pin name pin name pin name 1 vref 32 a5 62 vddq 93 vss 124 vss 154 /ras 2 dq0 33 dq24 63 /we 94 dq4 125 a6 155 dq45 3 vss 34 vss 64 dq41 95 dq5 126 dq28 156 vddq 4 dq1 35 dq25 65 /cas 96 vddq 127 dq29 157 /cs0 5 dqs0 36 dqs3 66 vss 97 dm0,dqs9 128 vddq 158 /cs1 6 dq2 37 a4 67 dqs5 98 dq6 129 dm3,dqs12 159 dm5,dqs14 7 vdd 38 vdd 68 dq42 99 dq7 130 a3 160 vss 8 dq3 39 dq26 69 dq43 100 vss 131 dq30 161 dq46 9 nc 40 dq27 70 vdd 101 nc 132 vss 162 dq47 10 nc 41 a2 71 nc,/cs2 102 nc,test 133 dq31 163 nc,/cs3 11 vss 42 vss 72 dq48 103 nc,feten 134 cb4,nc 164 vddq 12 dq8 43 a1 73 dq49 104 vddq 135 cb5,nc 165 dq52 13 dq9 44 cb0,nc 74 vss 105 dq12 136 vddq 166 dq53 14 dqs1 45 cb1,nc 75 /ck2 106 dq13 137 ck0 167 nc,a13 15 vddq 46 vdd 76 ck2 107 dm1,dqs10 138 /ck0 168 vdd 16 ck1 47 nc,dqs8 77 vddq 108 vdd 139 vss 169 dm6 17 /ck1 48 a0 78 dqs6 109 dq14 140 dm8,dqs17 170 dq54 18 vss 49 cb2,nc 79 dq50 110 dq15 141 a10 171 dq55 19 dq10 50 vss 80 dq51 111 cke1 142 cb6,nc 172 vddq 20 dq11 51 cb3,nc 81 vss 112 vddq 143 vddq 173 nc 21 cke0 52 ba1 82 vddid 113 ba2 144 cb7,nc 174 dq60 22 vddq key 83 dq56 114 dq20 key 175 dq61 23 dq16 53 dq32 84 dq57 115 a12 145 vss 176 vss 24 dq17 54 vddq 85 vdd 116 vss 146 dq36 177 dm7,dqs16 25 dqs2 55 dq33 86 dqs7 117 dq21 147 dq37 178 dq62 26 vss 56 dqs4 87 dq58 118 a11 148 vdd 179 dq63 27 a9 57 dq34 88 dq59 119 dm2,dqs11 149 dm4,dqs13 180 vddq 28 dq18 58 vss 89 vss 120 vdd 150 dq38 181 sa0 29 a7 59 ba0 90 nc 121 dq22 151 dq39 182 sa1 30 vddq 60 dq35 91 sda 122 a8 152 vss 183 sa2 31 dq19 61 dq40 92 scl 123 dq23 153 dq44 184 vddspd
rev. 1.1 / may. 2005 4 1 184pin unbufferd ddr sdram dimms 256mb, 32m x 64 unbuffere d dimm: hymd 532646b[p]6[j] /cs0 w p scl sda a0 a1 a2 sa0 sa1 sa2 serial pd *clock wiring clock input sdrams *ck0, /ck0 *ck1, /ck1 *ck2, /ck2 nc 2 sdrams 2 sdrams *wire per clock loading table/wiring diagrams notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors : 22 ohms +- 5%. 4. vddid strap connections (for memory device vdd, vddq): strap out (open) : vdd = vddq strap in (vss) : vdd v ddq 5. bax, ax, ras, cas, we resistors : 7.5 ohms +- 5% ldm ldqs d1 dq18 dq19 dq20 dq21 dq22 dq23 udm udqs dm3/dqs12 dqs3 dq16 dq17 dm2/dqs11 dqs2 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 /cs dq26 dq27 dq28 dq29 dq30 dq31 dq24 dq25 ldm ldqs d2 dq34 dq35 dq36 dq37 dq38 dq39 udm udqs dm5/dqs14 dqs5 dq32 dq33 dm4/dqs13 dqs4 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 /cs dq42 dq43 dq44 dq45 dq46 dq47 dq40 dq41 ldm ldqs d0 dq2 dq3 dq4 dq5 dq6 dq7 udm udqs dm1/dqs10 dqs1 dq0 dq1 dm0/dqs9 dqs0 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 /cs dq10 dq11 dq12 dq13 dq14 dq15 dq8 dq9 ldm ldqs d3 dq50 dq51 dq52 dq53 dq54 dq55 udm udqs dm7/dqs16 dqs7 dq48 dq49 dm6/dqs15 dqs6 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 /cs dq58 dq59 dq60 dq61 dq62 dq63 dq56 dq57 vdd spd vdd /vddq vref vss vddid spd do-d3 do-d3 do-d3 strap:see note 4 ba0-ba1 a0-a13 /ras /cas cke0 /we ba0-ba1 : sdrams d0-d3 a0-a13 : sdrams d0-d3 /ras : sdrams d0-d3 /cas : sdrams d0-d3 cke : sdrams d0-d3 /we : sdrams d0-d3 functional block diagram
rev. 1.1 / may. 2005 5 1 184pin unbufferd ddr sdram dimms 512mb, 64m x 64 unbuffere d dimm: hymd 564646b[p]8[j] functional block diagram dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm /cs dqs d0 dq10 dq11 dq12 dq13 dq14 dq15 dm /cs dqs d1 dm /cs dqs d2 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm /cs dqs d3 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm /cs dqs d4 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm /cs dqs d5 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm /cs dqs d6 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm /cs dqs d7 dm0/dqs9 dqs0 dm4/dqs13 dqs4 dq8 dq9 dm1/dqs10 dqs1 dm2/dqs11 dqs2 dm3/dqs12 dqs3 dm7/dqs16 dqs7 dm6/dqs15 dqs6 dm5/dqs14 dqs5 / c s 0 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 w p scl sda a0 a1 a2 sa0 sa1 sa2 serial pd *clock wiring clock input sdrams *ck0, /ck0 *ck1, /ck1 *ck2, /ck2 2 sdrams 3 sdrams 3 sdrams *wire per clock loading table/wiring diagrams ba0-ba1 a0-a13 /ras /cas cke0 /we ba0-ba1 : sdrams d0-d7 a0-a13 : sdrams d0-d7 /ras : sdrams d0-d7 /cas : sdrams d0-d7 cke : sdrams d0-d7 /we : sdrams d0-d7 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors : 22 ohms +- 5%. 4. vddid stra p connections (for memory device vdd, vddq): strap out (open) : vdd = vddq strap in (vss) : vdd v ddq 5. bax, ax, ras, cas, we resistors : 5.1 ohms +- 5% strap:see note 4 vdd spd vdd /vddq vref vss vddid spd do-d8 do-d8 do-d8 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2
rev. 1.1 / may. 2005 6 1 184pin unbufferd ddr sdram dimms 512mb, 64m x 72 e cc unbuffered dimm : hymd564726b[p]8[j] functional block diagram dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm /cs dqs d0 dq10 dq11 dq12 dq13 dq14 dq15 dm /cs dqs d1 dm /cs dqs d2 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm /cs dqs d3 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm /cs dqs d4 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm /cs dqs d5 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm /cs dqs d6 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm /cs dqs d7 dm0/dqs9 dqs0 dm4/dqs13 dqs4 dq8 dq9 dm1/dqs10 dqs1 dm2/dqs11 dqs2 dm3/dqs12 dqs3 dm7/dqs16 dqs7 dm6/dqs15 dqs6 dm5/dqs14 dqs5 / c s 0 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 w p scl sda a0 a1 a2 sa0 sa1 sa2 serial pd *clock wiring clock input sdrams *ck0, /ck0 *ck1, /ck1 *ck2, /ck2 3 sdrams 3 sdrams 3 sdrams *wire per clock loading table/wiring diagrams ba0-ba1 a0-a13 /ras /cas cke0 /we ba0-ba1 : sdrams d0-d8 a0-a13 : sdrams d0-d8 /ras : sdrams d0-d8 /cas : sdrams d0-d8 cke : sdrams d0-d8 /we : sdrams d0-d8 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors : 22 ohms +- 5%. 4. vddid strap connections (for memory device vdd, vddq): strap out (open) : vdd = vddq strap in (vss) : vdd v ddq 5. bax, ax, ras, cas, we resistors : 5.1 ohms +- 5% strap:see note 4 vdd spd vdd /vddq vref vss vddid spd do-d8 do-d8 do-d8 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dm /cs dqs d8 dm3/dqs12 dqs3 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2
rev. 1.1 / may. 2005 7 1 184pin unbufferd ddr sdram dimms 1gb, 128m x 64 unbuffere d dimm : hymd512646b[p]8[j] functional block diagram note : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq,dqs,dm/dqs resistors : 22 ohms ? 5% 4. v ddid strap connections (for memory device v dd ,v ddq ) : strap out (open) : v dd = v ddq strap in (v ss ) : v dd v ddq 5. bax, ax, /ras, /cas, /we resistors : 3 ohms ? 5% dm /s dqs d8 dm /s dqs d9 dm /s dqs dm /s dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm /s dqs d0 dq10 dq11 dq12 dq13 dq14 dq15 dm /s dqs d1 dm /s dqs d2 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm /s dqs dq32 dq33 dq35 dq36 dq37 dq38 dq39 dm /s dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm /s dqs d5 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm /s dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm /s dqs d7 dm0 dqs0 dm4 dqs4 dq8 dq9 dm1 dqs1 dm2 dqs2 dm3 dqs3 dm7 dqs7 dm6 dqs6 dm5 dqs5 /s0 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm /s dqs d13 dm /s dqs d15 dm /s dqs d10 /s1 d11 d3 d14 d6 d4 d12 dm /s dqs d12 dq34 vddspd vref vss spd do-d15 do-d15 strap:see note 4 vdd/vddq vddid do-d15 a0-a13 /ras /cas cke0 cke1 /we a0-a13-> : sdrams d0-d15 /ras : sdrams d0-d15 /cas : sdrams d0-d15 cke : sdrams d8-d15 cke : sdrams d0-d7 /we : sdrams d0-d15 ba0-ba1 ba0-ba1-> : sdrams d0-d15 wp a0 scl a1 a2 sda sa0 sa1sa2 serial pd * clock wiring clock input sdrams *ck0,/ck0 4 sdrams *ck1,/ck1 6 sdrams *ck2,/ck2 6 sdrams * wire per clock loading table/wiring diagrams i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5
rev. 1.1 / may. 2005 8 1 184pin unbufferd ddr sdram dimms 1gb, 128m x 72 ecc unbuffere d dimm : hymd512726b[p]8[j] functional block diagram note : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq,dqs,dm/dqs resistors : 22 ohms ? 5% 4. v ddid strap connections (for memory device v dd ,v ddq ) : strap out (open) : v dd = v ddq strap in (v ss ) : v dd v ddq 5. bax, ax, /ras, /cas, /we resistors : 3 ohms ? 5% dm /s dqs d8 dm /s dqs d9 dm /s dqs dm /s dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm /s dqs d0 dq10 dq11 dq12 dq13 dq14 dq15 dm /s dqs d1 dm /s dqs d2 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm /s dqs dq32 dq33 dq35 dq36 dq37 dq38 dq39 dm /s dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm /s dqs d5 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm /s dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm /s dqs d7 dm0 dqs0 dm4 dqs4 dq8 dq9 dm1 dqs1 dm2 dqs2 dm3 dqs3 dm7 dqs7 dm6 dqs6 dm5 dqs5 /s0 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm /s dqs d13 dm /s dqs d15 dm /s dqs d10 /s1 d11 d3 d14 d6 d4 d12 dm /s dqs d12 dq34 dm /s dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dm /s dqs dm8 dqs8 d17 d8 a0-a13 /ras /cas cke0 cke1 /we a0-a13-> : sdrams d0-d17 /ras : sdrams d0-d17 /cas : sdrams d0-d17 cke : sdrams d8-d17 cke : sdrams d0-d8 /we : sdrams d0-d17 ba0-ba1 ba0-ba1-> : sdrams d0-d17 wp a0 scl a1 a2 sda sa0 sa1 sa2 serial pd * clock wiring clock input sdrams *ck0,/ck0 6 sdrams *ck1,/ck1 6 sdrams *ck2,/ck2 6 sdrams * wire per clock loading table/wiring diagrams vddspd vref vss spd do-d15 do-d15 strap:see note 4 vdd/ vddq vddid do-d15 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o7 i/o6 i/o1 i/o0 i/o5 i/o4 i/o3 i/o2 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5 i/o0 i/o1 i/o6 i/o7 i/o2 i/o3 i/o4 i/o5
rev. 1.1 / may. 2005 9 1 184pin unbufferd ddr sdram dimms absolute maximum ratings 1 note: 1. operation at above absolute maximum ra ting can adversely affe ct device reliability parameter symbol rating unit operating temperature (ambient) t a 0 ~ 70 o c storage temperature t stg -55 ~ 150 o c voltage on v dd relative to v ss v dd -1.0 ~ 3.6 v voltage on v ddq relative to v ss v ddq -1.0 ~ 3.6 v voltage on inputs relative to vss v input -1.0 ~ 3.6 v voltage on i/o pins relative to vss v io -0.5 ~3.6 v output short circuit current ios 50 ma soldering temperature ? time t solder 260 ? 10 o c ? sec dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note: 1. v ddq must not exceed the level of v dd . 2. for ddr400, vdd=2.6v 0.1v, vddq=2.6v 0.1v 3. v il (min) is acceptable -1.5v ac pulse width with < 5ns of duration. 4. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. p eak to peak noise on vref may not exceed 2% of the dc value. 5. vid is the magnitude of the difference between the input level on ck and the input level on /ck. 6. the ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera- ture and voltage range, for device drain to source voltages from 0.25v to 1.0v. for a given output, it represents the maximum d iffer- ence between pullup and pulldown drivers due to pr ocess variation. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. 7. vin=0 to vdd, all other pins are not tested under vin =0v. 8. dqs are disabled, vout=0 to vddq. parameter symbol min typ. max unit note power supply voltage (ddr 200, 266, 333) v dd 2.3 2.5 2.7 v power supply voltage (ddr 400) v dd 2.5 2.6 2.7 v 2 power supply voltage (ddr 200, 266, 333) v ddq 2.3 2.5 2.7 v 1 power supply voltage (ddr 400) v ddq 2.5 2.6 2.7 v 1,2 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 3 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 0.49*vddq 0.5*vddq 0.51*vddq v 4 input voltage level, ck and ck inputs vin(dc) -0.3 - vddq+0.3 v input differential voltage, ck and ck inputs vid(dc) 0.36 - vddq+0.6 v 5 v-i matching: pullup to pulldown current ratio vi(ratio) 0.71 - 1.4 - 6 input leakage current i li -2 - 2 ua 7 output leakage current i lo -5 - 5 ua 8 normal strength output driver (v out =vtt wu_[ p output high current (min vddq, min vref, min vtt) ioh -16.8 - - ma output low current (min vddq, max vref, max vtt) iol 16.8 - - ma half strength out- put driver (v out =vtt wu]_ p output high current (min vddq, min vref, min vtt) ioh -13.6 - - ma output low current (min vddq, max vref, max vtt) iol 13.6 - - ma
rev. 1.1 / may. 2005 10 1 184pin unbufferd ddr sdram dimms idd specification and conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) 256mb, 32m x 64 unbuffere d dimm: hymd532646b[p]6[j] * module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol test condition speed unit note ddr400b ddr333 ddr266b idd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 600 560 480 ma idd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 800 720 600 ma idd2p all banks idle; power down mode; cke=low, tck=tck(min) 40 40 40 ma idd2f /cs=high, all banks idle; tck=tck(min); cke= high; address and control inputs changing once per clock cycle. vin=vref for dq, dqs and dm 140 140 140 ma idd3p one bank active ; power down mode; cke=low, tck=tck(min) 48 48 48 ma idd3n /cs=high; cke=high; one bank; active-pre- charge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 200 180 160 ma idd4r burst=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma 1120 1000 840 ma idd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle 1320 1120 1000 ma idd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; dis- tributed refresh 1200 1120 1040 ma idd6 cke=<0.2v; external clock on; tck =tck(min) normal 20 20 20 ma low power 10 10 10 ma idd7 four bank interleaving with bl=4 refer to the fol- lowing page for detailed test condition 2160 1840 1520 ma
rev. 1.1 / may. 2005 11 1 184pin unbufferd ddr sdram dimms idd specification and conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) 512mb, 64m x 64 unbuffere d dimm: hymd564646b[p]8[j] * module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol test condition speed unit note ddr400b ddr333 ddr266b idd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1200 1120 960 ma idd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 1600 1440 1200 ma idd2p all banks idle; power down mode; cke=low, tck=tck(min) 80 80 80 ma idd2f /cs=high, all banks idle; tck=tck(min); cke= high; address and control inputs changing once per clock cycle. vin=vref for dq, dqs and dm 280 280 280 ma idd3p one bank active ; power down mode; cke=low, tck=tck(min) 96 96 96 ma idd3n /cs=high; cke=high; one bank; active-pre- charge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 400 360 320 ma idd4r burst=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma 2240 2000 1680 ma idd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle 2240 2000 1680 ma idd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; dis- tributed refresh 2400 2240 2080 ma idd6 cke=<0.2v; external clock on; tck =tck(min) normal 40 40 40 ma low power 20 20 20 ma idd7 four bank interleaving with bl=4 refer to the fol- lowing page for detailed test condition 4320 3680 3040 ma
rev. 1.1 / may. 2005 12 1 184pin unbufferd ddr sdram dimms idd specification and conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) 512mb, 64m x 72 ecc unbuffer ed dimm: hymd564726b[p]8[j] * module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol test condition speed unit note ddr400b ddr333 ddr266b idd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1350 1260 1080 ma idd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 1800 1620 1350 ma idd2p all banks idle; power down mode; cke=low, tck=tck(min) 90 90 90 ma idd2f /cs=high, all banks idle; tck=tck(min); cke= high; address and control inputs changing once per clock cycle. vin=vref for dq, dqs and dm 315 315 315 ma idd3p one bank active ; powe r down mode; cke=low, tck=tck(min) 108 108 108 ma idd3n /cs=high; cke=high; one bank; active-pre- charge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 450 105 360 ma idd4r burst=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma 2520 2250 1890 ma idd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle 2520 2250 1890 ma idd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; dis- tributed refresh 2700 2520 2340 ma idd6 cke=<0.2v; external clock on; tck =tck(min) normal 45 45 45 ma low power 23 23 23 ma idd7 four bank interleaving with bl=4 refer to the fol- lowing page for detailed test condition 4860 4140 3420 ma
rev. 1.1 / may. 2005 13 1 184pin unbufferd ddr sdram dimms idd specification and conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) 1gb, 128m x 64 unbuffere d dimm: hymd 512646b[p]8[j] * module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol test condition speed unit note ddr400b ddr333 ddr266b idd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1600 1480 1280 ma idd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 2000 1800 1520 ma idd2p all banks idle; power down mode; cke=low, tck=tck(min) 160 160 160 ma idd2f /cs=high, all banks idle; tck=tck(min); cke= high; address and control inputs changing once per clock cycle. vin=vref for dq, dqs and dm 560 560 560 ma idd3p one bank active; power down mode; cke=low, tck=tck(min) 192 192 192 ma idd3n /cs=high; cke=high; one bank; active-pre- charge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 800 720 640 ma idd4r burst=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma 2640 2360 2000 ma idd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle 2640 2360 2000 ma idd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; dis- tributed refresh 2800 2600 2400 ma idd6 cke=<0.2v; external clock on; tck =tck(min) normal 80 80 80 ma low power 40 40 40 ma idd7 four bank interleaving with bl=4 refer to the fol- lowing page for detailed test condition 4720 4040 3360 ma
rev. 1.1 / may. 2005 14 1 184pin unbufferd ddr sdram dimms idd specification and conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) 1gb, 128m x 72 ecc unbuffe red dimm: hymd512726b[p]8[j] * module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol test condition speed unit note ddr400b ddr333 ddr266b idd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1800 1665 1440 ma idd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changi ng once per clock cycle 2250 2025 1710 ma idd2p all banks idle; power down mode; cke=low, tck=tck(min) 180 180 180 ma idd2f /cs=high, all banks idle; tck=tck(min); cke= high; address and control inputs changing once per clock cycle. vin=vref for dq, dqs and dm 630 630 630 ma idd3p one bank active ; power down mode; cke=low, tck=tck(min) 216 216 216 ma idd3n /cs=high; cke=high; one bank; active-pre- charge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 900 810 720 ma idd4r burst=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma 2970 2655 2250 ma idd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle 2970 2655 2250 ma idd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; dis- tributed refresh 3150 2925 2700 ma idd6 cke=<0.2v; external clock on; tck =tck(min) normal 90 90 90 ma low power 45 45 45 ma idd7 four bank interleaving with bl=4 refer to the fol- lowing page for detailed test condition 5310 4545 3780 ma
rev. 1.1 / may. 2005 15 1 184pin unbufferd ddr sdram dimms ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note: 1. vid is the magnitude of the difference between the input level on ck and the input on /ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) output load circuit parameter symbol min max unit note input high (logic 1) voltag e, dq, dqs and dm signals v ih(ac) v ref + 0.31 - v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) -v ref - 0.31 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t )50 ? series resistor (r s )25 ? output load capacitance for access time measurement (c l )30 pf v ref v tt r t =50 ? zo=50 ? c l =30pf output
rev. 1.1 / may. 2005 16 1 184pin unbufferd ddr sdram dimms capacitance (t a =25 o c, f=100mhz) 256mb: hymd532646b[p]6[j] 512mb: hymd564646b[p]8[j] 512mb (with ecc): hymd564726b[p]8[j] input/output pins symbol min max unit a0 ~ a12, ba0, ba1 c in1 40 52 pf /ras, /cas, /we c in2 40 52 pf cke c in3 40 52 pf /cs c in4 40 52 pf ck0, /ck0, ck1, /ck1, ck2, /ck2 c in5 22 32 pf dm0 ~ dm7 c in6 712pf dq0 ~ dq63, dqs0 ~ dqs7 c io1 712pf input/output pins symbol min max unit a0 ~ a12, ba0, ba1 c in1 58 71 pf /ras, /cas, /we c in2 58 71 pf cke c in3 58 72 pf /cs c in4 58 72 pf ck0, /ck0, ck1, /ck1, ck2, /ck2 c in5 25 40 pf dm0 ~ dm7 c in6 712pf dq0 ~ dq63, dqs0 ~ dqs7 c io1 712pf input/output pins symbol min max unit a0 ~ a12, ba0, ba1 c in1 60 75 pf /ras, /cas, /we c in2 60 75 pf cke c in3 60 75 pf /cs c in4 60 75 pf ck0, /ck0, ck1, /ck1, ck2, /ck2 c in5 27 45 pf dm0 ~ dm7 c in6 712pf dq0 ~ dq63, dqs0 ~ dqs7 c io1 712pf cb0 ~ cb7 c io2 712pf
rev. 1.1 / may. 2005 17 1 184pin unbufferd ddr sdram dimms capacitance (t a =25 o c, f=100mhz) 1gb: hymd512646b[p]8[j] 1gb (with ecc): hymd512726b[p]8[j] input/output pins symbol min max unit a0 ~ a12, ba0, ba1 c in1 90 104 pf /ras, /cas, /we c in2 90 104 pf cke0, cke1 c in3 58 72 pf /cs0, /cs1 c in4 58 72 pf ck0, /ck0, ck1, /ck1, ck2, /ck2 c in5 30 45 pf dm0 ~ dm7 c in6 12 18 pf dq0 ~ dq63, dqs0 ~ dqs7 c io1 12 18 pf input/output pins symbol min max unit a0 ~ a12, ba0, ba1 c in1 95 110 pf /ras, /cas, /we c in2 95 110 pf cke0, cke1 c in3 60 80 pf /cs0,/cs1 c in4 60 80 pf ck0, /ck0, ck1, /ck1, ck2, /ck2 c in5 32 45 pf dm0 ~ dm7 c in6 12 18 pf dq0 ~ dq63, dqs0 ~ dqs7 c io1 12 18 pf cb0 ~ cb7 c io2 12 18 pf
rev. 1.1 / may. 2005 18 1 184pin unbufferd ddr sdram dimms ac characteristics (note: 1 - 9 / ac operating conditions unless otherwise noted) parameter symbol ddr400b ddr333 ddr266a ddr266b ddr200 unit min max min max min max min max min max row cycle time trc 55 - 60 - 65 - 65 - 70 - ns auto refresh row cycle time trfc 70 - 72 - 75 - 75 - 80 - ns row active time tras 40 70k 42 70k 45 120k 45 120k 50 120k ns active to read with auto precharge delay trap trcd or trasmin - trcd or trasmin - trcd or trasmin - trcd or trasmin - trcd or trasmin -ns row address to column address delay trcd 15 - 18 - 20 - 20 - 20 - ns row active to row active delay trrd 10 - 12 - 15 - 15 - 15 - ns column address to column address delay tccd1-1-1-1-1-tck row precharge time trp 15 - 18 - 20 - 20 - 20 - ns write recovery time twr 15 - 15 - 15 - 15 - 15 - ns internal write to read command delay twtr2-1-1-1-1-tck auto precharge write recovery + precharge time 22 tdal (twr/ tck) + (trp/tck) - (twr/ tck) + (trp/tck) - (twr/ tck) + (trp/tck) - (twr/ tck) + (trp/tck) - (twr/ tck) + (trp/tck) -tck system clock cycle time 24 cl = 3 tck 510-------- cl = 2.5 - - 6 12 7.5 12 7.5 12 8.0 12 ns cl = 2 - - 7.5127.51210121012ns clock high level width tch 0.45 0.55 0. 45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0. 45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck data-out edge to clock edge skew tac -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns dqs-out edge to clock edge skew tdqsck -0.55 0.55 -0.6 0.6 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns dqs-out edge to data- out edge skew 21 tdqsq - 0.4 - 0.45 - 0.5 - 0.5 - 0.6 ns data-out hold time from dqs 20 tqh thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs -ns clock half period 19,20 thp min (tcl,tch) - min (tcl,tch) - min (tcl,tch) - min (tcl,tch) - min (tcl,tch) -ns data hold skew factor 20 tqhs - 0.5 - 0.55 - 0.75 - 0.75 - 0.75 ns valid data output window tdv tqh-tdqsq tqh-tdqsq tqh-tdqsq tqh-tdqsq tqh-tdqsq ns
rev. 1.1 / may. 2005 19 1 184pin unbufferd ddr sdram dimms - continue parameter symbol ddr400b ddr333 ddr266a ddr266b ddr200 unit min max min max min max min max min max data-out high-impedance window from ck,/ck 10 thz -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns data-out low-impedance window from ck, /ck 10 tlz -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns input setup time (fast slew rate) 14,16-18 tis 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns input hold time (fast slew rate) 14,16-18 tih 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns input setup time (slow slew rate) 15-18 tis 0.7 - 0.8 - 1.0 - 1.0 - 1.1 - ns input hold time (slow slew rate) 15-18 tih 0.7 - 0.8 - 1.0 - 1.0 - 1.1 - ns input pulse width 17 tipw 2.2 - 2.2 - 2.2 - 2.2 - 2.5 - ns write dqs high level width tdqsh 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tck write dqs low level width tdqsl 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tck clock to first rising edge of dqs- in tdqss 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs falling edge to ck setup time tdss 0.2 -0.2 -0.2 -0.2 -0.2 -tck dqs falling edge hold time from ck tdsh 0.2 -0.2 -0.2 -0.2 -0.2 -tck dq & dm input setup time 25 tds 0.4 - 0.45 - 0.5 - 0.5 - 0.6 - ns dq & dm input hold time 25 tdh 0.4 - 0.45 - 0.5 - 0.5 - 0.6 - ns dq & dm input pulse width 17 tdipw 1.75 - 1.75 - 1.75 - 1.75 - 2 - ns read dqs preamble time trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read dqs postamble time trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck write dqs preamble setup time 12 twpres 0 -0-0- 0 -0 -ns write dqs preamble hold time twpreh 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - tck write dqs postamble time 11 twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck mode register set delay tmrd 2 -2-2- 2 -2 -tck exit self refresh to non-read command 23 txsnr 75 - 75 - 75 - 75 - 80 - ns exit self refresh to read command txsrd 200 - 200 - 200 - 200 - 200 - tck average periodic refresh interval 13,25 trefi - 7.8 - 7.8 - 7.8 - 7.8 - 7.8 us
rev. 1.1 / may. 2005 20 1 184pin unbufferd ddr sdram dimms note: 1. all voltages referenced to vss. 2. tests for ac timing, idd, an d electrical, ac and dc characte ristics, may be conducted at nominal reference/supply voltage le vels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. below figure represents the timing refere nce load used in defining the relevant timing parameters of the part. it is not int ended to be either a precise representation of the typical system environment nor a depiction of the actual load pr esented by a producti on tester. system designers will use ibis or other simulation tools to correlate the timing referenc e load to a system environment . manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the teste r elec- tronics). 4. ac timing and idd tests may use a vil to vihswing of up to 1.5 v in the test environment, but input timing is still referenc ed to vref (or to the crossing point for ck, /ck) , and parameter specifications are guarante ed for the specified ac input levels unde r normal use conditions. the minimum slew rate for the input signals is 1 v/ns in the rang e between vil(ac) and vih(ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e ., the receiver will effectively switch a s a result of the signal crossing the ac in put level and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 6. inputs are not recognized as valid until vref stabilizes. exception: during the period before vref stabilizes, cke < 0.2vddq is recognized as low. 7. the ck, /ck input reference level (for timing referenced to ck , /ck) is the point at which ck and /ck cross; the input refer ence level for signals other than ck, /ck is vref. 8. the output timing reference voltage level is vtt. 9 . operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 10. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not reference d to a specific voltage level but specify when the device output is no longer driving (hz), or begins driving (lz). 11. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter , but system performance (bus turnar ound) will degrade accordingly. 12. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this ck edge . a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were prev i- ously in progress on the bus, dqs will be transitioning from hi gh-z to logic low. if a previous write was in progress, dqs coul d be high, low, or transitioning from high to low at this time, depending on tdqss. 13. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 14. for command/address input slew rate 1.0 v/ns. 15. for command/address input slew rate 0.5 v/ns and 1.0 v/ns 16. for ck & / ck slew rate 1.0 v/ns (single-ended) 17. these parameters guarantee device timing, but they are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. 18. slew rate is measured between voh(ac) and vol(ac). 19. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tcl and tch). for example, tcl and tch are = 50% of the period, less the half period jitter (tjit(hp)) of the clock source, and less th e half period jitter due to crosstalk (tjit(crosstalk)) into the clock traces. figure: timing reference load vddq 50 output (vout) 30 pf
rev. 1.1 / may. 2005 21 1 184pin unbufferd ddr sdram dimms 20.tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs accounts fo r 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push--out of dqs on one transition followed by the worst case pull--in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effect s, and p-channel to n-ch annel variation of the output drivers. 21. tdqsq: consists of data pin skew and output pattern effects, an d p-channel to n-channel variation of the output drivers for any g iven cycle. 22. tdal = (twr/tck) + (trp/tck) for each of the terms above, if not alre ady an integer, round to the next highest integer. example: for ddr266b at cl=2.5 and tck=7.5 ns tdal = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks = ((2) + (3)) clocks = 5 clocks 23. in all circumstances, txsnr can be satisfied using txsnr = trfcmin + 1*tck 24. the only time that the clock frequency is al lowed to change is during self-refresh mode. 25. if refresh timing or tds/tdh is violated, data corruption ma y occur and the data must be re-w ritten with valid data before a valid read can be executed.
rev. 1.1 / may. 2005 22 1 184pin unbufferd ddr sdram dimms system characteristics co nditions for ddr sdrams the following tables are described specification parameters that required in systems using ddr devices to ensure proper performannce. these characteri stics are for system simulation purposes and are guaranteed by design. input slew rate for dq/dm/dqs (table a.) address & control input setup & hold time derating (table b.) dq & dm input setup & hold time derating (table c.) dq & dm input setup & hold time derating for rise/fall delta slew rate (table d.) output slew rate characteristics (for x4, x8 devices) (table e.) output slew rate characte ristics (for x16 device) (table f.) output slew rate matchi ng ratio characteristics (table g.) ac characteristics ddr400 ddr333 ddr266 ddr200 unit note parameter symbol min max min max min max min max dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew 0.5 4.0 0.5 4.0 0.5 4.0 0.5 4.0 v/ns 1,12 input slew rate delta tis delta tih unit note 0.5 v/ns 0 0 ps 9 0.4 v/ns +50 0 ps 9 0.3 v/ns +100 0 ps 9 input slew rate delta tds delta tdh unit note 0.5 v/ns 0 0 ps 11 0.4 v/ns +75 0 ps 11 0.3 v/ns +150 0 ps 11 input slew rate delta tds delta tdh unit note 0.0 ns/v 00ps10 0.25 ns/v +50 +50 ps 10 0.5 ns/v +100 +100 ps 10 slew rate characteristic typical range (v/ ns) minimum (v/ns) maximum (v/ns) note pullup slew rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8 pulldown slew rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8 slew rate characteristic typical range (v/ ns) minimum (v/ns) maximum (v/ns) note pullup slew rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8 pulldown slew rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8 slew rate characteristic ddr266a ddr266b ddr200 note parameter min max min max min max output slew rate matching ratio (pullup to pulldown) - - - - 0.71 1.4 5,12
rev. 1.1 / may. 2005 23 1 184pin unbufferd ddr sdram dimms note: 1. pullup slew rate is characterized under the test conditions as shown in below figure. 2. pulldown slew rate is measured under the test conditions shown in below figure. 3. pullup slew rate is measured between (vddq/2 - 320 mv 250mv) pulldown slew rate is measured between (vddq/2 + 320mv 250mv) pullup and pulldown slew rate conditions are to be met fo r any pattern of data, including all outputs switching and only on e output switching. example: for typical slew, dq0 is switching for minimum slew rate, all dq bits are switching worst case pattern for maximum slew rate, only one dq is switching from either high to low, or low to high. the remaining dq bi ts remain the same as for previous state. 4. evaluation conditions typical: 25 o c (ambient), vddq = nominal, typical process minimum: 70 o c (ambient), vddq = mini mum, slow-slow process maximum: 0 o c (ambient), vddq = maximum, fast-fast process 5. the ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire tempe rature and voltage range. for a given ou tput, it represents the maximum difference betw een pullup and pulldown drivers due to process variation. 6. verified under typical condit ions for qualification purposes. 7. tsop-ii package devices only. 8. only intended for operation up to 256 mbps per pin. 9. a derating factor will be used to increase tis and tih in the case where the input slew rate is below 0.5 v/ns as shown in t able b. the input slew rate is based on the lesser of the slew rates dete rmined by either vih(ac) to vil( ac) or vih(dc) to vil(dc), sim - ilarly for rising transitions. 10. a derating factor will be used to increase tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tab les c & d. input slew rate is based on the larger of ac-ac delta rise, fall rate and dc-dc delta rise, fall rate. input slew rate is based on the lesser of the slew rates determined by either vih(ac) to vi l(ac) or vih(dc) to vil(dc), sim ilarly for rising transitions. t he delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example: if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is -0.5 ns/v. using the table given , this would result in the need for an increase in tds and tdh of 100ps. 11. table c is used to increase tds and tdh in the case where th e i/o slew rate is below 0.5 v/ns . the i/o slew rate is based o n the lesser of the ac-ac slew rate and the dc-dc slew rate. the input slew rate is based on the lesser of the slew rates determined by either vih(ac) to vil(ac) or vih(dc) to vi l(dc), and similarly fo r rising transitions. 12. dqs, dm, and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal t ran- sitions through the dc region must be monotonic. 50 output (vout) vssq test point figure: pullup slew rate vddq 50 test point output (vout) figure: pulldown slew rate
rev. 1.1 / may. 2005 24 1 184pin unbufferd ddr sdram dimms simplified command truth table note : 1. dm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a 0 ~a 12 and ba 0 ~ba 1 used for mode registering duing extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+trp). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+ 1+twr+trp). write recovery time(twr) is needed to guarantee that the last data has been completely written. 5. if a10/ap is high when row precharge command being issued, ba0 /ba1 are ignored and all banks are selected to be precharged. write mask truth table note: 1. write mask command masks burst write data with reference to ldqs/udqs(data strobes) and it is not related with read data. in case of x16 data i/o, ldm and udm control lowe r byte(dq0~7) and upper byte(dq8~15) respectively. command cken-1 cken /cs /ras /cas /we addr a10/ap ba note extended mode register set h x llll op code 1,2 mode register set h x llll op code 1,2 device deselect hx hxxx x1 no operation lhhh bank active h x l l h h ra v 1 read h x lhlhca l v 1 read with autoprecharge h1,3 write hxlhllca l v 1 write with autoprecharge h1,4 precharge all banks hxllhlx hx1,5 precharge selected bank lv1 read burst stop h x l h h l x 1 auto refresh h h lllh x 1 self refresh entryh l lllh x 1 exit l h hxxx 1 lhhh precharge power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 active power down mode entry h l hxxx x 1 lvvv 1 exit l h x 1 function cken-1 cken /cs, /ras, /cas, /we dm addr a10/ap ba note data write h x x l x 1 data-in mask h x x h x 1 ( h=logic high level, l=logic low level, x=don?t care, v=vali d data input, op code=operand code, nop=no operation )
rev. 1.1 / may. 2005 25 1 184pin unbufferd ddr sdram dimms package dimensions 256mb, 32m x 64 unbuffere d dimm: hymd532646b[p]6[j] 2.30 .91 17.80 .700 .394 10.0 0.098 2.5 (2) 0 5.077 front 128.95 131.35 5.171 133.35 5.25 31.75 1.250 (2x)4.00 .157 side (front) 3.18 .125max 1.27+/-0.10 .050+/-.004 back millimeters inches un it :
rev. 1.1 / may. 2005 26 1 184pin unbufferd ddr sdram dimms package dimensions 512mb, 64m x 64 unbuffere d dimm: hymd 564646b[p]8[j] 2.30 0.91 17.80 0.700 0.394 10.0 0.098 2.5 5.077 front 128.95 131.35 5.171 133.35 5.25 (2x)4.00 0.157 back (2) 0 side (front) 3.18 0.125max 1.27+/-0.10 0.050+/-0.004 31.75 1.250 millimeters inches un it :
rev. 1.1 / may. 2005 27 1 184pin unbufferd ddr sdram dimms package dimensions 512mb, 64m x 72 e cc unbuffered dimm: hymd564726b[p]8[j] 2.30 0.91 17.80 0.700 0.394 10.0 0.098 2.5 5.077 front 128.95 131.35 5.171 133.35 5.25 (2x)4.00 0.157 back (2) 0 side (front) 3.18 0.125max 1.27+/-0.10 0.050+/-0.004 31.75 1.250 millimeters inches un it :
rev. 1.1 / may. 2005 28 1 184pin unbufferd ddr sdram dimms package dimensions 1gb, 128m x 64 unbuffered dimm : hymd564646b[p]8[j] 2.30 0.91 17.80 0.700 0.394 10.0 0.098 2.5 5.077 front 128.95 131.35 5.171 133.35 5.25 (2x)4.00 0.157 back (2) 0 side (front) 4.00 0.157max 1.27+/-0.10 0.050+/-0.004 31.75 1.250 millimeters inches un it :
rev. 1.1 / may. 2005 29 1 184pin unbufferd ddr sdram dimms 1gb, 128m x 72 ecc unbuffe red dimm: hymd512726b[p]8[j] package dimensions 2.30 0.91 17.80 0.700 0.394 10.0 0.098 2.5 5.077 front 128.95 131.35 5.171 133.35 5.25 (2x)4.00 0.157 back (2) 0 side (front) 4.00 0.157max 1.27+/-0.10 0.050+/-0.004 31.75 1.250 millimeters inches un it :
rev. 1.1 / may. 2005 30 1 184pin unbufferd ddr sdram dimms revision history revision history date remark 1.0 first version release - datasheet coverage is changed from an individual module part to a component based module family feb. 2005 1.1 corrected pin description and pin assignment tables may. 2005

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