ma31750 - application note 14 1/3 the following applications note presents information which will be of use to design engineers who are evaluating the n iteration of the ma31750 microprocessor. in particular, it defines the aspects of the current device operation which do not ful ly meet the requirements of the specification. this note covers all of the known problems found to date with the n iteration parts . 1. long loads and stores in 1750b mode when using the long load instructions in 1750b mode, the status word does not update the flags bits according to the data just loaded. if a conditional branch or jump is to be determined on the data long loaded, then an explicit compare must be executed before the branch or jump instruction. during long load and store instructions, the status word is written between each memory access. in the status word written during the loads / stores the ps bits mimic the as bits. this can be a problem if there is an mmu present in the system as it may cause illegal memory accesses due to access locks and keys no longer matching. 2. extended multiplication in 1750b mode in 1750b mode, when using efm / efmr to multiply 2 numbers, both with an exponent of 0x80, the normalisation method incorrectly determines that an overflow has occurred. the result is forced to the largest positive value (7fff ff7f ffff) if the signs of the multiplicands were the same, and to the largest negative number (8000 007f 0000) if the signs of the multiplicands were different. in both cases, the overflow flag is set. a workaround within the overflow interrupt service routine would be to check the exponent of the multiplicand that has not been overwritten. if the exponent value is 0x80, then an overflow result must be erroneous and appropriate action can be taken if required. this problem does not occur in 1750a mode. 3. unsigned subtract in 1750b if a negative flag is set as the result of an unsigned subtract, the carry flag will also be set. this may be incorrect. 4. fault mask writes in 1750b mode the fault mask is permanantly stuck at ffff h . the fault mask write xio is legal in 1750b mode, but has no effect on the contents of the mask register. 5. bus timeouts and the fault register when rdyn stays high during an external memory or io access (ie. dsn is low), then a timeout fault (either bit 5 or bit 8), will be logged in the fault register. internally, the cpu sets a timeout flag. this timeout flag is only cleared by servicing the machine error interrupt or by executing the clir xio instruction. normally, when a fault is activated, the me interrupt is serviced immediately and the timeout flag is cleared. however, if the me interrupt is masked, any further external cycles will be flagged as having a timeout fault. this could erroneously set either bit 5 or bit 8 in the fault register. this is also a problem in console mode when console has priority over interrupts. 6. de-granting the processor it is strongly recommended that users should reference application note 11 for the ma31750, if the cpu is ever to be de-granted. 7. selecting multiple bpu devices when multiple bpus are present in a system (in1750b) the configuration register must have bpu0 set high otherwise the xio mpen is disabled. this means that 2mwords of bpu protection cannot be selected. 8. external cycles with no active data strobes during an external machine cycle, as can go active whilst dsn / rdn / wrn remain inactive. this is caused by the occurrance of aborted cycles. cycles can be aborted causing the following effects: a: if mproen and / or exaden are held low for 2 falling edges of tclk, the current machine cycle aborts without producing any data strobes. b: if pen is active when as falls, the following cycle (if it is external) will produce an active as with no data strobes (if the me interrupt is unmasked). this as can be extended by mproen and / or exaden being low. c: if a fixed point overflow occurs, the cpu begins to fetch the next instruction. it then aborts this fetch to go back and execute the overflow routine. this aborted fetch is a fixed machine cycle of 2 clks. the as is active for a fixed length of 1.5 clk cycles. this cannot be extended by mproen, exaden or rdyn. this has implications when using an mmu and bpu in the system at 16mhz, as a cache miss for both the mmu and bpu would mean that mproen could be invalid when the cpu samples it on as falling. if the system is restricted to the use of either an mmu or a bpu, there is enough time available to ensure that mproen is valid before it is sampled. alternatively, if the system speed is slowed to approximately 10mhz, both an mmu and a bpu can be used. a further implication of external cycles with no data strobes is that wait state generators must not be started on the as rising edge, but on dsn active. (an additional reason for this is that the nma31750 inserts clk cycles between as rising and dsn falling if mproen or exaden are active or if an interrupt occurs). AN4030 ma31750 - use of nma31750 samples application note replaces july 2000 version, AN4030-8.0 AN4030-8.1 july 2002
ma31750 - application note 14 2/3 13. floating subtracts if the subtraction 0x800001xx - 0x800000xx is done, the ma31750 gives the eroneous result of zero. (xx represents any exponent. (both numbers have the same exponent). 14. parity checking the nma31750 has a slow path within its data parity checking circuit which will affect the device when running at speeds over 120mhz, at high temperatures and low voltages. this slow path can result in 2 types of error: case (a) if a parity error has occurred on a cycle when dparn is low, and dparn is then raised, the following external cycle will be logged as having a parity error. case (b) if a genuine parity error has occurred a machine error interrupt will be flagged but no parity error interrupt will be flagged but no parity error is set in the fault register. if parity checking is required at high speeds over the military temperature and voltage range, either a valid parity bit should be generated at all times, or dparn low should be extended to cover an extra external cycle to prevent case (a) from occuring. case (b) cannot be avoided unless clock speeds are reduced. 9. early wait states after abort if the machine error interrupt is masked, and an early wait timeout occurs, the current cycle is aborted. if the subsequent cycle is external, early wait states cannot be added. 10. bus fault timeout servicing if a bus fault timeout occurs, due to rdyn held high for 2 falling edges of tclk, and the machine error interrupt is unmasked, the processor will service the me interrupt service routine. this isr is erroneously aborted and restarted by the microprocessor which causes the cpu to enter a continuous loop. this can only be halted by an active resetn signal. 11. extended floating point adds and subtracts if the answer produced as the result of an extended floating point add or subtract is a small positive number, which is contained within the 8 least significant bits before normalisation, then the answer will be incorrectly set to zero. the macros are available to replace the extended floating point adds and subtracts. these are given in the ma31750, an16. 12. extended floating point compares if 2 numbers are compared and the result is a small positive number contained in the 16 lsb's, then the status flag will incorrectly indicate zero rather than positive. a macro is available to replace the extended floating point compare instructions. this is given in ma31750, an16.
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